2 * A V4L2 driver for OmniVision OV7670 cameras.
4 * Copyright 2006 One Laptop Per Child Association, Inc. Written
5 * by Jonathan Corbet with substantial inspiration from Mark
6 * McClelland's ovcamchip code.
8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 * This file may be distributed under the terms of the GNU General
11 * Public License, version 2.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
17 #include <linux/delay.h>
18 #include <linux/videodev2.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-mediabus.h>
22 #include <media/v4l2-image-sizes.h>
23 #include <media/ov7670.h>
25 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
26 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
27 MODULE_LICENSE("GPL");
30 module_param(debug, bool, 0644);
31 MODULE_PARM_DESC(debug, "Debug level (0-1)");
34 * The 7670 sits on i2c with ID 0x42
36 #define OV7670_I2C_ADDR 0x42
41 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
42 #define REG_BLUE 0x01 /* blue gain */
43 #define REG_RED 0x02 /* red gain */
44 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
45 #define REG_COM1 0x04 /* Control 1 */
46 #define COM1_CCIR656 0x40 /* CCIR656 enable */
47 #define REG_BAVE 0x05 /* U/B Average level */
48 #define REG_GbAVE 0x06 /* Y/Gb Average level */
49 #define REG_AECHH 0x07 /* AEC MS 5 bits */
50 #define REG_RAVE 0x08 /* V/R Average level */
51 #define REG_COM2 0x09 /* Control 2 */
52 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
53 #define REG_PID 0x0a /* Product ID MSB */
54 #define REG_VER 0x0b /* Product ID LSB */
55 #define REG_COM3 0x0c /* Control 3 */
56 #define COM3_SWAP 0x40 /* Byte swap */
57 #define COM3_SCALEEN 0x08 /* Enable scaling */
58 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
59 #define REG_COM4 0x0d /* Control 4 */
60 #define REG_COM5 0x0e /* All "reserved" */
61 #define REG_COM6 0x0f /* Control 6 */
62 #define REG_AECH 0x10 /* More bits of AEC value */
63 #define REG_CLKRC 0x11 /* Clocl control */
64 #define CLK_EXT 0x40 /* Use external clock directly */
65 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
66 #define REG_COM7 0x12 /* Control 7 */
67 #define COM7_RESET 0x80 /* Register reset */
68 #define COM7_FMT_MASK 0x38
69 #define COM7_FMT_VGA 0x00
70 #define COM7_FMT_CIF 0x20 /* CIF format */
71 #define COM7_FMT_QVGA 0x10 /* QVGA format */
72 #define COM7_FMT_QCIF 0x08 /* QCIF format */
73 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
74 #define COM7_YUV 0x00 /* YUV */
75 #define COM7_BAYER 0x01 /* Bayer format */
76 #define COM7_PBAYER 0x05 /* "Processed bayer" */
77 #define REG_COM8 0x13 /* Control 8 */
78 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
79 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
80 #define COM8_BFILT 0x20 /* Band filter enable */
81 #define COM8_AGC 0x04 /* Auto gain enable */
82 #define COM8_AWB 0x02 /* White balance enable */
83 #define COM8_AEC 0x01 /* Auto exposure enable */
84 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
85 #define REG_COM10 0x15 /* Control 10 */
86 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
87 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
88 #define COM10_HREF_REV 0x08 /* Reverse HREF */
89 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
90 #define COM10_VS_NEG 0x02 /* VSYNC negative */
91 #define COM10_HS_NEG 0x01 /* HSYNC negative */
92 #define REG_HSTART 0x17 /* Horiz start high bits */
93 #define REG_HSTOP 0x18 /* Horiz stop high bits */
94 #define REG_VSTART 0x19 /* Vert start high bits */
95 #define REG_VSTOP 0x1a /* Vert stop high bits */
96 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
97 #define REG_MIDH 0x1c /* Manuf. ID high */
98 #define REG_MIDL 0x1d /* Manuf. ID low */
99 #define REG_MVFP 0x1e /* Mirror / vflip */
100 #define MVFP_MIRROR 0x20 /* Mirror image */
101 #define MVFP_FLIP 0x10 /* Vertical flip */
103 #define REG_AEW 0x24 /* AGC upper limit */
104 #define REG_AEB 0x25 /* AGC lower limit */
105 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
106 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
107 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
108 #define REG_HREF 0x32 /* HREF pieces */
109 #define REG_TSLB 0x3a /* lots of stuff */
110 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
111 #define REG_COM11 0x3b /* Control 11 */
112 #define COM11_NIGHT 0x80 /* NIght mode enable */
113 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
114 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
115 #define COM11_50HZ 0x08 /* Manual 50Hz select */
116 #define COM11_EXP 0x02
117 #define REG_COM12 0x3c /* Control 12 */
118 #define COM12_HREF 0x80 /* HREF always */
119 #define REG_COM13 0x3d /* Control 13 */
120 #define COM13_GAMMA 0x80 /* Gamma enable */
121 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
122 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
123 #define REG_COM14 0x3e /* Control 14 */
124 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
125 #define REG_EDGE 0x3f /* Edge enhancement factor */
126 #define REG_COM15 0x40 /* Control 15 */
127 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
128 #define COM15_R01FE 0x80 /* 01 to FE */
129 #define COM15_R00FF 0xc0 /* 00 to FF */
130 #define COM15_RGB565 0x10 /* RGB565 output */
131 #define COM15_RGB555 0x30 /* RGB555 output */
132 #define REG_COM16 0x41 /* Control 16 */
133 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
134 #define REG_COM17 0x42 /* Control 17 */
135 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
136 #define COM17_CBAR 0x08 /* DSP Color bar */
139 * This matrix defines how the colors are generated, must be
140 * tweaked to adjust hue and saturation.
142 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
144 * They are nine-bit signed quantities, with the sign bit
145 * stored in 0x58. Sign for v-red is bit 0, and up from there.
147 #define REG_CMATRIX_BASE 0x4f
148 #define CMATRIX_LEN 6
149 #define REG_CMATRIX_SIGN 0x58
152 #define REG_BRIGHT 0x55 /* Brightness */
153 #define REG_CONTRAS 0x56 /* Contrast control */
155 #define REG_GFIX 0x69 /* Fix gain control */
157 #define REG_DBLV 0x6b /* PLL control an debugging */
158 #define DBLV_BYPASS 0x00 /* Bypass PLL */
159 #define DBLV_X4 0x01 /* clock x4 */
160 #define DBLV_X6 0x10 /* clock x6 */
161 #define DBLV_X8 0x11 /* clock x8 */
163 #define REG_REG76 0x76 /* OV's name */
164 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
165 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
167 #define REG_RGB444 0x8c /* RGB 444 control */
168 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
169 #define R444_RGBX 0x01 /* Empty nibble at end */
171 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
172 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
174 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
175 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
176 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
177 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
178 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
179 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
180 #define REG_BD60MAX 0xab /* 60hz banding step limit */
187 struct ov7670_win_size {
190 unsigned char com7_bit;
191 int hstart; /* Start/stop values for the camera. Note */
192 int hstop; /* that they do not always make complete */
193 int vstart; /* sense to humans, but evidently the sensor */
194 int vstop; /* will do the right thing... */
195 struct regval_list *regs; /* Regs to tweak */
198 struct ov7670_devtype {
199 /* formats supported for each model */
200 struct ov7670_win_size *win_sizes;
201 unsigned int n_win_sizes;
202 /* callbacks for frame rate control */
203 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
204 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
208 * Information we maintain about a known sensor.
210 struct ov7670_format_struct; /* coming later */
212 struct v4l2_subdev sd;
213 struct v4l2_ctrl_handler hdl;
216 struct v4l2_ctrl *auto_gain;
217 struct v4l2_ctrl *gain;
220 /* exposure cluster */
221 struct v4l2_ctrl *auto_exposure;
222 struct v4l2_ctrl *exposure;
225 /* saturation/hue cluster */
226 struct v4l2_ctrl *saturation;
227 struct v4l2_ctrl *hue;
229 struct ov7670_format_struct *fmt; /* Current format */
230 int min_width; /* Filter out smaller sizes */
231 int min_height; /* Filter out smaller sizes */
232 int clock_speed; /* External clock speed (MHz) */
233 u8 clkrc; /* Clock divider value */
234 bool use_smbus; /* Use smbus I/O instead of I2C */
236 bool pclk_hb_disable;
237 const struct ov7670_devtype *devtype; /* Device specifics */
240 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
242 return container_of(sd, struct ov7670_info, sd);
245 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
247 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd;
253 * The default register settings, as obtained from OmniVision. There
254 * is really no making sense of most of these - lots of "reserved" values
257 * These settings give VGA YUYV.
261 unsigned char reg_num;
265 static struct regval_list ov7670_default_regs[] = {
266 { REG_COM7, COM7_RESET },
268 * Clock scale: 3 = 15fps
272 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
273 { REG_TSLB, 0x04 }, /* OV */
274 { REG_COM7, 0 }, /* VGA */
276 * Set the hardware window. These values from OV don't entirely
277 * make sense - hstop is less than hstart. But they work...
279 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
280 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
281 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
283 { REG_COM3, 0 }, { REG_COM14, 0 },
284 /* Mystery scaling numbers */
285 { 0x70, 0x3a }, { 0x71, 0x35 },
286 { 0x72, 0x11 }, { 0x73, 0xf0 },
287 { 0xa2, 0x02 }, { REG_COM10, 0x0 },
289 /* Gamma curve values */
290 { 0x7a, 0x20 }, { 0x7b, 0x10 },
291 { 0x7c, 0x1e }, { 0x7d, 0x35 },
292 { 0x7e, 0x5a }, { 0x7f, 0x69 },
293 { 0x80, 0x76 }, { 0x81, 0x80 },
294 { 0x82, 0x88 }, { 0x83, 0x8f },
295 { 0x84, 0x96 }, { 0x85, 0xa3 },
296 { 0x86, 0xaf }, { 0x87, 0xc4 },
297 { 0x88, 0xd7 }, { 0x89, 0xe8 },
299 /* AGC and AEC parameters. Note we start by disabling those features,
300 then turn them only after tweaking the values. */
301 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
302 { REG_GAIN, 0 }, { REG_AECH, 0 },
303 { REG_COM4, 0x40 }, /* magic reserved bit */
304 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
305 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
306 { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
307 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
308 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
309 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
310 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
311 { REG_HAECC7, 0x94 },
312 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
314 /* Almost all of these are magic "reserved" values. */
315 { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
316 { 0x16, 0x02 }, { REG_MVFP, 0x07 },
317 { 0x21, 0x02 }, { 0x22, 0x91 },
318 { 0x29, 0x07 }, { 0x33, 0x0b },
319 { 0x35, 0x0b }, { 0x37, 0x1d },
320 { 0x38, 0x71 }, { 0x39, 0x2a },
321 { REG_COM12, 0x78 }, { 0x4d, 0x40 },
322 { 0x4e, 0x20 }, { REG_GFIX, 0 },
323 { 0x6b, 0x4a }, { 0x74, 0x10 },
324 { 0x8d, 0x4f }, { 0x8e, 0 },
325 { 0x8f, 0 }, { 0x90, 0 },
326 { 0x91, 0 }, { 0x96, 0 },
327 { 0x9a, 0 }, { 0xb0, 0x84 },
328 { 0xb1, 0x0c }, { 0xb2, 0x0e },
329 { 0xb3, 0x82 }, { 0xb8, 0x0a },
331 /* More reserved magic, some of which tweaks white balance */
332 { 0x43, 0x0a }, { 0x44, 0xf0 },
333 { 0x45, 0x34 }, { 0x46, 0x58 },
334 { 0x47, 0x28 }, { 0x48, 0x3a },
335 { 0x59, 0x88 }, { 0x5a, 0x88 },
336 { 0x5b, 0x44 }, { 0x5c, 0x67 },
337 { 0x5d, 0x49 }, { 0x5e, 0x0e },
338 { 0x6c, 0x0a }, { 0x6d, 0x55 },
339 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
340 { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
342 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
344 /* Matrix coefficients */
345 { 0x4f, 0x80 }, { 0x50, 0x80 },
346 { 0x51, 0 }, { 0x52, 0x22 },
347 { 0x53, 0x5e }, { 0x54, 0x80 },
350 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
351 { 0x75, 0x05 }, { 0x76, 0xe1 },
352 { 0x4c, 0 }, { 0x77, 0x01 },
353 { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
354 { 0xc9, 0x60 }, { REG_COM16, 0x38 },
357 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
358 { 0xa4, 0x88 }, { 0x96, 0 },
359 { 0x97, 0x30 }, { 0x98, 0x20 },
360 { 0x99, 0x30 }, { 0x9a, 0x84 },
361 { 0x9b, 0x29 }, { 0x9c, 0x03 },
362 { 0x9d, 0x4c }, { 0x9e, 0x3f },
365 /* Extra-weird stuff. Some sort of multiplexor register */
366 { 0x79, 0x01 }, { 0xc8, 0xf0 },
367 { 0x79, 0x0f }, { 0xc8, 0x00 },
368 { 0x79, 0x10 }, { 0xc8, 0x7e },
369 { 0x79, 0x0a }, { 0xc8, 0x80 },
370 { 0x79, 0x0b }, { 0xc8, 0x01 },
371 { 0x79, 0x0c }, { 0xc8, 0x0f },
372 { 0x79, 0x0d }, { 0xc8, 0x20 },
373 { 0x79, 0x09 }, { 0xc8, 0x80 },
374 { 0x79, 0x02 }, { 0xc8, 0xc0 },
375 { 0x79, 0x03 }, { 0xc8, 0x40 },
376 { 0x79, 0x05 }, { 0xc8, 0x30 },
379 { 0xff, 0xff }, /* END MARKER */
384 * Here we'll try to encapsulate the changes for just the output
387 * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
389 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
393 static struct regval_list ov7670_fmt_yuv422[] = {
394 { REG_COM7, 0x0 }, /* Selects YUV mode */
395 { REG_RGB444, 0 }, /* No RGB444 please */
396 { REG_COM1, 0 }, /* CCIR601 */
397 { REG_COM15, COM15_R00FF },
398 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
399 { 0x4f, 0x80 }, /* "matrix coefficient 1" */
400 { 0x50, 0x80 }, /* "matrix coefficient 2" */
401 { 0x51, 0 }, /* vb */
402 { 0x52, 0x22 }, /* "matrix coefficient 4" */
403 { 0x53, 0x5e }, /* "matrix coefficient 5" */
404 { 0x54, 0x80 }, /* "matrix coefficient 6" */
405 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
409 static struct regval_list ov7670_fmt_rgb565[] = {
410 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
411 { REG_RGB444, 0 }, /* No RGB444 please */
412 { REG_COM1, 0x0 }, /* CCIR601 */
413 { REG_COM15, COM15_RGB565 },
414 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
415 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
416 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
417 { 0x51, 0 }, /* vb */
418 { 0x52, 0x3d }, /* "matrix coefficient 4" */
419 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
420 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
421 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
425 static struct regval_list ov7670_fmt_rgb444[] = {
426 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
427 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
428 { REG_COM1, 0x0 }, /* CCIR601 */
429 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
430 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
431 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
432 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
433 { 0x51, 0 }, /* vb */
434 { 0x52, 0x3d }, /* "matrix coefficient 4" */
435 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
436 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
437 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
441 static struct regval_list ov7670_fmt_raw[] = {
442 { REG_COM7, COM7_BAYER },
443 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
444 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
445 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
452 * Low-level register I/O.
454 * Note that there are two versions of these. On the XO 1, the
455 * i2c controller only does SMBUS, so that's what we use. The
456 * ov7670 is not really an SMBUS device, though, so the communication
457 * is not always entirely reliable.
459 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg,
460 unsigned char *value)
462 struct i2c_client *client = v4l2_get_subdevdata(sd);
465 ret = i2c_smbus_read_byte_data(client, reg);
467 *value = (unsigned char)ret;
474 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg,
477 struct i2c_client *client = v4l2_get_subdevdata(sd);
478 int ret = i2c_smbus_write_byte_data(client, reg, value);
480 if (reg == REG_COM7 && (value & COM7_RESET))
481 msleep(5); /* Wait for reset to run */
486 * On most platforms, we'd rather do straight i2c I/O.
488 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg,
489 unsigned char *value)
491 struct i2c_client *client = v4l2_get_subdevdata(sd);
497 * Send out the register address...
499 msg.addr = client->addr;
503 ret = i2c_transfer(client->adapter, &msg, 1);
505 printk(KERN_ERR "Error %d on register write\n", ret);
509 * ...then read back the result.
511 msg.flags = I2C_M_RD;
512 ret = i2c_transfer(client->adapter, &msg, 1);
521 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg,
524 struct i2c_client *client = v4l2_get_subdevdata(sd);
526 unsigned char data[2] = { reg, value };
529 msg.addr = client->addr;
533 ret = i2c_transfer(client->adapter, &msg, 1);
536 if (reg == REG_COM7 && (value & COM7_RESET))
537 msleep(5); /* Wait for reset to run */
541 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
542 unsigned char *value)
544 struct ov7670_info *info = to_state(sd);
546 return ov7670_read_smbus(sd, reg, value);
548 return ov7670_read_i2c(sd, reg, value);
551 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
554 struct ov7670_info *info = to_state(sd);
556 return ov7670_write_smbus(sd, reg, value);
558 return ov7670_write_i2c(sd, reg, value);
562 * Write a list of register settings; ff/ff stops the process.
564 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
566 while (vals->reg_num != 0xff || vals->value != 0xff) {
567 int ret = ov7670_write(sd, vals->reg_num, vals->value);
577 * Stuff that knows about the sensor.
579 static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
581 ov7670_write(sd, REG_COM7, COM7_RESET);
587 static int ov7670_init(struct v4l2_subdev *sd, u32 val)
589 return ov7670_write_array(sd, ov7670_default_regs);
594 static int ov7670_detect(struct v4l2_subdev *sd)
599 ret = ov7670_init(sd, 0);
602 ret = ov7670_read(sd, REG_MIDH, &v);
605 if (v != 0x7f) /* OV manuf. id. */
607 ret = ov7670_read(sd, REG_MIDL, &v);
613 * OK, we know we have an OmniVision chip...but which one?
615 ret = ov7670_read(sd, REG_PID, &v);
618 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
620 ret = ov7670_read(sd, REG_VER, &v);
623 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
630 * Store information about the video data format. The color matrix
631 * is deeply tied into the format, so keep the relevant values here.
632 * The magic matrix numbers come from OmniVision.
634 static struct ov7670_format_struct {
636 enum v4l2_colorspace colorspace;
637 struct regval_list *regs;
638 int cmatrix[CMATRIX_LEN];
639 } ov7670_formats[] = {
641 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
642 .colorspace = V4L2_COLORSPACE_JPEG,
643 .regs = ov7670_fmt_yuv422,
644 .cmatrix = { 128, -128, 0, -34, -94, 128 },
647 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
648 .colorspace = V4L2_COLORSPACE_SRGB,
649 .regs = ov7670_fmt_rgb444,
650 .cmatrix = { 179, -179, 0, -61, -176, 228 },
653 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
654 .colorspace = V4L2_COLORSPACE_SRGB,
655 .regs = ov7670_fmt_rgb565,
656 .cmatrix = { 179, -179, 0, -61, -176, 228 },
659 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
660 .colorspace = V4L2_COLORSPACE_SRGB,
661 .regs = ov7670_fmt_raw,
662 .cmatrix = { 0, 0, 0, 0, 0, 0 },
665 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
669 * Then there is the issue of window sizes. Try to capture the info here.
673 * QCIF mode is done (by OV) in a very strange way - it actually looks like
674 * VGA with weird scaling options - they do *not* use the canned QCIF mode
675 * which is allegedly provided by the sensor. So here's the weird register
678 static struct regval_list ov7670_qcif_regs[] = {
679 { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
680 { REG_COM3, COM3_DCWEN },
681 { REG_COM14, COM14_DCWEN | 0x01},
697 static struct ov7670_win_size ov7670_win_sizes[] = {
701 .height = VGA_HEIGHT,
702 .com7_bit = COM7_FMT_VGA,
703 .hstart = 158, /* These values from */
704 .hstop = 14, /* Omnivision */
712 .height = CIF_HEIGHT,
713 .com7_bit = COM7_FMT_CIF,
714 .hstart = 170, /* Empirically determined */
723 .height = QVGA_HEIGHT,
724 .com7_bit = COM7_FMT_QVGA,
725 .hstart = 168, /* Empirically determined */
734 .height = QCIF_HEIGHT,
735 .com7_bit = COM7_FMT_VGA, /* see comment above */
736 .hstart = 456, /* Empirically determined */
740 .regs = ov7670_qcif_regs,
744 static struct ov7670_win_size ov7675_win_sizes[] = {
746 * Currently, only VGA is supported. Theoretically it could be possible
747 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a
748 * base and tweak them empirically could be required.
752 .height = VGA_HEIGHT,
753 .com7_bit = COM7_FMT_VGA,
754 .hstart = 158, /* These values from */
755 .hstop = 14, /* Omnivision */
756 .vstart = 14, /* Empirically determined */
762 static void ov7675_get_framerate(struct v4l2_subdev *sd,
763 struct v4l2_fract *tpf)
765 struct ov7670_info *info = to_state(sd);
766 u32 clkrc = info->clkrc;
769 if (info->pll_bypass)
772 pll_factor = PLL_FACTOR;
775 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
776 clkrc = (clkrc >> 1);
779 tpf->denominator = (5 * pll_factor * info->clock_speed) /
783 static int ov7675_set_framerate(struct v4l2_subdev *sd,
784 struct v4l2_fract *tpf)
786 struct ov7670_info *info = to_state(sd);
792 * The formula is fps = 5/4*pixclk for YUV/RGB and
793 * fps = 5/2*pixclk for RAW.
795 * pixclk = clock_speed / (clkrc + 1) * PLLfactor
798 if (info->pll_bypass) {
800 ret = ov7670_write(sd, REG_DBLV, DBLV_BYPASS);
802 pll_factor = PLL_FACTOR;
803 ret = ov7670_write(sd, REG_DBLV, DBLV_X4);
808 if (tpf->numerator == 0 || tpf->denominator == 0) {
811 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) /
812 (4 * tpf->denominator);
813 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
814 clkrc = (clkrc << 1);
819 * The datasheet claims that clkrc = 0 will divide the input clock by 1
820 * but we've checked with an oscilloscope that it divides by 2 instead.
821 * So, if clkrc = 0 just bypass the divider.
825 else if (clkrc > CLK_SCALE)
829 /* Recalculate frame rate */
830 ov7675_get_framerate(sd, tpf);
832 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
836 return ov7670_write(sd, REG_DBLV, DBLV_X4);
839 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd,
840 struct v4l2_fract *tpf)
842 struct ov7670_info *info = to_state(sd);
845 tpf->denominator = info->clock_speed;
846 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
847 tpf->denominator /= (info->clkrc & CLK_SCALE);
850 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd,
851 struct v4l2_fract *tpf)
853 struct ov7670_info *info = to_state(sd);
856 if (tpf->numerator == 0 || tpf->denominator == 0)
857 div = 1; /* Reset to full rate */
859 div = (tpf->numerator * info->clock_speed) / tpf->denominator;
862 else if (div > CLK_SCALE)
864 info->clkrc = (info->clkrc & 0x80) | div;
866 tpf->denominator = info->clock_speed / div;
867 return ov7670_write(sd, REG_CLKRC, info->clkrc);
871 * Store a set of start/stop values into the camera.
873 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
874 int vstart, int vstop)
879 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
880 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
881 * a mystery "edge offset" value in the top two bits of href.
883 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
884 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
885 ret += ov7670_read(sd, REG_HREF, &v);
886 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
888 ret += ov7670_write(sd, REG_HREF, v);
890 * Vertical: similar arrangement, but only 10 bits.
892 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
893 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
894 ret += ov7670_read(sd, REG_VREF, &v);
895 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
897 ret += ov7670_write(sd, REG_VREF, v);
902 static int ov7670_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
905 if (index >= N_OV7670_FMTS)
908 *code = ov7670_formats[index].mbus_code;
912 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
913 struct v4l2_mbus_framefmt *fmt,
914 struct ov7670_format_struct **ret_fmt,
915 struct ov7670_win_size **ret_wsize)
918 struct ov7670_win_size *wsize;
919 struct ov7670_info *info = to_state(sd);
920 unsigned int n_win_sizes = info->devtype->n_win_sizes;
921 unsigned int win_sizes_limit = n_win_sizes;
923 for (index = 0; index < N_OV7670_FMTS; index++)
924 if (ov7670_formats[index].mbus_code == fmt->code)
926 if (index >= N_OV7670_FMTS) {
927 /* default to first format */
929 fmt->code = ov7670_formats[0].mbus_code;
932 *ret_fmt = ov7670_formats + index;
934 * Fields: the OV devices claim to be progressive.
936 fmt->field = V4L2_FIELD_NONE;
939 * Don't consider values that don't match min_height and min_width
942 if (info->min_width || info->min_height)
943 for (i = 0; i < n_win_sizes; i++) {
944 wsize = info->devtype->win_sizes + i;
946 if (wsize->width < info->min_width ||
947 wsize->height < info->min_height) {
953 * Round requested image size down to the nearest
954 * we support, but not below the smallest.
956 for (wsize = info->devtype->win_sizes;
957 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++)
958 if (fmt->width >= wsize->width && fmt->height >= wsize->height)
960 if (wsize >= info->devtype->win_sizes + win_sizes_limit)
961 wsize--; /* Take the smallest one */
962 if (ret_wsize != NULL)
965 * Note the size we'll actually handle.
967 fmt->width = wsize->width;
968 fmt->height = wsize->height;
969 fmt->colorspace = ov7670_formats[index].colorspace;
973 static int ov7670_try_mbus_fmt(struct v4l2_subdev *sd,
974 struct v4l2_mbus_framefmt *fmt)
976 return ov7670_try_fmt_internal(sd, fmt, NULL, NULL);
982 static int ov7670_s_mbus_fmt(struct v4l2_subdev *sd,
983 struct v4l2_mbus_framefmt *fmt)
985 struct ov7670_format_struct *ovfmt;
986 struct ov7670_win_size *wsize;
987 struct ov7670_info *info = to_state(sd);
991 ret = ov7670_try_fmt_internal(sd, fmt, &ovfmt, &wsize);
996 * COM7 is a pain in the ass, it doesn't like to be read then
997 * quickly written afterward. But we have everything we need
998 * to set it absolutely here, as long as the format-specific
999 * register sets list it first.
1001 com7 = ovfmt->regs[0].value;
1002 com7 |= wsize->com7_bit;
1003 ov7670_write(sd, REG_COM7, com7);
1005 * Now write the rest of the array. Also store start/stops
1007 ov7670_write_array(sd, ovfmt->regs + 1);
1008 ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
1012 ret = ov7670_write_array(sd, wsize->regs);
1016 * If we're running RGB565, we must rewrite clkrc after setting
1017 * the other parameters or the image looks poor. If we're *not*
1018 * doing RGB565, we must not rewrite clkrc or the image looks
1021 * (Update) Now that we retain clkrc state, we should be able
1022 * to write it unconditionally, and that will make the frame
1023 * rate persistent too.
1026 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
1031 * Implement G/S_PARM. There is a "high quality" mode we could try
1032 * to do someday; for now, we just do the frame rate tweak.
1034 static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
1036 struct v4l2_captureparm *cp = &parms->parm.capture;
1037 struct ov7670_info *info = to_state(sd);
1039 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1042 memset(cp, 0, sizeof(struct v4l2_captureparm));
1043 cp->capability = V4L2_CAP_TIMEPERFRAME;
1044 info->devtype->get_framerate(sd, &cp->timeperframe);
1049 static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
1051 struct v4l2_captureparm *cp = &parms->parm.capture;
1052 struct v4l2_fract *tpf = &cp->timeperframe;
1053 struct ov7670_info *info = to_state(sd);
1055 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1057 if (cp->extendedmode != 0)
1060 return info->devtype->set_framerate(sd, tpf);
1065 * Frame intervals. Since frame rates are controlled with the clock
1066 * divider, we can only do 30/n for integer n values. So no continuous
1067 * or stepwise options. Here we just pick a handful of logical values.
1070 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 };
1072 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd,
1073 struct v4l2_subdev_pad_config *cfg,
1074 struct v4l2_subdev_frame_interval_enum *fie)
1078 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates))
1080 fie->interval.numerator = 1;
1081 fie->interval.denominator = ov7670_frame_rates[fie->index];
1086 * Frame size enumeration
1088 static int ov7670_enum_frame_size(struct v4l2_subdev *sd,
1089 struct v4l2_subdev_pad_config *cfg,
1090 struct v4l2_subdev_frame_size_enum *fse)
1092 struct ov7670_info *info = to_state(sd);
1095 __u32 index = fse->index;
1096 unsigned int n_win_sizes = info->devtype->n_win_sizes;
1102 * If a minimum width/height was requested, filter out the capture
1103 * windows that fall outside that.
1105 for (i = 0; i < n_win_sizes; i++) {
1106 struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1107 if (info->min_width && win->width < info->min_width)
1109 if (info->min_height && win->height < info->min_height)
1111 if (index == ++num_valid) {
1112 fse->min_width = fse->max_width = win->width;
1113 fse->min_height = fse->max_height = win->height;
1122 * Code for dealing with controls.
1125 static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
1126 int matrix[CMATRIX_LEN])
1129 unsigned char signbits = 0;
1132 * Weird crap seems to exist in the upper part of
1133 * the sign bits register, so let's preserve it.
1135 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
1138 for (i = 0; i < CMATRIX_LEN; i++) {
1141 if (matrix[i] < 0) {
1142 signbits |= (1 << i);
1143 if (matrix[i] < -255)
1146 raw = (-1 * matrix[i]) & 0xff;
1149 if (matrix[i] > 255)
1152 raw = matrix[i] & 0xff;
1154 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
1156 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
1162 * Hue also requires messing with the color matrix. It also requires
1163 * trig functions, which tend not to be well supported in the kernel.
1164 * So here is a simple table of sine values, 0-90 degrees, in steps
1165 * of five degrees. Values are multiplied by 1000.
1167 * The following naive approximate trig functions require an argument
1168 * carefully limited to -180 <= theta <= 180.
1171 static const int ov7670_sin_table[] = {
1172 0, 87, 173, 258, 342, 422,
1173 499, 573, 642, 707, 766, 819,
1174 866, 906, 939, 965, 984, 996,
1178 static int ov7670_sine(int theta)
1188 sine = ov7670_sin_table[theta/SIN_STEP];
1191 sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
1196 static int ov7670_cosine(int theta)
1201 else if (theta < -180)
1203 return ov7670_sine(theta);
1209 static void ov7670_calc_cmatrix(struct ov7670_info *info,
1210 int matrix[CMATRIX_LEN], int sat, int hue)
1214 * Apply the current saturation setting first.
1216 for (i = 0; i < CMATRIX_LEN; i++)
1217 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7;
1219 * Then, if need be, rotate the hue value.
1222 int sinth, costh, tmpmatrix[CMATRIX_LEN];
1224 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
1225 sinth = ov7670_sine(hue);
1226 costh = ov7670_cosine(hue);
1228 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
1229 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
1230 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
1231 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
1232 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
1233 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
1239 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue)
1241 struct ov7670_info *info = to_state(sd);
1242 int matrix[CMATRIX_LEN];
1245 ov7670_calc_cmatrix(info, matrix, sat, hue);
1246 ret = ov7670_store_cmatrix(sd, matrix);
1252 * Some weird registers seem to store values in a sign/magnitude format!
1255 static unsigned char ov7670_abs_to_sm(unsigned char v)
1259 return (128 - v) | 0x80;
1262 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
1264 unsigned char com8 = 0, v;
1267 ov7670_read(sd, REG_COM8, &com8);
1269 ov7670_write(sd, REG_COM8, com8);
1270 v = ov7670_abs_to_sm(value);
1271 ret = ov7670_write(sd, REG_BRIGHT, v);
1275 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
1277 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
1280 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
1282 unsigned char v = 0;
1285 ret = ov7670_read(sd, REG_MVFP, &v);
1290 msleep(10); /* FIXME */
1291 ret += ov7670_write(sd, REG_MVFP, v);
1295 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
1297 unsigned char v = 0;
1300 ret = ov7670_read(sd, REG_MVFP, &v);
1305 msleep(10); /* FIXME */
1306 ret += ov7670_write(sd, REG_MVFP, v);
1311 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes
1312 * the data sheet, the VREF parts should be the most significant, but
1313 * experience shows otherwise. There seems to be little value in
1314 * messing with the VREF bits, so we leave them alone.
1316 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
1321 ret = ov7670_read(sd, REG_GAIN, &gain);
1326 static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
1331 ret = ov7670_write(sd, REG_GAIN, value & 0xff);
1332 /* Have to turn off AGC as well */
1334 ret = ov7670_read(sd, REG_COM8, &com8);
1335 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
1343 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
1348 ret = ov7670_read(sd, REG_COM8, &com8);
1354 ret = ov7670_write(sd, REG_COM8, com8);
1359 static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
1362 unsigned char com1, com8, aech, aechh;
1364 ret = ov7670_read(sd, REG_COM1, &com1) +
1365 ov7670_read(sd, REG_COM8, &com8);
1366 ov7670_read(sd, REG_AECHH, &aechh);
1370 com1 = (com1 & 0xfc) | (value & 0x03);
1371 aech = (value >> 2) & 0xff;
1372 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
1373 ret = ov7670_write(sd, REG_COM1, com1) +
1374 ov7670_write(sd, REG_AECH, aech) +
1375 ov7670_write(sd, REG_AECHH, aechh);
1376 /* Have to turn off AEC as well */
1378 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
1383 * Tweak autoexposure.
1385 static int ov7670_s_autoexp(struct v4l2_subdev *sd,
1386 enum v4l2_exposure_auto_type value)
1391 ret = ov7670_read(sd, REG_COM8, &com8);
1393 if (value == V4L2_EXPOSURE_AUTO)
1397 ret = ov7670_write(sd, REG_COM8, com8);
1403 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1405 struct v4l2_subdev *sd = to_sd(ctrl);
1406 struct ov7670_info *info = to_state(sd);
1409 case V4L2_CID_AUTOGAIN:
1410 return ov7670_g_gain(sd, &info->gain->val);
1415 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl)
1417 struct v4l2_subdev *sd = to_sd(ctrl);
1418 struct ov7670_info *info = to_state(sd);
1421 case V4L2_CID_BRIGHTNESS:
1422 return ov7670_s_brightness(sd, ctrl->val);
1423 case V4L2_CID_CONTRAST:
1424 return ov7670_s_contrast(sd, ctrl->val);
1425 case V4L2_CID_SATURATION:
1426 return ov7670_s_sat_hue(sd,
1427 info->saturation->val, info->hue->val);
1428 case V4L2_CID_VFLIP:
1429 return ov7670_s_vflip(sd, ctrl->val);
1430 case V4L2_CID_HFLIP:
1431 return ov7670_s_hflip(sd, ctrl->val);
1432 case V4L2_CID_AUTOGAIN:
1433 /* Only set manual gain if auto gain is not explicitly
1436 /* ov7670_s_gain turns off auto gain */
1437 return ov7670_s_gain(sd, info->gain->val);
1439 return ov7670_s_autogain(sd, ctrl->val);
1440 case V4L2_CID_EXPOSURE_AUTO:
1441 /* Only set manual exposure if auto exposure is not explicitly
1443 if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
1444 /* ov7670_s_exp turns off auto exposure */
1445 return ov7670_s_exp(sd, info->exposure->val);
1447 return ov7670_s_autoexp(sd, ctrl->val);
1452 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = {
1453 .s_ctrl = ov7670_s_ctrl,
1454 .g_volatile_ctrl = ov7670_g_volatile_ctrl,
1457 #ifdef CONFIG_VIDEO_ADV_DEBUG
1458 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1460 unsigned char val = 0;
1463 ret = ov7670_read(sd, reg->reg & 0xff, &val);
1469 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1471 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
1476 /* ----------------------------------------------------------------------- */
1478 static const struct v4l2_subdev_core_ops ov7670_core_ops = {
1479 .reset = ov7670_reset,
1480 .init = ov7670_init,
1481 #ifdef CONFIG_VIDEO_ADV_DEBUG
1482 .g_register = ov7670_g_register,
1483 .s_register = ov7670_s_register,
1487 static const struct v4l2_subdev_video_ops ov7670_video_ops = {
1488 .enum_mbus_fmt = ov7670_enum_mbus_fmt,
1489 .try_mbus_fmt = ov7670_try_mbus_fmt,
1490 .s_mbus_fmt = ov7670_s_mbus_fmt,
1491 .s_parm = ov7670_s_parm,
1492 .g_parm = ov7670_g_parm,
1495 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = {
1496 .enum_frame_interval = ov7670_enum_frame_interval,
1497 .enum_frame_size = ov7670_enum_frame_size,
1500 static const struct v4l2_subdev_ops ov7670_ops = {
1501 .core = &ov7670_core_ops,
1502 .video = &ov7670_video_ops,
1503 .pad = &ov7670_pad_ops,
1506 /* ----------------------------------------------------------------------- */
1508 static const struct ov7670_devtype ov7670_devdata[] = {
1510 .win_sizes = ov7670_win_sizes,
1511 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes),
1512 .set_framerate = ov7670_set_framerate_legacy,
1513 .get_framerate = ov7670_get_framerate_legacy,
1516 .win_sizes = ov7675_win_sizes,
1517 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes),
1518 .set_framerate = ov7675_set_framerate,
1519 .get_framerate = ov7675_get_framerate,
1523 static int ov7670_probe(struct i2c_client *client,
1524 const struct i2c_device_id *id)
1526 struct v4l2_fract tpf;
1527 struct v4l2_subdev *sd;
1528 struct ov7670_info *info;
1531 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
1535 v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
1537 info->clock_speed = 30; /* default: a guess */
1538 if (client->dev.platform_data) {
1539 struct ov7670_config *config = client->dev.platform_data;
1542 * Must apply configuration before initializing device, because it
1543 * selects I/O method.
1545 info->min_width = config->min_width;
1546 info->min_height = config->min_height;
1547 info->use_smbus = config->use_smbus;
1549 if (config->clock_speed)
1550 info->clock_speed = config->clock_speed;
1553 * It should be allowed for ov7670 too when it is migrated to
1554 * the new frame rate formula.
1556 if (config->pll_bypass && id->driver_data != MODEL_OV7670)
1557 info->pll_bypass = true;
1559 if (config->pclk_hb_disable)
1560 info->pclk_hb_disable = true;
1563 /* Make sure it's an ov7670 */
1564 ret = ov7670_detect(sd);
1566 v4l_dbg(1, debug, client,
1567 "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
1568 client->addr << 1, client->adapter->name);
1571 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1572 client->addr << 1, client->adapter->name);
1574 info->devtype = &ov7670_devdata[id->driver_data];
1575 info->fmt = &ov7670_formats[0];
1578 /* Set default frame rate to 30 fps */
1580 tpf.denominator = 30;
1581 info->devtype->set_framerate(sd, &tpf);
1583 if (info->pclk_hb_disable)
1584 ov7670_write(sd, REG_COM10, COM10_PCLK_HB);
1586 v4l2_ctrl_handler_init(&info->hdl, 10);
1587 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1588 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1589 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1590 V4L2_CID_CONTRAST, 0, 127, 1, 64);
1591 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1592 V4L2_CID_VFLIP, 0, 1, 1, 0);
1593 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1594 V4L2_CID_HFLIP, 0, 1, 1, 0);
1595 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1596 V4L2_CID_SATURATION, 0, 256, 1, 128);
1597 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1598 V4L2_CID_HUE, -180, 180, 5, 0);
1599 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1600 V4L2_CID_GAIN, 0, 255, 1, 128);
1601 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1602 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1603 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1604 V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
1605 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops,
1606 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1607 V4L2_EXPOSURE_AUTO);
1608 sd->ctrl_handler = &info->hdl;
1609 if (info->hdl.error) {
1610 int err = info->hdl.error;
1612 v4l2_ctrl_handler_free(&info->hdl);
1616 * We have checked empirically that hw allows to read back the gain
1617 * value chosen by auto gain but that's not the case for auto exposure.
1619 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true);
1620 v4l2_ctrl_auto_cluster(2, &info->auto_exposure,
1621 V4L2_EXPOSURE_MANUAL, false);
1622 v4l2_ctrl_cluster(2, &info->saturation);
1623 v4l2_ctrl_handler_setup(&info->hdl);
1629 static int ov7670_remove(struct i2c_client *client)
1631 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1632 struct ov7670_info *info = to_state(sd);
1634 v4l2_device_unregister_subdev(sd);
1635 v4l2_ctrl_handler_free(&info->hdl);
1639 static const struct i2c_device_id ov7670_id[] = {
1640 { "ov7670", MODEL_OV7670 },
1641 { "ov7675", MODEL_OV7675 },
1644 MODULE_DEVICE_TABLE(i2c, ov7670_id);
1646 static struct i2c_driver ov7670_driver = {
1648 .owner = THIS_MODULE,
1651 .probe = ov7670_probe,
1652 .remove = ov7670_remove,
1653 .id_table = ov7670_id,
1656 module_i2c_driver(ov7670_driver);