drivers/media/i2c/s5k4ecgx.c

   1 /*
   2  * Driver for Samsung S5K4ECGX 1/4" 5Mp CMOS Image Sensor SoC
   3  * with an Embedded Image Signal Processor.
   4  *
   5  * Copyright (C) 2012, Linaro, Sangwook Lee <sangwook.lee@linaro.org>
   6  * Copyright (C) 2012, Insignal Co,. Ltd, Homin Lee <suapapa@insignal.co.kr>
   7  *
   8  * Based on s5k6aa and noon010pc30 driver
   9  * Copyright (C) 2011, Samsung Electronics Co., Ltd.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/crc32.h>
  19 #include <linux/ctype.h>
  20 #include <linux/delay.h>
  21 #include <linux/firmware.h>
  22 #include <linux/gpio.h>
  23 #include <linux/i2c.h>
  24 #include <linux/module.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/slab.h>
  27 #include <asm/unaligned.h>
  28
  29 #include <media/media-entity.h>
  30 #include <media/s5k4ecgx.h>
  31 #include <media/v4l2-ctrls.h>
  32 #include <media/v4l2-device.h>
  33 #include <media/v4l2-mediabus.h>
  34 #include <media/v4l2-subdev.h>
  35
  36 static int debug;
  37 module_param(debug, int, 0644);
  38
  39 #define S5K4ECGX_DRIVER_NAME            "s5k4ecgx"
  40 #define S5K4ECGX_FIRMWARE               "s5k4ecgx.bin"
  41
  42 /* Firmware revision information */
  43 #define REG_FW_REVISION                 0x700001a6
  44 #define REG_FW_VERSION                  0x700001a4
  45 #define S5K4ECGX_REVISION_1_1           0x11
  46 #define S5K4ECGX_FW_VERSION             0x4ec0
  47
  48 /* General purpose parameters */
  49 #define REG_USER_BRIGHTNESS             0x7000022c
  50 #define REG_USER_CONTRAST               0x7000022e
  51 #define REG_USER_SATURATION             0x70000230
  52
  53 #define REG_G_ENABLE_PREV               0x7000023e
  54 #define REG_G_ENABLE_PREV_CHG           0x70000240
  55 #define REG_G_NEW_CFG_SYNC              0x7000024a
  56 #define REG_G_PREV_IN_WIDTH             0x70000250
  57 #define REG_G_PREV_IN_HEIGHT            0x70000252
  58 #define REG_G_PREV_IN_XOFFS             0x70000254
  59 #define REG_G_PREV_IN_YOFFS             0x70000256
  60 #define REG_G_CAP_IN_WIDTH              0x70000258
  61 #define REG_G_CAP_IN_HEIGHT             0x7000025a
  62 #define REG_G_CAP_IN_XOFFS              0x7000025c
  63 #define REG_G_CAP_IN_YOFFS              0x7000025e
  64 #define REG_G_INPUTS_CHANGE_REQ         0x70000262
  65 #define REG_G_ACTIVE_PREV_CFG           0x70000266
  66 #define REG_G_PREV_CFG_CHG              0x70000268
  67 #define REG_G_PREV_OPEN_AFTER_CH        0x7000026a
  68
  69 /* Preview context register sets. n = 0...4. */
  70 #define PREG(n, x)                      ((n) * 0x30 + (x))
  71 #define REG_P_OUT_WIDTH(n)              PREG(n, 0x700002a6)
  72 #define REG_P_OUT_HEIGHT(n)             PREG(n, 0x700002a8)
  73 #define REG_P_FMT(n)                    PREG(n, 0x700002aa)
  74 #define REG_P_PVI_MASK(n)               PREG(n, 0x700002b4)
  75 #define REG_P_FR_TIME_TYPE(n)           PREG(n, 0x700002be)
  76 #define  FR_TIME_DYNAMIC                0
  77 #define  FR_TIME_FIXED                  1
  78 #define  FR_TIME_FIXED_ACCURATE         2
  79 #define REG_P_FR_TIME_Q_TYPE(n)         PREG(n, 0x700002c0)
  80 #define  FR_TIME_Q_DYNAMIC              0
  81 #define  FR_TIME_Q_BEST_FRRATE          1
  82 #define  FR_TIME_Q_BEST_QUALITY         2
  83
  84 /* Frame period in 0.1 ms units */
  85 #define REG_P_MAX_FR_TIME(n)            PREG(n, 0x700002c2)
  86 #define REG_P_MIN_FR_TIME(n)            PREG(n, 0x700002c4)
  87 #define  US_TO_FR_TIME(__t)             ((__t) / 100)
  88 #define REG_P_PREV_MIRROR(n)            PREG(n, 0x700002d0)
  89 #define REG_P_CAP_MIRROR(n)             PREG(n, 0x700002d2)
  90
  91 #define REG_G_PREVZOOM_IN_WIDTH         0x70000494
  92 #define REG_G_PREVZOOM_IN_HEIGHT        0x70000496
  93 #define REG_G_PREVZOOM_IN_XOFFS         0x70000498
  94 #define REG_G_PREVZOOM_IN_YOFFS         0x7000049a
  95 #define REG_G_CAPZOOM_IN_WIDTH          0x7000049c
  96 #define REG_G_CAPZOOM_IN_HEIGHT         0x7000049e
  97 #define REG_G_CAPZOOM_IN_XOFFS          0x700004a0
  98 #define REG_G_CAPZOOM_IN_YOFFS          0x700004a2
  99
 100 /* n = 0...4 */
 101 #define REG_USER_SHARPNESS(n)           (0x70000a28 + (n) * 0xb6)
 102
 103 /* Reduce sharpness range for user space API */
 104 #define SHARPNESS_DIV                   8208
 105 #define TOK_TERM                        0xffffffff
 106
 107 /*
 108  * FIXME: This is copied from s5k6aa, because of no information
 109  * in the S5K4ECGX datasheet.
 110  * H/W register Interface (0xd0000000 - 0xd0000fff)
 111  */
 112 #define AHB_MSB_ADDR_PTR                0xfcfc
 113 #define GEN_REG_OFFSH                   0xd000
 114 #define REG_CMDWR_ADDRH                 0x0028
 115 #define REG_CMDWR_ADDRL                 0x002a
 116 #define REG_CMDRD_ADDRH                 0x002c
 117 #define REG_CMDRD_ADDRL                 0x002e
 118 #define REG_CMDBUF0_ADDR                0x0f12
 119
 120 struct s5k4ecgx_frmsize {
 121         struct v4l2_frmsize_discrete size;
 122         /* Fixed sensor matrix crop rectangle */
 123         struct v4l2_rect input_window;
 124 };
 125
 126 struct regval_list {
 127         u32 addr;
 128         u16 val;
 129 };
 130
 131 /*
 132  * TODO: currently only preview is supported and snapshot (capture)
 133  * is not implemented yet
 134  */
 135 static const struct s5k4ecgx_frmsize s5k4ecgx_prev_sizes[] = {
 136         {
 137                 .size = { 176, 144 },
 138                 .input_window = { 0x00, 0x00, 0x928, 0x780 },
 139         }, {
 140                 .size = { 352, 288 },
 141                 .input_window = { 0x00, 0x00, 0x928, 0x780 },
 142         }, {
 143                 .size = { 640, 480 },
 144                 .input_window = { 0x00, 0x00, 0xa00, 0x780 },
 145         }, {
 146                 .size = { 720, 480 },
 147                 .input_window = { 0x00, 0x00, 0xa00, 0x6a8 },
 148         }
 149 };
 150
 151 #define S5K4ECGX_NUM_PREV ARRAY_SIZE(s5k4ecgx_prev_sizes)
 152
 153 struct s5k4ecgx_pixfmt {
 154         enum v4l2_mbus_pixelcode code;
 155         u32 colorspace;
 156         /* REG_TC_PCFG_Format register value */
 157         u16 reg_p_format;
 158 };
 159
 160 /* By default value, output from sensor will be YUV422 0-255 */
 161 static const struct s5k4ecgx_pixfmt s5k4ecgx_formats[] = {
 162         { V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG, 5 },
 163 };
 164
 165 static const char * const s5k4ecgx_supply_names[] = {
 166         /*
 167          * Usually 2.8V is used for analog power (vdda)
 168          * and digital IO (vddio, vdddcore)
 169          */
 170         "vdda",
 171         "vddio",
 172         "vddcore",
 173         "vddreg", /* The internal s5k4ecgx regulator's supply (1.8V) */
 174 };
 175
 176 #define S5K4ECGX_NUM_SUPPLIES ARRAY_SIZE(s5k4ecgx_supply_names)
 177
 178 enum s5k4ecgx_gpio_id {
 179         STBY,
 180         RST,
 181         GPIO_NUM,
 182 };
 183
 184 struct s5k4ecgx {
 185         struct v4l2_subdev sd;
 186         struct media_pad pad;
 187         struct v4l2_ctrl_handler handler;
 188
 189         struct s5k4ecgx_platform_data *pdata;
 190         const struct s5k4ecgx_pixfmt *curr_pixfmt;
 191         const struct s5k4ecgx_frmsize *curr_frmsize;
 192         struct mutex lock;
 193         u8 streaming;
 194         u8 set_params;
 195
 196         struct regulator_bulk_data supplies[S5K4ECGX_NUM_SUPPLIES];
 197         struct s5k4ecgx_gpio gpio[GPIO_NUM];
 198 };
 199
 200 static inline struct s5k4ecgx *to_s5k4ecgx(struct v4l2_subdev *sd)
 201 {
 202         return container_of(sd, struct s5k4ecgx, sd);
 203 }
 204
 205 static int s5k4ecgx_i2c_read(struct i2c_client *client, u16 addr, u16 *val)
 206 {
 207         u8 wbuf[2] = { addr >> 8, addr & 0xff };
 208         struct i2c_msg msg[2];
 209         u8 rbuf[2];
 210         int ret;
 211
 212         msg[0].addr = client->addr;
 213         msg[0].flags = 0;
 214         msg[0].len = 2;
 215         msg[0].buf = wbuf;
 216
 217         msg[1].addr = client->addr;
 218         msg[1].flags = I2C_M_RD;
 219         msg[1].len = 2;
 220         msg[1].buf = rbuf;
 221
 222         ret = i2c_transfer(client->adapter, msg, 2);
 223         *val = be16_to_cpu(*((u16 *)rbuf));
 224
 225         v4l2_dbg(4, debug, client, "i2c_read: 0x%04X : 0x%04x\n", addr, *val);
 226
 227         return ret == 2 ? 0 : ret;
 228 }
 229
 230 static int s5k4ecgx_i2c_write(struct i2c_client *client, u16 addr, u16 val)
 231 {
 232         u8 buf[4] = { addr >> 8, addr & 0xff, val >> 8, val & 0xff };
 233
 234         int ret = i2c_master_send(client, buf, 4);
 235         v4l2_dbg(4, debug, client, "i2c_write: 0x%04x : 0x%04x\n", addr, val);
 236
 237         return ret == 4 ? 0 : ret;
 238 }
 239
 240 static int s5k4ecgx_write(struct i2c_client *client, u32 addr, u16 val)
 241 {
 242         u16 high = addr >> 16, low = addr & 0xffff;
 243         int ret;
 244
 245         v4l2_dbg(3, debug, client, "write: 0x%08x : 0x%04x\n", addr, val);
 246
 247         ret = s5k4ecgx_i2c_write(client, REG_CMDWR_ADDRH, high);
 248         if (!ret)
 249                 ret = s5k4ecgx_i2c_write(client, REG_CMDWR_ADDRL, low);
 250         if (!ret)
 251                 ret = s5k4ecgx_i2c_write(client, REG_CMDBUF0_ADDR, val);
 252
 253         return ret;
 254 }
 255
 256 static int s5k4ecgx_read(struct i2c_client *client, u32 addr, u16 *val)
 257 {
 258         u16 high = addr >> 16, low =  addr & 0xffff;
 259         int ret;
 260
 261         ret = s5k4ecgx_i2c_write(client, REG_CMDRD_ADDRH, high);
 262         if (!ret)
 263                 ret = s5k4ecgx_i2c_write(client, REG_CMDRD_ADDRL, low);
 264         if (!ret)
 265                 ret = s5k4ecgx_i2c_read(client, REG_CMDBUF0_ADDR, val);
 266         if (!ret)
 267                 dev_err(&client->dev, "Failed to execute read command\n");
 268
 269         return ret;
 270 }
 271
 272 static int s5k4ecgx_read_fw_ver(struct v4l2_subdev *sd)
 273 {
 274         struct i2c_client *client = v4l2_get_subdevdata(sd);
 275         u16 hw_rev, fw_ver = 0;
 276         int ret;
 277
 278         ret = s5k4ecgx_read(client, REG_FW_VERSION, &fw_ver);
 279         if (ret < 0 || fw_ver != S5K4ECGX_FW_VERSION) {
 280                 v4l2_err(sd, "FW version check failed!\n");
 281                 return -ENODEV;
 282         }
 283
 284         ret = s5k4ecgx_read(client, REG_FW_REVISION, &hw_rev);
 285         if (ret < 0)
 286                 return ret;
 287
 288         v4l2_info(sd, "chip found FW ver: 0x%x, HW rev: 0x%x\n",
 289                                                 fw_ver, hw_rev);
 290         return 0;
 291 }
 292
 293 static int s5k4ecgx_set_ahb_address(struct v4l2_subdev *sd)
 294 {
 295         struct i2c_client *client = v4l2_get_subdevdata(sd);
 296         int ret;
 297
 298         /* Set APB peripherals start address */
 299         ret = s5k4ecgx_i2c_write(client, AHB_MSB_ADDR_PTR, GEN_REG_OFFSH);
 300         if (ret < 0)
 301                 return ret;
 302         /*
 303          * FIXME: This is copied from s5k6aa, because of no information
 304          * in s5k4ecgx's datasheet.
 305          * sw_reset is activated to put device into idle status
 306          */
 307         ret = s5k4ecgx_i2c_write(client, 0x0010, 0x0001);
 308         if (ret < 0)
 309                 return ret;
 310
 311         ret = s5k4ecgx_i2c_write(client, 0x1030, 0x0000);
 312         if (ret < 0)
 313                 return ret;
 314         /* Halt ARM CPU */
 315         return s5k4ecgx_i2c_write(client, 0x0014, 0x0001);
 316 }
 317
 318 #define FW_CRC_SIZE     4
 319 /* Register address, value are 4, 2 bytes */
 320 #define FW_RECORD_SIZE  6
 321 /*
 322  * The firmware has following format:
 323  * < total number of records (4 bytes + 2 bytes padding) N >,
 324  * < record 0 >, ..., < record N - 1 >, < CRC32-CCITT (4-bytes) >,
 325  * where "record" is a 4-byte register address followed by 2-byte
 326  * register value (little endian).
 327  * The firmware generator can be found in following git repository:
 328  * git://git.linaro.org/people/sangwook/fimc-v4l2-app.git
 329  */
 330 static int s5k4ecgx_load_firmware(struct v4l2_subdev *sd)
 331 {
 332         struct i2c_client *client = v4l2_get_subdevdata(sd);
 333         const struct firmware *fw;
 334         const u8 *ptr;
 335         int err, i, regs_num;
 336         u32 addr, crc, crc_file, addr_inc = 0;
 337         u16 val;
 338
 339         err = request_firmware(&fw, S5K4ECGX_FIRMWARE, sd->v4l2_dev->dev);
 340         if (err) {
 341                 v4l2_err(sd, "Failed to read firmware %s\n", S5K4ECGX_FIRMWARE);
 342                 return err;
 343         }
 344         regs_num = le32_to_cpu(get_unaligned_le32(fw->data));
 345
 346         v4l2_dbg(3, debug, sd, "FW: %s size %zu register sets %d\n",
 347                  S5K4ECGX_FIRMWARE, fw->size, regs_num);
 348
 349         regs_num++; /* Add header */
 350         if (fw->size != regs_num * FW_RECORD_SIZE + FW_CRC_SIZE) {
 351                 err = -EINVAL;
 352                 goto fw_out;
 353         }
 354         crc_file = le32_to_cpu(get_unaligned_le32(fw->data +
 355                                                   regs_num * FW_RECORD_SIZE));
 356         crc = crc32_le(~0, fw->data, regs_num * FW_RECORD_SIZE);
 357         if (crc != crc_file) {
 358                 v4l2_err(sd, "FW: invalid crc (%#x:%#x)\n", crc, crc_file);
 359                 err = -EINVAL;
 360                 goto fw_out;
 361         }
 362         ptr = fw->data + FW_RECORD_SIZE;
 363         for (i = 1; i < regs_num; i++) {
 364                 addr = le32_to_cpu(get_unaligned_le32(ptr));
 365                 ptr += sizeof(u32);
 366                 val = le16_to_cpu(get_unaligned_le16(ptr));
 367                 ptr += sizeof(u16);
 368                 if (addr - addr_inc != 2)
 369                         err = s5k4ecgx_write(client, addr, val);
 370                 else
 371                         err = s5k4ecgx_i2c_write(client, REG_CMDBUF0_ADDR, val);
 372                 if (err)
 373                         break;
 374                 addr_inc = addr;
 375         }
 376 fw_out:
 377         release_firmware(fw);
 378         return err;
 379 }
 380
 381 /* Set preview and capture input window */
 382 static int s5k4ecgx_set_input_window(struct i2c_client *c,
 383                                      const struct v4l2_rect *r)
 384 {
 385         int ret;
 386
 387         ret = s5k4ecgx_write(c, REG_G_PREV_IN_WIDTH, r->width);
 388         if (!ret)
 389                 ret = s5k4ecgx_write(c, REG_G_PREV_IN_HEIGHT, r->height);
 390         if (!ret)
 391                 ret = s5k4ecgx_write(c, REG_G_PREV_IN_XOFFS, r->left);
 392         if (!ret)
 393                 ret = s5k4ecgx_write(c, REG_G_PREV_IN_YOFFS, r->top);
 394         if (!ret)
 395                 ret = s5k4ecgx_write(c, REG_G_CAP_IN_WIDTH, r->width);
 396         if (!ret)
 397                 ret = s5k4ecgx_write(c, REG_G_CAP_IN_HEIGHT, r->height);
 398         if (!ret)
 399                 ret = s5k4ecgx_write(c, REG_G_CAP_IN_XOFFS, r->left);
 400         if (!ret)
 401                 ret = s5k4ecgx_write(c, REG_G_CAP_IN_YOFFS, r->top);
 402
 403         return ret;
 404 }
 405
 406 /* Set preview and capture zoom input window */
 407 static int s5k4ecgx_set_zoom_window(struct i2c_client *c,
 408                                     const struct v4l2_rect *r)
 409 {
 410         int ret;
 411
 412         ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_WIDTH, r->width);
 413         if (!ret)
 414                 ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_HEIGHT, r->height);
 415         if (!ret)
 416                 ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_XOFFS, r->left);
 417         if (!ret)
 418                 ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_YOFFS, r->top);
 419         if (!ret)
 420                 ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_WIDTH, r->width);
 421         if (!ret)
 422                 ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_HEIGHT, r->height);
 423         if (!ret)
 424                 ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_XOFFS, r->left);
 425         if (!ret)
 426                 ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_YOFFS, r->top);
 427
 428         return ret;
 429 }
 430
 431 static int s5k4ecgx_set_output_framefmt(struct s5k4ecgx *priv)
 432 {
 433         struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
 434         int ret;
 435
 436         ret = s5k4ecgx_write(client, REG_P_OUT_WIDTH(0),
 437                              priv->curr_frmsize->size.width);
 438         if (!ret)
 439                 ret = s5k4ecgx_write(client, REG_P_OUT_HEIGHT(0),
 440                                      priv->curr_frmsize->size.height);
 441         if (!ret)
 442                 ret = s5k4ecgx_write(client, REG_P_FMT(0),
 443                                      priv->curr_pixfmt->reg_p_format);
 444         return ret;
 445 }
 446
 447 static int s5k4ecgx_init_sensor(struct v4l2_subdev *sd)
 448 {
 449         int ret;
 450
 451         ret = s5k4ecgx_set_ahb_address(sd);
 452
 453         /* The delay is from manufacturer's settings */
 454         msleep(100);
 455
 456         if (!ret)
 457                 ret = s5k4ecgx_load_firmware(sd);
 458         if (ret)
 459                 v4l2_err(sd, "Failed to write initial settings\n");
 460
 461         return ret;
 462 }
 463
 464 static int s5k4ecgx_gpio_set_value(struct s5k4ecgx *priv, int id, u32 val)
 465 {
 466         if (!gpio_is_valid(priv->gpio[id].gpio))
 467                 return 0;
 468         gpio_set_value(priv->gpio[id].gpio, val);
 469
 470         return 1;
 471 }
 472
 473 static int __s5k4ecgx_power_on(struct s5k4ecgx *priv)
 474 {
 475         int ret;
 476
 477         ret = regulator_bulk_enable(S5K4ECGX_NUM_SUPPLIES, priv->supplies);
 478         if (ret)
 479                 return ret;
 480         usleep_range(30, 50);
 481
 482         /* The polarity of STBY is controlled by TSP */
 483         if (s5k4ecgx_gpio_set_value(priv, STBY, priv->gpio[STBY].level))
 484                 usleep_range(30, 50);
 485
 486         if (s5k4ecgx_gpio_set_value(priv, RST, priv->gpio[RST].level))
 487                 usleep_range(30, 50);
 488
 489         return 0;
 490 }
 491
 492 static int __s5k4ecgx_power_off(struct s5k4ecgx *priv)
 493 {
 494         if (s5k4ecgx_gpio_set_value(priv, RST, !priv->gpio[RST].level))
 495                 usleep_range(30, 50);
 496
 497         if (s5k4ecgx_gpio_set_value(priv, STBY, !priv->gpio[STBY].level))
 498                 usleep_range(30, 50);
 499
 500         priv->streaming = 0;
 501
 502         return regulator_bulk_disable(S5K4ECGX_NUM_SUPPLIES, priv->supplies);
 503 }
 504
 505 /* Find nearest matching image pixel size. */
 506 static int s5k4ecgx_try_frame_size(struct v4l2_mbus_framefmt *mf,
 507                                   const struct s5k4ecgx_frmsize **size)
 508 {
 509         unsigned int min_err = ~0;
 510         int i = ARRAY_SIZE(s5k4ecgx_prev_sizes);
 511         const struct s5k4ecgx_frmsize *fsize = &s5k4ecgx_prev_sizes[0],
 512                 *match = NULL;
 513
 514         while (i--) {
 515                 int err = abs(fsize->size.width - mf->width)
 516                                 + abs(fsize->size.height - mf->height);
 517                 if (err < min_err) {
 518                         min_err = err;
 519                         match = fsize;
 520                 }
 521                 fsize++;
 522         }
 523         if (match) {
 524                 mf->width  = match->size.width;
 525                 mf->height = match->size.height;
 526                 if (size)
 527                         *size = match;
 528                 return 0;
 529         }
 530
 531         return -EINVAL;
 532 }
 533
 534 static int s5k4ecgx_enum_mbus_code(struct v4l2_subdev *sd,
 535                                    struct v4l2_subdev_fh *fh,
 536                                    struct v4l2_subdev_mbus_code_enum *code)
 537 {
 538         if (code->index >= ARRAY_SIZE(s5k4ecgx_formats))
 539                 return -EINVAL;
 540         code->code = s5k4ecgx_formats[code->index].code;
 541
 542         return 0;
 543 }
 544
 545 static int s5k4ecgx_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 546                            struct v4l2_subdev_format *fmt)
 547 {
 548         struct s5k4ecgx *priv = to_s5k4ecgx(sd);
 549         struct v4l2_mbus_framefmt *mf;
 550
 551         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
 552                 if (fh) {
 553                         mf = v4l2_subdev_get_try_format(fh, 0);
 554                         fmt->format = *mf;
 555                 }
 556                 return 0;
 557         }
 558
 559         mf = &fmt->format;
 560
 561         mutex_lock(&priv->lock);
 562         mf->width = priv->curr_frmsize->size.width;
 563         mf->height = priv->curr_frmsize->size.height;
 564         mf->code = priv->curr_pixfmt->code;
 565         mf->colorspace = priv->curr_pixfmt->colorspace;
 566         mf->field = V4L2_FIELD_NONE;
 567         mutex_unlock(&priv->lock);
 568
 569         return 0;
 570 }
 571
 572 static const struct s5k4ecgx_pixfmt *s5k4ecgx_try_fmt(struct v4l2_subdev *sd,
 573                                             struct v4l2_mbus_framefmt *mf)
 574 {
 575         int i = ARRAY_SIZE(s5k4ecgx_formats);
 576
 577         while (--i)
 578                 if (mf->code == s5k4ecgx_formats[i].code)
 579                         break;
 580         mf->code = s5k4ecgx_formats[i].code;
 581
 582         return &s5k4ecgx_formats[i];
 583 }
 584
 585 static int s5k4ecgx_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 586                             struct v4l2_subdev_format *fmt)
 587 {
 588         struct s5k4ecgx *priv = to_s5k4ecgx(sd);
 589         const struct s5k4ecgx_frmsize *fsize = NULL;
 590         const struct s5k4ecgx_pixfmt *pf;
 591         struct v4l2_mbus_framefmt *mf;
 592         int ret = 0;
 593
 594         pf = s5k4ecgx_try_fmt(sd, &fmt->format);
 595         s5k4ecgx_try_frame_size(&fmt->format, &fsize);
 596         fmt->format.colorspace = V4L2_COLORSPACE_JPEG;
 597         fmt->format.field = V4L2_FIELD_NONE;
 598
 599         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
 600                 if (fh) {
 601                         mf = v4l2_subdev_get_try_format(fh, 0);
 602                         *mf = fmt->format;
 603                 }
 604                 return 0;
 605         }
 606
 607         mutex_lock(&priv->lock);
 608         if (!priv->streaming) {
 609                 priv->curr_frmsize = fsize;
 610                 priv->curr_pixfmt = pf;
 611                 priv->set_params = 1;
 612         } else {
 613                 ret = -EBUSY;
 614         }
 615         mutex_unlock(&priv->lock);
 616
 617         return ret;
 618 }
 619
 620 static const struct v4l2_subdev_pad_ops s5k4ecgx_pad_ops = {
 621         .enum_mbus_code = s5k4ecgx_enum_mbus_code,
 622         .get_fmt        = s5k4ecgx_get_fmt,
 623         .set_fmt        = s5k4ecgx_set_fmt,
 624 };
 625
 626 /*
 627  * V4L2 subdev controls
 628  */
 629 static int s5k4ecgx_s_ctrl(struct v4l2_ctrl *ctrl)
 630 {
 631         struct v4l2_subdev *sd = &container_of(ctrl->handler, struct s5k4ecgx,
 632                                                 handler)->sd;
 633         struct i2c_client *client = v4l2_get_subdevdata(sd);
 634         struct s5k4ecgx *priv = to_s5k4ecgx(sd);
 635         unsigned int i;
 636         int err = 0;
 637
 638         v4l2_dbg(1, debug, sd, "ctrl: 0x%x, value: %d\n", ctrl->id, ctrl->val);
 639
 640         mutex_lock(&priv->lock);
 641         switch (ctrl->id) {
 642         case V4L2_CID_CONTRAST:
 643                 err = s5k4ecgx_write(client, REG_USER_CONTRAST, ctrl->val);
 644                 break;
 645
 646         case V4L2_CID_SATURATION:
 647                 err = s5k4ecgx_write(client, REG_USER_SATURATION, ctrl->val);
 648                 break;
 649
 650         case V4L2_CID_SHARPNESS:
 651                 /* TODO: Revisit, is this setting for all presets ? */
 652                 for (i = 0; i < 4 && !err; i++)
 653                         err = s5k4ecgx_write(client, REG_USER_SHARPNESS(i),
 654                                              ctrl->val * SHARPNESS_DIV);
 655                 break;
 656
 657         case V4L2_CID_BRIGHTNESS:
 658                 err = s5k4ecgx_write(client, REG_USER_BRIGHTNESS, ctrl->val);
 659                 break;
 660         }
 661         mutex_unlock(&priv->lock);
 662         if (err < 0)
 663                 v4l2_err(sd, "Failed to write s_ctrl err %d\n", err);
 664
 665         return err;
 666 }
 667
 668 static const struct v4l2_ctrl_ops s5k4ecgx_ctrl_ops = {
 669         .s_ctrl = s5k4ecgx_s_ctrl,
 670 };
 671
 672 /*
 673  * Reading s5k4ecgx version information
 674  */
 675 static int s5k4ecgx_registered(struct v4l2_subdev *sd)
 676 {
 677         int ret;
 678         struct s5k4ecgx *priv = to_s5k4ecgx(sd);
 679
 680         mutex_lock(&priv->lock);
 681         ret = __s5k4ecgx_power_on(priv);
 682         if (!ret) {
 683                 ret = s5k4ecgx_read_fw_ver(sd);
 684                 __s5k4ecgx_power_off(priv);
 685         }
 686         mutex_unlock(&priv->lock);
 687
 688         return ret;
 689 }
 690
 691 /*
 692  * V4L2 subdev internal operations
 693  */
 694 static int s5k4ecgx_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
 695 {
 696         struct v4l2_mbus_framefmt *mf = v4l2_subdev_get_try_format(fh, 0);
 697
 698         mf->width = s5k4ecgx_prev_sizes[0].size.width;
 699         mf->height = s5k4ecgx_prev_sizes[0].size.height;
 700         mf->code = s5k4ecgx_formats[0].code;
 701         mf->colorspace = V4L2_COLORSPACE_JPEG;
 702         mf->field = V4L2_FIELD_NONE;
 703
 704         return 0;
 705 }
 706
 707 static const struct v4l2_subdev_internal_ops s5k4ecgx_subdev_internal_ops = {
 708         .registered = s5k4ecgx_registered,
 709         .open = s5k4ecgx_open,
 710 };
 711
 712 static int s5k4ecgx_s_power(struct v4l2_subdev *sd, int on)
 713 {
 714         struct s5k4ecgx *priv = to_s5k4ecgx(sd);
 715         int ret;
 716
 717         v4l2_dbg(1, debug, sd, "Switching %s\n", on ? "on" : "off");
 718
 719         if (on) {
 720                 ret = __s5k4ecgx_power_on(priv);
 721                 if (ret < 0)
 722                         return ret;
 723                 /* Time to stabilize sensor */
 724                 msleep(100);
 725                 ret = s5k4ecgx_init_sensor(sd);
 726                 if (ret < 0)
 727                         __s5k4ecgx_power_off(priv);
 728                 else
 729                         priv->set_params = 1;
 730         } else {
 731                 ret = __s5k4ecgx_power_off(priv);
 732         }
 733
 734         return ret;
 735 }
 736
 737 static int s5k4ecgx_log_status(struct v4l2_subdev *sd)
 738 {
 739         v4l2_ctrl_handler_log_status(sd->ctrl_handler, sd->name);
 740
 741         return 0;
 742 }
 743
 744 static const struct v4l2_subdev_core_ops s5k4ecgx_core_ops = {
 745         .s_power        = s5k4ecgx_s_power,
 746         .log_status     = s5k4ecgx_log_status,
 747 };
 748
 749 static int __s5k4ecgx_s_params(struct s5k4ecgx *priv)
 750 {
 751         struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
 752         const struct v4l2_rect *crop_rect = &priv->curr_frmsize->input_window;
 753         int ret;
 754
 755         ret = s5k4ecgx_set_input_window(client, crop_rect);
 756         if (!ret)
 757                 ret = s5k4ecgx_set_zoom_window(client, crop_rect);
 758         if (!ret)
 759                 ret = s5k4ecgx_write(client, REG_G_INPUTS_CHANGE_REQ, 1);
 760         if (!ret)
 761                 ret = s5k4ecgx_write(client, 0x70000a1e, 0x28);
 762         if (!ret)
 763                 ret = s5k4ecgx_write(client, 0x70000ad4, 0x3c);
 764         if (!ret)
 765                 ret = s5k4ecgx_set_output_framefmt(priv);
 766         if (!ret)
 767                 ret = s5k4ecgx_write(client, REG_P_PVI_MASK(0), 0x52);
 768         if (!ret)
 769                 ret = s5k4ecgx_write(client, REG_P_FR_TIME_TYPE(0),
 770                                      FR_TIME_DYNAMIC);
 771         if (!ret)
 772                 ret = s5k4ecgx_write(client, REG_P_FR_TIME_Q_TYPE(0),
 773                                      FR_TIME_Q_BEST_FRRATE);
 774         if (!ret)
 775                 ret = s5k4ecgx_write(client,  REG_P_MIN_FR_TIME(0),
 776                                      US_TO_FR_TIME(33300));
 777         if (!ret)
 778                 ret = s5k4ecgx_write(client, REG_P_MAX_FR_TIME(0),
 779                                      US_TO_FR_TIME(66600));
 780         if (!ret)
 781                 ret = s5k4ecgx_write(client, REG_P_PREV_MIRROR(0), 0);
 782         if (!ret)
 783                 ret = s5k4ecgx_write(client, REG_P_CAP_MIRROR(0), 0);
 784         if (!ret)
 785                 ret = s5k4ecgx_write(client, REG_G_ACTIVE_PREV_CFG, 0);
 786         if (!ret)
 787                 ret = s5k4ecgx_write(client, REG_G_PREV_OPEN_AFTER_CH, 1);
 788         if (!ret)
 789                 ret = s5k4ecgx_write(client, REG_G_NEW_CFG_SYNC, 1);
 790         if (!ret)
 791                 ret = s5k4ecgx_write(client, REG_G_PREV_CFG_CHG, 1);
 792
 793         return ret;
 794 }
 795
 796 static int __s5k4ecgx_s_stream(struct s5k4ecgx *priv, int on)
 797 {
 798         struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
 799         int ret;
 800
 801         if (on && priv->set_params) {
 802                 ret = __s5k4ecgx_s_params(priv);
 803                 if (ret < 0)
 804                         return ret;
 805                 priv->set_params = 0;
 806         }
 807         /*
 808          * This enables/disables preview stream only. Capture requests
 809          * are not supported yet.
 810          */
 811         ret = s5k4ecgx_write(client, REG_G_ENABLE_PREV, on);
 812         if (ret < 0)
 813                 return ret;
 814         return s5k4ecgx_write(client, REG_G_ENABLE_PREV_CHG, 1);
 815 }
 816
 817 static int s5k4ecgx_s_stream(struct v4l2_subdev *sd, int on)
 818 {
 819         struct s5k4ecgx *priv = to_s5k4ecgx(sd);
 820         int ret = 0;
 821
 822         v4l2_dbg(1, debug, sd, "Turn streaming %s\n", on ? "on" : "off");
 823
 824         mutex_lock(&priv->lock);
 825
 826         if (priv->streaming == !on) {
 827                 ret = __s5k4ecgx_s_stream(priv, on);
 828                 if (!ret)
 829                         priv->streaming = on & 1;
 830         }
 831
 832         mutex_unlock(&priv->lock);
 833         return ret;
 834 }
 835
 836 static const struct v4l2_subdev_video_ops s5k4ecgx_video_ops = {
 837         .s_stream = s5k4ecgx_s_stream,
 838 };
 839
 840 static const struct v4l2_subdev_ops s5k4ecgx_ops = {
 841         .core = &s5k4ecgx_core_ops,
 842         .pad = &s5k4ecgx_pad_ops,
 843         .video = &s5k4ecgx_video_ops,
 844 };
 845
 846 /*
 847  * GPIO setup
 848  */
 849 static int s5k4ecgx_config_gpio(int nr, int val, const char *name)
 850 {
 851         unsigned long flags = val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
 852         int ret;
 853
 854         if (!gpio_is_valid(nr))
 855                 return 0;
 856         ret = gpio_request_one(nr, flags, name);
 857         if (!ret)
 858                 gpio_export(nr, 0);
 859
 860         return ret;
 861 }
 862
 863 static void s5k4ecgx_free_gpios(struct s5k4ecgx *priv)
 864 {
 865         int i;
 866
 867         for (i = 0; i < ARRAY_SIZE(priv->gpio); i++) {
 868                 if (!gpio_is_valid(priv->gpio[i].gpio))
 869                         continue;
 870                 gpio_free(priv->gpio[i].gpio);
 871                 priv->gpio[i].gpio = -EINVAL;
 872         }
 873 }
 874
 875 static int s5k4ecgx_config_gpios(struct s5k4ecgx *priv,
 876                                   const struct s5k4ecgx_platform_data *pdata)
 877 {
 878         const struct s5k4ecgx_gpio *gpio = &pdata->gpio_stby;
 879         int ret;
 880
 881         priv->gpio[STBY].gpio = -EINVAL;
 882         priv->gpio[RST].gpio  = -EINVAL;
 883
 884         ret = s5k4ecgx_config_gpio(gpio->gpio, gpio->level, "S5K4ECGX_STBY");
 885
 886         if (ret) {
 887                 s5k4ecgx_free_gpios(priv);
 888                 return ret;
 889         }
 890         priv->gpio[STBY] = *gpio;
 891         if (gpio_is_valid(gpio->gpio))
 892                 gpio_set_value(gpio->gpio, 0);
 893
 894         gpio = &pdata->gpio_reset;
 895
 896         ret = s5k4ecgx_config_gpio(gpio->gpio, gpio->level, "S5K4ECGX_RST");
 897         if (ret) {
 898                 s5k4ecgx_free_gpios(priv);
 899                 return ret;
 900         }
 901         priv->gpio[RST] = *gpio;
 902         if (gpio_is_valid(gpio->gpio))
 903                 gpio_set_value(gpio->gpio, 0);
 904
 905         return 0;
 906 }
 907
 908 static int s5k4ecgx_init_v4l2_ctrls(struct s5k4ecgx *priv)
 909 {
 910         const struct v4l2_ctrl_ops *ops = &s5k4ecgx_ctrl_ops;
 911         struct v4l2_ctrl_handler *hdl = &priv->handler;
 912         int ret;
 913
 914         ret = v4l2_ctrl_handler_init(hdl, 4);
 915         if (ret)
 916                 return ret;
 917
 918         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -208, 127, 1, 0);
 919         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -127, 127, 1, 0);
 920         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -127, 127, 1, 0);
 921
 922         /* Sharpness default is 24612, and then (24612/SHARPNESS_DIV) = 2 */
 923         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, -32704/SHARPNESS_DIV,
 924                           24612/SHARPNESS_DIV, 1, 2);
 925         if (hdl->error) {
 926                 ret = hdl->error;
 927                 v4l2_ctrl_handler_free(hdl);
 928                 return ret;
 929         }
 930         priv->sd.ctrl_handler = hdl;
 931
 932         return 0;
 933 };
 934
 935 static int s5k4ecgx_probe(struct i2c_client *client,
 936                           const struct i2c_device_id *id)
 937 {
 938         struct s5k4ecgx_platform_data *pdata = client->dev.platform_data;
 939         struct v4l2_subdev *sd;
 940         struct s5k4ecgx *priv;
 941         int ret, i;
 942
 943         if (pdata == NULL) {
 944                 dev_err(&client->dev, "platform data is missing!\n");
 945                 return -EINVAL;
 946         }
 947
 948         priv = devm_kzalloc(&client->dev, sizeof(struct s5k4ecgx), GFP_KERNEL);
 949         if (!priv)
 950                 return -ENOMEM;
 951
 952         mutex_init(&priv->lock);
 953         priv->streaming = 0;
 954
 955         sd = &priv->sd;
 956         /* Registering subdev */
 957         v4l2_i2c_subdev_init(sd, client, &s5k4ecgx_ops);
 958         strlcpy(sd->name, S5K4ECGX_DRIVER_NAME, sizeof(sd->name));
 959
 960         sd->internal_ops = &s5k4ecgx_subdev_internal_ops;
 961         /* Support v4l2 sub-device user space API */
 962         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
 963
 964         priv->pad.flags = MEDIA_PAD_FL_SOURCE;
 965         sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
 966         ret = media_entity_init(&sd->entity, 1, &priv->pad, 0);
 967         if (ret)
 968                 return ret;
 969
 970         ret = s5k4ecgx_config_gpios(priv, pdata);
 971         if (ret) {
 972                 dev_err(&client->dev, "Failed to set gpios\n");
 973                 goto out_err1;
 974         }
 975         for (i = 0; i < S5K4ECGX_NUM_SUPPLIES; i++)
 976                 priv->supplies[i].supply = s5k4ecgx_supply_names[i];
 977
 978         ret = devm_regulator_bulk_get(&client->dev, S5K4ECGX_NUM_SUPPLIES,
 979                                  priv->supplies);
 980         if (ret) {
 981                 dev_err(&client->dev, "Failed to get regulators\n");
 982                 goto out_err2;
 983         }
 984         ret = s5k4ecgx_init_v4l2_ctrls(priv);
 985         if (ret)
 986                 goto out_err2;
 987
 988         priv->curr_pixfmt = &s5k4ecgx_formats[0];
 989         priv->curr_frmsize = &s5k4ecgx_prev_sizes[0];
 990
 991         return 0;
 992
 993 out_err2:
 994         s5k4ecgx_free_gpios(priv);
 995 out_err1:
 996         media_entity_cleanup(&priv->sd.entity);
 997
 998         return ret;
 999 }
1000
1001 static int s5k4ecgx_remove(struct i2c_client *client)
1002 {
1003         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1004         struct s5k4ecgx *priv = to_s5k4ecgx(sd);
1005
1006         mutex_destroy(&priv->lock);
1007         s5k4ecgx_free_gpios(priv);
1008         v4l2_device_unregister_subdev(sd);
1009         v4l2_ctrl_handler_free(&priv->handler);
1010         media_entity_cleanup(&sd->entity);
1011
1012         return 0;
1013 }
1014
1015 static const struct i2c_device_id s5k4ecgx_id[] = {
1016         { S5K4ECGX_DRIVER_NAME, 0 },
1017         {}
1018 };
1019 MODULE_DEVICE_TABLE(i2c, s5k4ecgx_id);
1020
1021 static struct i2c_driver v4l2_i2c_driver = {
1022         .driver = {
1023                 .owner  = THIS_MODULE,
1024                 .name = S5K4ECGX_DRIVER_NAME,
1025         },
1026         .probe = s5k4ecgx_probe,
1027         .remove = s5k4ecgx_remove,
1028         .id_table = s5k4ecgx_id,
1029 };
1030
1031 module_i2c_driver(v4l2_i2c_driver);
1032
1033 MODULE_DESCRIPTION("Samsung S5K4ECGX 5MP SOC camera");
1034 MODULE_AUTHOR("Sangwook Lee <sangwook.lee@linaro.org>");
1035 MODULE_AUTHOR("Seok-Young Jang <quartz.jang@samsung.com>");
1036 MODULE_LICENSE("GPL");
1037 MODULE_FIRMWARE(S5K4ECGX_FIRMWARE);