drivers/media/i2c/saa7115.c

   1 /* saa711x - Philips SAA711x video decoder driver
   2  * This driver can work with saa7111, saa7111a, saa7113, saa7114,
   3  *                           saa7115 and saa7118.
   4  *
   5  * Based on saa7114 driver by Maxim Yevtyushkin, which is based on
   6  * the saa7111 driver by Dave Perks.
   7  *
   8  * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
   9  * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com>
  10  *
  11  * Slight changes for video timing and attachment output by
  12  * Wolfgang Scherr <scherr@net4you.net>
  13  *
  14  * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003)
  15  * by Ronald Bultje <rbultje@ronald.bitfreak.net>
  16  *
  17  * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com>
  18  * (2/17/2003)
  19  *
  20  * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl>
  21  *
  22  * Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
  23  *      SAA7111, SAA7113 and SAA7118 support
  24  *
  25  * This program is free software; you can redistribute it and/or
  26  * modify it under the terms of the GNU General Public License
  27  * as published by the Free Software Foundation; either version 2
  28  * of the License, or (at your option) any later version.
  29  *
  30  * This program is distributed in the hope that it will be useful,
  31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  33  * GNU General Public License for more details.
  34  *
  35  * You should have received a copy of the GNU General Public License
  36  * along with this program; if not, write to the Free Software
  37  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  38  */
  39
  40 #include "saa711x_regs.h"
  41
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/slab.h>
  45 #include <linux/i2c.h>
  46 #include <linux/videodev2.h>
  47 #include <media/v4l2-device.h>
  48 #include <media/v4l2-ctrls.h>
  49 #include <media/saa7115.h>
  50 #include <asm/div64.h>
  51
  52 #define VRES_60HZ       (480+16)
  53
  54 MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver");
  55 MODULE_AUTHOR(  "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
  56                 "Hans Verkuil, Mauro Carvalho Chehab");
  57 MODULE_LICENSE("GPL");
  58
  59 static bool debug;
  60 module_param(debug, bool, 0644);
  61
  62 MODULE_PARM_DESC(debug, "Debug level (0-1)");
  63
  64
  65 enum saa711x_model {
  66         SAA7111A,
  67         SAA7111,
  68         SAA7113,
  69         GM7113C,
  70         SAA7114,
  71         SAA7115,
  72         SAA7118,
  73 };
  74
  75 struct saa711x_state {
  76         struct v4l2_subdev sd;
  77         struct v4l2_ctrl_handler hdl;
  78
  79         struct {
  80                 /* chroma gain control cluster */
  81                 struct v4l2_ctrl *agc;
  82                 struct v4l2_ctrl *gain;
  83         };
  84
  85         v4l2_std_id std;
  86         int input;
  87         int output;
  88         int enable;
  89         int radio;
  90         int width;
  91         int height;
  92         enum saa711x_model ident;
  93         u32 audclk_freq;
  94         u32 crystal_freq;
  95         bool ucgc;
  96         u8 cgcdiv;
  97         bool apll;
  98         bool double_asclk;
  99 };
 100
 101 static inline struct saa711x_state *to_state(struct v4l2_subdev *sd)
 102 {
 103         return container_of(sd, struct saa711x_state, sd);
 104 }
 105
 106 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 107 {
 108         return &container_of(ctrl->handler, struct saa711x_state, hdl)->sd;
 109 }
 110
 111 /* ----------------------------------------------------------------------- */
 112
 113 static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value)
 114 {
 115         struct i2c_client *client = v4l2_get_subdevdata(sd);
 116
 117         return i2c_smbus_write_byte_data(client, reg, value);
 118 }
 119
 120 /* Sanity routine to check if a register is present */
 121 static int saa711x_has_reg(const int id, const u8 reg)
 122 {
 123         if (id == SAA7111)
 124                 return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
 125                        (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e;
 126         if (id == SAA7111A)
 127                 return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
 128                        reg != 0x14 && reg != 0x18 && reg != 0x19 &&
 129                        reg != 0x1d && reg != 0x1e;
 130
 131         /* common for saa7113/4/5/8 */
 132         if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f ||
 133             reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) ||
 134             reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) ||
 135             reg == 0x82 || (reg >= 0x89 && reg <= 0x8e)))
 136                 return 0;
 137
 138         switch (id) {
 139         case GM7113C:
 140                 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && reg < 0x20;
 141         case SAA7113:
 142                 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) &&
 143                        reg != 0x5d && reg < 0x63;
 144         case SAA7114:
 145                 return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) &&
 146                        (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 &&
 147                        reg != 0x81 && reg < 0xf0;
 148         case SAA7115:
 149                 return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe);
 150         case SAA7118:
 151                 return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) &&
 152                        (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 &&
 153                        (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0;
 154         }
 155         return 1;
 156 }
 157
 158 static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs)
 159 {
 160         struct saa711x_state *state = to_state(sd);
 161         unsigned char reg, data;
 162
 163         while (*regs != 0x00) {
 164                 reg = *(regs++);
 165                 data = *(regs++);
 166
 167                 /* According with datasheets, reserved regs should be
 168                    filled with 0 - seems better not to touch on they */
 169                 if (saa711x_has_reg(state->ident, reg)) {
 170                         if (saa711x_write(sd, reg, data) < 0)
 171                                 return -1;
 172                 } else {
 173                         v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg);
 174                 }
 175         }
 176         return 0;
 177 }
 178
 179 static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg)
 180 {
 181         struct i2c_client *client = v4l2_get_subdevdata(sd);
 182
 183         return i2c_smbus_read_byte_data(client, reg);
 184 }
 185
 186 /* ----------------------------------------------------------------------- */
 187
 188 /* SAA7111 initialization table */
 189 static const unsigned char saa7111_init[] = {
 190         R_01_INC_DELAY, 0x00,           /* reserved */
 191
 192         /*front end */
 193         R_02_INPUT_CNTL_1, 0xd0,        /* FUSE=3, GUDL=2, MODE=0 */
 194         R_03_INPUT_CNTL_2, 0x23,        /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0,
 195                                          * GAFIX=0, GAI1=256, GAI2=256 */
 196         R_04_INPUT_CNTL_3, 0x00,        /* GAI1=256 */
 197         R_05_INPUT_CNTL_4, 0x00,        /* GAI2=256 */
 198
 199         /* decoder */
 200         R_06_H_SYNC_START, 0xf3,        /* HSB at  13(50Hz) /  17(60Hz)
 201                                          * pixels after end of last line */
 202         R_07_H_SYNC_STOP, 0xe8,         /* HSS seems to be needed to
 203                                          * work with NTSC, too */
 204         R_08_SYNC_CNTL, 0xc8,           /* AUFD=1, FSEL=1, EXFIL=0,
 205                                          * VTRC=1, HPLL=0, VNOI=0 */
 206         R_09_LUMA_CNTL, 0x01,           /* BYPS=0, PREF=0, BPSS=0,
 207                                          * VBLB=0, UPTCV=0, APER=1 */
 208         R_0A_LUMA_BRIGHT_CNTL, 0x80,
 209         R_0B_LUMA_CONTRAST_CNTL, 0x47,  /* 0b - CONT=1.109 */
 210         R_0C_CHROMA_SAT_CNTL, 0x40,
 211         R_0D_CHROMA_HUE_CNTL, 0x00,
 212         R_0E_CHROMA_CNTL_1, 0x01,       /* 0e - CDTO=0, CSTD=0, DCCF=0,
 213                                          * FCTC=0, CHBW=1 */
 214         R_0F_CHROMA_GAIN_CNTL, 0x00,    /* reserved */
 215         R_10_CHROMA_CNTL_2, 0x48,       /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */
 216         R_11_MODE_DELAY_CNTL, 0x1c,     /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1,
 217                                          * OEYC=1, OEHV=1, VIPB=0, COLO=0 */
 218         R_12_RT_SIGNAL_CNTL, 0x00,      /* 12 - output control 2 */
 219         R_13_RT_X_PORT_OUT_CNTL, 0x00,  /* 13 - output control 3 */
 220         R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
 221         R_15_VGATE_START_FID_CHG, 0x00,
 222         R_16_VGATE_STOP, 0x00,
 223         R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
 224
 225         0x00, 0x00
 226 };
 227
 228 /* This table has one illegal value, and some values that are not
 229    correct according to the datasheet initialization table.
 230
 231    If you need a table with legal/default values tell the driver in
 232    i2c_board_info.platform_data, and you will get the gm7113c_init
 233    table instead. */
 234
 235 /* SAA7113 Init codes */
 236 static const unsigned char saa7113_init[] = {
 237         R_01_INC_DELAY, 0x08,
 238         R_02_INPUT_CNTL_1, 0xc2,
 239         R_03_INPUT_CNTL_2, 0x30,
 240         R_04_INPUT_CNTL_3, 0x00,
 241         R_05_INPUT_CNTL_4, 0x00,
 242         R_06_H_SYNC_START, 0x89,        /* Illegal value -119,
 243                                          * min. value = -108 (0x94) */
 244         R_07_H_SYNC_STOP, 0x0d,
 245         R_08_SYNC_CNTL, 0x88,           /* Not datasheet default.
 246                                          * HTC = VTR mode, should be 0x98 */
 247         R_09_LUMA_CNTL, 0x01,
 248         R_0A_LUMA_BRIGHT_CNTL, 0x80,
 249         R_0B_LUMA_CONTRAST_CNTL, 0x47,
 250         R_0C_CHROMA_SAT_CNTL, 0x40,
 251         R_0D_CHROMA_HUE_CNTL, 0x00,
 252         R_0E_CHROMA_CNTL_1, 0x01,
 253         R_0F_CHROMA_GAIN_CNTL, 0x2a,
 254         R_10_CHROMA_CNTL_2, 0x08,       /* Not datsheet default.
 255                                          * VRLN enabled, should be 0x00 */
 256         R_11_MODE_DELAY_CNTL, 0x0c,
 257         R_12_RT_SIGNAL_CNTL, 0x07,      /* Not datasheet default,
 258                                          * should be 0x01 */
 259         R_13_RT_X_PORT_OUT_CNTL, 0x00,
 260         R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
 261         R_15_VGATE_START_FID_CHG, 0x00,
 262         R_16_VGATE_STOP, 0x00,
 263         R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
 264
 265         0x00, 0x00
 266 };
 267
 268 /* GM7113C is a clone of the SAA7113 chip
 269    This init table is copied out of the saa7113 datasheet.
 270    In R_08 we enable "Automatic Field Detection" [AUFD],
 271    this is disabled when saa711x_set_v4lstd is called. */
 272 static const unsigned char gm7113c_init[] = {
 273         R_01_INC_DELAY, 0x08,
 274         R_02_INPUT_CNTL_1, 0xc0,
 275         R_03_INPUT_CNTL_2, 0x33,
 276         R_04_INPUT_CNTL_3, 0x00,
 277         R_05_INPUT_CNTL_4, 0x00,
 278         R_06_H_SYNC_START, 0xe9,
 279         R_07_H_SYNC_STOP, 0x0d,
 280         R_08_SYNC_CNTL, 0x98,
 281         R_09_LUMA_CNTL, 0x01,
 282         R_0A_LUMA_BRIGHT_CNTL, 0x80,
 283         R_0B_LUMA_CONTRAST_CNTL, 0x47,
 284         R_0C_CHROMA_SAT_CNTL, 0x40,
 285         R_0D_CHROMA_HUE_CNTL, 0x00,
 286         R_0E_CHROMA_CNTL_1, 0x01,
 287         R_0F_CHROMA_GAIN_CNTL, 0x2a,
 288         R_10_CHROMA_CNTL_2, 0x00,
 289         R_11_MODE_DELAY_CNTL, 0x0c,
 290         R_12_RT_SIGNAL_CNTL, 0x01,
 291         R_13_RT_X_PORT_OUT_CNTL, 0x00,
 292         R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
 293         R_15_VGATE_START_FID_CHG, 0x00,
 294         R_16_VGATE_STOP, 0x00,
 295         R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
 296
 297         0x00, 0x00
 298 };
 299
 300 /* If a value differs from the Hauppauge driver values, then the comment starts with
 301    'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
 302    Hauppauge driver sets. */
 303
 304 /* SAA7114 and SAA7115 initialization table */
 305 static const unsigned char saa7115_init_auto_input[] = {
 306                 /* Front-End Part */
 307         R_01_INC_DELAY, 0x48,                   /* white peak control disabled */
 308         R_03_INPUT_CNTL_2, 0x20,                /* was 0x30. 0x20: long vertical blanking */
 309         R_04_INPUT_CNTL_3, 0x90,                /* analog gain set to 0 */
 310         R_05_INPUT_CNTL_4, 0x90,                /* analog gain set to 0 */
 311                 /* Decoder Part */
 312         R_06_H_SYNC_START, 0xeb,                /* horiz sync begin = -21 */
 313         R_07_H_SYNC_STOP, 0xe0,                 /* horiz sync stop = -17 */
 314         R_09_LUMA_CNTL, 0x53,                   /* 0x53, was 0x56 for 60hz. luminance control */
 315         R_0A_LUMA_BRIGHT_CNTL, 0x80,            /* was 0x88. decoder brightness, 0x80 is itu standard */
 316         R_0B_LUMA_CONTRAST_CNTL, 0x44,          /* was 0x48. decoder contrast, 0x44 is itu standard */
 317         R_0C_CHROMA_SAT_CNTL, 0x40,             /* was 0x47. decoder saturation, 0x40 is itu standard */
 318         R_0D_CHROMA_HUE_CNTL, 0x00,
 319         R_0F_CHROMA_GAIN_CNTL, 0x00,            /* use automatic gain  */
 320         R_10_CHROMA_CNTL_2, 0x06,               /* chroma: active adaptive combfilter */
 321         R_11_MODE_DELAY_CNTL, 0x00,
 322         R_12_RT_SIGNAL_CNTL, 0x9d,              /* RTS0 output control: VGATE */
 323         R_13_RT_X_PORT_OUT_CNTL, 0x80,          /* ITU656 standard mode, RTCO output enable RTCE */
 324         R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
 325         R_18_RAW_DATA_GAIN_CNTL, 0x40,          /* gain 0x00 = nominal */
 326         R_19_RAW_DATA_OFF_CNTL, 0x80,
 327         R_1A_COLOR_KILL_LVL_CNTL, 0x77,         /* recommended value */
 328         R_1B_MISC_TVVCRDET, 0x42,               /* recommended value */
 329         R_1C_ENHAN_COMB_CTRL1, 0xa9,            /* recommended value */
 330         R_1D_ENHAN_COMB_CTRL2, 0x01,            /* recommended value */
 331
 332
 333         R_80_GLOBAL_CNTL_1, 0x0,                /* No tasks enabled at init */
 334
 335                 /* Power Device Control */
 336         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,    /* reset device */
 337         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,    /* set device programmed, all in operational mode */
 338         0x00, 0x00
 339 };
 340
 341 /* Used to reset saa7113, saa7114 and saa7115 */
 342 static const unsigned char saa7115_cfg_reset_scaler[] = {
 343         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00,    /* disable I-port output */
 344         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 345         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,            /* activate scaler */
 346         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,    /* enable I-port output */
 347         0x00, 0x00
 348 };
 349
 350 /* ============== SAA7715 VIDEO templates =============  */
 351
 352 static const unsigned char saa7115_cfg_60hz_video[] = {
 353         R_80_GLOBAL_CNTL_1, 0x00,                       /* reset tasks */
 354         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 355
 356         R_15_VGATE_START_FID_CHG, 0x03,
 357         R_16_VGATE_STOP, 0x11,
 358         R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
 359
 360         R_08_SYNC_CNTL, 0x68,                   /* 0xBO: auto detection, 0x68 = NTSC */
 361         R_0E_CHROMA_CNTL_1, 0x07,               /* video autodetection is on */
 362
 363         R_5A_V_OFF_FOR_SLICER, 0x06,            /* standard 60hz value for ITU656 line counting */
 364
 365         /* Task A */
 366         R_90_A_TASK_HANDLING_CNTL, 0x80,
 367         R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
 368         R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
 369         R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
 370
 371         /* hoffset low (input), 0x0002 is minimum */
 372         R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
 373         R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 374
 375         /* hsize low (input), 0x02d0 = 720 */
 376         R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 377         R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 378
 379         R_98_A_VERT_INPUT_WINDOW_START, 0x05,
 380         R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
 381
 382         R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
 383         R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
 384
 385         R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
 386         R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
 387
 388         R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
 389         R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
 390
 391         /* Task B */
 392         R_C0_B_TASK_HANDLING_CNTL, 0x00,
 393         R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
 394         R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
 395         R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
 396
 397         /* 0x0002 is minimum */
 398         R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
 399         R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 400
 401         /* 0x02d0 = 720 */
 402         R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 403         R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 404
 405         /* vwindow start 0x12 = 18 */
 406         R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
 407         R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
 408
 409         /* vwindow length 0xf8 = 248 */
 410         R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1,
 411         R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9,
 412
 413         /* hwindow 0x02d0 = 720 */
 414         R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
 415         R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
 416
 417         R_F0_LFCO_PER_LINE, 0xad,               /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
 418         R_F1_P_I_PARAM_SELECT, 0x05,            /* low bit with 0xF0 */
 419         R_F5_PULSGEN_LINE_LENGTH, 0xad,
 420         R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
 421
 422         0x00, 0x00
 423 };
 424
 425 static const unsigned char saa7115_cfg_50hz_video[] = {
 426         R_80_GLOBAL_CNTL_1, 0x00,
 427         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,    /* reset scaler */
 428
 429         R_15_VGATE_START_FID_CHG, 0x37,         /* VGATE start */
 430         R_16_VGATE_STOP, 0x16,
 431         R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
 432
 433         R_08_SYNC_CNTL, 0x28,                   /* 0x28 = PAL */
 434         R_0E_CHROMA_CNTL_1, 0x07,
 435
 436         R_5A_V_OFF_FOR_SLICER, 0x03,            /* standard 50hz value */
 437
 438         /* Task A */
 439         R_90_A_TASK_HANDLING_CNTL, 0x81,
 440         R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
 441         R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
 442         R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
 443
 444         /* This is weird: the datasheet says that you should use 2 as the minimum value, */
 445         /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
 446         /* hoffset low (input), 0x0002 is minimum */
 447         R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
 448         R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 449
 450         /* hsize low (input), 0x02d0 = 720 */
 451         R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 452         R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 453
 454         R_98_A_VERT_INPUT_WINDOW_START, 0x03,
 455         R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
 456
 457         /* vsize 0x12 = 18 */
 458         R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
 459         R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
 460
 461         /* hsize 0x05a0 = 1440 */
 462         R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
 463         R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,    /* hsize hi (output) */
 464         R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12,         /* vsize low (output), 0x12 = 18 */
 465         R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,     /* vsize hi (output) */
 466
 467         /* Task B */
 468         R_C0_B_TASK_HANDLING_CNTL, 0x00,
 469         R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
 470         R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
 471         R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
 472
 473         /* This is weird: the datasheet says that you should use 2 as the minimum value, */
 474         /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
 475         /* hoffset low (input), 0x0002 is minimum. See comment above. */
 476         R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
 477         R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 478
 479         /* hsize 0x02d0 = 720 */
 480         R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 481         R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 482
 483         /* voffset 0x16 = 22 */
 484         R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
 485         R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
 486
 487         /* vsize 0x0120 = 288 */
 488         R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
 489         R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
 490
 491         /* hsize 0x02d0 = 720 */
 492         R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
 493         R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
 494
 495         R_F0_LFCO_PER_LINE, 0xb0,               /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
 496         R_F1_P_I_PARAM_SELECT, 0x05,            /* low bit with 0xF0, (was 0x05) */
 497         R_F5_PULSGEN_LINE_LENGTH, 0xb0,
 498         R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
 499
 500         0x00, 0x00
 501 };
 502
 503 /* ============== SAA7715 VIDEO templates (end) =======  */
 504
 505 static const unsigned char saa7115_cfg_vbi_on[] = {
 506         R_80_GLOBAL_CNTL_1, 0x00,                       /* reset tasks */
 507         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 508         R_80_GLOBAL_CNTL_1, 0x30,                       /* Activate both tasks */
 509         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,            /* activate scaler */
 510         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,    /* Enable I-port output */
 511
 512         0x00, 0x00
 513 };
 514
 515 static const unsigned char saa7115_cfg_vbi_off[] = {
 516         R_80_GLOBAL_CNTL_1, 0x00,                       /* reset tasks */
 517         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 518         R_80_GLOBAL_CNTL_1, 0x20,                       /* Activate only task "B" */
 519         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,            /* activate scaler */
 520         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,    /* Enable I-port output */
 521
 522         0x00, 0x00
 523 };
 524
 525
 526 static const unsigned char saa7115_init_misc[] = {
 527         R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
 528         R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
 529         R_84_I_PORT_SIGNAL_DEF, 0x20,
 530         R_85_I_PORT_SIGNAL_POLAR, 0x21,
 531         R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
 532         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
 533
 534         /* Task A */
 535         R_A0_A_HORIZ_PRESCALING, 0x01,
 536         R_A1_A_ACCUMULATION_LENGTH, 0x00,
 537         R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
 538
 539         /* Configure controls at nominal value*/
 540         R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
 541         R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
 542         R_A6_A_CHROMA_SATURATION_CNTL, 0x40,
 543
 544         /* note: 2 x zoom ensures that VBI lines have same length as video lines. */
 545         R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
 546         R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
 547
 548         R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,
 549
 550         /* must be horiz lum scaling / 2 */
 551         R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
 552         R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
 553
 554         /* must be offset luma / 2 */
 555         R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,
 556
 557         R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
 558         R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,
 559
 560         R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
 561         R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 562
 563         R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,
 564
 565         R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
 566         R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
 567         R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
 568         R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,
 569
 570         R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
 571         R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
 572         R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
 573         R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
 574
 575         /* Task B */
 576         R_D0_B_HORIZ_PRESCALING, 0x01,
 577         R_D1_B_ACCUMULATION_LENGTH, 0x00,
 578         R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
 579
 580         /* Configure controls at nominal value*/
 581         R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
 582         R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
 583         R_D6_B_CHROMA_SATURATION_CNTL, 0x40,
 584
 585         /* hor lum scaling 0x0400 = 1 */
 586         R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
 587         R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
 588
 589         R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,
 590
 591         /* must be hor lum scaling / 2 */
 592         R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
 593         R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
 594
 595         /* must be offset luma / 2 */
 596         R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
 597
 598         R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
 599         R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
 600
 601         R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
 602         R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 603
 604         R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,
 605
 606         R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
 607         R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
 608         R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
 609         R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,
 610
 611         R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
 612         R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
 613         R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
 614         R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,
 615
 616         R_F2_NOMINAL_PLL2_DTO, 0x50,            /* crystal clock = 24.576 MHz, target = 27MHz */
 617         R_F3_PLL_INCREMENT, 0x46,
 618         R_F4_PLL2_STATUS, 0x00,
 619         R_F7_PULSE_A_POS_MSB, 0x4b,             /* not the recommended settings! */
 620         R_F8_PULSE_B_POS, 0x00,
 621         R_F9_PULSE_B_POS_MSB, 0x4b,
 622         R_FA_PULSE_C_POS, 0x00,
 623         R_FB_PULSE_C_POS_MSB, 0x4b,
 624
 625         /* PLL2 lock detection settings: 71 lines 50% phase error */
 626         R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
 627
 628         /* Turn off VBI */
 629         R_40_SLICER_CNTL_1, 0x20,             /* No framing code errors allowed. */
 630         R_41_LCR_BASE, 0xff,
 631         R_41_LCR_BASE+1, 0xff,
 632         R_41_LCR_BASE+2, 0xff,
 633         R_41_LCR_BASE+3, 0xff,
 634         R_41_LCR_BASE+4, 0xff,
 635         R_41_LCR_BASE+5, 0xff,
 636         R_41_LCR_BASE+6, 0xff,
 637         R_41_LCR_BASE+7, 0xff,
 638         R_41_LCR_BASE+8, 0xff,
 639         R_41_LCR_BASE+9, 0xff,
 640         R_41_LCR_BASE+10, 0xff,
 641         R_41_LCR_BASE+11, 0xff,
 642         R_41_LCR_BASE+12, 0xff,
 643         R_41_LCR_BASE+13, 0xff,
 644         R_41_LCR_BASE+14, 0xff,
 645         R_41_LCR_BASE+15, 0xff,
 646         R_41_LCR_BASE+16, 0xff,
 647         R_41_LCR_BASE+17, 0xff,
 648         R_41_LCR_BASE+18, 0xff,
 649         R_41_LCR_BASE+19, 0xff,
 650         R_41_LCR_BASE+20, 0xff,
 651         R_41_LCR_BASE+21, 0xff,
 652         R_41_LCR_BASE+22, 0xff,
 653         R_58_PROGRAM_FRAMING_CODE, 0x40,
 654         R_59_H_OFF_FOR_SLICER, 0x47,
 655         R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
 656         R_5D_DID, 0xbd,
 657         R_5E_SDID, 0x35,
 658
 659         R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */
 660
 661         R_80_GLOBAL_CNTL_1, 0x20,               /* enable task B */
 662         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
 663         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
 664         0x00, 0x00
 665 };
 666
 667 static int saa711x_odd_parity(u8 c)
 668 {
 669         c ^= (c >> 4);
 670         c ^= (c >> 2);
 671         c ^= (c >> 1);
 672
 673         return c & 1;
 674 }
 675
 676 static int saa711x_decode_vps(u8 *dst, u8 *p)
 677 {
 678         static const u8 biphase_tbl[] = {
 679                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 680                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 681                 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
 682                 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
 683                 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
 684                 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
 685                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 686                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 687                 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
 688                 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
 689                 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
 690                 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
 691                 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
 692                 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
 693                 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
 694                 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
 695                 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
 696                 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
 697                 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
 698                 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
 699                 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
 700                 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
 701                 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
 702                 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
 703                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 704                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 705                 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
 706                 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
 707                 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
 708                 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
 709                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 710                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 711         };
 712         int i;
 713         u8 c, err = 0;
 714
 715         for (i = 0; i < 2 * 13; i += 2) {
 716                 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
 717                 c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4);
 718                 dst[i / 2] = c;
 719         }
 720         return err & 0xf0;
 721 }
 722
 723 static int saa711x_decode_wss(u8 *p)
 724 {
 725         static const int wss_bits[8] = {
 726                 0, 0, 0, 1, 0, 1, 1, 1
 727         };
 728         unsigned char parity;
 729         int wss = 0;
 730         int i;
 731
 732         for (i = 0; i < 16; i++) {
 733                 int b1 = wss_bits[p[i] & 7];
 734                 int b2 = wss_bits[(p[i] >> 3) & 7];
 735
 736                 if (b1 == b2)
 737                         return -1;
 738                 wss |= b2 << i;
 739         }
 740         parity = wss & 15;
 741         parity ^= parity >> 2;
 742         parity ^= parity >> 1;
 743
 744         if (!(parity & 1))
 745                 return -1;
 746
 747         return wss;
 748 }
 749
 750 static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
 751 {
 752         struct saa711x_state *state = to_state(sd);
 753         u32 acpf;
 754         u32 acni;
 755         u32 hz;
 756         u64 f;
 757         u8 acc = 0;     /* reg 0x3a, audio clock control */
 758
 759         /* Checks for chips that don't have audio clock (saa7111, saa7113) */
 760         if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD))
 761                 return 0;
 762
 763         v4l2_dbg(1, debug, sd, "set audio clock freq: %d\n", freq);
 764
 765         /* sanity check */
 766         if (freq < 32000 || freq > 48000)
 767                 return -EINVAL;
 768
 769         /* hz is the refresh rate times 100 */
 770         hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
 771         /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
 772         acpf = (25600 * freq) / hz;
 773         /* acni = (256 * freq * 2^23) / crystal_frequency =
 774                   (freq * 2^(8+23)) / crystal_frequency =
 775                   (freq << 31) / crystal_frequency */
 776         f = freq;
 777         f = f << 31;
 778         do_div(f, state->crystal_freq);
 779         acni = f;
 780         if (state->ucgc) {
 781                 acpf = acpf * state->cgcdiv / 16;
 782                 acni = acni * state->cgcdiv / 16;
 783                 acc = 0x80;
 784                 if (state->cgcdiv == 3)
 785                         acc |= 0x40;
 786         }
 787         if (state->apll)
 788                 acc |= 0x08;
 789
 790         if (state->double_asclk) {
 791                 acpf <<= 1;
 792                 acni <<= 1;
 793         }
 794         saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
 795         saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk);
 796         saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
 797
 798         saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
 799         saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
 800                                                         (acpf >> 8) & 0xff);
 801         saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
 802                                                         (acpf >> 16) & 0x03);
 803
 804         saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
 805         saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
 806         saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
 807         state->audclk_freq = freq;
 808         return 0;
 809 }
 810
 811 static int saa711x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
 812 {
 813         struct v4l2_subdev *sd = to_sd(ctrl);
 814         struct saa711x_state *state = to_state(sd);
 815
 816         switch (ctrl->id) {
 817         case V4L2_CID_CHROMA_AGC:
 818                 /* chroma gain cluster */
 819                 if (state->agc->val)
 820                         state->gain->val =
 821                                 saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f;
 822                 break;
 823         }
 824         return 0;
 825 }
 826
 827 static int saa711x_s_ctrl(struct v4l2_ctrl *ctrl)
 828 {
 829         struct v4l2_subdev *sd = to_sd(ctrl);
 830         struct saa711x_state *state = to_state(sd);
 831
 832         switch (ctrl->id) {
 833         case V4L2_CID_BRIGHTNESS:
 834                 saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val);
 835                 break;
 836
 837         case V4L2_CID_CONTRAST:
 838                 saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val);
 839                 break;
 840
 841         case V4L2_CID_SATURATION:
 842                 saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val);
 843                 break;
 844
 845         case V4L2_CID_HUE:
 846                 saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val);
 847                 break;
 848
 849         case V4L2_CID_CHROMA_AGC:
 850                 /* chroma gain cluster */
 851                 if (state->agc->val)
 852                         saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val);
 853                 else
 854                         saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80);
 855                 break;
 856
 857         default:
 858                 return -EINVAL;
 859         }
 860
 861         return 0;
 862 }
 863
 864 static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height)
 865 {
 866         struct saa711x_state *state = to_state(sd);
 867         int HPSC, HFSC;
 868         int VSCY;
 869         int res;
 870         int is_50hz = state->std & V4L2_STD_625_50;
 871         int Vsrc = is_50hz ? 576 : 480;
 872
 873         v4l2_dbg(1, debug, sd, "decoder set size to %ix%i\n", width, height);
 874
 875         /* FIXME need better bounds checking here */
 876         if ((width < 1) || (width > 1440))
 877                 return -EINVAL;
 878         if ((height < 1) || (height > Vsrc))
 879                 return -EINVAL;
 880
 881         if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) {
 882                 /* Decoder only supports 720 columns and 480 or 576 lines */
 883                 if (width != 720)
 884                         return -EINVAL;
 885                 if (height != Vsrc)
 886                         return -EINVAL;
 887         }
 888
 889         state->width = width;
 890         state->height = height;
 891
 892         if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH))
 893                 return 0;
 894
 895         /* probably have a valid size, let's set it */
 896         /* Set output width/height */
 897         /* width */
 898
 899         saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
 900                                         (u8) (width & 0xff));
 901         saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
 902                                         (u8) ((width >> 8) & 0xff));
 903
 904         /* Vertical Scaling uses height/2 */
 905         res = height / 2;
 906
 907         /* On 60Hz, it is using a higher Vertical Output Size */
 908         if (!is_50hz)
 909                 res += (VRES_60HZ - 480) >> 1;
 910
 911                 /* height */
 912         saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
 913                                         (u8) (res & 0xff));
 914         saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
 915                                         (u8) ((res >> 8) & 0xff));
 916
 917         /* Scaling settings */
 918         /* Hprescaler is floor(inres/outres) */
 919         HPSC = (int)(720 / width);
 920         /* 0 is not allowed (div. by zero) */
 921         HPSC = HPSC ? HPSC : 1;
 922         HFSC = (int)((1024 * 720) / (HPSC * width));
 923         /* FIXME hardcodes to "Task B"
 924          * write H prescaler integer */
 925         saa711x_write(sd, R_D0_B_HORIZ_PRESCALING,
 926                                 (u8) (HPSC & 0x3f));
 927
 928         v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
 929         /* write H fine-scaling (luminance) */
 930         saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC,
 931                                 (u8) (HFSC & 0xff));
 932         saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
 933                                 (u8) ((HFSC >> 8) & 0xff));
 934         /* write H fine-scaling (chrominance)
 935          * must be lum/2, so i'll just bitshift :) */
 936         saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING,
 937                                 (u8) ((HFSC >> 1) & 0xff));
 938         saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
 939                                 (u8) ((HFSC >> 9) & 0xff));
 940
 941         VSCY = (int)((1024 * Vsrc) / height);
 942         v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
 943
 944         /* Correct Contrast and Luminance */
 945         saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL,
 946                                         (u8) (64 * 1024 / VSCY));
 947         saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL,
 948                                         (u8) (64 * 1024 / VSCY));
 949
 950                 /* write V fine-scaling (luminance) */
 951         saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC,
 952                                         (u8) (VSCY & 0xff));
 953         saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
 954                                         (u8) ((VSCY >> 8) & 0xff));
 955                 /* write V fine-scaling (chrominance) */
 956         saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC,
 957                                         (u8) (VSCY & 0xff));
 958         saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
 959                                         (u8) ((VSCY >> 8) & 0xff));
 960
 961         saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
 962
 963         /* Activates task "B" */
 964         saa711x_write(sd, R_80_GLOBAL_CNTL_1,
 965                                 saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20);
 966
 967         return 0;
 968 }
 969
 970 static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std)
 971 {
 972         struct saa711x_state *state = to_state(sd);
 973
 974         /* Prevent unnecessary standard changes. During a standard
 975            change the I-Port is temporarily disabled. Any devices
 976            reading from that port can get confused.
 977            Note that s_std is also used to switch from
 978            radio to TV mode, so if a s_std is broadcast to
 979            all I2C devices then you do not want to have an unwanted
 980            side-effect here. */
 981         if (std == state->std)
 982                 return;
 983
 984         state->std = std;
 985
 986         // This works for NTSC-M, SECAM-L and the 50Hz PAL variants.
 987         if (std & V4L2_STD_525_60) {
 988                 v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz\n");
 989                 if (state->ident == GM7113C) {
 990                         u8 reg = saa711x_read(sd, R_08_SYNC_CNTL);
 991                         reg &= ~(SAA7113_R_08_FSEL | SAA7113_R_08_AUFD);
 992                         reg |= SAA7113_R_08_FSEL;
 993                         saa711x_write(sd, R_08_SYNC_CNTL, reg);
 994                 } else {
 995                         saa711x_writeregs(sd, saa7115_cfg_60hz_video);
 996                 }
 997                 saa711x_set_size(sd, 720, 480);
 998         } else {
 999                 v4l2_dbg(1, debug, sd, "decoder set standard 50 Hz\n");
1000                 if (state->ident == GM7113C) {
1001                         u8 reg = saa711x_read(sd, R_08_SYNC_CNTL);
1002                         reg &= ~(SAA7113_R_08_FSEL | SAA7113_R_08_AUFD);
1003                         saa711x_write(sd, R_08_SYNC_CNTL, reg);
1004                 } else {
1005                         saa711x_writeregs(sd, saa7115_cfg_50hz_video);
1006                 }
1007                 saa711x_set_size(sd, 720, 576);
1008         }
1009
1010         /* Register 0E - Bits D6-D4 on NO-AUTO mode
1011                 (SAA7111 and SAA7113 doesn't have auto mode)
1012             50 Hz / 625 lines           60 Hz / 525 lines
1013         000 PAL BGDHI (4.43Mhz)         NTSC M (3.58MHz)
1014         001 NTSC 4.43 (50 Hz)           PAL 4.43 (60 Hz)
1015         010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz)
1016         011 NTSC N (3.58MHz)            PAL M (3.58MHz)
1017         100 reserved                    NTSC-Japan (3.58MHz)
1018         */
1019         if (state->ident <= SAA7113 ||
1020             state->ident == GM7113C) {
1021                 u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f;
1022
1023                 if (std == V4L2_STD_PAL_M) {
1024                         reg |= 0x30;
1025                 } else if (std == V4L2_STD_PAL_Nc) {
1026                         reg |= 0x20;
1027                 } else if (std == V4L2_STD_PAL_60) {
1028                         reg |= 0x10;
1029                 } else if (std == V4L2_STD_NTSC_M_JP) {
1030                         reg |= 0x40;
1031                 } else if (std & V4L2_STD_SECAM) {
1032                         reg |= 0x50;
1033                 }
1034                 saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg);
1035         } else {
1036                 /* restart task B if needed */
1037                 int taskb = saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10;
1038
1039                 if (taskb && state->ident == SAA7114)
1040                         saa711x_writeregs(sd, saa7115_cfg_vbi_on);
1041
1042                 /* switch audio mode too! */
1043                 saa711x_s_clock_freq(sd, state->audclk_freq);
1044         }
1045 }
1046
1047 /* setup the sliced VBI lcr registers according to the sliced VBI format */
1048 static void saa711x_set_lcr(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
1049 {
1050         struct saa711x_state *state = to_state(sd);
1051         int is_50hz = (state->std & V4L2_STD_625_50);
1052         u8 lcr[24];
1053         int i, x;
1054
1055 #if 1
1056         /* saa7113/7114/7118 VBI support are experimental */
1057         if (!saa711x_has_reg(state->ident, R_41_LCR_BASE))
1058                 return;
1059
1060 #else
1061         /* SAA7113 and SAA7118 also should support VBI - Need testing */
1062         if (state->ident != SAA7115)
1063                 return;
1064 #endif
1065
1066         for (i = 0; i <= 23; i++)
1067                 lcr[i] = 0xff;
1068
1069         if (fmt == NULL) {
1070                 /* raw VBI */
1071                 if (is_50hz)
1072                         for (i = 6; i <= 23; i++)
1073                                 lcr[i] = 0xdd;
1074                 else
1075                         for (i = 10; i <= 21; i++)
1076                                 lcr[i] = 0xdd;
1077         } else {
1078                 /* sliced VBI */
1079                 /* first clear lines that cannot be captured */
1080                 if (is_50hz) {
1081                         for (i = 0; i <= 5; i++)
1082                                 fmt->service_lines[0][i] =
1083                                         fmt->service_lines[1][i] = 0;
1084                 }
1085                 else {
1086                         for (i = 0; i <= 9; i++)
1087                                 fmt->service_lines[0][i] =
1088                                         fmt->service_lines[1][i] = 0;
1089                         for (i = 22; i <= 23; i++)
1090                                 fmt->service_lines[0][i] =
1091                                         fmt->service_lines[1][i] = 0;
1092                 }
1093
1094                 /* Now set the lcr values according to the specified service */
1095                 for (i = 6; i <= 23; i++) {
1096                         lcr[i] = 0;
1097                         for (x = 0; x <= 1; x++) {
1098                                 switch (fmt->service_lines[1-x][i]) {
1099                                         case 0:
1100                                                 lcr[i] |= 0xf << (4 * x);
1101                                                 break;
1102                                         case V4L2_SLICED_TELETEXT_B:
1103                                                 lcr[i] |= 1 << (4 * x);
1104                                                 break;
1105                                         case V4L2_SLICED_CAPTION_525:
1106                                                 lcr[i] |= 4 << (4 * x);
1107                                                 break;
1108                                         case V4L2_SLICED_WSS_625:
1109                                                 lcr[i] |= 5 << (4 * x);
1110                                                 break;
1111                                         case V4L2_SLICED_VPS:
1112                                                 lcr[i] |= 7 << (4 * x);
1113                                                 break;
1114                                 }
1115                         }
1116                 }
1117         }
1118
1119         /* write the lcr registers */
1120         for (i = 2; i <= 23; i++) {
1121                 saa711x_write(sd, i - 2 + R_41_LCR_BASE, lcr[i]);
1122         }
1123
1124         /* enable/disable raw VBI capturing */
1125         saa711x_writeregs(sd, fmt == NULL ?
1126                                 saa7115_cfg_vbi_on :
1127                                 saa7115_cfg_vbi_off);
1128 }
1129
1130 static int saa711x_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *sliced)
1131 {
1132         static u16 lcr2vbi[] = {
1133                 0, V4L2_SLICED_TELETEXT_B, 0,   /* 1 */
1134                 0, V4L2_SLICED_CAPTION_525,     /* 4 */
1135                 V4L2_SLICED_WSS_625, 0,         /* 5 */
1136                 V4L2_SLICED_VPS, 0, 0, 0, 0,    /* 7 */
1137                 0, 0, 0, 0
1138         };
1139         int i;
1140
1141         memset(sliced->service_lines, 0, sizeof(sliced->service_lines));
1142         sliced->service_set = 0;
1143         /* done if using raw VBI */
1144         if (saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10)
1145                 return 0;
1146         for (i = 2; i <= 23; i++) {
1147                 u8 v = saa711x_read(sd, i - 2 + R_41_LCR_BASE);
1148
1149                 sliced->service_lines[0][i] = lcr2vbi[v >> 4];
1150                 sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
1151                 sliced->service_set |=
1152                         sliced->service_lines[0][i] | sliced->service_lines[1][i];
1153         }
1154         return 0;
1155 }
1156
1157 static int saa711x_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
1158 {
1159         saa711x_set_lcr(sd, NULL);
1160         return 0;
1161 }
1162
1163 static int saa711x_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
1164 {
1165         saa711x_set_lcr(sd, fmt);
1166         return 0;
1167 }
1168
1169 static int saa711x_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
1170 {
1171         if (fmt->code != V4L2_MBUS_FMT_FIXED)
1172                 return -EINVAL;
1173         fmt->field = V4L2_FIELD_INTERLACED;
1174         fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1175         return saa711x_set_size(sd, fmt->width, fmt->height);
1176 }
1177
1178 /* Decode the sliced VBI data stream as created by the saa7115.
1179    The format is described in the saa7115 datasheet in Tables 25 and 26
1180    and in Figure 33.
1181    The current implementation uses SAV/EAV codes and not the ancillary data
1182    headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV
1183    code. */
1184 static int saa711x_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi)
1185 {
1186         struct saa711x_state *state = to_state(sd);
1187         static const char vbi_no_data_pattern[] = {
1188                 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0
1189         };
1190         u8 *p = vbi->p;
1191         u32 wss;
1192         int id1, id2;   /* the ID1 and ID2 bytes from the internal header */
1193
1194         vbi->type = 0;  /* mark result as a failure */
1195         id1 = p[2];
1196         id2 = p[3];
1197         /* Note: the field bit is inverted for 60 Hz video */
1198         if (state->std & V4L2_STD_525_60)
1199                 id1 ^= 0x40;
1200
1201         /* Skip internal header, p now points to the start of the payload */
1202         p += 4;
1203         vbi->p = p;
1204
1205         /* calculate field and line number of the VBI packet (1-23) */
1206         vbi->is_second_field = ((id1 & 0x40) != 0);
1207         vbi->line = (id1 & 0x3f) << 3;
1208         vbi->line |= (id2 & 0x70) >> 4;
1209
1210         /* Obtain data type */
1211         id2 &= 0xf;
1212
1213         /* If the VBI slicer does not detect any signal it will fill up
1214            the payload buffer with 0xa0 bytes. */
1215         if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern)))
1216                 return 0;
1217
1218         /* decode payloads */
1219         switch (id2) {
1220         case 1:
1221                 vbi->type = V4L2_SLICED_TELETEXT_B;
1222                 break;
1223         case 4:
1224                 if (!saa711x_odd_parity(p[0]) || !saa711x_odd_parity(p[1]))
1225                         return 0;
1226                 vbi->type = V4L2_SLICED_CAPTION_525;
1227                 break;
1228         case 5:
1229                 wss = saa711x_decode_wss(p);
1230                 if (wss == -1)
1231                         return 0;
1232                 p[0] = wss & 0xff;
1233                 p[1] = wss >> 8;
1234                 vbi->type = V4L2_SLICED_WSS_625;
1235                 break;
1236         case 7:
1237                 if (saa711x_decode_vps(p, p) != 0)
1238                         return 0;
1239                 vbi->type = V4L2_SLICED_VPS;
1240                 break;
1241         default:
1242                 break;
1243         }
1244         return 0;
1245 }
1246
1247 /* ============ SAA7115 AUDIO settings (end) ============= */
1248
1249 static int saa711x_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1250 {
1251         struct saa711x_state *state = to_state(sd);
1252         int status;
1253
1254         if (state->radio)
1255                 return 0;
1256         status = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1257
1258         v4l2_dbg(1, debug, sd, "status: 0x%02x\n", status);
1259         vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
1260         return 0;
1261 }
1262
1263 static int saa711x_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1264 {
1265         struct saa711x_state *state = to_state(sd);
1266
1267         state->radio = 0;
1268         saa711x_set_v4lstd(sd, std);
1269         return 0;
1270 }
1271
1272 static int saa711x_s_radio(struct v4l2_subdev *sd)
1273 {
1274         struct saa711x_state *state = to_state(sd);
1275
1276         state->radio = 1;
1277         return 0;
1278 }
1279
1280 static int saa711x_s_routing(struct v4l2_subdev *sd,
1281                              u32 input, u32 output, u32 config)
1282 {
1283         struct saa711x_state *state = to_state(sd);
1284         u8 mask = (state->ident <= SAA7111A) ? 0xf8 : 0xf0;
1285
1286         v4l2_dbg(1, debug, sd, "decoder set input %d output %d\n",
1287                 input, output);
1288
1289         /* saa7111/3 does not have these inputs */
1290         if ((state->ident <= SAA7113 ||
1291              state->ident == GM7113C) &&
1292             (input == SAA7115_COMPOSITE4 ||
1293              input == SAA7115_COMPOSITE5)) {
1294                 return -EINVAL;
1295         }
1296         if (input > SAA7115_SVIDEO3)
1297                 return -EINVAL;
1298         if (state->input == input && state->output == output)
1299                 return 0;
1300         v4l2_dbg(1, debug, sd, "now setting %s input %s output\n",
1301                 (input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite",
1302                 (output == SAA7115_IPORT_ON) ? "iport on" : "iport off");
1303         state->input = input;
1304
1305         /* saa7111 has slightly different input numbering */
1306         if (state->ident <= SAA7111A) {
1307                 if (input >= SAA7115_COMPOSITE4)
1308                         input -= 2;
1309                 /* saa7111 specific */
1310                 saa711x_write(sd, R_10_CHROMA_CNTL_2,
1311                                 (saa711x_read(sd, R_10_CHROMA_CNTL_2) & 0x3f) |
1312                                 ((output & 0xc0) ^ 0x40));
1313                 saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL,
1314                                 (saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL) & 0xf0) |
1315                                 ((output & 2) ? 0x0a : 0));
1316         }
1317
1318         /* select mode */
1319         saa711x_write(sd, R_02_INPUT_CNTL_1,
1320                       (saa711x_read(sd, R_02_INPUT_CNTL_1) & mask) |
1321                        input);
1322
1323         /* bypass chrominance trap for S-Video modes */
1324         saa711x_write(sd, R_09_LUMA_CNTL,
1325                         (saa711x_read(sd, R_09_LUMA_CNTL) & 0x7f) |
1326                         (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
1327
1328         state->output = output;
1329         if (state->ident == SAA7114 ||
1330                         state->ident == SAA7115) {
1331                 saa711x_write(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK,
1332                                 (saa711x_read(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK) & 0xfe) |
1333                                 (state->output & 0x01));
1334         }
1335         if (state->ident > SAA7111A) {
1336                 if (config & SAA7115_IDQ_IS_DEFAULT)
1337                         saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x20);
1338                 else
1339                         saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x21);
1340         }
1341         return 0;
1342 }
1343
1344 static int saa711x_s_gpio(struct v4l2_subdev *sd, u32 val)
1345 {
1346         struct saa711x_state *state = to_state(sd);
1347
1348         if (state->ident > SAA7111A)
1349                 return -EINVAL;
1350         saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) |
1351                 (val ? 0x80 : 0));
1352         return 0;
1353 }
1354
1355 static int saa711x_s_stream(struct v4l2_subdev *sd, int enable)
1356 {
1357         struct saa711x_state *state = to_state(sd);
1358
1359         v4l2_dbg(1, debug, sd, "%s output\n",
1360                         enable ? "enable" : "disable");
1361
1362         if (state->enable == enable)
1363                 return 0;
1364         state->enable = enable;
1365         if (!saa711x_has_reg(state->ident, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED))
1366                 return 0;
1367         saa711x_write(sd, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, state->enable);
1368         return 0;
1369 }
1370
1371 static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags)
1372 {
1373         struct saa711x_state *state = to_state(sd);
1374
1375         if (freq != SAA7115_FREQ_32_11_MHZ && freq != SAA7115_FREQ_24_576_MHZ)
1376                 return -EINVAL;
1377         state->crystal_freq = freq;
1378         state->double_asclk = flags & SAA7115_FREQ_FL_DOUBLE_ASCLK;
1379         state->cgcdiv = (flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4;
1380         state->ucgc = flags & SAA7115_FREQ_FL_UCGC;
1381         state->apll = flags & SAA7115_FREQ_FL_APLL;
1382         saa711x_s_clock_freq(sd, state->audclk_freq);
1383         return 0;
1384 }
1385
1386 static int saa711x_reset(struct v4l2_subdev *sd, u32 val)
1387 {
1388         v4l2_dbg(1, debug, sd, "decoder RESET\n");
1389         saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
1390         return 0;
1391 }
1392
1393 static int saa711x_g_vbi_data(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_data *data)
1394 {
1395         /* Note: the internal field ID is inverted for NTSC,
1396            so data->field 0 maps to the saa7115 even field,
1397            whereas for PAL it maps to the saa7115 odd field. */
1398         switch (data->id) {
1399         case V4L2_SLICED_WSS_625:
1400                 if (saa711x_read(sd, 0x6b) & 0xc0)
1401                         return -EIO;
1402                 data->data[0] = saa711x_read(sd, 0x6c);
1403                 data->data[1] = saa711x_read(sd, 0x6d);
1404                 return 0;
1405         case V4L2_SLICED_CAPTION_525:
1406                 if (data->field == 0) {
1407                         /* CC */
1408                         if (saa711x_read(sd, 0x66) & 0x30)
1409                                 return -EIO;
1410                         data->data[0] = saa711x_read(sd, 0x69);
1411                         data->data[1] = saa711x_read(sd, 0x6a);
1412                         return 0;
1413                 }
1414                 /* XDS */
1415                 if (saa711x_read(sd, 0x66) & 0xc0)
1416                         return -EIO;
1417                 data->data[0] = saa711x_read(sd, 0x67);
1418                 data->data[1] = saa711x_read(sd, 0x68);
1419                 return 0;
1420         default:
1421                 return -EINVAL;
1422         }
1423 }
1424
1425 static int saa711x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
1426 {
1427         struct saa711x_state *state = to_state(sd);
1428         int reg1f, reg1e;
1429
1430         /*
1431          * The V4L2 core already initializes std with all supported
1432          * Standards. All driver needs to do is to mask it, to remove
1433          * standards that don't apply from the mask
1434          */
1435
1436         reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1437
1438         if (state->ident == SAA7115) {
1439                 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1440
1441                 v4l2_dbg(1, debug, sd, "Status byte 1 (0x1e)=0x%02x\n", reg1e);
1442
1443                 switch (reg1e & 0x03) {
1444                 case 1:
1445                         *std &= V4L2_STD_NTSC;
1446                         break;
1447                 case 2:
1448                         /*
1449                          * V4L2_STD_PAL just cover the european PAL standards.
1450                          * This is wrong, as the device could also be using an
1451                          * other PAL standard.
1452                          */
1453                         *std &= V4L2_STD_PAL   | V4L2_STD_PAL_N  | V4L2_STD_PAL_Nc |
1454                                 V4L2_STD_PAL_M | V4L2_STD_PAL_60;
1455                         break;
1456                 case 3:
1457                         *std &= V4L2_STD_SECAM;
1458                         break;
1459                 default:
1460                         *std = V4L2_STD_UNKNOWN;
1461                         /* Can't detect anything */
1462                         break;
1463                 }
1464         }
1465
1466         v4l2_dbg(1, debug, sd, "Status byte 2 (0x1f)=0x%02x\n", reg1f);
1467
1468         /* horizontal/vertical not locked */
1469         if (reg1f & 0x40) {
1470                 *std = V4L2_STD_UNKNOWN;
1471                 goto ret;
1472         }
1473
1474         if (reg1f & 0x20)
1475                 *std &= V4L2_STD_525_60;
1476         else
1477                 *std &= V4L2_STD_625_50;
1478
1479 ret:
1480         v4l2_dbg(1, debug, sd, "detected std mask = %08Lx\n", *std);
1481
1482         return 0;
1483 }
1484
1485 static int saa711x_g_input_status(struct v4l2_subdev *sd, u32 *status)
1486 {
1487         struct saa711x_state *state = to_state(sd);
1488         int reg1e = 0x80;
1489         int reg1f;
1490
1491         *status = V4L2_IN_ST_NO_SIGNAL;
1492         if (state->ident == SAA7115)
1493                 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1494         reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1495         if ((reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80)
1496                 *status = 0;
1497         return 0;
1498 }
1499
1500 #ifdef CONFIG_VIDEO_ADV_DEBUG
1501 static int saa711x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1502 {
1503         reg->val = saa711x_read(sd, reg->reg & 0xff);
1504         reg->size = 1;
1505         return 0;
1506 }
1507
1508 static int saa711x_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1509 {
1510         saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff);
1511         return 0;
1512 }
1513 #endif
1514
1515 static int saa711x_log_status(struct v4l2_subdev *sd)
1516 {
1517         struct saa711x_state *state = to_state(sd);
1518         int reg1e, reg1f;
1519         int signalOk;
1520         int vcr;
1521
1522         v4l2_info(sd, "Audio frequency: %d Hz\n", state->audclk_freq);
1523         if (state->ident != SAA7115) {
1524                 /* status for the saa7114 */
1525                 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1526                 signalOk = (reg1f & 0xc1) == 0x81;
1527                 v4l2_info(sd, "Video signal:    %s\n", signalOk ? "ok" : "bad");
1528                 v4l2_info(sd, "Frequency:       %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
1529                 return 0;
1530         }
1531
1532         /* status for the saa7115 */
1533         reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1534         reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1535
1536         signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
1537         vcr = !(reg1f & 0x10);
1538
1539         if (state->input >= 6)
1540                 v4l2_info(sd, "Input:           S-Video %d\n", state->input - 6);
1541         else
1542                 v4l2_info(sd, "Input:           Composite %d\n", state->input);
1543         v4l2_info(sd, "Video signal:    %s\n", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad");
1544         v4l2_info(sd, "Frequency:       %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
1545
1546         switch (reg1e & 0x03) {
1547         case 1:
1548                 v4l2_info(sd, "Detected format: NTSC\n");
1549                 break;
1550         case 2:
1551                 v4l2_info(sd, "Detected format: PAL\n");
1552                 break;
1553         case 3:
1554                 v4l2_info(sd, "Detected format: SECAM\n");
1555                 break;
1556         default:
1557                 v4l2_info(sd, "Detected format: BW/No color\n");
1558                 break;
1559         }
1560         v4l2_info(sd, "Width, Height:   %d, %d\n", state->width, state->height);
1561         v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
1562         return 0;
1563 }
1564
1565 /* ----------------------------------------------------------------------- */
1566
1567 static const struct v4l2_ctrl_ops saa711x_ctrl_ops = {
1568         .s_ctrl = saa711x_s_ctrl,
1569         .g_volatile_ctrl = saa711x_g_volatile_ctrl,
1570 };
1571
1572 static const struct v4l2_subdev_core_ops saa711x_core_ops = {
1573         .log_status = saa711x_log_status,
1574         .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1575         .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1576         .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1577         .g_ctrl = v4l2_subdev_g_ctrl,
1578         .s_ctrl = v4l2_subdev_s_ctrl,
1579         .queryctrl = v4l2_subdev_queryctrl,
1580         .querymenu = v4l2_subdev_querymenu,
1581         .s_std = saa711x_s_std,
1582         .reset = saa711x_reset,
1583         .s_gpio = saa711x_s_gpio,
1584 #ifdef CONFIG_VIDEO_ADV_DEBUG
1585         .g_register = saa711x_g_register,
1586         .s_register = saa711x_s_register,
1587 #endif
1588 };
1589
1590 static const struct v4l2_subdev_tuner_ops saa711x_tuner_ops = {
1591         .s_radio = saa711x_s_radio,
1592         .g_tuner = saa711x_g_tuner,
1593 };
1594
1595 static const struct v4l2_subdev_audio_ops saa711x_audio_ops = {
1596         .s_clock_freq = saa711x_s_clock_freq,
1597 };
1598
1599 static const struct v4l2_subdev_video_ops saa711x_video_ops = {
1600         .s_routing = saa711x_s_routing,
1601         .s_crystal_freq = saa711x_s_crystal_freq,
1602         .s_mbus_fmt = saa711x_s_mbus_fmt,
1603         .s_stream = saa711x_s_stream,
1604         .querystd = saa711x_querystd,
1605         .g_input_status = saa711x_g_input_status,
1606 };
1607
1608 static const struct v4l2_subdev_vbi_ops saa711x_vbi_ops = {
1609         .g_vbi_data = saa711x_g_vbi_data,
1610         .decode_vbi_line = saa711x_decode_vbi_line,
1611         .g_sliced_fmt = saa711x_g_sliced_fmt,
1612         .s_sliced_fmt = saa711x_s_sliced_fmt,
1613         .s_raw_fmt = saa711x_s_raw_fmt,
1614 };
1615
1616 static const struct v4l2_subdev_ops saa711x_ops = {
1617         .core = &saa711x_core_ops,
1618         .tuner = &saa711x_tuner_ops,
1619         .audio = &saa711x_audio_ops,
1620         .video = &saa711x_video_ops,
1621         .vbi = &saa711x_vbi_ops,
1622 };
1623
1624 #define CHIP_VER_SIZE   16
1625
1626 /* ----------------------------------------------------------------------- */
1627
1628 static void saa711x_write_platform_data(struct saa711x_state *state,
1629                                         struct saa7115_platform_data *data)
1630 {
1631         struct v4l2_subdev *sd = &state->sd;
1632         u8 work;
1633
1634         if (state->ident != GM7113C &&
1635             state->ident != SAA7113)
1636                 return;
1637
1638         if (data->saa7113_r08_htc) {
1639                 work = saa711x_read(sd, R_08_SYNC_CNTL);
1640                 work &= ~SAA7113_R_08_HTC_MASK;
1641                 work |= ((*data->saa7113_r08_htc) << SAA7113_R_08_HTC_OFFSET);
1642                 saa711x_write(sd, R_08_SYNC_CNTL, work);
1643         }
1644
1645         if (data->saa7113_r10_vrln) {
1646                 work = saa711x_read(sd, R_10_CHROMA_CNTL_2);
1647                 work &= ~SAA7113_R_10_VRLN_MASK;
1648                 if (*data->saa7113_r10_vrln)
1649                         work |= (1 << SAA7113_R_10_VRLN_OFFSET);
1650                 saa711x_write(sd, R_10_CHROMA_CNTL_2, work);
1651         }
1652
1653         if (data->saa7113_r10_ofts) {
1654                 work = saa711x_read(sd, R_10_CHROMA_CNTL_2);
1655                 work &= ~SAA7113_R_10_OFTS_MASK;
1656                 work |= (*data->saa7113_r10_ofts << SAA7113_R_10_OFTS_OFFSET);
1657                 saa711x_write(sd, R_10_CHROMA_CNTL_2, work);
1658         }
1659
1660         if (data->saa7113_r12_rts0) {
1661                 work = saa711x_read(sd, R_12_RT_SIGNAL_CNTL);
1662                 work &= ~SAA7113_R_12_RTS0_MASK;
1663                 work |= (*data->saa7113_r12_rts0 << SAA7113_R_12_RTS0_OFFSET);
1664
1665                 /* According to the datasheet,
1666                  * SAA7113_RTS_DOT_IN should only be used on RTS1 */
1667                 WARN_ON(*data->saa7113_r12_rts0 == SAA7113_RTS_DOT_IN);
1668                 saa711x_write(sd, R_12_RT_SIGNAL_CNTL, work);
1669         }
1670
1671         if (data->saa7113_r12_rts1) {
1672                 work = saa711x_read(sd, R_12_RT_SIGNAL_CNTL);
1673                 work &= ~SAA7113_R_12_RTS1_MASK;
1674                 work |= (*data->saa7113_r12_rts1 << SAA7113_R_12_RTS1_OFFSET);
1675                 saa711x_write(sd, R_12_RT_SIGNAL_CNTL, work);
1676         }
1677
1678         if (data->saa7113_r13_adlsb) {
1679                 work = saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL);
1680                 work &= ~SAA7113_R_13_ADLSB_MASK;
1681                 if (*data->saa7113_r13_adlsb)
1682                         work |= (1 << SAA7113_R_13_ADLSB_OFFSET);
1683                 saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL, work);
1684         }
1685 }
1686
1687 /**
1688  * saa711x_detect_chip - Detects the saa711x (or clone) variant
1689  * @client:             I2C client structure.
1690  * @id:                 I2C device ID structure.
1691  * @name:               Name of the device to be filled.
1692  *
1693  * Detects the Philips/NXP saa711x chip, or some clone of it.
1694  * if 'id' is NULL or id->driver_data is equal to 1, it auto-probes
1695  * the analog demod.
1696  * If the tuner is not found, it returns -ENODEV.
1697  * If auto-detection is disabled and the tuner doesn't match what it was
1698  *      requred, it returns -EINVAL and fills 'name'.
1699  * If the chip is found, it returns the chip ID and fills 'name'.
1700  */
1701 static int saa711x_detect_chip(struct i2c_client *client,
1702                                const struct i2c_device_id *id,
1703                                char *name)
1704 {
1705         char chip_ver[CHIP_VER_SIZE];
1706         char chip_id;
1707         int i;
1708         int autodetect;
1709
1710         autodetect = !id || id->driver_data == 1;
1711
1712         /* Read the chip version register */
1713         for (i = 0; i < CHIP_VER_SIZE; i++) {
1714                 i2c_smbus_write_byte_data(client, 0, i);
1715                 chip_ver[i] = i2c_smbus_read_byte_data(client, 0);
1716                 name[i] = (chip_ver[i] & 0x0f) + '0';
1717                 if (name[i] > '9')
1718                         name[i] += 'a' - '9' - 1;
1719         }
1720         name[i] = '\0';
1721
1722         /* Check if it is a Philips/NXP chip */
1723         if (!memcmp(name + 1, "f711", 4)) {
1724                 chip_id = name[5];
1725                 snprintf(name, CHIP_VER_SIZE, "saa711%c", chip_id);
1726
1727                 if (!autodetect && strcmp(name, id->name))
1728                         return -EINVAL;
1729
1730                 switch (chip_id) {
1731                 case '1':
1732                         if (chip_ver[0] & 0xf0) {
1733                                 snprintf(name, CHIP_VER_SIZE, "saa711%ca", chip_id);
1734                                 v4l_info(client, "saa7111a variant found\n");
1735                                 return SAA7111A;
1736                         }
1737                         return SAA7111;
1738                 case '3':
1739                         return SAA7113;
1740                 case '4':
1741                         return SAA7114;
1742                 case '5':
1743                         return SAA7115;
1744                 case '8':
1745                         return SAA7118;
1746                 default:
1747                         v4l2_info(client,
1748                                   "WARNING: Philips/NXP chip unknown - Falling back to saa7111\n");
1749                         return SAA7111;
1750                 }
1751         }
1752
1753         /* Check if it is a gm7113c */
1754         if (!memcmp(name, "0000", 4)) {
1755                 chip_id = 0;
1756                 for (i = 0; i < 4; i++) {
1757                         chip_id = chip_id << 1;
1758                         chip_id |= (chip_ver[i] & 0x80) ? 1 : 0;
1759                 }
1760
1761                 /*
1762                  * Note: From the datasheet, only versions 1 and 2
1763                  * exists. However, tests on a device labeled as:
1764                  * "GM7113C 1145" returned "10" on all 16 chip
1765                  * version (reg 0x00) reads. So, we need to also
1766                  * accept at least verion 0. For now, let's just
1767                  * assume that a device that returns "0000" for
1768                  * the lower nibble is a gm7113c.
1769                  */
1770
1771                 strlcpy(name, "gm7113c", CHIP_VER_SIZE);
1772
1773                 if (!autodetect && strcmp(name, id->name))
1774                         return -EINVAL;
1775
1776                 v4l_dbg(1, debug, client,
1777                         "It seems to be a %s chip (%*ph) @ 0x%x.\n",
1778                         name, 16, chip_ver, client->addr << 1);
1779
1780                 return GM7113C;
1781         }
1782
1783         /* Chip was not discovered. Return its ID and don't bind */
1784         v4l_dbg(1, debug, client, "chip %*ph @ 0x%x is unknown.\n",
1785                 16, chip_ver, client->addr << 1);
1786         return -ENODEV;
1787 }
1788
1789 static int saa711x_probe(struct i2c_client *client,
1790                          const struct i2c_device_id *id)
1791 {
1792         struct saa711x_state *state;
1793         struct v4l2_subdev *sd;
1794         struct v4l2_ctrl_handler *hdl;
1795         struct saa7115_platform_data *pdata;
1796         int ident;
1797         char name[CHIP_VER_SIZE + 1];
1798
1799         /* Check if the adapter supports the needed features */
1800         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1801                 return -EIO;
1802
1803         ident = saa711x_detect_chip(client, id, name);
1804         if (ident == -EINVAL) {
1805                 /* Chip exists, but doesn't match */
1806                 v4l_warn(client, "found %s while %s was expected\n",
1807                          name, id->name);
1808                 return -ENODEV;
1809         }
1810         if (ident < 0)
1811                 return ident;
1812
1813         strlcpy(client->name, name, sizeof(client->name));
1814
1815         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1816         if (state == NULL)
1817                 return -ENOMEM;
1818         sd = &state->sd;
1819         v4l2_i2c_subdev_init(sd, client, &saa711x_ops);
1820
1821         v4l_info(client, "%s found @ 0x%x (%s)\n", name,
1822                  client->addr << 1, client->adapter->name);
1823         hdl = &state->hdl;
1824         v4l2_ctrl_handler_init(hdl, 6);
1825         /* add in ascending ID order */
1826         v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1827                         V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1828         v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1829                         V4L2_CID_CONTRAST, 0, 127, 1, 64);
1830         v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1831                         V4L2_CID_SATURATION, 0, 127, 1, 64);
1832         v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1833                         V4L2_CID_HUE, -128, 127, 1, 0);
1834         state->agc = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1835                         V4L2_CID_CHROMA_AGC, 0, 1, 1, 1);
1836         state->gain = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1837                         V4L2_CID_CHROMA_GAIN, 0, 127, 1, 40);
1838         sd->ctrl_handler = hdl;
1839         if (hdl->error) {
1840                 int err = hdl->error;
1841
1842                 v4l2_ctrl_handler_free(hdl);
1843                 return err;
1844         }
1845         v4l2_ctrl_auto_cluster(2, &state->agc, 0, true);
1846
1847         state->input = -1;
1848         state->output = SAA7115_IPORT_ON;
1849         state->enable = 1;
1850         state->radio = 0;
1851         state->ident = ident;
1852
1853         state->audclk_freq = 48000;
1854
1855         v4l2_dbg(1, debug, sd, "writing init values\n");
1856
1857         /* init to 60hz/48khz */
1858         state->crystal_freq = SAA7115_FREQ_24_576_MHZ;
1859         pdata = client->dev.platform_data;
1860         switch (state->ident) {
1861         case SAA7111:
1862         case SAA7111A:
1863                 saa711x_writeregs(sd, saa7111_init);
1864                 break;
1865         case GM7113C:
1866                 saa711x_writeregs(sd, gm7113c_init);
1867                 break;
1868         case SAA7113:
1869                 if (pdata && pdata->saa7113_force_gm7113c_init)
1870                         saa711x_writeregs(sd, gm7113c_init);
1871                 else
1872                         saa711x_writeregs(sd, saa7113_init);
1873                 break;
1874         default:
1875                 state->crystal_freq = SAA7115_FREQ_32_11_MHZ;
1876                 saa711x_writeregs(sd, saa7115_init_auto_input);
1877         }
1878         if (state->ident > SAA7111A && state->ident != GM7113C)
1879                 saa711x_writeregs(sd, saa7115_init_misc);
1880
1881         if (pdata)
1882                 saa711x_write_platform_data(state, pdata);
1883
1884         saa711x_set_v4lstd(sd, V4L2_STD_NTSC);
1885         v4l2_ctrl_handler_setup(hdl);
1886
1887         v4l2_dbg(1, debug, sd, "status: (1E) 0x%02x, (1F) 0x%02x\n",
1888                 saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC),
1889                 saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC));
1890         return 0;
1891 }
1892
1893 /* ----------------------------------------------------------------------- */
1894
1895 static int saa711x_remove(struct i2c_client *client)
1896 {
1897         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1898
1899         v4l2_device_unregister_subdev(sd);
1900         v4l2_ctrl_handler_free(sd->ctrl_handler);
1901         return 0;
1902 }
1903
1904 static const struct i2c_device_id saa711x_id[] = {
1905         { "saa7115_auto", 1 }, /* autodetect */
1906         { "saa7111", 0 },
1907         { "saa7113", 0 },
1908         { "saa7114", 0 },
1909         { "saa7115", 0 },
1910         { "saa7118", 0 },
1911         { "gm7113c", 0 },
1912         { }
1913 };
1914 MODULE_DEVICE_TABLE(i2c, saa711x_id);
1915
1916 static struct i2c_driver saa711x_driver = {
1917         .driver = {
1918                 .owner  = THIS_MODULE,
1919                 .name   = "saa7115",
1920         },
1921         .probe          = saa711x_probe,
1922         .remove         = saa711x_remove,
1923         .id_table       = saa711x_id,
1924 };
1925
1926 module_i2c_driver(saa711x_driver);