1 /* saa711x - Philips SAA711x video decoder driver
2 * This driver can work with saa7111, saa7111a, saa7113, saa7114,
5 * Based on saa7114 driver by Maxim Yevtyushkin, which is based on
6 * the saa7111 driver by Dave Perks.
8 * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
9 * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com>
11 * Slight changes for video timing and attachment output by
12 * Wolfgang Scherr <scherr@net4you.net>
14 * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003)
15 * by Ronald Bultje <rbultje@ronald.bitfreak.net>
17 * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com>
20 * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl>
22 * Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
23 * SAA7111, SAA7113 and SAA7118 support
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
40 #include "saa711x_regs.h"
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/slab.h>
45 #include <linux/i2c.h>
46 #include <linux/videodev2.h>
47 #include <media/v4l2-device.h>
48 #include <media/v4l2-ctrls.h>
49 #include <media/v4l2-chip-ident.h>
50 #include <media/saa7115.h>
51 #include <asm/div64.h>
53 #define VRES_60HZ (480+16)
55 MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver");
56 MODULE_AUTHOR( "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
57 "Hans Verkuil, Mauro Carvalho Chehab");
58 MODULE_LICENSE("GPL");
61 module_param(debug, bool, 0644);
63 MODULE_PARM_DESC(debug, "Debug level (0-1)");
66 struct saa711x_state {
67 struct v4l2_subdev sd;
68 struct v4l2_ctrl_handler hdl;
71 /* chroma gain control cluster */
72 struct v4l2_ctrl *agc;
73 struct v4l2_ctrl *gain;
92 static inline struct saa711x_state *to_state(struct v4l2_subdev *sd)
94 return container_of(sd, struct saa711x_state, sd);
97 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
99 return &container_of(ctrl->handler, struct saa711x_state, hdl)->sd;
102 /* ----------------------------------------------------------------------- */
104 static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value)
106 struct i2c_client *client = v4l2_get_subdevdata(sd);
108 return i2c_smbus_write_byte_data(client, reg, value);
111 /* Sanity routine to check if a register is present */
112 static int saa711x_has_reg(const int id, const u8 reg)
114 if (id == V4L2_IDENT_SAA7111)
115 return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
116 (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e;
117 if (id == V4L2_IDENT_SAA7111A)
118 return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
119 reg != 0x14 && reg != 0x18 && reg != 0x19 &&
120 reg != 0x1d && reg != 0x1e;
122 /* common for saa7113/4/5/8 */
123 if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f ||
124 reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) ||
125 reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) ||
126 reg == 0x82 || (reg >= 0x89 && reg <= 0x8e)))
130 case V4L2_IDENT_GM7113C:
131 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && reg < 0x20;
132 case V4L2_IDENT_SAA7113:
133 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) &&
134 reg != 0x5d && reg < 0x63;
135 case V4L2_IDENT_SAA7114:
136 return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) &&
137 (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 &&
138 reg != 0x81 && reg < 0xf0;
139 case V4L2_IDENT_SAA7115:
140 return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe);
141 case V4L2_IDENT_SAA7118:
142 return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) &&
143 (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 &&
144 (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0;
149 static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs)
151 struct saa711x_state *state = to_state(sd);
152 unsigned char reg, data;
154 while (*regs != 0x00) {
158 /* According with datasheets, reserved regs should be
159 filled with 0 - seems better not to touch on they */
160 if (saa711x_has_reg(state->ident, reg)) {
161 if (saa711x_write(sd, reg, data) < 0)
164 v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg);
170 static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg)
172 struct i2c_client *client = v4l2_get_subdevdata(sd);
174 return i2c_smbus_read_byte_data(client, reg);
177 /* ----------------------------------------------------------------------- */
179 /* SAA7111 initialization table */
180 static const unsigned char saa7111_init[] = {
181 R_01_INC_DELAY, 0x00, /* reserved */
184 R_02_INPUT_CNTL_1, 0xd0, /* FUSE=3, GUDL=2, MODE=0 */
185 R_03_INPUT_CNTL_2, 0x23, /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0,
186 * GAFIX=0, GAI1=256, GAI2=256 */
187 R_04_INPUT_CNTL_3, 0x00, /* GAI1=256 */
188 R_05_INPUT_CNTL_4, 0x00, /* GAI2=256 */
191 R_06_H_SYNC_START, 0xf3, /* HSB at 13(50Hz) / 17(60Hz)
192 * pixels after end of last line */
193 R_07_H_SYNC_STOP, 0xe8, /* HSS seems to be needed to
194 * work with NTSC, too */
195 R_08_SYNC_CNTL, 0xc8, /* AUFD=1, FSEL=1, EXFIL=0,
196 * VTRC=1, HPLL=0, VNOI=0 */
197 R_09_LUMA_CNTL, 0x01, /* BYPS=0, PREF=0, BPSS=0,
198 * VBLB=0, UPTCV=0, APER=1 */
199 R_0A_LUMA_BRIGHT_CNTL, 0x80,
200 R_0B_LUMA_CONTRAST_CNTL, 0x47, /* 0b - CONT=1.109 */
201 R_0C_CHROMA_SAT_CNTL, 0x40,
202 R_0D_CHROMA_HUE_CNTL, 0x00,
203 R_0E_CHROMA_CNTL_1, 0x01, /* 0e - CDTO=0, CSTD=0, DCCF=0,
205 R_0F_CHROMA_GAIN_CNTL, 0x00, /* reserved */
206 R_10_CHROMA_CNTL_2, 0x48, /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */
207 R_11_MODE_DELAY_CNTL, 0x1c, /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1,
208 * OEYC=1, OEHV=1, VIPB=0, COLO=0 */
209 R_12_RT_SIGNAL_CNTL, 0x00, /* 12 - output control 2 */
210 R_13_RT_X_PORT_OUT_CNTL, 0x00, /* 13 - output control 3 */
211 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
212 R_15_VGATE_START_FID_CHG, 0x00,
213 R_16_VGATE_STOP, 0x00,
214 R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
219 /* SAA7113/GM7113C init codes
220 * It's important that R_14... R_17 == 0x00
221 * for the gm7113c chip to deliver stable video
223 static const unsigned char saa7113_init[] = {
224 R_01_INC_DELAY, 0x08,
225 R_02_INPUT_CNTL_1, 0xc2,
226 R_03_INPUT_CNTL_2, 0x30,
227 R_04_INPUT_CNTL_3, 0x00,
228 R_05_INPUT_CNTL_4, 0x00,
229 R_06_H_SYNC_START, 0x89,
230 R_07_H_SYNC_STOP, 0x0d,
231 R_08_SYNC_CNTL, 0x88,
232 R_09_LUMA_CNTL, 0x01,
233 R_0A_LUMA_BRIGHT_CNTL, 0x80,
234 R_0B_LUMA_CONTRAST_CNTL, 0x47,
235 R_0C_CHROMA_SAT_CNTL, 0x40,
236 R_0D_CHROMA_HUE_CNTL, 0x00,
237 R_0E_CHROMA_CNTL_1, 0x01,
238 R_0F_CHROMA_GAIN_CNTL, 0x2a,
239 R_10_CHROMA_CNTL_2, 0x08,
240 R_11_MODE_DELAY_CNTL, 0x0c,
241 R_12_RT_SIGNAL_CNTL, 0x07,
242 R_13_RT_X_PORT_OUT_CNTL, 0x00,
243 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
244 R_15_VGATE_START_FID_CHG, 0x00,
245 R_16_VGATE_STOP, 0x00,
246 R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
251 /* If a value differs from the Hauppauge driver values, then the comment starts with
252 'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
253 Hauppauge driver sets. */
255 /* SAA7114 and SAA7115 initialization table */
256 static const unsigned char saa7115_init_auto_input[] = {
258 R_01_INC_DELAY, 0x48, /* white peak control disabled */
259 R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */
260 R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */
261 R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */
263 R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */
264 R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */
265 R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */
266 R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */
267 R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */
268 R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */
269 R_0D_CHROMA_HUE_CNTL, 0x00,
270 R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */
271 R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */
272 R_11_MODE_DELAY_CNTL, 0x00,
273 R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */
274 R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */
275 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
276 R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */
277 R_19_RAW_DATA_OFF_CNTL, 0x80,
278 R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */
279 R_1B_MISC_TVVCRDET, 0x42, /* recommended value */
280 R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */
281 R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */
284 R_80_GLOBAL_CNTL_1, 0x0, /* No tasks enabled at init */
286 /* Power Device Control */
287 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */
288 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */
292 /* Used to reset saa7113, saa7114 and saa7115 */
293 static const unsigned char saa7115_cfg_reset_scaler[] = {
294 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */
295 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
296 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
297 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */
301 /* ============== SAA7715 VIDEO templates ============= */
303 static const unsigned char saa7115_cfg_60hz_video[] = {
304 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
305 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
307 R_15_VGATE_START_FID_CHG, 0x03,
308 R_16_VGATE_STOP, 0x11,
309 R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
311 R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */
312 R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */
314 R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */
317 R_90_A_TASK_HANDLING_CNTL, 0x80,
318 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
319 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
320 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
322 /* hoffset low (input), 0x0002 is minimum */
323 R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
324 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
326 /* hsize low (input), 0x02d0 = 720 */
327 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
328 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
330 R_98_A_VERT_INPUT_WINDOW_START, 0x05,
331 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
333 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
334 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
336 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
337 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
339 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
340 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
343 R_C0_B_TASK_HANDLING_CNTL, 0x00,
344 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
345 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
346 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
348 /* 0x0002 is minimum */
349 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
350 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
353 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
354 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
356 /* vwindow start 0x12 = 18 */
357 R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
358 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
360 /* vwindow length 0xf8 = 248 */
361 R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1,
362 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9,
364 /* hwindow 0x02d0 = 720 */
365 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
366 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
368 R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
369 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */
370 R_F5_PULSGEN_LINE_LENGTH, 0xad,
371 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
376 static const unsigned char saa7115_cfg_50hz_video[] = {
377 R_80_GLOBAL_CNTL_1, 0x00,
378 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
380 R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */
381 R_16_VGATE_STOP, 0x16,
382 R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
384 R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */
385 R_0E_CHROMA_CNTL_1, 0x07,
387 R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */
390 R_90_A_TASK_HANDLING_CNTL, 0x81,
391 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
392 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
393 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
395 /* This is weird: the datasheet says that you should use 2 as the minimum value, */
396 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
397 /* hoffset low (input), 0x0002 is minimum */
398 R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
399 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
401 /* hsize low (input), 0x02d0 = 720 */
402 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
403 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
405 R_98_A_VERT_INPUT_WINDOW_START, 0x03,
406 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
408 /* vsize 0x12 = 18 */
409 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
410 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
412 /* hsize 0x05a0 = 1440 */
413 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
414 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */
415 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */
416 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */
419 R_C0_B_TASK_HANDLING_CNTL, 0x00,
420 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
421 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
422 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
424 /* This is weird: the datasheet says that you should use 2 as the minimum value, */
425 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
426 /* hoffset low (input), 0x0002 is minimum. See comment above. */
427 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
428 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
430 /* hsize 0x02d0 = 720 */
431 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
432 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
434 /* voffset 0x16 = 22 */
435 R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
436 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
438 /* vsize 0x0120 = 288 */
439 R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
440 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
442 /* hsize 0x02d0 = 720 */
443 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
444 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
446 R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
447 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */
448 R_F5_PULSGEN_LINE_LENGTH, 0xb0,
449 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
454 /* ============== SAA7715 VIDEO templates (end) ======= */
456 /* ============== GM7113C VIDEO templates ============= */
457 static const unsigned char gm7113c_cfg_60hz_video[] = {
458 R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */
459 R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */
464 static const unsigned char gm7113c_cfg_50hz_video[] = {
465 R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */
466 R_0E_CHROMA_CNTL_1, 0x07,
471 /* ============== GM7113C VIDEO templates (end) ======= */
474 static const unsigned char saa7115_cfg_vbi_on[] = {
475 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
476 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
477 R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */
478 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
479 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
484 static const unsigned char saa7115_cfg_vbi_off[] = {
485 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
486 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
487 R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */
488 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
489 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
495 static const unsigned char saa7115_init_misc[] = {
496 R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
497 R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
498 R_84_I_PORT_SIGNAL_DEF, 0x20,
499 R_85_I_PORT_SIGNAL_POLAR, 0x21,
500 R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
501 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
504 R_A0_A_HORIZ_PRESCALING, 0x01,
505 R_A1_A_ACCUMULATION_LENGTH, 0x00,
506 R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
508 /* Configure controls at nominal value*/
509 R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
510 R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
511 R_A6_A_CHROMA_SATURATION_CNTL, 0x40,
513 /* note: 2 x zoom ensures that VBI lines have same length as video lines. */
514 R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
515 R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
517 R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,
519 /* must be horiz lum scaling / 2 */
520 R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
521 R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
523 /* must be offset luma / 2 */
524 R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,
526 R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
527 R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,
529 R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
530 R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
532 R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,
534 R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
535 R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
536 R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
537 R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,
539 R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
540 R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
541 R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
542 R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
545 R_D0_B_HORIZ_PRESCALING, 0x01,
546 R_D1_B_ACCUMULATION_LENGTH, 0x00,
547 R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
549 /* Configure controls at nominal value*/
550 R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
551 R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
552 R_D6_B_CHROMA_SATURATION_CNTL, 0x40,
554 /* hor lum scaling 0x0400 = 1 */
555 R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
556 R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
558 R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,
560 /* must be hor lum scaling / 2 */
561 R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
562 R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
564 /* must be offset luma / 2 */
565 R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
567 R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
568 R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
570 R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
571 R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
573 R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,
575 R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
576 R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
577 R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
578 R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,
580 R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
581 R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
582 R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
583 R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,
585 R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */
586 R_F3_PLL_INCREMENT, 0x46,
587 R_F4_PLL2_STATUS, 0x00,
588 R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */
589 R_F8_PULSE_B_POS, 0x00,
590 R_F9_PULSE_B_POS_MSB, 0x4b,
591 R_FA_PULSE_C_POS, 0x00,
592 R_FB_PULSE_C_POS_MSB, 0x4b,
594 /* PLL2 lock detection settings: 71 lines 50% phase error */
595 R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
598 R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */
600 R_41_LCR_BASE+1, 0xff,
601 R_41_LCR_BASE+2, 0xff,
602 R_41_LCR_BASE+3, 0xff,
603 R_41_LCR_BASE+4, 0xff,
604 R_41_LCR_BASE+5, 0xff,
605 R_41_LCR_BASE+6, 0xff,
606 R_41_LCR_BASE+7, 0xff,
607 R_41_LCR_BASE+8, 0xff,
608 R_41_LCR_BASE+9, 0xff,
609 R_41_LCR_BASE+10, 0xff,
610 R_41_LCR_BASE+11, 0xff,
611 R_41_LCR_BASE+12, 0xff,
612 R_41_LCR_BASE+13, 0xff,
613 R_41_LCR_BASE+14, 0xff,
614 R_41_LCR_BASE+15, 0xff,
615 R_41_LCR_BASE+16, 0xff,
616 R_41_LCR_BASE+17, 0xff,
617 R_41_LCR_BASE+18, 0xff,
618 R_41_LCR_BASE+19, 0xff,
619 R_41_LCR_BASE+20, 0xff,
620 R_41_LCR_BASE+21, 0xff,
621 R_41_LCR_BASE+22, 0xff,
622 R_58_PROGRAM_FRAMING_CODE, 0x40,
623 R_59_H_OFF_FOR_SLICER, 0x47,
624 R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
628 R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */
630 R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */
631 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
632 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
636 static int saa711x_odd_parity(u8 c)
645 static int saa711x_decode_vps(u8 *dst, u8 *p)
647 static const u8 biphase_tbl[] = {
648 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
649 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
650 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
651 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
652 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
653 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
654 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
655 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
656 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
657 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
658 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
659 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
660 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
661 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
662 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
663 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
664 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
665 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
666 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
667 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
668 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
669 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
670 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
671 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
672 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
673 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
674 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
675 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
676 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
677 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
678 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
679 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
684 for (i = 0; i < 2 * 13; i += 2) {
685 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
686 c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4);
692 static int saa711x_decode_wss(u8 *p)
694 static const int wss_bits[8] = {
695 0, 0, 0, 1, 0, 1, 1, 1
697 unsigned char parity;
701 for (i = 0; i < 16; i++) {
702 int b1 = wss_bits[p[i] & 7];
703 int b2 = wss_bits[(p[i] >> 3) & 7];
710 parity ^= parity >> 2;
711 parity ^= parity >> 1;
719 static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
721 struct saa711x_state *state = to_state(sd);
726 u8 acc = 0; /* reg 0x3a, audio clock control */
728 /* Checks for chips that don't have audio clock (saa7111, saa7113) */
729 if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD))
732 v4l2_dbg(1, debug, sd, "set audio clock freq: %d\n", freq);
735 if (freq < 32000 || freq > 48000)
738 /* hz is the refresh rate times 100 */
739 hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
740 /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
741 acpf = (25600 * freq) / hz;
742 /* acni = (256 * freq * 2^23) / crystal_frequency =
743 (freq * 2^(8+23)) / crystal_frequency =
744 (freq << 31) / crystal_frequency */
747 do_div(f, state->crystal_freq);
750 acpf = acpf * state->cgcdiv / 16;
751 acni = acni * state->cgcdiv / 16;
753 if (state->cgcdiv == 3)
759 if (state->double_asclk) {
763 saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
764 saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk);
765 saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
767 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
768 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
770 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
771 (acpf >> 16) & 0x03);
773 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
774 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
775 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
776 state->audclk_freq = freq;
780 static int saa711x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
782 struct v4l2_subdev *sd = to_sd(ctrl);
783 struct saa711x_state *state = to_state(sd);
786 case V4L2_CID_CHROMA_AGC:
787 /* chroma gain cluster */
790 saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f;
796 static int saa711x_s_ctrl(struct v4l2_ctrl *ctrl)
798 struct v4l2_subdev *sd = to_sd(ctrl);
799 struct saa711x_state *state = to_state(sd);
802 case V4L2_CID_BRIGHTNESS:
803 saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val);
806 case V4L2_CID_CONTRAST:
807 saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val);
810 case V4L2_CID_SATURATION:
811 saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val);
815 saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val);
818 case V4L2_CID_CHROMA_AGC:
819 /* chroma gain cluster */
821 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val);
823 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80);
833 static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height)
835 struct saa711x_state *state = to_state(sd);
839 int is_50hz = state->std & V4L2_STD_625_50;
840 int Vsrc = is_50hz ? 576 : 480;
842 v4l2_dbg(1, debug, sd, "decoder set size to %ix%i\n", width, height);
844 /* FIXME need better bounds checking here */
845 if ((width < 1) || (width > 1440))
847 if ((height < 1) || (height > Vsrc))
850 if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) {
851 /* Decoder only supports 720 columns and 480 or 576 lines */
858 state->width = width;
859 state->height = height;
861 if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH))
864 /* probably have a valid size, let's set it */
865 /* Set output width/height */
868 saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
869 (u8) (width & 0xff));
870 saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
871 (u8) ((width >> 8) & 0xff));
873 /* Vertical Scaling uses height/2 */
876 /* On 60Hz, it is using a higher Vertical Output Size */
878 res += (VRES_60HZ - 480) >> 1;
881 saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
883 saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
884 (u8) ((res >> 8) & 0xff));
886 /* Scaling settings */
887 /* Hprescaler is floor(inres/outres) */
888 HPSC = (int)(720 / width);
889 /* 0 is not allowed (div. by zero) */
890 HPSC = HPSC ? HPSC : 1;
891 HFSC = (int)((1024 * 720) / (HPSC * width));
892 /* FIXME hardcodes to "Task B"
893 * write H prescaler integer */
894 saa711x_write(sd, R_D0_B_HORIZ_PRESCALING,
897 v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
898 /* write H fine-scaling (luminance) */
899 saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC,
901 saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
902 (u8) ((HFSC >> 8) & 0xff));
903 /* write H fine-scaling (chrominance)
904 * must be lum/2, so i'll just bitshift :) */
905 saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING,
906 (u8) ((HFSC >> 1) & 0xff));
907 saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
908 (u8) ((HFSC >> 9) & 0xff));
910 VSCY = (int)((1024 * Vsrc) / height);
911 v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
913 /* Correct Contrast and Luminance */
914 saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL,
915 (u8) (64 * 1024 / VSCY));
916 saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL,
917 (u8) (64 * 1024 / VSCY));
919 /* write V fine-scaling (luminance) */
920 saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC,
922 saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
923 (u8) ((VSCY >> 8) & 0xff));
924 /* write V fine-scaling (chrominance) */
925 saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC,
927 saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
928 (u8) ((VSCY >> 8) & 0xff));
930 saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
932 /* Activates task "B" */
933 saa711x_write(sd, R_80_GLOBAL_CNTL_1,
934 saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20);
939 static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std)
941 struct saa711x_state *state = to_state(sd);
943 /* Prevent unnecessary standard changes. During a standard
944 change the I-Port is temporarily disabled. Any devices
945 reading from that port can get confused.
946 Note that s_std is also used to switch from
947 radio to TV mode, so if a s_std is broadcast to
948 all I2C devices then you do not want to have an unwanted
950 if (std == state->std)
955 // This works for NTSC-M, SECAM-L and the 50Hz PAL variants.
956 if (std & V4L2_STD_525_60) {
957 v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz\n");
958 if (state->ident == V4L2_IDENT_GM7113C)
959 saa711x_writeregs(sd, gm7113c_cfg_60hz_video);
961 saa711x_writeregs(sd, saa7115_cfg_60hz_video);
962 saa711x_set_size(sd, 720, 480);
964 v4l2_dbg(1, debug, sd, "decoder set standard 50 Hz\n");
965 if (state->ident == V4L2_IDENT_GM7113C)
966 saa711x_writeregs(sd, gm7113c_cfg_50hz_video);
968 saa711x_writeregs(sd, saa7115_cfg_50hz_video);
969 saa711x_set_size(sd, 720, 576);
972 /* Register 0E - Bits D6-D4 on NO-AUTO mode
973 (SAA7111 and SAA7113 doesn't have auto mode)
974 50 Hz / 625 lines 60 Hz / 525 lines
975 000 PAL BGDHI (4.43Mhz) NTSC M (3.58MHz)
976 001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz)
977 010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz)
978 011 NTSC N (3.58MHz) PAL M (3.58MHz)
979 100 reserved NTSC-Japan (3.58MHz)
981 if (state->ident <= V4L2_IDENT_SAA7113 ||
982 state->ident == V4L2_IDENT_GM7113C) {
983 u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f;
985 if (std == V4L2_STD_PAL_M) {
987 } else if (std == V4L2_STD_PAL_Nc) {
989 } else if (std == V4L2_STD_PAL_60) {
991 } else if (std == V4L2_STD_NTSC_M_JP) {
993 } else if (std & V4L2_STD_SECAM) {
996 saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg);
998 /* restart task B if needed */
999 int taskb = saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10;
1001 if (taskb && state->ident == V4L2_IDENT_SAA7114) {
1002 saa711x_writeregs(sd, saa7115_cfg_vbi_on);
1005 /* switch audio mode too! */
1006 saa711x_s_clock_freq(sd, state->audclk_freq);
1010 /* setup the sliced VBI lcr registers according to the sliced VBI format */
1011 static void saa711x_set_lcr(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
1013 struct saa711x_state *state = to_state(sd);
1014 int is_50hz = (state->std & V4L2_STD_625_50);
1019 /* saa7113/7114/7118 VBI support are experimental */
1020 if (!saa711x_has_reg(state->ident, R_41_LCR_BASE))
1024 /* SAA7113 and SAA7118 also should support VBI - Need testing */
1025 if (state->ident != V4L2_IDENT_SAA7115)
1029 for (i = 0; i <= 23; i++)
1035 for (i = 6; i <= 23; i++)
1038 for (i = 10; i <= 21; i++)
1042 /* first clear lines that cannot be captured */
1044 for (i = 0; i <= 5; i++)
1045 fmt->service_lines[0][i] =
1046 fmt->service_lines[1][i] = 0;
1049 for (i = 0; i <= 9; i++)
1050 fmt->service_lines[0][i] =
1051 fmt->service_lines[1][i] = 0;
1052 for (i = 22; i <= 23; i++)
1053 fmt->service_lines[0][i] =
1054 fmt->service_lines[1][i] = 0;
1057 /* Now set the lcr values according to the specified service */
1058 for (i = 6; i <= 23; i++) {
1060 for (x = 0; x <= 1; x++) {
1061 switch (fmt->service_lines[1-x][i]) {
1063 lcr[i] |= 0xf << (4 * x);
1065 case V4L2_SLICED_TELETEXT_B:
1066 lcr[i] |= 1 << (4 * x);
1068 case V4L2_SLICED_CAPTION_525:
1069 lcr[i] |= 4 << (4 * x);
1071 case V4L2_SLICED_WSS_625:
1072 lcr[i] |= 5 << (4 * x);
1074 case V4L2_SLICED_VPS:
1075 lcr[i] |= 7 << (4 * x);
1082 /* write the lcr registers */
1083 for (i = 2; i <= 23; i++) {
1084 saa711x_write(sd, i - 2 + R_41_LCR_BASE, lcr[i]);
1087 /* enable/disable raw VBI capturing */
1088 saa711x_writeregs(sd, fmt == NULL ?
1089 saa7115_cfg_vbi_on :
1090 saa7115_cfg_vbi_off);
1093 static int saa711x_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *sliced)
1095 static u16 lcr2vbi[] = {
1096 0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */
1097 0, V4L2_SLICED_CAPTION_525, /* 4 */
1098 V4L2_SLICED_WSS_625, 0, /* 5 */
1099 V4L2_SLICED_VPS, 0, 0, 0, 0, /* 7 */
1104 memset(sliced->service_lines, 0, sizeof(sliced->service_lines));
1105 sliced->service_set = 0;
1106 /* done if using raw VBI */
1107 if (saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10)
1109 for (i = 2; i <= 23; i++) {
1110 u8 v = saa711x_read(sd, i - 2 + R_41_LCR_BASE);
1112 sliced->service_lines[0][i] = lcr2vbi[v >> 4];
1113 sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
1114 sliced->service_set |=
1115 sliced->service_lines[0][i] | sliced->service_lines[1][i];
1120 static int saa711x_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
1122 saa711x_set_lcr(sd, NULL);
1126 static int saa711x_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
1128 saa711x_set_lcr(sd, fmt);
1132 static int saa711x_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
1134 if (fmt->code != V4L2_MBUS_FMT_FIXED)
1136 fmt->field = V4L2_FIELD_INTERLACED;
1137 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1138 return saa711x_set_size(sd, fmt->width, fmt->height);
1141 /* Decode the sliced VBI data stream as created by the saa7115.
1142 The format is described in the saa7115 datasheet in Tables 25 and 26
1144 The current implementation uses SAV/EAV codes and not the ancillary data
1145 headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV
1147 static int saa711x_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi)
1149 struct saa711x_state *state = to_state(sd);
1150 static const char vbi_no_data_pattern[] = {
1151 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0
1155 int id1, id2; /* the ID1 and ID2 bytes from the internal header */
1157 vbi->type = 0; /* mark result as a failure */
1160 /* Note: the field bit is inverted for 60 Hz video */
1161 if (state->std & V4L2_STD_525_60)
1164 /* Skip internal header, p now points to the start of the payload */
1168 /* calculate field and line number of the VBI packet (1-23) */
1169 vbi->is_second_field = ((id1 & 0x40) != 0);
1170 vbi->line = (id1 & 0x3f) << 3;
1171 vbi->line |= (id2 & 0x70) >> 4;
1173 /* Obtain data type */
1176 /* If the VBI slicer does not detect any signal it will fill up
1177 the payload buffer with 0xa0 bytes. */
1178 if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern)))
1181 /* decode payloads */
1184 vbi->type = V4L2_SLICED_TELETEXT_B;
1187 if (!saa711x_odd_parity(p[0]) || !saa711x_odd_parity(p[1]))
1189 vbi->type = V4L2_SLICED_CAPTION_525;
1192 wss = saa711x_decode_wss(p);
1197 vbi->type = V4L2_SLICED_WSS_625;
1200 if (saa711x_decode_vps(p, p) != 0)
1202 vbi->type = V4L2_SLICED_VPS;
1210 /* ============ SAA7115 AUDIO settings (end) ============= */
1212 static int saa711x_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1214 struct saa711x_state *state = to_state(sd);
1219 status = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1221 v4l2_dbg(1, debug, sd, "status: 0x%02x\n", status);
1222 vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
1226 static int saa711x_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1228 struct saa711x_state *state = to_state(sd);
1231 saa711x_set_v4lstd(sd, std);
1235 static int saa711x_s_radio(struct v4l2_subdev *sd)
1237 struct saa711x_state *state = to_state(sd);
1243 static int saa711x_s_routing(struct v4l2_subdev *sd,
1244 u32 input, u32 output, u32 config)
1246 struct saa711x_state *state = to_state(sd);
1247 u8 mask = (state->ident <= V4L2_IDENT_SAA7111A) ? 0xf8 : 0xf0;
1249 v4l2_dbg(1, debug, sd, "decoder set input %d output %d\n",
1252 /* saa7111/3 does not have these inputs */
1253 if ((state->ident <= V4L2_IDENT_SAA7113 ||
1254 state->ident == V4L2_IDENT_GM7113C) &&
1255 (input == SAA7115_COMPOSITE4 ||
1256 input == SAA7115_COMPOSITE5)) {
1259 if (input > SAA7115_SVIDEO3)
1261 if (state->input == input && state->output == output)
1263 v4l2_dbg(1, debug, sd, "now setting %s input %s output\n",
1264 (input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite",
1265 (output == SAA7115_IPORT_ON) ? "iport on" : "iport off");
1266 state->input = input;
1268 /* saa7111 has slightly different input numbering */
1269 if (state->ident <= V4L2_IDENT_SAA7111A) {
1270 if (input >= SAA7115_COMPOSITE4)
1272 /* saa7111 specific */
1273 saa711x_write(sd, R_10_CHROMA_CNTL_2,
1274 (saa711x_read(sd, R_10_CHROMA_CNTL_2) & 0x3f) |
1275 ((output & 0xc0) ^ 0x40));
1276 saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL,
1277 (saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL) & 0xf0) |
1278 ((output & 2) ? 0x0a : 0));
1282 saa711x_write(sd, R_02_INPUT_CNTL_1,
1283 (saa711x_read(sd, R_02_INPUT_CNTL_1) & mask) |
1286 /* bypass chrominance trap for S-Video modes */
1287 saa711x_write(sd, R_09_LUMA_CNTL,
1288 (saa711x_read(sd, R_09_LUMA_CNTL) & 0x7f) |
1289 (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
1291 state->output = output;
1292 if (state->ident == V4L2_IDENT_SAA7114 ||
1293 state->ident == V4L2_IDENT_SAA7115) {
1294 saa711x_write(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK,
1295 (saa711x_read(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK) & 0xfe) |
1296 (state->output & 0x01));
1298 if (state->ident > V4L2_IDENT_SAA7111A) {
1299 if (config & SAA7115_IDQ_IS_DEFAULT)
1300 saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x20);
1302 saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x21);
1307 static int saa711x_s_gpio(struct v4l2_subdev *sd, u32 val)
1309 struct saa711x_state *state = to_state(sd);
1311 if (state->ident > V4L2_IDENT_SAA7111A)
1313 saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) |
1318 static int saa711x_s_stream(struct v4l2_subdev *sd, int enable)
1320 struct saa711x_state *state = to_state(sd);
1322 v4l2_dbg(1, debug, sd, "%s output\n",
1323 enable ? "enable" : "disable");
1325 if (state->enable == enable)
1327 state->enable = enable;
1328 if (!saa711x_has_reg(state->ident, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED))
1330 saa711x_write(sd, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, state->enable);
1334 static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags)
1336 struct saa711x_state *state = to_state(sd);
1338 if (freq != SAA7115_FREQ_32_11_MHZ && freq != SAA7115_FREQ_24_576_MHZ)
1340 state->crystal_freq = freq;
1341 state->double_asclk = flags & SAA7115_FREQ_FL_DOUBLE_ASCLK;
1342 state->cgcdiv = (flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4;
1343 state->ucgc = flags & SAA7115_FREQ_FL_UCGC;
1344 state->apll = flags & SAA7115_FREQ_FL_APLL;
1345 saa711x_s_clock_freq(sd, state->audclk_freq);
1349 static int saa711x_reset(struct v4l2_subdev *sd, u32 val)
1351 v4l2_dbg(1, debug, sd, "decoder RESET\n");
1352 saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
1356 static int saa711x_g_vbi_data(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_data *data)
1358 /* Note: the internal field ID is inverted for NTSC,
1359 so data->field 0 maps to the saa7115 even field,
1360 whereas for PAL it maps to the saa7115 odd field. */
1362 case V4L2_SLICED_WSS_625:
1363 if (saa711x_read(sd, 0x6b) & 0xc0)
1365 data->data[0] = saa711x_read(sd, 0x6c);
1366 data->data[1] = saa711x_read(sd, 0x6d);
1368 case V4L2_SLICED_CAPTION_525:
1369 if (data->field == 0) {
1371 if (saa711x_read(sd, 0x66) & 0x30)
1373 data->data[0] = saa711x_read(sd, 0x69);
1374 data->data[1] = saa711x_read(sd, 0x6a);
1378 if (saa711x_read(sd, 0x66) & 0xc0)
1380 data->data[0] = saa711x_read(sd, 0x67);
1381 data->data[1] = saa711x_read(sd, 0x68);
1388 static int saa711x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
1390 struct saa711x_state *state = to_state(sd);
1394 * The V4L2 core already initializes std with all supported
1395 * Standards. All driver needs to do is to mask it, to remove
1396 * standards that don't apply from the mask
1399 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1401 if (state->ident == V4L2_IDENT_SAA7115) {
1402 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1404 v4l2_dbg(1, debug, sd, "Status byte 1 (0x1e)=0x%02x\n", reg1e);
1406 switch (reg1e & 0x03) {
1408 *std &= V4L2_STD_NTSC;
1412 * V4L2_STD_PAL just cover the european PAL standards.
1413 * This is wrong, as the device could also be using an
1414 * other PAL standard.
1416 *std &= V4L2_STD_PAL | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc |
1417 V4L2_STD_PAL_M | V4L2_STD_PAL_60;
1420 *std &= V4L2_STD_SECAM;
1423 /* Can't detect anything */
1428 v4l2_dbg(1, debug, sd, "Status byte 2 (0x1f)=0x%02x\n", reg1f);
1430 /* horizontal/vertical not locked */
1435 *std &= V4L2_STD_525_60;
1437 *std &= V4L2_STD_625_50;
1440 v4l2_dbg(1, debug, sd, "detected std mask = %08Lx\n", *std);
1445 static int saa711x_g_input_status(struct v4l2_subdev *sd, u32 *status)
1447 struct saa711x_state *state = to_state(sd);
1451 *status = V4L2_IN_ST_NO_SIGNAL;
1452 if (state->ident == V4L2_IDENT_SAA7115)
1453 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1454 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1455 if ((reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80)
1460 #ifdef CONFIG_VIDEO_ADV_DEBUG
1461 static int saa711x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1463 struct i2c_client *client = v4l2_get_subdevdata(sd);
1465 if (!v4l2_chip_match_i2c_client(client, ®->match))
1467 reg->val = saa711x_read(sd, reg->reg & 0xff);
1472 static int saa711x_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1474 struct i2c_client *client = v4l2_get_subdevdata(sd);
1476 if (!v4l2_chip_match_i2c_client(client, ®->match))
1478 saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff);
1483 static int saa711x_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
1485 struct saa711x_state *state = to_state(sd);
1486 struct i2c_client *client = v4l2_get_subdevdata(sd);
1488 return v4l2_chip_ident_i2c_client(client, chip, state->ident, 0);
1491 static int saa711x_log_status(struct v4l2_subdev *sd)
1493 struct saa711x_state *state = to_state(sd);
1498 v4l2_info(sd, "Audio frequency: %d Hz\n", state->audclk_freq);
1499 if (state->ident != V4L2_IDENT_SAA7115) {
1500 /* status for the saa7114 */
1501 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1502 signalOk = (reg1f & 0xc1) == 0x81;
1503 v4l2_info(sd, "Video signal: %s\n", signalOk ? "ok" : "bad");
1504 v4l2_info(sd, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
1508 /* status for the saa7115 */
1509 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1510 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1512 signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
1513 vcr = !(reg1f & 0x10);
1515 if (state->input >= 6)
1516 v4l2_info(sd, "Input: S-Video %d\n", state->input - 6);
1518 v4l2_info(sd, "Input: Composite %d\n", state->input);
1519 v4l2_info(sd, "Video signal: %s\n", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad");
1520 v4l2_info(sd, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
1522 switch (reg1e & 0x03) {
1524 v4l2_info(sd, "Detected format: NTSC\n");
1527 v4l2_info(sd, "Detected format: PAL\n");
1530 v4l2_info(sd, "Detected format: SECAM\n");
1533 v4l2_info(sd, "Detected format: BW/No color\n");
1536 v4l2_info(sd, "Width, Height: %d, %d\n", state->width, state->height);
1537 v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
1541 /* ----------------------------------------------------------------------- */
1543 static const struct v4l2_ctrl_ops saa711x_ctrl_ops = {
1544 .s_ctrl = saa711x_s_ctrl,
1545 .g_volatile_ctrl = saa711x_g_volatile_ctrl,
1548 static const struct v4l2_subdev_core_ops saa711x_core_ops = {
1549 .log_status = saa711x_log_status,
1550 .g_chip_ident = saa711x_g_chip_ident,
1551 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1552 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1553 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1554 .g_ctrl = v4l2_subdev_g_ctrl,
1555 .s_ctrl = v4l2_subdev_s_ctrl,
1556 .queryctrl = v4l2_subdev_queryctrl,
1557 .querymenu = v4l2_subdev_querymenu,
1558 .s_std = saa711x_s_std,
1559 .reset = saa711x_reset,
1560 .s_gpio = saa711x_s_gpio,
1561 #ifdef CONFIG_VIDEO_ADV_DEBUG
1562 .g_register = saa711x_g_register,
1563 .s_register = saa711x_s_register,
1567 static const struct v4l2_subdev_tuner_ops saa711x_tuner_ops = {
1568 .s_radio = saa711x_s_radio,
1569 .g_tuner = saa711x_g_tuner,
1572 static const struct v4l2_subdev_audio_ops saa711x_audio_ops = {
1573 .s_clock_freq = saa711x_s_clock_freq,
1576 static const struct v4l2_subdev_video_ops saa711x_video_ops = {
1577 .s_routing = saa711x_s_routing,
1578 .s_crystal_freq = saa711x_s_crystal_freq,
1579 .s_mbus_fmt = saa711x_s_mbus_fmt,
1580 .s_stream = saa711x_s_stream,
1581 .querystd = saa711x_querystd,
1582 .g_input_status = saa711x_g_input_status,
1585 static const struct v4l2_subdev_vbi_ops saa711x_vbi_ops = {
1586 .g_vbi_data = saa711x_g_vbi_data,
1587 .decode_vbi_line = saa711x_decode_vbi_line,
1588 .g_sliced_fmt = saa711x_g_sliced_fmt,
1589 .s_sliced_fmt = saa711x_s_sliced_fmt,
1590 .s_raw_fmt = saa711x_s_raw_fmt,
1593 static const struct v4l2_subdev_ops saa711x_ops = {
1594 .core = &saa711x_core_ops,
1595 .tuner = &saa711x_tuner_ops,
1596 .audio = &saa711x_audio_ops,
1597 .video = &saa711x_video_ops,
1598 .vbi = &saa711x_vbi_ops,
1601 #define CHIP_VER_SIZE 16
1603 /* ----------------------------------------------------------------------- */
1606 * saa711x_detect_chip - Detects the saa711x (or clone) variant
1607 * @client: I2C client structure.
1608 * @id: I2C device ID structure.
1609 * @name: Name of the device to be filled.
1611 * Detects the Philips/NXP saa711x chip, or some clone of it.
1612 * if 'id' is NULL or id->driver_data is equal to 1, it auto-probes
1614 * If the tuner is not found, it returns -ENODEV.
1615 * If auto-detection is disabled and the tuner doesn't match what it was
1616 * requred, it returns -EINVAL and fills 'name'.
1617 * If the chip is found, it returns the chip ID and fills 'name'.
1619 static int saa711x_detect_chip(struct i2c_client *client,
1620 const struct i2c_device_id *id,
1623 char chip_ver[CHIP_VER_SIZE];
1628 autodetect = !id || id->driver_data == 1;
1630 /* Read the chip version register */
1631 for (i = 0; i < CHIP_VER_SIZE; i++) {
1632 i2c_smbus_write_byte_data(client, 0, i);
1633 chip_ver[i] = i2c_smbus_read_byte_data(client, 0);
1634 name[i] = (chip_ver[i] & 0x0f) + '0';
1636 name[i] += 'a' - '9' - 1;
1640 /* Check if it is a Philips/NXP chip */
1641 if (!memcmp(name + 1, "f711", 4)) {
1643 snprintf(name, CHIP_VER_SIZE, "saa711%c", chip_id);
1645 if (!autodetect && strcmp(name, id->name))
1650 if (chip_ver[0] & 0xf0) {
1651 snprintf(name, CHIP_VER_SIZE, "saa711%ca", chip_id);
1652 v4l_info(client, "saa7111a variant found\n");
1653 return V4L2_IDENT_SAA7111A;
1655 return V4L2_IDENT_SAA7111;
1657 return V4L2_IDENT_SAA7113;
1659 return V4L2_IDENT_SAA7114;
1661 return V4L2_IDENT_SAA7115;
1663 return V4L2_IDENT_SAA7118;
1666 "WARNING: Philips/NXP chip unknown - Falling back to saa7111\n");
1667 return V4L2_IDENT_SAA7111;
1671 /* Check if it is a gm7113c */
1672 if (!memcmp(name, "0000", 4)) {
1674 for (i = 0; i < 4; i++) {
1675 chip_id = chip_id << 1;
1676 chip_id |= (chip_ver[i] & 0x80) ? 1 : 0;
1680 * Note: From the datasheet, only versions 1 and 2
1681 * exists. However, tests on a device labeled as:
1682 * "GM7113C 1145" returned "10" on all 16 chip
1683 * version (reg 0x00) reads. So, we need to also
1684 * accept at least verion 0. For now, let's just
1685 * assume that a device that returns "0000" for
1686 * the lower nibble is a gm7113c.
1689 strlcpy(name, "gm7113c", CHIP_VER_SIZE);
1691 if (!autodetect && strcmp(name, id->name))
1694 v4l_dbg(1, debug, client,
1695 "It seems to be a %s chip (%*ph) @ 0x%x.\n",
1696 name, 16, chip_ver, client->addr << 1);
1698 return V4L2_IDENT_GM7113C;
1701 /* Chip was not discovered. Return its ID and don't bind */
1702 v4l_dbg(1, debug, client, "chip %*ph @ 0x%x is unknown.\n",
1703 16, chip_ver, client->addr << 1);
1707 static int saa711x_probe(struct i2c_client *client,
1708 const struct i2c_device_id *id)
1710 struct saa711x_state *state;
1711 struct v4l2_subdev *sd;
1712 struct v4l2_ctrl_handler *hdl;
1714 char name[CHIP_VER_SIZE + 1];
1716 /* Check if the adapter supports the needed features */
1717 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1720 ident = saa711x_detect_chip(client, id, name);
1721 if (ident == -EINVAL) {
1722 /* Chip exists, but doesn't match */
1723 v4l_warn(client, "found %s while %s was expected\n",
1730 strlcpy(client->name, name, sizeof(client->name));
1732 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1736 v4l2_i2c_subdev_init(sd, client, &saa711x_ops);
1739 v4l2_ctrl_handler_init(hdl, 6);
1740 /* add in ascending ID order */
1741 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1742 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1743 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1744 V4L2_CID_CONTRAST, 0, 127, 1, 64);
1745 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1746 V4L2_CID_SATURATION, 0, 127, 1, 64);
1747 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1748 V4L2_CID_HUE, -128, 127, 1, 0);
1749 state->agc = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1750 V4L2_CID_CHROMA_AGC, 0, 1, 1, 1);
1751 state->gain = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1752 V4L2_CID_CHROMA_GAIN, 0, 127, 1, 40);
1753 sd->ctrl_handler = hdl;
1755 int err = hdl->error;
1757 v4l2_ctrl_handler_free(hdl);
1760 v4l2_ctrl_auto_cluster(2, &state->agc, 0, true);
1763 state->output = SAA7115_IPORT_ON;
1766 state->ident = ident;
1768 state->audclk_freq = 48000;
1770 v4l2_dbg(1, debug, sd, "writing init values\n");
1772 /* init to 60hz/48khz */
1773 state->crystal_freq = SAA7115_FREQ_24_576_MHZ;
1774 switch (state->ident) {
1775 case V4L2_IDENT_SAA7111:
1776 case V4L2_IDENT_SAA7111A:
1777 saa711x_writeregs(sd, saa7111_init);
1779 case V4L2_IDENT_GM7113C:
1780 case V4L2_IDENT_SAA7113:
1781 saa711x_writeregs(sd, saa7113_init);
1784 state->crystal_freq = SAA7115_FREQ_32_11_MHZ;
1785 saa711x_writeregs(sd, saa7115_init_auto_input);
1787 if (state->ident > V4L2_IDENT_SAA7111A)
1788 saa711x_writeregs(sd, saa7115_init_misc);
1789 saa711x_set_v4lstd(sd, V4L2_STD_NTSC);
1790 v4l2_ctrl_handler_setup(hdl);
1792 v4l2_dbg(1, debug, sd, "status: (1E) 0x%02x, (1F) 0x%02x\n",
1793 saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC),
1794 saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC));
1798 /* ----------------------------------------------------------------------- */
1800 static int saa711x_remove(struct i2c_client *client)
1802 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1804 v4l2_device_unregister_subdev(sd);
1805 v4l2_ctrl_handler_free(sd->ctrl_handler);
1809 static const struct i2c_device_id saa711x_id[] = {
1810 { "saa7115_auto", 1 }, /* autodetect */
1819 MODULE_DEVICE_TABLE(i2c, saa711x_id);
1821 static struct i2c_driver saa711x_driver = {
1823 .owner = THIS_MODULE,
1826 .probe = saa711x_probe,
1827 .remove = saa711x_remove,
1828 .id_table = saa711x_id,
1831 module_i2c_driver(saa711x_driver);