2 * mt9t112 Camera Driver
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 * Based on ov772x driver, mt9m111 driver,
9 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
11 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
12 * Copyright (C) 2008 Magnus Damm
13 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/delay.h>
21 #include <linux/i2c.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/v4l2-mediabus.h>
26 #include <linux/videodev2.h>
28 #include <media/mt9t112.h>
29 #include <media/soc_camera.h>
30 #include <media/v4l2-chip-ident.h>
31 #include <media/v4l2-common.h>
33 /* you can check PLL/clock info */
34 /* #define EXT_CLOCK 24000000 */
36 /************************************************************************
38 ************************************************************************/
42 #define MAX_WIDTH 2048
43 #define MAX_HEIGHT 1536
46 #define VGA_HEIGHT 480
51 #define ECHECKER(ret, x) \
58 #define mt9t112_reg_write(ret, client, a, b) \
59 ECHECKER(ret, __mt9t112_reg_write(client, a, b))
60 #define mt9t112_mcu_write(ret, client, a, b) \
61 ECHECKER(ret, __mt9t112_mcu_write(client, a, b))
63 #define mt9t112_reg_mask_set(ret, client, a, b, c) \
64 ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c))
65 #define mt9t112_mcu_mask_set(ret, client, a, b, c) \
66 ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c))
68 #define mt9t112_reg_read(ret, client, a) \
69 ECHECKER(ret, __mt9t112_reg_read(client, a))
74 #define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff))
75 #define VAR(id, offset) _VAR(id, offset, 0x0000)
76 #define VAR8(id, offset) _VAR(id, offset, 0x8000)
78 /************************************************************************
80 ************************************************************************/
81 struct mt9t112_format {
82 enum v4l2_mbus_pixelcode code;
83 enum v4l2_colorspace colorspace;
89 struct v4l2_subdev subdev;
90 struct mt9t112_camera_info *info;
91 struct i2c_client *client;
92 struct v4l2_rect frame;
93 const struct mt9t112_format *format;
98 #define INIT_DONE (1 << 0)
99 #define PCLK_RISING (1 << 1)
102 /************************************************************************
104 ************************************************************************/
106 static const struct mt9t112_format mt9t112_cfmts[] = {
108 .code = V4L2_MBUS_FMT_UYVY8_2X8,
109 .colorspace = V4L2_COLORSPACE_JPEG,
113 .code = V4L2_MBUS_FMT_VYUY8_2X8,
114 .colorspace = V4L2_COLORSPACE_JPEG,
118 .code = V4L2_MBUS_FMT_YUYV8_2X8,
119 .colorspace = V4L2_COLORSPACE_JPEG,
123 .code = V4L2_MBUS_FMT_YVYU8_2X8,
124 .colorspace = V4L2_COLORSPACE_JPEG,
128 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
129 .colorspace = V4L2_COLORSPACE_SRGB,
133 .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
134 .colorspace = V4L2_COLORSPACE_SRGB,
140 /************************************************************************
142 ************************************************************************/
143 static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client)
145 return container_of(i2c_get_clientdata(client),
150 static int __mt9t112_reg_read(const struct i2c_client *client, u16 command)
152 struct i2c_msg msg[2];
156 command = swab16(command);
158 msg[0].addr = client->addr;
161 msg[0].buf = (u8 *)&command;
163 msg[1].addr = client->addr;
164 msg[1].flags = I2C_M_RD;
169 * if return value of this function is < 0,
171 * else, under 16bit is valid data.
173 ret = i2c_transfer(client->adapter, msg, 2);
177 memcpy(&ret, buf, 2);
181 static int __mt9t112_reg_write(const struct i2c_client *client,
182 u16 command, u16 data)
188 command = swab16(command);
191 memcpy(buf + 0, &command, 2);
192 memcpy(buf + 2, &data, 2);
194 msg.addr = client->addr;
200 * i2c_transfer return message length,
201 * but this function should return 0 if correct case
203 ret = i2c_transfer(client->adapter, &msg, 1);
210 static int __mt9t112_reg_mask_set(const struct i2c_client *client,
215 int val = __mt9t112_reg_read(client, command);
222 return __mt9t112_reg_write(client, command, val);
226 static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command)
230 ret = __mt9t112_reg_write(client, 0x098E, command);
234 return __mt9t112_reg_read(client, 0x0990);
237 static int __mt9t112_mcu_write(const struct i2c_client *client,
238 u16 command, u16 data)
242 ret = __mt9t112_reg_write(client, 0x098E, command);
246 return __mt9t112_reg_write(client, 0x0990, data);
249 static int __mt9t112_mcu_mask_set(const struct i2c_client *client,
254 int val = __mt9t112_mcu_read(client, command);
261 return __mt9t112_mcu_write(client, command, val);
264 static int mt9t112_reset(const struct i2c_client *client)
268 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001);
270 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000);
276 #define CLOCK_INFO(a, b)
278 #define CLOCK_INFO(a, b) mt9t112_clock_info(a, b)
279 static int mt9t112_clock_info(const struct i2c_client *client, u32 ext)
281 int m, n, p1, p2, p3, p4, p5, p6, p7;
285 ext /= 1000; /* kbyte order */
287 mt9t112_reg_read(n, client, 0x0012);
294 mt9t112_reg_read(n, client, 0x002a);
301 mt9t112_reg_read(n, client, 0x002c);
304 mt9t112_reg_read(n, client, 0x0010);
306 n = (n >> 8) & 0x003f;
308 enable = ((6000 > ext) || (54000 < ext)) ? "X" : "";
309 dev_dbg(&client->dev, "EXTCLK : %10u K %s\n", ext, enable);
311 vco = 2 * m * ext / (n+1);
312 enable = ((384000 > vco) || (768000 < vco)) ? "X" : "";
313 dev_dbg(&client->dev, "VCO : %10u K %s\n", vco, enable);
315 clk = vco / (p1+1) / (p2+1);
316 enable = (96000 < clk) ? "X" : "";
317 dev_dbg(&client->dev, "PIXCLK : %10u K %s\n", clk, enable);
320 enable = (768000 < clk) ? "X" : "";
321 dev_dbg(&client->dev, "MIPICLK : %10u K %s\n", clk, enable);
324 enable = (96000 < clk) ? "X" : "";
325 dev_dbg(&client->dev, "MCU CLK : %10u K %s\n", clk, enable);
328 enable = (54000 < clk) ? "X" : "";
329 dev_dbg(&client->dev, "SOC CLK : %10u K %s\n", clk, enable);
332 enable = (70000 < clk) ? "X" : "";
333 dev_dbg(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable);
336 dev_dbg(&client->dev, "External sensor : %10u K\n", clk);
339 enable = ((2000 > clk) || (24000 < clk)) ? "X" : "";
340 dev_dbg(&client->dev, "PFD : %10u K %s\n", clk, enable);
346 static void mt9t112_frame_check(u32 *width, u32 *height, u32 *left, u32 *top)
348 soc_camera_limit_side(left, width, 0, 0, MAX_WIDTH);
349 soc_camera_limit_side(top, height, 0, 0, MAX_HEIGHT);
352 static int mt9t112_set_a_frame_size(const struct i2c_client *client,
357 u16 wstart = (MAX_WIDTH - width) / 2;
358 u16 hstart = (MAX_HEIGHT - height) / 2;
360 /* (Context A) Image Width/Height */
361 mt9t112_mcu_write(ret, client, VAR(26, 0), width);
362 mt9t112_mcu_write(ret, client, VAR(26, 2), height);
364 /* (Context A) Output Width/Height */
365 mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width);
366 mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height);
368 /* (Context A) Start Row/Column */
369 mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart);
370 mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart);
372 /* (Context A) End Row/Column */
373 mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart);
374 mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart);
376 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
381 static int mt9t112_set_pll_dividers(const struct i2c_client *client,
393 mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val);
396 val = ((p3 & 0x0F) << 8) |
399 mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val);
406 mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val);
411 mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val);
416 static int mt9t112_init_pll(const struct i2c_client *client)
418 struct mt9t112_priv *priv = to_mt9t112(client);
421 mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001);
423 /* PLL control: BYPASS PLL = 8517 */
424 mt9t112_reg_write(ret, client, 0x0014, 0x2145);
426 /* Replace these registers when new timing parameters are generated */
427 mt9t112_set_pll_dividers(client,
428 priv->info->divider.m,
429 priv->info->divider.n,
430 priv->info->divider.p1,
431 priv->info->divider.p2,
432 priv->info->divider.p3,
433 priv->info->divider.p4,
434 priv->info->divider.p5,
435 priv->info->divider.p6,
436 priv->info->divider.p7);
444 mt9t112_reg_write(ret, client, 0x0014, 0x2525);
445 mt9t112_reg_write(ret, client, 0x0014, 0x2527);
446 mt9t112_reg_write(ret, client, 0x0014, 0x3427);
447 mt9t112_reg_write(ret, client, 0x0014, 0x3027);
453 * Reference clock count
454 * I2C Master Clock Divider
456 mt9t112_reg_write(ret, client, 0x0014, 0x3046);
457 mt9t112_reg_write(ret, client, 0x0016, 0x0400); /* JPEG initialization workaround */
458 mt9t112_reg_write(ret, client, 0x0022, 0x0190);
459 mt9t112_reg_write(ret, client, 0x3B84, 0x0212);
461 /* External sensor clock is PLL bypass */
462 mt9t112_reg_write(ret, client, 0x002E, 0x0500);
464 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002);
465 mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004);
468 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004);
471 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0);
477 * Disable Secondary I2C Pads
479 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
481 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
483 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
485 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
487 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
489 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
492 /* poll to verify out of standby. Must Poll this bit */
493 for (i = 0; i < 100; i++) {
494 mt9t112_reg_read(data, client, 0x0018);
495 if (!(0x4000 & data))
504 static int mt9t112_init_setting(const struct i2c_client *client)
509 /* Adaptive Output Clock (A) */
510 mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000);
513 mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024);
515 /* Fine Correction (A) */
516 mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC);
518 /* Fine IT Min (A) */
519 mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1);
521 /* Fine IT Max Margin (A) */
522 mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF);
524 /* Base Frame Lines (A) */
525 mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D);
527 /* Min Line Length (A) */
528 mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a);
530 /* Line Length (A) */
531 mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0);
533 /* Adaptive Output Clock (B) */
534 mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000);
537 mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004);
539 /* Column Start (B) */
540 mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004);
543 mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B);
546 mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B);
548 /* Fine Correction (B) */
549 mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C);
551 /* Fine IT Min (B) */
552 mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1);
554 /* Fine IT Max Margin (B) */
555 mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF);
557 /* Base Frame Lines (B) */
558 mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668);
560 /* Min Line Length (B) */
561 mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0);
563 /* Line Length (B) */
564 mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0);
567 * Flicker Dectection registers
568 * This section should be replaced whenever new Timing file is generated
569 * All the following registers need to be replaced
570 * Following registers are generated from Register Wizard but user can
571 * modify them. For detail see auto flicker detection tuning
574 /* FD_FDPERIOD_SELECT */
575 mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01);
577 /* PRI_B_CONFIG_FD_ALGO_RUN */
578 mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003);
580 /* PRI_A_CONFIG_FD_ALGO_RUN */
581 mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003);
584 * AFD range detection tuning registers
588 mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25);
591 mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28);
594 mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C);
597 mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F);
599 /* period_50Hz (A) */
600 mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA);
602 /* secret register by aptina */
603 /* period_50Hz (A MSB) */
604 mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00);
606 /* period_60Hz (A) */
607 mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B);
609 /* secret register by aptina */
610 /* period_60Hz (A MSB) */
611 mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00);
613 /* period_50Hz (B) */
614 mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82);
616 /* secret register by aptina */
617 /* period_50Hz (B) MSB */
618 mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00);
620 /* period_60Hz (B) */
621 mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D);
623 /* secret register by aptina */
624 /* period_60Hz (B) MSB */
625 mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00);
628 mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10);
631 mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02);
634 mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03);
637 mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A);
639 /* RX FIFO Watermark (A) */
640 mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014);
642 /* RX FIFO Watermark (B) */
643 mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014);
647 * CorePixCLK: 36.5 MHz
649 mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133);
650 mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110);
651 mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130);
652 mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108);
654 mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27);
655 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30);
656 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32);
657 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35);
662 static int mt9t112_auto_focus_setting(const struct i2c_client *client)
666 mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F);
667 mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F);
668 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
670 mt9t112_reg_write(ret, client, 0x0614, 0x0000);
672 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
673 mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02);
674 mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002);
675 mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001);
676 mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025);
677 mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193);
678 mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18);
679 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
684 static int mt9t112_auto_focus_trigger(const struct i2c_client *client)
688 mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01);
693 static int mt9t112_init_camera(const struct i2c_client *client)
697 ECHECKER(ret, mt9t112_reset(client));
699 ECHECKER(ret, mt9t112_init_pll(client));
701 ECHECKER(ret, mt9t112_init_setting(client));
703 ECHECKER(ret, mt9t112_auto_focus_setting(client));
705 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0);
707 /* Analog setting B */
708 mt9t112_reg_write(ret, client, 0x3084, 0x2409);
709 mt9t112_reg_write(ret, client, 0x3092, 0x0A49);
710 mt9t112_reg_write(ret, client, 0x3094, 0x4949);
711 mt9t112_reg_write(ret, client, 0x3096, 0x4950);
714 * Disable adaptive clock
715 * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR
716 * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
718 mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E);
719 mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E);
721 /* Configure STatus in Status_before_length Format and enable header */
722 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
723 mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4);
725 /* Enable JPEG in context B */
726 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
727 mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01);
729 /* Disable Dac_TXLO */
730 mt9t112_reg_write(ret, client, 0x316C, 0x350F);
732 /* Set max slew rates */
733 mt9t112_reg_write(ret, client, 0x1E, 0x777);
738 /************************************************************************
740 ************************************************************************/
741 static int mt9t112_g_chip_ident(struct v4l2_subdev *sd,
742 struct v4l2_dbg_chip_ident *id)
744 struct i2c_client *client = v4l2_get_subdevdata(sd);
745 struct mt9t112_priv *priv = to_mt9t112(client);
747 id->ident = priv->model;
753 #ifdef CONFIG_VIDEO_ADV_DEBUG
754 static int mt9t112_g_register(struct v4l2_subdev *sd,
755 struct v4l2_dbg_register *reg)
757 struct i2c_client *client = v4l2_get_subdevdata(sd);
761 mt9t112_reg_read(ret, client, reg->reg);
763 reg->val = (__u64)ret;
768 static int mt9t112_s_register(struct v4l2_subdev *sd,
769 const struct v4l2_dbg_register *reg)
771 struct i2c_client *client = v4l2_get_subdevdata(sd);
774 mt9t112_reg_write(ret, client, reg->reg, reg->val);
780 static int mt9t112_s_power(struct v4l2_subdev *sd, int on)
782 struct i2c_client *client = v4l2_get_subdevdata(sd);
783 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
785 return soc_camera_set_power(&client->dev, ssdd, on);
788 static struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = {
789 .g_chip_ident = mt9t112_g_chip_ident,
790 #ifdef CONFIG_VIDEO_ADV_DEBUG
791 .g_register = mt9t112_g_register,
792 .s_register = mt9t112_s_register,
794 .s_power = mt9t112_s_power,
798 /************************************************************************
799 v4l2_subdev_video_ops
800 ************************************************************************/
801 static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable)
803 struct i2c_client *client = v4l2_get_subdevdata(sd);
804 struct mt9t112_priv *priv = to_mt9t112(client);
810 * If user selected large output size,
811 * and used it long time,
812 * mt9t112 camera will be very warm.
814 * But current driver can not stop mt9t112 camera.
815 * So, set small size here to solve this problem.
817 mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT);
821 if (!(priv->flags & INIT_DONE)) {
822 u16 param = PCLK_RISING & priv->flags ? 0x0001 : 0x0000;
824 ECHECKER(ret, mt9t112_init_camera(client));
826 /* Invert PCLK (Data sampled on falling edge of pixclk) */
827 mt9t112_reg_write(ret, client, 0x3C20, param);
831 priv->flags |= INIT_DONE;
834 mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt);
835 mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order);
836 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
838 mt9t112_set_a_frame_size(client,
842 ECHECKER(ret, mt9t112_auto_focus_trigger(client));
844 dev_dbg(&client->dev, "format : %d\n", priv->format->code);
845 dev_dbg(&client->dev, "size : %d x %d\n",
849 CLOCK_INFO(client, EXT_CLOCK);
854 static int mt9t112_set_params(struct mt9t112_priv *priv,
855 const struct v4l2_rect *rect,
856 enum v4l2_mbus_pixelcode code)
863 for (i = 0; i < priv->num_formats; i++)
864 if (mt9t112_cfmts[i].code == code)
867 if (i == priv->num_formats)
875 mt9t112_frame_check(&priv->frame.width, &priv->frame.height,
876 &priv->frame.left, &priv->frame.top);
878 priv->format = mt9t112_cfmts + i;
883 static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
887 a->bounds.width = MAX_WIDTH;
888 a->bounds.height = MAX_HEIGHT;
891 a->defrect.width = VGA_WIDTH;
892 a->defrect.height = VGA_HEIGHT;
893 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
894 a->pixelaspect.numerator = 1;
895 a->pixelaspect.denominator = 1;
900 static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
902 struct i2c_client *client = v4l2_get_subdevdata(sd);
903 struct mt9t112_priv *priv = to_mt9t112(client);
906 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
911 static int mt9t112_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a)
913 struct i2c_client *client = v4l2_get_subdevdata(sd);
914 struct mt9t112_priv *priv = to_mt9t112(client);
915 const struct v4l2_rect *rect = &a->c;
917 return mt9t112_set_params(priv, rect, priv->format->code);
920 static int mt9t112_g_fmt(struct v4l2_subdev *sd,
921 struct v4l2_mbus_framefmt *mf)
923 struct i2c_client *client = v4l2_get_subdevdata(sd);
924 struct mt9t112_priv *priv = to_mt9t112(client);
926 mf->width = priv->frame.width;
927 mf->height = priv->frame.height;
928 mf->colorspace = priv->format->colorspace;
929 mf->code = priv->format->code;
930 mf->field = V4L2_FIELD_NONE;
935 static int mt9t112_s_fmt(struct v4l2_subdev *sd,
936 struct v4l2_mbus_framefmt *mf)
938 struct i2c_client *client = v4l2_get_subdevdata(sd);
939 struct mt9t112_priv *priv = to_mt9t112(client);
940 struct v4l2_rect rect = {
942 .height = mf->height,
943 .left = priv->frame.left,
944 .top = priv->frame.top,
948 ret = mt9t112_set_params(priv, &rect, mf->code);
951 mf->colorspace = priv->format->colorspace;
956 static int mt9t112_try_fmt(struct v4l2_subdev *sd,
957 struct v4l2_mbus_framefmt *mf)
959 struct i2c_client *client = v4l2_get_subdevdata(sd);
960 struct mt9t112_priv *priv = to_mt9t112(client);
961 unsigned int top, left;
964 for (i = 0; i < priv->num_formats; i++)
965 if (mt9t112_cfmts[i].code == mf->code)
968 if (i == priv->num_formats) {
969 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
970 mf->colorspace = V4L2_COLORSPACE_JPEG;
972 mf->colorspace = mt9t112_cfmts[i].colorspace;
975 mt9t112_frame_check(&mf->width, &mf->height, &left, &top);
977 mf->field = V4L2_FIELD_NONE;
982 static int mt9t112_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
983 enum v4l2_mbus_pixelcode *code)
985 struct i2c_client *client = v4l2_get_subdevdata(sd);
986 struct mt9t112_priv *priv = to_mt9t112(client);
988 if (index >= priv->num_formats)
991 *code = mt9t112_cfmts[index].code;
996 static int mt9t112_g_mbus_config(struct v4l2_subdev *sd,
997 struct v4l2_mbus_config *cfg)
999 struct i2c_client *client = v4l2_get_subdevdata(sd);
1000 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1002 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1003 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_DATA_ACTIVE_HIGH |
1004 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING;
1005 cfg->type = V4L2_MBUS_PARALLEL;
1006 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
1011 static int mt9t112_s_mbus_config(struct v4l2_subdev *sd,
1012 const struct v4l2_mbus_config *cfg)
1014 struct i2c_client *client = v4l2_get_subdevdata(sd);
1015 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1016 struct mt9t112_priv *priv = to_mt9t112(client);
1018 if (soc_camera_apply_board_flags(ssdd, cfg) & V4L2_MBUS_PCLK_SAMPLE_RISING)
1019 priv->flags |= PCLK_RISING;
1024 static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = {
1025 .s_stream = mt9t112_s_stream,
1026 .g_mbus_fmt = mt9t112_g_fmt,
1027 .s_mbus_fmt = mt9t112_s_fmt,
1028 .try_mbus_fmt = mt9t112_try_fmt,
1029 .cropcap = mt9t112_cropcap,
1030 .g_crop = mt9t112_g_crop,
1031 .s_crop = mt9t112_s_crop,
1032 .enum_mbus_fmt = mt9t112_enum_fmt,
1033 .g_mbus_config = mt9t112_g_mbus_config,
1034 .s_mbus_config = mt9t112_s_mbus_config,
1037 /************************************************************************
1039 ************************************************************************/
1040 static struct v4l2_subdev_ops mt9t112_subdev_ops = {
1041 .core = &mt9t112_subdev_core_ops,
1042 .video = &mt9t112_subdev_video_ops,
1045 static int mt9t112_camera_probe(struct i2c_client *client)
1047 struct mt9t112_priv *priv = to_mt9t112(client);
1048 const char *devname;
1052 ret = mt9t112_s_power(&priv->subdev, 1);
1057 * check and show chip ID
1059 mt9t112_reg_read(chipid, client, 0x0000);
1063 devname = "mt9t111";
1064 priv->model = V4L2_IDENT_MT9T111;
1065 priv->num_formats = 1;
1068 devname = "mt9t112";
1069 priv->model = V4L2_IDENT_MT9T112;
1070 priv->num_formats = ARRAY_SIZE(mt9t112_cfmts);
1073 dev_err(&client->dev, "Product ID error %04x\n", chipid);
1078 dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid);
1081 mt9t112_s_power(&priv->subdev, 0);
1085 static int mt9t112_probe(struct i2c_client *client,
1086 const struct i2c_device_id *did)
1088 struct mt9t112_priv *priv;
1089 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1090 struct v4l2_rect rect = {
1092 .height = VGA_HEIGHT,
1093 .left = (MAX_WIDTH - VGA_WIDTH) / 2,
1094 .top = (MAX_HEIGHT - VGA_HEIGHT) / 2,
1098 if (!ssdd || !ssdd->drv_priv) {
1099 dev_err(&client->dev, "mt9t112: missing platform data!\n");
1103 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1107 priv->info = ssdd->drv_priv;
1109 v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops);
1111 ret = mt9t112_camera_probe(client);
1115 /* Cannot fail: using the default supported pixel code */
1116 mt9t112_set_params(priv, &rect, V4L2_MBUS_FMT_UYVY8_2X8);
1121 static int mt9t112_remove(struct i2c_client *client)
1126 static const struct i2c_device_id mt9t112_id[] = {
1130 MODULE_DEVICE_TABLE(i2c, mt9t112_id);
1132 static struct i2c_driver mt9t112_i2c_driver = {
1136 .probe = mt9t112_probe,
1137 .remove = mt9t112_remove,
1138 .id_table = mt9t112_id,
1141 module_i2c_driver(mt9t112_i2c_driver);
1143 MODULE_DESCRIPTION("SoC Camera driver for mt9t112");
1144 MODULE_AUTHOR("Kuninori Morimoto");
1145 MODULE_LICENSE("GPL v2");