2 * Driver for the Conexant CX23885/7/8 PCIe bridge
4 * CX23888 Integrated Consumer Infrared Controller
6 * Copyright (C) 2009 Andy Walls <awalls@md.metrocast.net>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 #include <linux/kfifo.h>
25 #include <linux/slab.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-chip-ident.h>
29 #include <media/rc-core.h>
33 static unsigned int ir_888_debug;
34 module_param(ir_888_debug, int, 0644);
35 MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
37 #define CX23888_IR_REG_BASE 0x170000
39 * These CX23888 register offsets have a straightforward one to one mapping
40 * to the CX23885 register offsets of 0x200 through 0x218
42 #define CX23888_IR_CNTRL_REG 0x170000
43 #define CNTRL_WIN_3_3 0x00000000
44 #define CNTRL_WIN_4_3 0x00000001
45 #define CNTRL_WIN_3_4 0x00000002
46 #define CNTRL_WIN_4_4 0x00000003
47 #define CNTRL_WIN 0x00000003
48 #define CNTRL_EDG_NONE 0x00000000
49 #define CNTRL_EDG_FALL 0x00000004
50 #define CNTRL_EDG_RISE 0x00000008
51 #define CNTRL_EDG_BOTH 0x0000000C
52 #define CNTRL_EDG 0x0000000C
53 #define CNTRL_DMD 0x00000010
54 #define CNTRL_MOD 0x00000020
55 #define CNTRL_RFE 0x00000040
56 #define CNTRL_TFE 0x00000080
57 #define CNTRL_RXE 0x00000100
58 #define CNTRL_TXE 0x00000200
59 #define CNTRL_RIC 0x00000400
60 #define CNTRL_TIC 0x00000800
61 #define CNTRL_CPL 0x00001000
62 #define CNTRL_LBM 0x00002000
63 #define CNTRL_R 0x00004000
64 /* CX23888 specific control flag */
65 #define CNTRL_IVO 0x00008000
67 #define CX23888_IR_TXCLK_REG 0x170004
68 #define TXCLK_TCD 0x0000FFFF
70 #define CX23888_IR_RXCLK_REG 0x170008
71 #define RXCLK_RCD 0x0000FFFF
73 #define CX23888_IR_CDUTY_REG 0x17000C
74 #define CDUTY_CDC 0x0000000F
76 #define CX23888_IR_STATS_REG 0x170010
77 #define STATS_RTO 0x00000001
78 #define STATS_ROR 0x00000002
79 #define STATS_RBY 0x00000004
80 #define STATS_TBY 0x00000008
81 #define STATS_RSR 0x00000010
82 #define STATS_TSR 0x00000020
84 #define CX23888_IR_IRQEN_REG 0x170014
85 #define IRQEN_RTE 0x00000001
86 #define IRQEN_ROE 0x00000002
87 #define IRQEN_RSE 0x00000010
88 #define IRQEN_TSE 0x00000020
90 #define CX23888_IR_FILTR_REG 0x170018
91 #define FILTR_LPF 0x0000FFFF
93 /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */
94 #define CX23888_IR_FIFO_REG 0x170040
95 #define FIFO_RXTX 0x0000FFFF
96 #define FIFO_RXTX_LVL 0x00010000
97 #define FIFO_RXTX_RTO 0x0001FFFF
98 #define FIFO_RX_NDV 0x00020000
99 #define FIFO_RX_DEPTH 8
100 #define FIFO_TX_DEPTH 8
102 /* CX23888 unique registers */
103 #define CX23888_IR_SEEDP_REG 0x17001C
104 #define CX23888_IR_TIMOL_REG 0x170020
105 #define CX23888_IR_WAKE0_REG 0x170024
106 #define CX23888_IR_WAKE1_REG 0x170028
107 #define CX23888_IR_WAKE2_REG 0x17002C
108 #define CX23888_IR_MASK0_REG 0x170030
109 #define CX23888_IR_MASK1_REG 0x170034
110 #define CX23888_IR_MAKS2_REG 0x170038
111 #define CX23888_IR_DPIPG_REG 0x17003C
112 #define CX23888_IR_LEARN_REG 0x170044
114 #define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
115 #define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2)
118 * We use this union internally for convenience, but callers to tx_write
119 * and rx_read will be expecting records of type struct ir_raw_event.
120 * Always ensure the size of this union is dictated by struct ir_raw_event.
122 union cx23888_ir_fifo_rec {
124 struct ir_raw_event ir_core_data;
127 #define CX23888_IR_RX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec))
128 #define CX23888_IR_TX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec))
130 struct cx23888_ir_state {
131 struct v4l2_subdev sd;
132 struct cx23885_dev *dev;
136 struct v4l2_subdev_ir_parameters rx_params;
137 struct mutex rx_params_lock;
138 atomic_t rxclk_divider;
141 struct kfifo rx_kfifo;
142 spinlock_t rx_kfifo_lock;
144 struct v4l2_subdev_ir_parameters tx_params;
145 struct mutex tx_params_lock;
146 atomic_t txclk_divider;
149 static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd)
151 return v4l2_get_subdevdata(sd);
155 * IR register block read and write functions
158 inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value)
160 cx_write(addr, value);
164 static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr)
166 return cx_read(addr);
169 static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
170 u32 and_mask, u32 or_value)
172 cx_andor(addr, ~and_mask, or_value);
177 * Rx and Tx Clock Divider register computations
179 * Note the largest clock divider value of 0xffff corresponds to:
180 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
181 * which fits in 21 bits, so we'll use unsigned int for time arguments.
183 static inline u16 count_to_clock_divider(unsigned int d)
185 if (d > RXCLK_RCD + 1)
194 static inline u16 ns_to_clock_divider(unsigned int ns)
196 return count_to_clock_divider(
197 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
200 static inline unsigned int clock_divider_to_ns(unsigned int divider)
202 /* Period of the Rx or Tx clock in ns */
203 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
204 CX23888_IR_REFCLK_FREQ / 1000000);
207 static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
209 return count_to_clock_divider(
210 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16));
213 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
215 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
218 static inline u16 freq_to_clock_divider(unsigned int freq,
219 unsigned int rollovers)
221 return count_to_clock_divider(
222 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers));
225 static inline unsigned int clock_divider_to_freq(unsigned int divider,
226 unsigned int rollovers)
228 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ,
229 (divider + 1) * rollovers);
233 * Low Pass Filter register calculations
235 * Note the largest count value of 0xffff corresponds to:
236 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
237 * which fits in 21 bits, so we'll use unsigned int for time arguments.
239 static inline u16 count_to_lpf_count(unsigned int d)
248 static inline u16 ns_to_lpf_count(unsigned int ns)
250 return count_to_lpf_count(
251 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
254 static inline unsigned int lpf_count_to_ns(unsigned int count)
256 /* Duration of the Low Pass Filter rejection window in ns */
257 return DIV_ROUND_CLOSEST(count * 1000,
258 CX23888_IR_REFCLK_FREQ / 1000000);
261 static inline unsigned int lpf_count_to_us(unsigned int count)
263 /* Duration of the Low Pass Filter rejection window in us */
264 return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000);
268 * FIFO register pulse width count compuations
270 static u32 clock_divider_to_resolution(u16 divider)
273 * Resolution is the duration of 1 tick of the readable portion of
274 * of the pulse width counter as read from the FIFO. The two lsb's are
275 * not readable, hence the << 2. This function returns ns.
277 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
278 CX23888_IR_REFCLK_FREQ / 1000000);
281 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
287 * The 2 lsb's of the pulse width timer count are not readable, hence
288 * the (count << 2) | 0x3
290 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
291 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
292 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
297 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
303 * The 2 lsb's of the pulse width timer count are not readable, hence
304 * the (count << 2) | 0x3
306 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
307 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
308 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
310 return (unsigned int) n;
314 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
316 * The total pulse clock count is an 18 bit pulse width timer count as the most
317 * significant part and (up to) 16 bit clock divider count as a modulus.
318 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
319 * width timer count's least significant bit.
321 static u64 ns_to_pulse_clocks(u32 ns)
325 clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
326 rem = do_div(clocks, 1000); /* /1000 = cycles */
332 static u16 pulse_clocks_to_clock_divider(u64 count)
334 do_div(count, (FIFO_RXTX << 2) | 0x3);
336 /* net result needs to be rounded down and decremented by 1 */
337 if (count > RXCLK_RCD + 1)
347 * IR Control Register helpers
349 enum tx_fifo_watermark {
350 TX_FIFO_HALF_EMPTY = 0,
351 TX_FIFO_EMPTY = CNTRL_TIC,
354 enum rx_fifo_watermark {
355 RX_FIFO_HALF_FULL = 0,
356 RX_FIFO_NOT_EMPTY = CNTRL_RIC,
359 static inline void control_tx_irq_watermark(struct cx23885_dev *dev,
360 enum tx_fifo_watermark level)
362 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level);
365 static inline void control_rx_irq_watermark(struct cx23885_dev *dev,
366 enum rx_fifo_watermark level)
368 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level);
371 static inline void control_tx_enable(struct cx23885_dev *dev, bool enable)
373 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
374 enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
377 static inline void control_rx_enable(struct cx23885_dev *dev, bool enable)
379 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
380 enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
383 static inline void control_tx_modulation_enable(struct cx23885_dev *dev,
386 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD,
387 enable ? CNTRL_MOD : 0);
390 static inline void control_rx_demodulation_enable(struct cx23885_dev *dev,
393 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD,
394 enable ? CNTRL_DMD : 0);
397 static inline void control_rx_s_edge_detection(struct cx23885_dev *dev,
400 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
401 edge_types & CNTRL_EDG_BOTH);
404 static void control_rx_s_carrier_window(struct cx23885_dev *dev,
405 unsigned int carrier,
406 unsigned int *carrier_range_low,
407 unsigned int *carrier_range_high)
410 unsigned int c16 = carrier * 16;
412 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
414 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
417 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
420 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
422 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
425 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
427 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v);
430 static inline void control_tx_polarity_invert(struct cx23885_dev *dev,
433 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL,
434 invert ? CNTRL_CPL : 0);
437 static inline void control_tx_level_invert(struct cx23885_dev *dev,
440 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO,
441 invert ? CNTRL_IVO : 0);
445 * IR Rx & Tx Clock Register helpers
447 static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev,
451 *divider = carrier_freq_to_clock_divider(freq);
452 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
453 return clock_divider_to_carrier_freq(*divider);
456 static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev,
460 *divider = carrier_freq_to_clock_divider(freq);
461 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
462 return clock_divider_to_carrier_freq(*divider);
465 static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
470 if (ns > IR_MAX_DURATION)
471 ns = IR_MAX_DURATION;
472 pulse_clocks = ns_to_pulse_clocks(ns);
473 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
474 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
475 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
478 static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
483 if (ns > IR_MAX_DURATION)
484 ns = IR_MAX_DURATION;
485 pulse_clocks = ns_to_pulse_clocks(ns);
486 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
487 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
488 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
492 * IR Tx Carrier Duty Cycle register helpers
494 static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev,
495 unsigned int duty_cycle)
498 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
503 cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n);
504 return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
508 * IR Filter Register helpers
510 static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns)
512 u32 count = ns_to_lpf_count(min_width_ns);
513 cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count);
514 return lpf_count_to_ns(count);
518 * IR IRQ Enable Register helpers
520 static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask)
522 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
523 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG,
524 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
527 static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask)
530 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask);
534 * V4L2 Subdevice IR Ops
536 static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status,
539 struct cx23888_ir_state *state = to_state(sd);
540 struct cx23885_dev *dev = state->dev;
543 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
544 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
545 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
547 union cx23888_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
548 unsigned int i, j, k;
550 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
552 tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
553 rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
554 rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
555 ror = stats & STATS_ROR; /* Rx FIFO Over Run */
557 tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
558 rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
559 rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
560 roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
563 v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n",
564 tsr ? "tsr" : " ", rsr ? "rsr" : " ",
565 rto ? "rto" : " ", ror ? "ror" : " ",
566 stats & STATS_TBY ? "tby" : " ",
567 stats & STATS_RBY ? "rby" : " ");
569 v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n",
570 tse ? "tse" : " ", rse ? "rse" : " ",
571 rte ? "rte" : " ", roe ? "roe" : " ");
574 * Transmitter interrupt service
579 * Check the watermark threshold setting
580 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
581 * Push the data to the hardware FIFO.
582 * If there was nothing more to send in the tx_kfifo, disable
583 * the TSR IRQ and notify the v4l2_device.
584 * If there was something in the tx_kfifo, check the tx_kfifo
585 * level and notify the v4l2_device, if it is low.
587 /* For now, inhibit TSR interrupt until Tx is implemented */
588 irqenable_tx(dev, 0);
589 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
590 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
595 * Receiver interrupt service
598 if ((rse && rsr) || (rte && rto)) {
600 * Receive data on RSR to clear the STATS_RSR.
601 * Receive data on RTO, since we may not have yet hit the RSR
602 * watermark when we receive the RTO.
604 for (i = 0, v = FIFO_RX_NDV;
605 (v & FIFO_RX_NDV) && !kror; i = 0) {
607 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
608 v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG);
609 rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
614 j = i * sizeof(union cx23888_ir_fifo_rec);
615 k = kfifo_in_locked(&state->rx_kfifo,
616 (unsigned char *) rx_data, j,
617 &state->rx_kfifo_lock);
619 kror++; /* rx_kfifo over run */
627 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
628 v4l2_err(sd, "IR receiver software FIFO overrun\n");
632 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
633 * the Rx FIFO Over Run status (STATS_ROR)
636 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
637 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
641 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
642 * the Rx Pulse Width Timer Time Out (STATS_RTO)
645 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
648 /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
649 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
650 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
654 spin_lock_irqsave(&state->rx_kfifo_lock, flags);
655 if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2)
656 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
657 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
660 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
665 static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
668 struct cx23888_ir_state *state = to_state(sd);
669 bool invert = (bool) atomic_read(&state->rx_invert);
670 u16 divider = (u16) atomic_read(&state->rxclk_divider);
673 union cx23888_ir_fifo_rec *p;
676 n = count / sizeof(union cx23888_ir_fifo_rec)
677 * sizeof(union cx23888_ir_fifo_rec);
683 n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock);
685 n /= sizeof(union cx23888_ir_fifo_rec);
686 *num = n * sizeof(union cx23888_ir_fifo_rec);
688 for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
690 if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
691 /* Assume RTO was because of no IR light input */
695 u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
701 v = (unsigned) pulse_width_count_to_ns(
702 (u16) (p->hw_fifo_data & FIFO_RXTX), divider);
703 if (v > IR_MAX_DURATION)
706 init_ir_raw_event(&p->ir_core_data);
707 p->ir_core_data.pulse = u;
708 p->ir_core_data.duration = v;
709 p->ir_core_data.timeout = w;
711 v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s %s\n",
712 v, u ? "mark" : "space", w ? "(timed out)" : "");
714 v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n");
719 static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd,
720 struct v4l2_subdev_ir_parameters *p)
722 struct cx23888_ir_state *state = to_state(sd);
723 mutex_lock(&state->rx_params_lock);
724 memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters));
725 mutex_unlock(&state->rx_params_lock);
729 static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd)
731 struct cx23888_ir_state *state = to_state(sd);
732 struct cx23885_dev *dev = state->dev;
734 mutex_lock(&state->rx_params_lock);
736 /* Disable or slow down all IR Rx circuits and counters */
737 irqenable_rx(dev, 0);
738 control_rx_enable(dev, false);
739 control_rx_demodulation_enable(dev, false);
740 control_rx_s_edge_detection(dev, CNTRL_EDG_NONE);
741 filter_rx_s_min_width(dev, 0);
742 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD);
744 state->rx_params.shutdown = true;
746 mutex_unlock(&state->rx_params_lock);
750 static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd,
751 struct v4l2_subdev_ir_parameters *p)
753 struct cx23888_ir_state *state = to_state(sd);
754 struct cx23885_dev *dev = state->dev;
755 struct v4l2_subdev_ir_parameters *o = &state->rx_params;
759 return cx23888_ir_rx_shutdown(sd);
761 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
764 mutex_lock(&state->rx_params_lock);
766 o->shutdown = p->shutdown;
768 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
770 o->bytes_per_data_element = p->bytes_per_data_element
771 = sizeof(union cx23888_ir_fifo_rec);
773 /* Before we tweak the hardware, we have to disable the receiver */
774 irqenable_rx(dev, 0);
775 control_rx_enable(dev, false);
777 control_rx_demodulation_enable(dev, p->modulation);
778 o->modulation = p->modulation;
781 p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq,
784 o->carrier_freq = p->carrier_freq;
786 o->duty_cycle = p->duty_cycle = 50;
788 control_rx_s_carrier_window(dev, p->carrier_freq,
789 &p->carrier_range_lower,
790 &p->carrier_range_upper);
791 o->carrier_range_lower = p->carrier_range_lower;
792 o->carrier_range_upper = p->carrier_range_upper;
795 (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
798 rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width,
801 o->max_pulse_width = p->max_pulse_width;
802 atomic_set(&state->rxclk_divider, rxclk_divider);
804 p->noise_filter_min_width =
805 filter_rx_s_min_width(dev, p->noise_filter_min_width);
806 o->noise_filter_min_width = p->noise_filter_min_width;
808 p->resolution = clock_divider_to_resolution(rxclk_divider);
809 o->resolution = p->resolution;
811 /* FIXME - make this dependent on resolution for better performance */
812 control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL);
814 control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH);
816 o->invert_level = p->invert_level;
817 atomic_set(&state->rx_invert, p->invert_level);
819 o->interrupt_enable = p->interrupt_enable;
820 o->enable = p->enable;
824 spin_lock_irqsave(&state->rx_kfifo_lock, flags);
825 kfifo_reset(&state->rx_kfifo);
826 /* reset tx_fifo too if there is one... */
827 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
828 if (p->interrupt_enable)
829 irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
830 control_rx_enable(dev, p->enable);
833 mutex_unlock(&state->rx_params_lock);
838 static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
841 struct cx23888_ir_state *state = to_state(sd);
842 struct cx23885_dev *dev = state->dev;
843 /* For now enable the Tx FIFO Service interrupt & pretend we did work */
844 irqenable_tx(dev, IRQEN_TSE);
849 static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd,
850 struct v4l2_subdev_ir_parameters *p)
852 struct cx23888_ir_state *state = to_state(sd);
853 mutex_lock(&state->tx_params_lock);
854 memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters));
855 mutex_unlock(&state->tx_params_lock);
859 static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd)
861 struct cx23888_ir_state *state = to_state(sd);
862 struct cx23885_dev *dev = state->dev;
864 mutex_lock(&state->tx_params_lock);
866 /* Disable or slow down all IR Tx circuits and counters */
867 irqenable_tx(dev, 0);
868 control_tx_enable(dev, false);
869 control_tx_modulation_enable(dev, false);
870 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD);
872 state->tx_params.shutdown = true;
874 mutex_unlock(&state->tx_params_lock);
878 static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd,
879 struct v4l2_subdev_ir_parameters *p)
881 struct cx23888_ir_state *state = to_state(sd);
882 struct cx23885_dev *dev = state->dev;
883 struct v4l2_subdev_ir_parameters *o = &state->tx_params;
887 return cx23888_ir_tx_shutdown(sd);
889 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
892 mutex_lock(&state->tx_params_lock);
894 o->shutdown = p->shutdown;
896 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
898 o->bytes_per_data_element = p->bytes_per_data_element
899 = sizeof(union cx23888_ir_fifo_rec);
901 /* Before we tweak the hardware, we have to disable the transmitter */
902 irqenable_tx(dev, 0);
903 control_tx_enable(dev, false);
905 control_tx_modulation_enable(dev, p->modulation);
906 o->modulation = p->modulation;
909 p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq,
911 o->carrier_freq = p->carrier_freq;
913 p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle);
914 o->duty_cycle = p->duty_cycle;
917 (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
920 txclk_tx_s_max_pulse_width(dev, p->max_pulse_width,
923 o->max_pulse_width = p->max_pulse_width;
924 atomic_set(&state->txclk_divider, txclk_divider);
926 p->resolution = clock_divider_to_resolution(txclk_divider);
927 o->resolution = p->resolution;
929 /* FIXME - make this dependent on resolution for better performance */
930 control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY);
932 control_tx_polarity_invert(dev, p->invert_carrier_sense);
933 o->invert_carrier_sense = p->invert_carrier_sense;
935 control_tx_level_invert(dev, p->invert_level);
936 o->invert_level = p->invert_level;
938 o->interrupt_enable = p->interrupt_enable;
939 o->enable = p->enable;
941 if (p->interrupt_enable)
942 irqenable_tx(dev, IRQEN_TSE);
943 control_tx_enable(dev, p->enable);
946 mutex_unlock(&state->tx_params_lock);
952 * V4L2 Subdevice Core Ops
954 static int cx23888_ir_log_status(struct v4l2_subdev *sd)
956 struct cx23888_ir_state *state = to_state(sd);
957 struct cx23885_dev *dev = state->dev;
961 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
962 u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD;
963 u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD;
964 u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC;
965 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
966 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
967 u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF;
969 v4l2_info(sd, "IR Receiver:\n");
970 v4l2_info(sd, "\tEnabled: %s\n",
971 cntrl & CNTRL_RXE ? "yes" : "no");
972 v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
973 cntrl & CNTRL_DMD ? "enabled" : "disabled");
974 v4l2_info(sd, "\tFIFO: %s\n",
975 cntrl & CNTRL_RFE ? "enabled" : "disabled");
976 switch (cntrl & CNTRL_EDG) {
987 s = "rising & falling edges";
993 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
994 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
995 cntrl & CNTRL_R ? "not loaded" : "overflow marker");
996 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
997 cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
998 v4l2_info(sd, "\tLoopback mode: %s\n",
999 cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
1000 if (cntrl & CNTRL_DMD) {
1001 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
1002 clock_divider_to_carrier_freq(rxclk));
1003 switch (cntrl & CNTRL_WIN) {
1025 v4l2_info(sd, "\tNext carrier edge window: 16 clocks "
1026 "-%1d/+%1d, %u to %u Hz\n", i, j,
1027 clock_divider_to_freq(rxclk, 16 + j),
1028 clock_divider_to_freq(rxclk, 16 - i));
1030 v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n",
1031 pulse_width_count_to_us(FIFO_RXTX, rxclk),
1032 pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1033 v4l2_info(sd, "\tLow pass filter: %s\n",
1034 filtr ? "enabled" : "disabled");
1036 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, "
1038 lpf_count_to_us(filtr),
1039 lpf_count_to_ns(filtr));
1040 v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
1041 stats & STATS_RTO ? "yes" : "no");
1042 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
1043 irqen & IRQEN_RTE ? "enabled" : "disabled");
1044 v4l2_info(sd, "\tFIFO overrun: %s\n",
1045 stats & STATS_ROR ? "yes" : "no");
1046 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
1047 irqen & IRQEN_ROE ? "enabled" : "disabled");
1048 v4l2_info(sd, "\tBusy: %s\n",
1049 stats & STATS_RBY ? "yes" : "no");
1050 v4l2_info(sd, "\tFIFO service requested: %s\n",
1051 stats & STATS_RSR ? "yes" : "no");
1052 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1053 irqen & IRQEN_RSE ? "enabled" : "disabled");
1055 v4l2_info(sd, "IR Transmitter:\n");
1056 v4l2_info(sd, "\tEnabled: %s\n",
1057 cntrl & CNTRL_TXE ? "yes" : "no");
1058 v4l2_info(sd, "\tModulation onto a carrier: %s\n",
1059 cntrl & CNTRL_MOD ? "enabled" : "disabled");
1060 v4l2_info(sd, "\tFIFO: %s\n",
1061 cntrl & CNTRL_TFE ? "enabled" : "disabled");
1062 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1063 cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1064 v4l2_info(sd, "\tOutput pin level inversion %s\n",
1065 cntrl & CNTRL_IVO ? "yes" : "no");
1066 v4l2_info(sd, "\tCarrier polarity: %s\n",
1067 cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1068 : "space:noburst mark:burst");
1069 if (cntrl & CNTRL_MOD) {
1070 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
1071 clock_divider_to_carrier_freq(txclk));
1072 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
1075 v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n",
1076 pulse_width_count_to_us(FIFO_RXTX, txclk),
1077 pulse_width_count_to_ns(FIFO_RXTX, txclk));
1078 v4l2_info(sd, "\tBusy: %s\n",
1079 stats & STATS_TBY ? "yes" : "no");
1080 v4l2_info(sd, "\tFIFO service requested: %s\n",
1081 stats & STATS_TSR ? "yes" : "no");
1082 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1083 irqen & IRQEN_TSE ? "enabled" : "disabled");
1088 static inline int cx23888_ir_dbg_match(const struct v4l2_dbg_match *match)
1090 return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 2;
1093 static int cx23888_ir_g_chip_ident(struct v4l2_subdev *sd,
1094 struct v4l2_dbg_chip_ident *chip)
1096 struct cx23888_ir_state *state = to_state(sd);
1098 if (cx23888_ir_dbg_match(&chip->match)) {
1099 chip->ident = state->id;
1100 chip->revision = state->rev;
1105 #ifdef CONFIG_VIDEO_ADV_DEBUG
1106 static int cx23888_ir_g_register(struct v4l2_subdev *sd,
1107 struct v4l2_dbg_register *reg)
1109 struct cx23888_ir_state *state = to_state(sd);
1110 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1112 if (!cx23888_ir_dbg_match(®->match))
1114 if ((addr & 0x3) != 0)
1116 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1118 if (!capable(CAP_SYS_ADMIN))
1121 reg->val = cx23888_ir_read4(state->dev, addr);
1125 static int cx23888_ir_s_register(struct v4l2_subdev *sd,
1126 struct v4l2_dbg_register *reg)
1128 struct cx23888_ir_state *state = to_state(sd);
1129 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1131 if (!cx23888_ir_dbg_match(®->match))
1133 if ((addr & 0x3) != 0)
1135 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1137 if (!capable(CAP_SYS_ADMIN))
1139 cx23888_ir_write4(state->dev, addr, reg->val);
1144 static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = {
1145 .g_chip_ident = cx23888_ir_g_chip_ident,
1146 .log_status = cx23888_ir_log_status,
1147 #ifdef CONFIG_VIDEO_ADV_DEBUG
1148 .g_register = cx23888_ir_g_register,
1149 .s_register = cx23888_ir_s_register,
1151 .interrupt_service_routine = cx23888_ir_irq_handler,
1154 static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = {
1155 .rx_read = cx23888_ir_rx_read,
1156 .rx_g_parameters = cx23888_ir_rx_g_parameters,
1157 .rx_s_parameters = cx23888_ir_rx_s_parameters,
1159 .tx_write = cx23888_ir_tx_write,
1160 .tx_g_parameters = cx23888_ir_tx_g_parameters,
1161 .tx_s_parameters = cx23888_ir_tx_s_parameters,
1164 static const struct v4l2_subdev_ops cx23888_ir_controller_ops = {
1165 .core = &cx23888_ir_core_ops,
1166 .ir = &cx23888_ir_ir_ops,
1169 static const struct v4l2_subdev_ir_parameters default_rx_params = {
1170 .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
1171 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1174 .interrupt_enable = false,
1178 .carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */
1180 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1181 /* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1182 .noise_filter_min_width = 333333, /* ns */
1183 .carrier_range_lower = 35000,
1184 .carrier_range_upper = 37000,
1185 .invert_level = false,
1188 static const struct v4l2_subdev_ir_parameters default_tx_params = {
1189 .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
1190 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1193 .interrupt_enable = false,
1197 .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1198 .duty_cycle = 25, /* 25 % - RC-5 carrier */
1199 .invert_level = false,
1200 .invert_carrier_sense = false,
1203 int cx23888_ir_probe(struct cx23885_dev *dev)
1205 struct cx23888_ir_state *state;
1206 struct v4l2_subdev *sd;
1207 struct v4l2_subdev_ir_parameters default_params;
1210 state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL);
1214 spin_lock_init(&state->rx_kfifo_lock);
1215 if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL))
1219 state->id = V4L2_IDENT_CX23888_IR;
1223 v4l2_subdev_init(sd, &cx23888_ir_controller_ops);
1224 v4l2_set_subdevdata(sd, state);
1225 /* FIXME - fix the formatting of dev->v4l2_dev.name and use it */
1226 snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name);
1227 sd->grp_id = CX23885_HW_888_IR;
1229 ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd);
1232 * Ensure no interrupts arrive from '888 specific conditions,
1233 * since we ignore them in this driver to have commonality with
1234 * similar IR controller cores.
1236 cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0);
1238 mutex_init(&state->rx_params_lock);
1239 memcpy(&default_params, &default_rx_params,
1240 sizeof(struct v4l2_subdev_ir_parameters));
1241 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1243 mutex_init(&state->tx_params_lock);
1244 memcpy(&default_params, &default_tx_params,
1245 sizeof(struct v4l2_subdev_ir_parameters));
1246 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1248 kfifo_free(&state->rx_kfifo);
1253 int cx23888_ir_remove(struct cx23885_dev *dev)
1255 struct v4l2_subdev *sd;
1256 struct cx23888_ir_state *state;
1258 sd = cx23885_find_hw(dev, CX23885_HW_888_IR);
1262 cx23888_ir_rx_shutdown(sd);
1263 cx23888_ir_tx_shutdown(sd);
1265 state = to_state(sd);
1266 v4l2_device_unregister_subdev(sd);
1267 kfifo_free(&state->rx_kfifo);
1269 /* Nothing more to free() as state held the actual v4l2_subdev object */