2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 #include "cx25821-video.h"
26 #include "cx25821-video-upstream-ch2.h"
29 #include <linux/errno.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/syscalls.h>
34 #include <linux/file.h>
35 #include <linux/fcntl.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
39 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
40 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
41 MODULE_LICENSE("GPL");
43 static int _intr_msk = FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC |
46 static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
47 __le32 *rp, unsigned int offset,
48 unsigned int bpl, u32 sync_line,
50 int fifo_enable, int field_type)
53 int dist_betwn_starts = bpl * 2;
55 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
57 if (USE_RISC_NOOP_VIDEO) {
58 for (i = 0; i < NUM_NO_OPS; i++)
59 *(rp++) = cpu_to_le32(RISC_NOOP);
63 for (line = 0; line < lines; line++) {
64 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
65 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
66 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
68 if ((lines <= NTSC_FIELD_HEIGHT) ||
69 (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC_ch2)) {
70 offset += dist_betwn_starts;
77 static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
79 dma_addr_t databuf_phys_addr,
81 u32 sync_line, unsigned int bpl,
83 int fifo_enable, int field_type)
86 struct sram_channel *sram_ch =
87 dev->channels[dev->_channel2_upstream_select].sram_channels;
88 int dist_betwn_starts = bpl * 2;
90 /* sync instruction */
91 if (sync_line != NO_SYNC_LINE)
92 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
94 if (USE_RISC_NOOP_VIDEO) {
95 for (i = 0; i < NUM_NO_OPS; i++)
96 *(rp++) = cpu_to_le32(RISC_NOOP);
100 for (line = 0; line < lines; line++) {
101 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
102 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
103 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
105 if ((lines <= NTSC_FIELD_HEIGHT) ||
106 (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC_ch2)) {
107 offset += dist_betwn_starts;
111 check if we need to enable the FIFO after the first 4 lines
112 For the upstream video channel, the risc engine will enable
115 if (fifo_enable && line == 3) {
116 *(rp++) = RISC_WRITECR;
117 *(rp++) = sram_ch->dma_ctl;
118 *(rp++) = FLD_VID_FIFO_EN;
119 *(rp++) = 0x00000001;
126 static int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
128 unsigned int top_offset,
134 int singlefield_lines = lines >> 1; /*get line count for single field */
135 int odd_num_lines = singlefield_lines;
138 int databuf_offset = 0;
139 int risc_program_size = 0;
140 int risc_flag = RISC_CNT_RESET;
141 unsigned int bottom_offset = bpl;
142 dma_addr_t risc_phys_jump_addr;
144 if (dev->_isNTSC_ch2) {
145 odd_num_lines = singlefield_lines + 1;
146 risc_program_size = FRAME1_VID_PROG_SIZE;
147 if (bpl == Y411_LINE_SZ)
148 frame_size = FRAME_SIZE_NTSC_Y411;
150 frame_size = FRAME_SIZE_NTSC_Y422;
152 risc_program_size = PAL_VID_PROG_SIZE;
153 if (bpl == Y411_LINE_SZ)
154 frame_size = FRAME_SIZE_PAL_Y411;
156 frame_size = FRAME_SIZE_PAL_Y422;
159 /* Virtual address of Risc buffer program */
160 rp = dev->_dma_virt_addr_ch2;
162 for (frame = 0; frame < NUM_FRAMES; frame++) {
163 databuf_offset = frame_size * frame;
165 if (UNSET != top_offset) {
166 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
167 rp = cx25821_risc_field_upstream_ch2(dev, rp,
168 dev->_data_buf_phys_addr_ch2 + databuf_offset,
169 top_offset, 0, bpl, odd_num_lines, fifo_enable,
173 fifo_enable = FIFO_DISABLE;
176 rp = cx25821_risc_field_upstream_ch2(dev, rp,
177 dev->_data_buf_phys_addr_ch2 + databuf_offset,
178 bottom_offset, 0x200, bpl, singlefield_lines,
179 fifo_enable, EVEN_FIELD);
182 risc_flag = RISC_CNT_RESET;
183 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2 +
186 risc_flag = RISC_CNT_INC;
187 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
191 * Loop to 2ndFrameRISC or to Start of
192 * Risc program & generate IRQ
194 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
195 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
196 *(rp++) = cpu_to_le32(0);
202 void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
204 struct sram_channel *sram_ch =
205 dev->channels[VID_UPSTREAM_SRAM_CHANNEL_J].sram_channels;
208 if (!dev->_is_running_ch2) {
209 pr_info("No video file is currently running so return!\n");
212 /* Disable RISC interrupts */
213 tmp = cx_read(sram_ch->int_msk);
214 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
216 /* Turn OFF risc and fifo */
217 tmp = cx_read(sram_ch->dma_ctl);
218 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
220 /* Clear data buffer memory */
221 if (dev->_data_buf_virt_addr_ch2)
222 memset(dev->_data_buf_virt_addr_ch2, 0,
223 dev->_data_buf_size_ch2);
225 dev->_is_running_ch2 = 0;
226 dev->_is_first_frame_ch2 = 0;
227 dev->_frame_count_ch2 = 0;
228 dev->_file_status_ch2 = END_OF_FILE;
230 kfree(dev->_irq_queues_ch2);
231 dev->_irq_queues_ch2 = NULL;
233 kfree(dev->_filename_ch2);
235 tmp = cx_read(VID_CH_MODE_SEL);
236 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
239 void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
241 if (dev->_is_running_ch2)
242 cx25821_stop_upstream_video_ch2(dev);
244 if (dev->_dma_virt_addr_ch2) {
245 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
246 dev->_dma_virt_addr_ch2,
247 dev->_dma_phys_addr_ch2);
248 dev->_dma_virt_addr_ch2 = NULL;
251 if (dev->_data_buf_virt_addr_ch2) {
252 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
253 dev->_data_buf_virt_addr_ch2,
254 dev->_data_buf_phys_addr_ch2);
255 dev->_data_buf_virt_addr_ch2 = NULL;
259 static int cx25821_get_frame_ch2(struct cx25821_dev *dev,
260 struct sram_channel *sram_ch)
263 int frame_index_temp = dev->_frame_index_ch2;
265 int line_size = (dev->_pixel_format_ch2 == PIXEL_FRMT_411) ?
266 Y411_LINE_SZ : Y422_LINE_SZ;
268 int frame_offset = 0;
269 ssize_t vfs_read_retval = 0;
270 char mybuf[line_size];
275 if (dev->_file_status_ch2 == END_OF_FILE)
278 if (dev->_isNTSC_ch2) {
279 frame_size = (line_size == Y411_LINE_SZ) ?
280 FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422;
282 frame_size = (line_size == Y411_LINE_SZ) ?
283 FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
286 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
287 file_offset = dev->_frame_count_ch2 * frame_size;
289 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
290 if (IS_ERR(myfile)) {
291 const int open_errno = -PTR_ERR(myfile);
292 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
293 __func__, dev->_filename_ch2, open_errno);
294 return PTR_ERR(myfile);
296 if (!(myfile->f_op)) {
297 pr_err("%s(): File has no file operations registered!\n",
299 filp_close(myfile, NULL);
303 if (!myfile->f_op->read) {
304 pr_err("%s(): File has no READ operations registered!\n",
306 filp_close(myfile, NULL);
314 for (i = 0; i < dev->_lines_count_ch2; i++) {
317 vfs_read_retval = vfs_read(myfile, mybuf, line_size,
320 if (vfs_read_retval > 0 && vfs_read_retval == line_size
321 && dev->_data_buf_virt_addr_ch2 != NULL) {
322 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
323 frame_offset / 4), mybuf,
327 file_offset += vfs_read_retval;
328 frame_offset += vfs_read_retval;
330 if (vfs_read_retval < line_size) {
331 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
338 dev->_frame_count_ch2++;
340 dev->_file_status_ch2 = (vfs_read_retval == line_size) ?
341 IN_PROGRESS : END_OF_FILE;
344 filp_close(myfile, NULL);
350 static void cx25821_vidups_handler_ch2(struct work_struct *work)
352 struct cx25821_dev *dev = container_of(work, struct cx25821_dev,
353 _irq_work_entry_ch2);
356 pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
361 cx25821_get_frame_ch2(dev, dev->channels[dev->
362 _channel2_upstream_select].sram_channels);
365 static int cx25821_openfile_ch2(struct cx25821_dev *dev,
366 struct sram_channel *sram_ch)
370 int line_size = (dev->_pixel_format_ch2 == PIXEL_FRMT_411) ?
371 Y411_LINE_SZ : Y422_LINE_SZ;
372 ssize_t vfs_read_retval = 0;
373 char mybuf[line_size];
375 loff_t offset = (unsigned long)0;
378 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
380 if (IS_ERR(myfile)) {
381 const int open_errno = -PTR_ERR(myfile);
382 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
383 __func__, dev->_filename_ch2, open_errno);
384 return PTR_ERR(myfile);
386 if (!(myfile->f_op)) {
387 pr_err("%s(): File has no file operations registered!\n",
389 filp_close(myfile, NULL);
393 if (!myfile->f_op->read) {
394 pr_err("%s(): File has no READ operations registered! Returning\n",
396 filp_close(myfile, NULL);
404 for (j = 0; j < NUM_FRAMES; j++) {
405 for (i = 0; i < dev->_lines_count_ch2; i++) {
408 vfs_read_retval = vfs_read(myfile, mybuf,
411 if (vfs_read_retval > 0 &&
412 vfs_read_retval == line_size &&
413 dev->_data_buf_virt_addr_ch2 != NULL) {
414 memcpy((void *)(dev->
415 _data_buf_virt_addr_ch2
416 + offset / 4), mybuf,
420 offset += vfs_read_retval;
422 if (vfs_read_retval < line_size) {
423 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
430 dev->_frame_count_ch2++;
432 if (vfs_read_retval < line_size)
436 dev->_file_status_ch2 = (vfs_read_retval == line_size) ?
437 IN_PROGRESS : END_OF_FILE;
441 filp_close(myfile, NULL);
447 static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
448 struct sram_channel *sram_ch,
453 dma_addr_t data_dma_addr;
455 if (dev->_dma_virt_addr_ch2 != NULL) {
456 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
457 dev->_dma_virt_addr_ch2,
458 dev->_dma_phys_addr_ch2);
461 dev->_dma_virt_addr_ch2 = pci_alloc_consistent(dev->pci,
462 dev->upstream_riscbuf_size_ch2, &dma_addr);
463 dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
464 dev->_dma_phys_start_addr_ch2 = dma_addr;
465 dev->_dma_phys_addr_ch2 = dma_addr;
466 dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
468 if (!dev->_dma_virt_addr_ch2) {
469 pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
473 /* Iniitize at this address until n bytes to 0 */
474 memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
476 if (dev->_data_buf_virt_addr_ch2 != NULL) {
477 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
478 dev->_data_buf_virt_addr_ch2,
479 dev->_data_buf_phys_addr_ch2);
481 /* For Video Data buffer allocation */
482 dev->_data_buf_virt_addr_ch2 = pci_alloc_consistent(dev->pci,
483 dev->upstream_databuf_size_ch2, &data_dma_addr);
484 dev->_data_buf_phys_addr_ch2 = data_dma_addr;
485 dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
487 if (!dev->_data_buf_virt_addr_ch2) {
488 pr_err("FAILED to allocate memory for data buffer! Returning\n");
492 /* Initialize at this address until n bytes to 0 */
493 memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
495 ret = cx25821_openfile_ch2(dev, sram_ch);
499 /* Creating RISC programs */
500 ret = cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
501 dev->_lines_count_ch2);
503 pr_info("Failed creating Video Upstream Risc programs!\n");
513 static int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev,
518 struct sram_channel *channel = dev->channels[chan_num].sram_channels;
519 int singlefield_lines = NTSC_FIELD_HEIGHT;
520 int line_size_in_bytes = Y422_LINE_SZ;
521 int odd_risc_prog_size = 0;
522 dma_addr_t risc_phys_jump_addr;
525 if (status & FLD_VID_SRC_RISC1) {
526 /* We should only process one program per call */
527 u32 prog_cnt = cx_read(channel->gpcnt);
530 * Since we've identified our IRQ, clear our bits from the
531 * interrupt mask and interrupt status registers
533 int_msk_tmp = cx_read(channel->int_msk);
534 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
535 cx_write(channel->int_stat, _intr_msk);
537 spin_lock(&dev->slock);
539 dev->_frame_index_ch2 = prog_cnt;
541 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
543 if (dev->_is_first_frame_ch2) {
544 dev->_is_first_frame_ch2 = 0;
546 if (dev->_isNTSC_ch2) {
547 singlefield_lines += 1;
548 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
550 singlefield_lines = PAL_FIELD_HEIGHT;
551 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
554 if (dev->_dma_virt_start_addr_ch2 != NULL) {
555 if (dev->_pixel_format_ch2 == PIXEL_FRMT_411)
556 line_size_in_bytes = Y411_LINE_SZ;
558 line_size_in_bytes = Y422_LINE_SZ;
559 risc_phys_jump_addr =
560 dev->_dma_phys_start_addr_ch2 +
563 rp = cx25821_update_riscprogram_ch2(dev,
564 dev->_dma_virt_start_addr_ch2,
565 TOP_OFFSET, line_size_in_bytes,
566 0x0, singlefield_lines,
567 FIFO_DISABLE, ODD_FIELD);
569 /* Jump to Even Risc program of 1st Frame */
570 *(rp++) = cpu_to_le32(RISC_JUMP);
571 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
572 *(rp++) = cpu_to_le32(0);
576 spin_unlock(&dev->slock);
579 if (dev->_file_status_ch2 == END_OF_FILE) {
580 pr_info("EOF Channel 2 Framecount = %d\n",
581 dev->_frame_count_ch2);
584 /* ElSE, set the interrupt mask register, re-enable irq. */
585 int_msk_tmp = cx_read(channel->int_msk);
586 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
591 static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
593 struct cx25821_dev *dev = dev_id;
597 struct sram_channel *sram_ch;
602 channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
603 sram_ch = dev->channels[channel_num].sram_channels;
605 vid_status = cx_read(sram_ch->int_stat);
607 /* Only deal with our interrupt */
609 handled = cx25821_video_upstream_irq_ch2(dev, channel_num,
613 cx25821_stop_upstream_video_ch2(dev);
617 return IRQ_RETVAL(handled);
620 static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
621 struct sram_channel *ch, int pix_format)
623 int width = WIDTH_D1;
624 int height = dev->_lines_count_ch2;
625 int num_lines, odd_num_lines;
627 int vip_mode = PIXEL_ENGINE_VIP1;
629 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
631 value |= dev->_isNTSC_ch2 ? 0 : 0x10;
632 cx_write(ch->vid_fmt_ctl, value);
635 * set number of active pixels in each line. Default is 720
636 * pixels in both NTSC and PAL format
638 cx_write(ch->vid_active_ctl1, width);
640 num_lines = (height / 2) & 0x3FF;
641 odd_num_lines = num_lines;
643 if (dev->_isNTSC_ch2)
646 value = (num_lines << 16) | odd_num_lines;
648 /* set number of active lines in field 0 (top) and field 1 (bottom) */
649 cx_write(ch->vid_active_ctl2, value);
651 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
654 static int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
655 struct sram_channel *sram_ch)
661 * 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface
664 tmp = cx_read(VID_CH_MODE_SEL);
665 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
668 * Set the physical start address of the RISC program in the initial
669 * program counter(IPC) member of the cmds.
671 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
672 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
675 cx_write(sram_ch->gpcnt_ctl, 3);
677 /* Clear our bits from the interrupt status register. */
678 cx_write(sram_ch->int_stat, _intr_msk);
680 /* Set the interrupt mask register, enable irq. */
681 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
682 tmp = cx_read(sram_ch->int_msk);
683 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
685 err = request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
686 IRQF_SHARED, dev->name, dev);
688 pr_err("%s: can't get upstream IRQ %d\n",
689 dev->name, dev->pci->irq);
692 /* Start the DMA engine */
693 tmp = cx_read(sram_ch->dma_ctl);
694 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
696 dev->_is_running_ch2 = 1;
697 dev->_is_first_frame_ch2 = 1;
702 cx25821_dev_unregister(dev);
706 int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
709 struct sram_channel *sram_ch;
712 int data_frame_size = 0;
713 int risc_buffer_size = 0;
715 if (dev->_is_running_ch2) {
716 pr_info("Video Channel is still running so return!\n");
720 dev->_channel2_upstream_select = channel_select;
721 sram_ch = dev->channels[channel_select].sram_channels;
723 INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
724 dev->_irq_queues_ch2 =
725 create_singlethread_workqueue("cx25821_workqueue2");
727 if (!dev->_irq_queues_ch2) {
728 pr_err("create_singlethread_workqueue() for Video FAILED!\n");
732 * 656/VIP SRC Upstream Channel I & J and 7 -
733 * Host Bus Interface for channel A-C
735 tmp = cx_read(VID_CH_MODE_SEL);
736 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
738 dev->_is_running_ch2 = 0;
739 dev->_frame_count_ch2 = 0;
740 dev->_file_status_ch2 = RESET_STATUS;
741 dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
742 dev->_pixel_format_ch2 = pixel_format;
743 dev->_line_size_ch2 = (dev->_pixel_format_ch2 == PIXEL_FRMT_422) ?
744 (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
745 data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
746 risc_buffer_size = dev->_isNTSC_ch2 ?
747 NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
749 if (dev->input_filename_ch2)
750 dev->_filename_ch2 = kstrdup(dev->input_filename_ch2,
753 dev->_filename_ch2 = kstrdup(dev->_defaultname_ch2,
756 if (!dev->_filename_ch2) {
761 /* Default if filename is empty string */
762 if (strcmp(dev->_filename_ch2, "") == 0) {
763 if (dev->_isNTSC_ch2) {
764 dev->_filename_ch2 = (dev->_pixel_format_ch2 ==
765 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
768 dev->_filename_ch2 = (dev->_pixel_format_ch2 ==
769 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
774 err = cx25821_sram_channel_setup_upstream(dev, sram_ch,
775 dev->_line_size_ch2, 0);
777 /* setup fifo + format */
778 cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
780 dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
781 dev->upstream_databuf_size_ch2 = data_frame_size * 2;
783 /* Allocating buffers and prepare RISC program */
784 err = cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
785 dev->_line_size_ch2);
787 pr_err("%s: Failed to set up Video upstream buffers!\n",
792 cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
797 cx25821_dev_unregister(dev);