2 * Copyright (C) 2008-2009 Texas Instruments Inc
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 * Image Sensor Interface (ISIF) driver
20 * This driver is for configuring the ISIF IP available on DM365 or any other
21 * TI SoCs. This is used for capturing yuv or bayer video or image data
22 * from a decoder or sensor. This IP is similar to the CCDC IP on DM355
23 * and DM6446, but with enhanced or additional ip blocks. The driver
24 * configures the ISIF upon commands from the vpfe bridge driver through
25 * ccdc_hw_device interface.
27 * TODO: 1) Raw bayer parameter settings and bayer capture
28 * 2) Add support for control ioctl
30 #include <linux/delay.h>
31 #include <linux/platform_device.h>
32 #include <linux/uaccess.h>
34 #include <linux/videodev2.h>
35 #include <linux/clk.h>
36 #include <linux/err.h>
37 #include <linux/module.h>
41 #include <media/davinci/isif.h>
42 #include <media/davinci/vpss.h>
44 #include "isif_regs.h"
45 #include "ccdc_hw_device.h"
47 /* Defaults for module configuration parameters */
48 static struct isif_config_params_raw isif_config_defaults = {
51 .corr_shft = ISIF_NO_SHIFT,
84 /* ISIF operation configuration */
85 static struct isif_oper_config {
87 enum vpfe_hw_if_type if_type;
88 struct isif_ycbcr_config ycbcr;
89 struct isif_params_raw bayer;
90 enum isif_data_pack data_pack;
93 /* ISIF base address */
94 void __iomem *base_addr;
95 /* ISIF Linear Table 0 */
96 void __iomem *linear_tbl0_addr;
97 /* ISIF Linear Table 1 */
98 void __iomem *linear_tbl1_addr;
101 .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
102 .frm_fmt = CCDC_FRMFMT_INTERLACED,
103 .win = ISIF_WIN_NTSC,
104 .fid_pol = VPFE_PINPOL_POSITIVE,
105 .vd_pol = VPFE_PINPOL_POSITIVE,
106 .hd_pol = VPFE_PINPOL_POSITIVE,
107 .pix_order = CCDC_PIXORDER_CBYCRY,
108 .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED,
111 .pix_fmt = CCDC_PIXFMT_RAW,
112 .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
114 .fid_pol = VPFE_PINPOL_POSITIVE,
115 .vd_pol = VPFE_PINPOL_POSITIVE,
116 .hd_pol = VPFE_PINPOL_POSITIVE,
123 .cfa_pat = ISIF_CFA_PAT_MOSAIC,
124 .data_msb = ISIF_BIT_MSB_11,
126 .data_shift = ISIF_NO_SHIFT,
128 .olop = ISIF_GREEN_BLUE,
131 .elep = ISIF_GREEN_RED,
134 .olop = ISIF_GREEN_BLUE,
137 .elep = ISIF_GREEN_RED,
142 .data_pack = ISIF_DATA_PACK8,
145 /* Raw Bayer formats */
146 static const u32 isif_raw_bayer_pix_formats[] = {
147 V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
149 /* Raw YUV formats */
150 static const u32 isif_raw_yuv_pix_formats[] = {
151 V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
153 /* register access routines */
154 static inline u32 regr(u32 offset)
156 return __raw_readl(isif_cfg.base_addr + offset);
159 static inline void regw(u32 val, u32 offset)
161 __raw_writel(val, isif_cfg.base_addr + offset);
164 /* reg_modify() - read, modify and write register */
165 static inline u32 reg_modify(u32 mask, u32 val, u32 offset)
167 u32 new_val = (regr(offset) & ~mask) | (val & mask);
169 regw(new_val, offset);
173 static inline void regw_lin_tbl(u32 val, u32 offset, int i)
176 __raw_writel(val, isif_cfg.linear_tbl0_addr + offset);
178 __raw_writel(val, isif_cfg.linear_tbl1_addr + offset);
181 static void isif_disable_all_modules(void)
189 /* disable linearization */
191 /* disable other modules here as they are supported */
194 static void isif_enable(int en)
197 /* Before disable isif, disable all ISIF modules */
198 isif_disable_all_modules();
200 * wait for next VD. Assume lowest scan rate is 12 Hz. So
201 * 100 msec delay is good enough
205 reg_modify(ISIF_SYNCEN_VDHDEN_MASK, en, SYNCEN);
208 static void isif_enable_output_to_sdram(int en)
210 reg_modify(ISIF_SYNCEN_WEN_MASK, en << ISIF_SYNCEN_WEN_SHIFT, SYNCEN);
213 static void isif_config_culling(struct isif_cul *cul)
217 /* Horizontal pattern */
218 val = (cul->hcpat_even << CULL_PAT_EVEN_LINE_SHIFT) | cul->hcpat_odd;
221 /* vertical pattern */
222 regw(cul->vcpat, CULV);
225 reg_modify(ISIF_LPF_MASK << ISIF_LPF_SHIFT,
226 cul->en_lpf << ISIF_LPF_SHIFT, MODESET);
229 static void isif_config_gain_offset(void)
231 struct isif_gain_offsets_adj *gain_off_p =
232 &isif_cfg.bayer.config_params.gain_offset;
235 val = (!!gain_off_p->gain_sdram_en << GAIN_SDRAM_EN_SHIFT) |
236 (!!gain_off_p->gain_ipipe_en << GAIN_IPIPE_EN_SHIFT) |
237 (!!gain_off_p->gain_h3a_en << GAIN_H3A_EN_SHIFT) |
238 (!!gain_off_p->offset_sdram_en << OFST_SDRAM_EN_SHIFT) |
239 (!!gain_off_p->offset_ipipe_en << OFST_IPIPE_EN_SHIFT) |
240 (!!gain_off_p->offset_h3a_en << OFST_H3A_EN_SHIFT);
242 reg_modify(GAIN_OFFSET_EN_MASK, val, CGAMMAWD);
244 val = (gain_off_p->gain.r_ye.integer << GAIN_INTEGER_SHIFT) |
245 gain_off_p->gain.r_ye.decimal;
248 val = (gain_off_p->gain.gr_cy.integer << GAIN_INTEGER_SHIFT) |
249 gain_off_p->gain.gr_cy.decimal;
252 val = (gain_off_p->gain.gb_g.integer << GAIN_INTEGER_SHIFT) |
253 gain_off_p->gain.gb_g.decimal;
256 val = (gain_off_p->gain.b_mg.integer << GAIN_INTEGER_SHIFT) |
257 gain_off_p->gain.b_mg.decimal;
260 regw(gain_off_p->offset, COFSTA);
263 static void isif_restore_defaults(void)
265 enum vpss_ccdc_source_sel source = VPSS_CCDCIN;
267 dev_dbg(isif_cfg.dev, "\nstarting isif_restore_defaults...");
268 isif_cfg.bayer.config_params = isif_config_defaults;
269 /* Enable clock to ISIF, IPIPEIF and BL */
270 vpss_enable_clock(VPSS_CCDC_CLOCK, 1);
271 vpss_enable_clock(VPSS_IPIPEIF_CLOCK, 1);
272 vpss_enable_clock(VPSS_BL_CLOCK, 1);
273 /* Set default offset and gain */
274 isif_config_gain_offset();
275 vpss_select_ccdc_source(source);
276 dev_dbg(isif_cfg.dev, "\nEnd of isif_restore_defaults...");
279 static int isif_open(struct device *device)
281 isif_restore_defaults();
285 /* This function will configure the window size to be capture in ISIF reg */
286 static void isif_setwin(struct v4l2_rect *image_win,
287 enum ccdc_frmfmt frm_fmt, int ppc)
289 int horz_start, horz_nr_pixels;
290 int vert_start, vert_nr_lines;
293 dev_dbg(isif_cfg.dev, "\nStarting isif_setwin...");
295 * ppc - per pixel count. indicates how many pixels per cell
296 * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
297 * raw capture this is 1
299 horz_start = image_win->left << (ppc - 1);
300 horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1;
302 /* Writing the horizontal info into the registers */
303 regw(horz_start & START_PX_HOR_MASK, SPH);
304 regw(horz_nr_pixels & NUM_PX_HOR_MASK, LNH);
305 vert_start = image_win->top;
307 if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
308 vert_nr_lines = (image_win->height >> 1) - 1;
310 /* To account for VD since line 0 doesn't have any data */
313 /* To account for VD since line 0 doesn't have any data */
315 vert_nr_lines = image_win->height - 1;
316 /* configure VDINT0 and VDINT1 */
317 mid_img = vert_start + (image_win->height / 2);
318 regw(mid_img, VDINT1);
322 regw(vert_start & START_VER_ONE_MASK, SLV0);
323 regw(vert_start & START_VER_TWO_MASK, SLV1);
324 regw(vert_nr_lines & NUM_LINES_VER, LNV);
327 static void isif_config_bclamp(struct isif_black_clamp *bc)
332 * DC Offset is always added to image data irrespective of bc enable
335 regw(bc->dc_offset, CLDCOFST);
338 val = bc->bc_mode_color << ISIF_BC_MODE_COLOR_SHIFT;
340 /* Enable BC and horizontal clamp caculation paramaters */
341 val = val | 1 | (bc->horz.mode << ISIF_HORZ_BC_MODE_SHIFT);
345 if (bc->horz.mode != ISIF_HORZ_BC_DISABLE) {
347 * Window count for calculation
348 * Base window selection
350 * Horizontal size of window
351 * vertical size of the window
352 * Horizontal start position of the window
353 * Vertical start position of the window
355 val = bc->horz.win_count_calc |
356 ((!!bc->horz.base_win_sel_calc) <<
357 ISIF_HORZ_BC_WIN_SEL_SHIFT) |
358 ((!!bc->horz.clamp_pix_limit) <<
359 ISIF_HORZ_BC_PIX_LIMIT_SHIFT) |
360 (bc->horz.win_h_sz_calc <<
361 ISIF_HORZ_BC_WIN_H_SIZE_SHIFT) |
362 (bc->horz.win_v_sz_calc <<
363 ISIF_HORZ_BC_WIN_V_SIZE_SHIFT);
366 regw(bc->horz.win_start_h_calc, CLHWIN1);
367 regw(bc->horz.win_start_v_calc, CLHWIN2);
370 /* vertical clamp caculation paramaters */
372 /* Reset clamp value sel for previous line */
374 (bc->vert.reset_val_sel << ISIF_VERT_BC_RST_VAL_SEL_SHIFT) |
375 (bc->vert.line_ave_coef << ISIF_VERT_BC_LINE_AVE_COEF_SHIFT);
378 /* Optical Black horizontal start position */
379 regw(bc->vert.ob_start_h, CLVWIN1);
380 /* Optical Black vertical start position */
381 regw(bc->vert.ob_start_v, CLVWIN2);
382 /* Optical Black vertical size for calculation */
383 regw(bc->vert.ob_v_sz_calc, CLVWIN3);
384 /* Vertical start position for BC subtraction */
385 regw(bc->vert_start_sub, CLSV);
389 static void isif_config_linearization(struct isif_linearize *linearize)
393 if (!linearize->en) {
398 /* shift value for correction & enable linearization (set lsb) */
399 val = (linearize->corr_shft << ISIF_LIN_CORRSFT_SHIFT) | 1;
403 val = ((!!linearize->scale_fact.integer) <<
404 ISIF_LIN_SCALE_FACT_INTEG_SHIFT) |
405 linearize->scale_fact.decimal;
408 for (i = 0; i < ISIF_LINEAR_TAB_SIZE; i++) {
410 regw_lin_tbl(linearize->table[i], ((i >> 1) << 2), 1);
412 regw_lin_tbl(linearize->table[i], ((i >> 1) << 2), 0);
416 static int isif_config_dfc(struct isif_dfc *vdfc)
418 /* initialize retries to loop for max ~ 250 usec */
419 u32 val, count, retries = loops_per_jiffy / (4000/HZ);
425 /* Correction mode */
426 val = (vdfc->corr_mode << ISIF_VDFC_CORR_MOD_SHIFT);
428 /* Correct whole line or partial */
429 if (vdfc->corr_whole_line)
430 val |= 1 << ISIF_VDFC_CORR_WHOLE_LN_SHIFT;
432 /* level shift value */
433 val |= vdfc->def_level_shift << ISIF_VDFC_LEVEL_SHFT_SHIFT;
437 /* Defect saturation level */
438 regw(vdfc->def_sat_level, VDFSATLV);
440 regw(vdfc->table[0].pos_vert, DFCMEM0);
441 regw(vdfc->table[0].pos_horz, DFCMEM1);
442 if (vdfc->corr_mode == ISIF_VDFC_NORMAL ||
443 vdfc->corr_mode == ISIF_VDFC_HORZ_INTERPOL_IF_SAT) {
444 regw(vdfc->table[0].level_at_pos, DFCMEM2);
445 regw(vdfc->table[0].level_up_pixels, DFCMEM3);
446 regw(vdfc->table[0].level_low_pixels, DFCMEM4);
449 /* set DFCMARST and set DFCMWR */
450 val = regr(DFCMEMCTL) | (1 << ISIF_DFCMEMCTL_DFCMARST_SHIFT) | 1;
451 regw(val, DFCMEMCTL);
454 while (count && (regr(DFCMEMCTL) & 0x1))
458 dev_dbg(isif_cfg.dev, "defect table write timeout !!!\n");
462 for (i = 1; i < vdfc->num_vdefects; i++) {
463 regw(vdfc->table[i].pos_vert, DFCMEM0);
464 regw(vdfc->table[i].pos_horz, DFCMEM1);
465 if (vdfc->corr_mode == ISIF_VDFC_NORMAL ||
466 vdfc->corr_mode == ISIF_VDFC_HORZ_INTERPOL_IF_SAT) {
467 regw(vdfc->table[i].level_at_pos, DFCMEM2);
468 regw(vdfc->table[i].level_up_pixels, DFCMEM3);
469 regw(vdfc->table[i].level_low_pixels, DFCMEM4);
471 val = regr(DFCMEMCTL);
472 /* clear DFCMARST and set DFCMWR */
473 val &= ~BIT(ISIF_DFCMEMCTL_DFCMARST_SHIFT);
475 regw(val, DFCMEMCTL);
478 while (count && (regr(DFCMEMCTL) & 0x1))
482 dev_err(isif_cfg.dev,
483 "defect table write timeout !!!\n");
487 if (vdfc->num_vdefects < ISIF_VDFC_TABLE_SIZE) {
488 /* Extra cycle needed */
490 regw(0x1FFF, DFCMEM1);
495 reg_modify((1 << ISIF_VDFC_EN_SHIFT), (1 << ISIF_VDFC_EN_SHIFT),
500 static void isif_config_csc(struct isif_df_csc *df_csc)
502 u32 val1 = 0, val2 = 0, i;
504 if (!df_csc->csc.en) {
508 for (i = 0; i < ISIF_CSC_NUM_COEFF; i++) {
511 val1 = (df_csc->csc.coeff[i].integer <<
512 ISIF_CSC_COEF_INTEG_SHIFT) |
513 df_csc->csc.coeff[i].decimal;
517 val2 = (df_csc->csc.coeff[i].integer <<
518 ISIF_CSC_COEF_INTEG_SHIFT) |
519 df_csc->csc.coeff[i].decimal;
520 val2 <<= ISIF_CSCM_MSB_SHIFT;
522 regw(val2, (CSCM0 + ((i - 1) << 1)));
526 /* program the active area */
527 regw(df_csc->start_pix, FMTSPH);
529 * one extra pixel as required for CSC. Actually number of
530 * pixel - 1 should be configured in this register. So we
531 * need to subtract 1 before writing to FMTSPH, but we will
532 * not do this since csc requires one extra pixel
534 regw(df_csc->num_pixels, FMTLNH);
535 regw(df_csc->start_line, FMTSLV);
537 * one extra line as required for CSC. See reason documented for
540 regw(df_csc->num_lines, FMTLNV);
546 static int isif_config_raw(void)
548 struct isif_params_raw *params = &isif_cfg.bayer;
549 struct isif_config_params_raw *module_params =
550 &isif_cfg.bayer.config_params;
551 struct vpss_pg_frame_size frame_size;
552 struct vpss_sync_pol sync;
555 dev_dbg(isif_cfg.dev, "\nStarting isif_config_raw..\n");
558 * Configure CCDCFG register:-
559 * Set CCD Not to swap input since input is RAW data
560 * Set FID detection function to Latch at V-Sync
561 * Set WENLOG - isif valid area
564 * Packed to 8 or 16 bits
567 val = ISIF_YCINSWP_RAW | ISIF_CCDCFG_FIDMD_LATCH_VSYNC |
568 ISIF_CCDCFG_WENLOG_AND | ISIF_CCDCFG_TRGSEL_WEN |
569 ISIF_CCDCFG_EXTRG_DISABLE | isif_cfg.data_pack;
571 dev_dbg(isif_cfg.dev, "Writing 0x%x to ...CCDCFG \n", val);
575 * Configure the vertical sync polarity(MODESET.VDPOL)
576 * Configure the horizontal sync polarity (MODESET.HDPOL)
577 * Configure frame id polarity (MODESET.FLDPOL)
578 * Configure data polarity
579 * Configure External WEN Selection
580 * Configure frame format(progressive or interlace)
581 * Configure pixel format (Input mode)
582 * Configure the data shift
585 val = ISIF_VDHDOUT_INPUT | (params->vd_pol << ISIF_VD_POL_SHIFT) |
586 (params->hd_pol << ISIF_HD_POL_SHIFT) |
587 (params->fid_pol << ISIF_FID_POL_SHIFT) |
588 (ISIF_DATAPOL_NORMAL << ISIF_DATAPOL_SHIFT) |
589 (ISIF_EXWEN_DISABLE << ISIF_EXWEN_SHIFT) |
590 (params->frm_fmt << ISIF_FRM_FMT_SHIFT) |
591 (params->pix_fmt << ISIF_INPUT_SHIFT) |
592 (params->config_params.data_shift << ISIF_DATASFT_SHIFT);
595 dev_dbg(isif_cfg.dev, "Writing 0x%x to MODESET...\n", val);
598 * Configure GAMMAWD register
599 * CFA pattern setting
601 val = params->cfa_pat << ISIF_GAMMAWD_CFA_SHIFT;
604 if (module_params->compress.alg == ISIF_ALAW)
605 val |= ISIF_ALAW_ENABLE;
607 val |= (params->data_msb << ISIF_ALAW_GAMA_WD_SHIFT);
610 /* Configure DPCM compression settings */
611 if (module_params->compress.alg == ISIF_DPCM) {
612 val = BIT(ISIF_DPCM_EN_SHIFT) |
613 (module_params->compress.pred <<
614 ISIF_DPCM_PREDICTOR_SHIFT);
619 /* Configure Gain & Offset */
620 isif_config_gain_offset();
622 /* Configure Color pattern */
623 val = (params->config_params.col_pat_field0.olop) |
624 (params->config_params.col_pat_field0.olep << 2) |
625 (params->config_params.col_pat_field0.elop << 4) |
626 (params->config_params.col_pat_field0.elep << 6) |
627 (params->config_params.col_pat_field1.olop << 8) |
628 (params->config_params.col_pat_field1.olep << 10) |
629 (params->config_params.col_pat_field1.elop << 12) |
630 (params->config_params.col_pat_field1.elep << 14);
632 dev_dbg(isif_cfg.dev, "Writing %x to CCOLP ...\n", val);
634 /* Configure HSIZE register */
635 val = (!!params->horz_flip_en) << ISIF_HSIZE_FLIP_SHIFT;
637 /* calculate line offset in 32 bytes based on pack value */
638 if (isif_cfg.data_pack == ISIF_PACK_8BIT)
639 val |= ((params->win.width + 31) >> 5);
640 else if (isif_cfg.data_pack == ISIF_PACK_12BIT)
641 val |= (((params->win.width +
642 (params->win.width >> 2)) + 31) >> 5);
644 val |= (((params->win.width * 2) + 31) >> 5);
647 /* Configure SDOFST register */
648 if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
649 if (params->image_invert_en) {
650 /* For interlace inverse mode */
651 regw(0x4B6D, SDOFST);
652 dev_dbg(isif_cfg.dev, "Writing 0x4B6D to SDOFST...\n");
654 /* For interlace non inverse mode */
655 regw(0x0B6D, SDOFST);
656 dev_dbg(isif_cfg.dev, "Writing 0x0B6D to SDOFST...\n");
658 } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
659 if (params->image_invert_en) {
660 /* For progressive inverse mode */
661 regw(0x4000, SDOFST);
662 dev_dbg(isif_cfg.dev, "Writing 0x4000 to SDOFST...\n");
664 /* For progressive non inverse mode */
665 regw(0x0000, SDOFST);
666 dev_dbg(isif_cfg.dev, "Writing 0x0000 to SDOFST...\n");
670 /* Configure video window */
671 isif_setwin(¶ms->win, params->frm_fmt, 1);
673 /* Configure Black Clamp */
674 isif_config_bclamp(&module_params->bclamp);
676 /* Configure Vertical Defection Pixel Correction */
677 if (isif_config_dfc(&module_params->dfc) < 0)
680 if (!module_params->df_csc.df_or_csc)
681 /* Configure Color Space Conversion */
682 isif_config_csc(&module_params->df_csc);
684 isif_config_linearization(&module_params->linearize);
686 /* Configure Culling */
687 isif_config_culling(&module_params->culling);
689 /* Configure horizontal and vertical offsets(DFC,LSC,Gain) */
690 regw(module_params->horz_offset, DATAHOFST);
691 regw(module_params->vert_offset, DATAVOFST);
693 /* Setup test pattern if enabled */
694 if (params->config_params.test_pat_gen) {
695 /* Use the HD/VD pol settings from user */
696 sync.ccdpg_hdpol = params->hd_pol;
697 sync.ccdpg_vdpol = params->vd_pol;
698 dm365_vpss_set_sync_pol(sync);
699 frame_size.hlpfr = isif_cfg.bayer.win.width;
700 frame_size.pplen = isif_cfg.bayer.win.height;
701 dm365_vpss_set_pg_frame_size(frame_size);
702 vpss_select_ccdc_source(VPSS_PGLPBK);
705 dev_dbg(isif_cfg.dev, "\nEnd of isif_config_ycbcr...\n");
709 static int isif_set_buftype(enum ccdc_buftype buf_type)
711 if (isif_cfg.if_type == VPFE_RAW_BAYER)
712 isif_cfg.bayer.buf_type = buf_type;
714 isif_cfg.ycbcr.buf_type = buf_type;
719 static enum ccdc_buftype isif_get_buftype(void)
721 if (isif_cfg.if_type == VPFE_RAW_BAYER)
722 return isif_cfg.bayer.buf_type;
724 return isif_cfg.ycbcr.buf_type;
727 static int isif_enum_pix(u32 *pix, int i)
731 if (isif_cfg.if_type == VPFE_RAW_BAYER) {
732 if (i < ARRAY_SIZE(isif_raw_bayer_pix_formats)) {
733 *pix = isif_raw_bayer_pix_formats[i];
737 if (i < ARRAY_SIZE(isif_raw_yuv_pix_formats)) {
738 *pix = isif_raw_yuv_pix_formats[i];
746 static int isif_set_pixel_format(unsigned int pixfmt)
748 if (isif_cfg.if_type == VPFE_RAW_BAYER) {
749 if (pixfmt == V4L2_PIX_FMT_SBGGR8) {
750 if ((isif_cfg.bayer.config_params.compress.alg !=
752 (isif_cfg.bayer.config_params.compress.alg !=
754 dev_dbg(isif_cfg.dev,
755 "Either configure A-Law or DPCM\n");
758 isif_cfg.data_pack = ISIF_PACK_8BIT;
759 } else if (pixfmt == V4L2_PIX_FMT_SBGGR16) {
760 isif_cfg.bayer.config_params.compress.alg =
762 isif_cfg.data_pack = ISIF_PACK_16BIT;
765 isif_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
767 if (pixfmt == V4L2_PIX_FMT_YUYV)
768 isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
769 else if (pixfmt == V4L2_PIX_FMT_UYVY)
770 isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
773 isif_cfg.data_pack = ISIF_PACK_8BIT;
778 static u32 isif_get_pixel_format(void)
782 if (isif_cfg.if_type == VPFE_RAW_BAYER)
783 if (isif_cfg.bayer.config_params.compress.alg == ISIF_ALAW ||
784 isif_cfg.bayer.config_params.compress.alg == ISIF_DPCM)
785 pixfmt = V4L2_PIX_FMT_SBGGR8;
787 pixfmt = V4L2_PIX_FMT_SBGGR16;
789 if (isif_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
790 pixfmt = V4L2_PIX_FMT_YUYV;
792 pixfmt = V4L2_PIX_FMT_UYVY;
797 static int isif_set_image_window(struct v4l2_rect *win)
799 if (isif_cfg.if_type == VPFE_RAW_BAYER) {
800 isif_cfg.bayer.win.top = win->top;
801 isif_cfg.bayer.win.left = win->left;
802 isif_cfg.bayer.win.width = win->width;
803 isif_cfg.bayer.win.height = win->height;
805 isif_cfg.ycbcr.win.top = win->top;
806 isif_cfg.ycbcr.win.left = win->left;
807 isif_cfg.ycbcr.win.width = win->width;
808 isif_cfg.ycbcr.win.height = win->height;
813 static void isif_get_image_window(struct v4l2_rect *win)
815 if (isif_cfg.if_type == VPFE_RAW_BAYER)
816 *win = isif_cfg.bayer.win;
818 *win = isif_cfg.ycbcr.win;
821 static unsigned int isif_get_line_length(void)
825 if (isif_cfg.if_type == VPFE_RAW_BAYER) {
826 if (isif_cfg.data_pack == ISIF_PACK_8BIT)
827 len = ((isif_cfg.bayer.win.width));
828 else if (isif_cfg.data_pack == ISIF_PACK_12BIT)
829 len = (((isif_cfg.bayer.win.width * 2) +
830 (isif_cfg.bayer.win.width >> 2)));
832 len = (((isif_cfg.bayer.win.width * 2)));
834 len = (((isif_cfg.ycbcr.win.width * 2)));
835 return ALIGN(len, 32);
838 static int isif_set_frame_format(enum ccdc_frmfmt frm_fmt)
840 if (isif_cfg.if_type == VPFE_RAW_BAYER)
841 isif_cfg.bayer.frm_fmt = frm_fmt;
843 isif_cfg.ycbcr.frm_fmt = frm_fmt;
846 static enum ccdc_frmfmt isif_get_frame_format(void)
848 if (isif_cfg.if_type == VPFE_RAW_BAYER)
849 return isif_cfg.bayer.frm_fmt;
850 return isif_cfg.ycbcr.frm_fmt;
853 static int isif_getfid(void)
855 return (regr(MODESET) >> 15) & 0x1;
858 /* misc operations */
859 static void isif_setfbaddr(unsigned long addr)
861 regw((addr >> 21) & 0x07ff, CADU);
862 regw((addr >> 5) & 0x0ffff, CADL);
865 static int isif_set_hw_if_params(struct vpfe_hw_if_param *params)
867 isif_cfg.if_type = params->if_type;
869 switch (params->if_type) {
871 case VPFE_BT656_10BIT:
872 case VPFE_YCBCR_SYNC_8:
873 isif_cfg.ycbcr.pix_fmt = CCDC_PIXFMT_YCBCR_8BIT;
874 isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
877 case VPFE_YCBCR_SYNC_16:
878 isif_cfg.ycbcr.pix_fmt = CCDC_PIXFMT_YCBCR_16BIT;
879 isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
882 isif_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
885 dev_dbg(isif_cfg.dev, "Invalid interface type\n");
892 /* This function will configure ISIF for YCbCr parameters. */
893 static int isif_config_ycbcr(void)
895 struct isif_ycbcr_config *params = &isif_cfg.ycbcr;
896 struct vpss_pg_frame_size frame_size;
897 u32 modeset = 0, ccdcfg = 0;
898 struct vpss_sync_pol sync;
900 dev_dbg(isif_cfg.dev, "\nStarting isif_config_ycbcr...");
902 /* configure pixel format or input mode */
903 modeset = modeset | (params->pix_fmt << ISIF_INPUT_SHIFT) |
904 (params->frm_fmt << ISIF_FRM_FMT_SHIFT) |
905 (params->fid_pol << ISIF_FID_POL_SHIFT) |
906 (params->hd_pol << ISIF_HD_POL_SHIFT) |
907 (params->vd_pol << ISIF_VD_POL_SHIFT);
909 /* pack the data to 8-bit ISIFCFG */
910 switch (isif_cfg.if_type) {
912 if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
913 dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
916 modeset |= (VPFE_PINPOL_NEGATIVE << ISIF_VD_POL_SHIFT);
918 ccdcfg = ccdcfg | ISIF_DATA_PACK8 | ISIF_YCINSWP_YCBCR;
920 case VPFE_BT656_10BIT:
921 if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
922 dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
925 /* setup BT.656, embedded sync */
927 /* enable 10 bit mode in ccdcfg */
928 ccdcfg = ccdcfg | ISIF_DATA_PACK8 | ISIF_YCINSWP_YCBCR |
932 if (params->pix_fmt != CCDC_PIXFMT_YCBCR_16BIT) {
933 dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
939 case VPFE_YCBCR_SYNC_8:
940 ccdcfg |= ISIF_DATA_PACK8;
941 ccdcfg |= ISIF_YCINSWP_YCBCR;
942 if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
943 dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
947 case VPFE_YCBCR_SYNC_16:
948 if (params->pix_fmt != CCDC_PIXFMT_YCBCR_16BIT) {
949 dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
954 /* should never come here */
955 dev_dbg(isif_cfg.dev, "Invalid interface type\n");
959 regw(modeset, MODESET);
961 /* Set up pix order */
962 ccdcfg |= params->pix_order << ISIF_PIX_ORDER_SHIFT;
964 regw(ccdcfg, CCDCFG);
966 /* configure video window */
967 if ((isif_cfg.if_type == VPFE_BT1120) ||
968 (isif_cfg.if_type == VPFE_YCBCR_SYNC_16))
969 isif_setwin(¶ms->win, params->frm_fmt, 1);
971 isif_setwin(¶ms->win, params->frm_fmt, 2);
974 * configure the horizontal line offset
975 * this is done by rounding up width to a multiple of 16 pixels
976 * and multiply by two to account for y:cb:cr 4:2:2 data
978 regw(((((params->win.width * 2) + 31) & 0xffffffe0) >> 5), HSIZE);
980 /* configure the memory line offset */
981 if ((params->frm_fmt == CCDC_FRMFMT_INTERLACED) &&
982 (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED))
983 /* two fields are interleaved in memory */
984 regw(0x00000249, SDOFST);
986 /* Setup test pattern if enabled */
987 if (isif_cfg.bayer.config_params.test_pat_gen) {
988 sync.ccdpg_hdpol = params->hd_pol;
989 sync.ccdpg_vdpol = params->vd_pol;
990 dm365_vpss_set_sync_pol(sync);
991 dm365_vpss_set_pg_frame_size(frame_size);
996 static int isif_configure(void)
998 if (isif_cfg.if_type == VPFE_RAW_BAYER)
999 return isif_config_raw();
1000 return isif_config_ycbcr();
1003 static int isif_close(struct device *device)
1005 /* copy defaults to module params */
1006 isif_cfg.bayer.config_params = isif_config_defaults;
1010 static struct ccdc_hw_device isif_hw_dev = {
1012 .owner = THIS_MODULE,
1015 .close = isif_close,
1016 .enable = isif_enable,
1017 .enable_out_to_sdram = isif_enable_output_to_sdram,
1018 .set_hw_if_params = isif_set_hw_if_params,
1019 .configure = isif_configure,
1020 .set_buftype = isif_set_buftype,
1021 .get_buftype = isif_get_buftype,
1022 .enum_pix = isif_enum_pix,
1023 .set_pixel_format = isif_set_pixel_format,
1024 .get_pixel_format = isif_get_pixel_format,
1025 .set_frame_format = isif_set_frame_format,
1026 .get_frame_format = isif_get_frame_format,
1027 .set_image_window = isif_set_image_window,
1028 .get_image_window = isif_get_image_window,
1029 .get_line_length = isif_get_line_length,
1030 .setfbaddr = isif_setfbaddr,
1031 .getfid = isif_getfid,
1035 static int isif_probe(struct platform_device *pdev)
1037 void (*setup_pinmux)(void);
1038 struct resource *res;
1043 * first try to register with vpfe. If not correct platform, then we
1044 * don't have to iomap
1046 status = vpfe_register_ccdc_device(&isif_hw_dev);
1050 /* Get and enable Master clock */
1051 isif_cfg.mclk = clk_get(&pdev->dev, "master");
1052 if (IS_ERR(isif_cfg.mclk)) {
1053 status = PTR_ERR(isif_cfg.mclk);
1056 if (clk_prepare_enable(isif_cfg.mclk)) {
1061 /* Platform data holds setup_pinmux function ptr */
1062 if (NULL == pdev->dev.platform_data) {
1066 setup_pinmux = pdev->dev.platform_data;
1068 * setup Mux configuration for ccdc which may be different for
1069 * different SoCs using this CCDC
1074 /* Get the ISIF base address, linearization table0 and table1 addr. */
1076 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1079 goto fail_nobase_res;
1081 res = request_mem_region(res->start, resource_size(res),
1085 goto fail_nobase_res;
1087 addr = ioremap_nocache(res->start, resource_size(res));
1090 goto fail_base_iomap;
1094 /* ISIF base address */
1095 isif_cfg.base_addr = addr;
1098 /* ISIF linear tbl0 address */
1099 isif_cfg.linear_tbl0_addr = addr;
1102 /* ISIF linear tbl0 address */
1103 isif_cfg.linear_tbl1_addr = addr;
1108 isif_cfg.dev = &pdev->dev;
1110 printk(KERN_NOTICE "%s is registered with vpfe.\n",
1114 release_mem_region(res->start, resource_size(res));
1117 if (isif_cfg.base_addr)
1118 iounmap(isif_cfg.base_addr);
1119 if (isif_cfg.linear_tbl0_addr)
1120 iounmap(isif_cfg.linear_tbl0_addr);
1123 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1124 release_mem_region(res->start, resource_size(res));
1128 clk_disable_unprepare(isif_cfg.mclk);
1129 clk_put(isif_cfg.mclk);
1130 vpfe_unregister_ccdc_device(&isif_hw_dev);
1134 static int isif_remove(struct platform_device *pdev)
1136 struct resource *res;
1139 iounmap(isif_cfg.base_addr);
1140 iounmap(isif_cfg.linear_tbl0_addr);
1141 iounmap(isif_cfg.linear_tbl1_addr);
1143 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1145 release_mem_region(res->start, resource_size(res));
1148 vpfe_unregister_ccdc_device(&isif_hw_dev);
1149 clk_disable_unprepare(isif_cfg.mclk);
1150 clk_put(isif_cfg.mclk);
1154 static struct platform_driver isif_driver = {
1157 .owner = THIS_MODULE,
1159 .remove = isif_remove,
1160 .probe = isif_probe,
1163 module_platform_driver(isif_driver);
1165 MODULE_LICENSE("GPL");