2 * vpif - Video Port Interface driver
3 * VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
4 * that receiveing video byte stream and two channels(2, 3) for video output.
5 * The hardware supports SDTV, HDTV formats, raw data capture.
6 * Currently, the driver supports NTSC and PAL standards.
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation version 2.
14 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
15 * kind, whether express or implied; without even the implied warranty
16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/spinlock.h>
24 #include <linux/kernel.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/v4l2-dv-timings.h>
30 #include <mach/hardware.h>
34 MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
35 MODULE_LICENSE("GPL");
37 #define VPIF_CH0_MAX_MODES (22)
38 #define VPIF_CH1_MAX_MODES (02)
39 #define VPIF_CH2_MAX_MODES (15)
40 #define VPIF_CH3_MAX_MODES (02)
42 static resource_size_t res_len;
43 static struct resource *res;
46 void __iomem *vpif_base;
50 * ch_params: video standard configuration parameters for vpif
51 * The table must include all presets from supported subdevices.
53 const struct vpif_channel_config_params ch_params[] = {
70 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
87 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
104 .dv_timings = V4L2_DV_BT_CEA_1280X720P50,
121 .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
141 .dv_timings = V4L2_DV_BT_CEA_1920X1080I50,
161 .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
178 .dv_timings = V4L2_DV_BT_CEA_1920X1080P60,
200 .stdid = V4L2_STD_525_60,
203 .name = "PAL_BDGHIK",
220 .stdid = V4L2_STD_625_50,
224 const unsigned int vpif_ch_params_count = ARRAY_SIZE(ch_params);
226 static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
229 vpif_set_bit(reg, bit);
231 vpif_clr_bit(reg, bit);
234 /* This structure is used to keep track of VPIF size register's offsets */
235 struct vpif_registers {
236 u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
237 u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
238 u32 vanc1_size, width_mask, len_mask;
242 static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
245 VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
246 VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
247 VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
252 VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
253 VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
254 VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
259 VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
260 VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
261 VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
262 VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
267 VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
268 VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
269 VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
270 VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
275 /* vpif_set_mode_info:
276 * This function is used to set horizontal and vertical config parameters
277 * As per the standard in the channel, configure the values of L1, L3,
278 * L5, L7 L9, L11 in VPIF Register , also write width and height
280 static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
281 u8 channel_id, u8 config_channel_id)
285 value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
286 value <<= VPIF_CH_LEN_SHIFT;
287 value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
288 regw(value, vpifregs[channel_id].h_cfg);
290 value = (config->l1 & vpifregs[config_channel_id].len_mask);
291 value <<= VPIF_CH_LEN_SHIFT;
292 value |= (config->l3 & vpifregs[config_channel_id].len_mask);
293 regw(value, vpifregs[channel_id].v_cfg_00);
295 value = (config->l5 & vpifregs[config_channel_id].len_mask);
296 value <<= VPIF_CH_LEN_SHIFT;
297 value |= (config->l7 & vpifregs[config_channel_id].len_mask);
298 regw(value, vpifregs[channel_id].v_cfg_01);
300 value = (config->l9 & vpifregs[config_channel_id].len_mask);
301 value <<= VPIF_CH_LEN_SHIFT;
302 value |= (config->l11 & vpifregs[config_channel_id].len_mask);
303 regw(value, vpifregs[channel_id].v_cfg_02);
305 value = (config->vsize & vpifregs[config_channel_id].len_mask);
306 regw(value, vpifregs[channel_id].v_cfg);
309 /* config_vpif_params
310 * Function to set the parameters of a channel
311 * Mainly modifies the channel ciontrol register
312 * It sets frame format, yc mux mode
314 static void config_vpif_params(struct vpif_params *vpifparams,
315 u8 channel_id, u8 found)
317 const struct vpif_channel_config_params *config = &vpifparams->std_info;
318 u32 value, ch_nip, reg;
323 end = channel_id + found;
325 for (i = start; i < end; i++) {
326 reg = vpifregs[i].ch_ctrl;
328 ch_nip = VPIF_CAPTURE_CH_NIP;
330 ch_nip = VPIF_DISPLAY_CH_NIP;
332 vpif_wr_bit(reg, ch_nip, config->frm_fmt);
333 vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
334 vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
335 vpifparams->video_params.storage_mode);
337 /* Set raster scanning SDR Format */
338 vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
339 vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
341 if (channel_id > 1) /* Set the Pixel enable bit */
342 vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
343 else if (config->capture_format) {
344 /* Set the polarity of various pins */
345 vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
346 vpifparams->iface.fid_pol);
347 vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
348 vpifparams->iface.vd_pol);
349 vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
350 vpifparams->iface.hd_pol);
355 VPIF_CH_DATA_WIDTH_BIT);
356 value |= ((vpifparams->params.data_sz) <<
357 VPIF_CH_DATA_WIDTH_BIT);
361 /* Write the pitch in the driver */
362 regw((vpifparams->video_params.hpitch),
363 vpifregs[i].line_offset);
367 /* vpif_set_video_params
368 * This function is used to set video parameters in VPIF register
370 int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
372 const struct vpif_channel_config_params *config = &vpifparams->std_info;
375 vpif_set_mode_info(config, channel_id, channel_id);
376 if (!config->ycmux_mode) {
377 /* YC are on separate channels (HDTV formats) */
378 vpif_set_mode_info(config, channel_id + 1, channel_id);
382 config_vpif_params(vpifparams, channel_id, found);
384 regw(0x80, VPIF_REQ_SIZE);
385 regw(0x01, VPIF_EMULATION_CTRL);
389 EXPORT_SYMBOL(vpif_set_video_params);
391 void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
396 value = 0x3F8 & (vbiparams->hstart0);
397 value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
398 regw(value, vpifregs[channel_id].vanc0_strt);
400 value = 0x3F8 & (vbiparams->hstart1);
401 value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
402 regw(value, vpifregs[channel_id].vanc1_strt);
404 value = 0x3F8 & (vbiparams->hsize0);
405 value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
406 regw(value, vpifregs[channel_id].vanc0_size);
408 value = 0x3F8 & (vbiparams->hsize1);
409 value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
410 regw(value, vpifregs[channel_id].vanc1_size);
413 EXPORT_SYMBOL(vpif_set_vbi_display_params);
415 int vpif_channel_getfid(u8 channel_id)
417 return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
418 >> VPIF_CH_FID_SHIFT;
420 EXPORT_SYMBOL(vpif_channel_getfid);
422 static int vpif_probe(struct platform_device *pdev)
426 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
430 res_len = resource_size(res);
432 res = request_mem_region(res->start, res_len, res->name);
436 vpif_base = ioremap(res->start, res_len);
442 vpif_clk = clk_get(&pdev->dev, "vpif");
443 if (IS_ERR(vpif_clk)) {
444 status = PTR_ERR(vpif_clk);
447 clk_prepare_enable(vpif_clk);
449 spin_lock_init(&vpif_lock);
450 dev_info(&pdev->dev, "vpif probe success\n");
456 release_mem_region(res->start, res_len);
460 static int vpif_remove(struct platform_device *pdev)
463 clk_disable_unprepare(vpif_clk);
468 release_mem_region(res->start, res_len);
473 static int vpif_suspend(struct device *dev)
475 clk_disable_unprepare(vpif_clk);
479 static int vpif_resume(struct device *dev)
481 clk_prepare_enable(vpif_clk);
485 static const struct dev_pm_ops vpif_pm = {
486 .suspend = vpif_suspend,
487 .resume = vpif_resume,
490 #define vpif_pm_ops (&vpif_pm)
492 #define vpif_pm_ops NULL
495 static struct platform_driver vpif_driver = {
498 .owner = THIS_MODULE,
501 .remove = vpif_remove,
505 static void vpif_exit(void)
507 platform_driver_unregister(&vpif_driver);
510 static int __init vpif_init(void)
512 return platform_driver_register(&vpif_driver);
514 subsys_initcall(vpif_init);
515 module_exit(vpif_exit);