2 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Samsung EXYNOS5 SoC series G-Scaler driver
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
14 #include <linux/delay.h>
19 void gsc_hw_set_sw_reset(struct gsc_dev *dev)
21 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET);
24 int gsc_wait_reset(struct gsc_dev *dev)
26 unsigned long end = jiffies + msecs_to_jiffies(50);
29 while (time_before(jiffies, end)) {
30 cfg = readl(dev->regs + GSC_SW_RESET);
39 void gsc_hw_set_frm_done_irq_mask(struct gsc_dev *dev, bool mask)
43 cfg = readl(dev->regs + GSC_IRQ);
45 cfg |= GSC_IRQ_FRMDONE_MASK;
47 cfg &= ~GSC_IRQ_FRMDONE_MASK;
48 writel(cfg, dev->regs + GSC_IRQ);
51 void gsc_hw_set_gsc_irq_enable(struct gsc_dev *dev, bool mask)
55 cfg = readl(dev->regs + GSC_IRQ);
57 cfg |= GSC_IRQ_ENABLE;
59 cfg &= ~GSC_IRQ_ENABLE;
60 writel(cfg, dev->regs + GSC_IRQ);
63 void gsc_hw_set_input_buf_masking(struct gsc_dev *dev, u32 shift,
66 u32 cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
67 u32 mask = 1 << shift;
70 cfg |= enable << shift;
72 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
73 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK);
74 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK);
77 void gsc_hw_set_output_buf_masking(struct gsc_dev *dev, u32 shift,
80 u32 cfg = readl(dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
81 u32 mask = 1 << shift;
84 cfg |= enable << shift;
86 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
87 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK);
88 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK);
91 void gsc_hw_set_input_addr(struct gsc_dev *dev, struct gsc_addr *addr,
94 pr_debug("src_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X", index,
95 addr->y, addr->cb, addr->cr);
96 writel(addr->y, dev->regs + GSC_IN_BASE_ADDR_Y(index));
97 writel(addr->cb, dev->regs + GSC_IN_BASE_ADDR_CB(index));
98 writel(addr->cr, dev->regs + GSC_IN_BASE_ADDR_CR(index));
102 void gsc_hw_set_output_addr(struct gsc_dev *dev,
103 struct gsc_addr *addr, int index)
105 pr_debug("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
106 index, addr->y, addr->cb, addr->cr);
107 writel(addr->y, dev->regs + GSC_OUT_BASE_ADDR_Y(index));
108 writel(addr->cb, dev->regs + GSC_OUT_BASE_ADDR_CB(index));
109 writel(addr->cr, dev->regs + GSC_OUT_BASE_ADDR_CR(index));
112 void gsc_hw_set_input_path(struct gsc_ctx *ctx)
114 struct gsc_dev *dev = ctx->gsc_dev;
116 u32 cfg = readl(dev->regs + GSC_IN_CON);
117 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
119 if (ctx->in_path == GSC_DMA)
120 cfg |= GSC_IN_PATH_MEMORY;
122 writel(cfg, dev->regs + GSC_IN_CON);
125 void gsc_hw_set_in_size(struct gsc_ctx *ctx)
127 struct gsc_dev *dev = ctx->gsc_dev;
128 struct gsc_frame *frame = &ctx->s_frame;
131 /* Set input pixel offset */
132 cfg = GSC_SRCIMG_OFFSET_X(frame->crop.left);
133 cfg |= GSC_SRCIMG_OFFSET_Y(frame->crop.top);
134 writel(cfg, dev->regs + GSC_SRCIMG_OFFSET);
136 /* Set input original size */
137 cfg = GSC_SRCIMG_WIDTH(frame->f_width);
138 cfg |= GSC_SRCIMG_HEIGHT(frame->f_height);
139 writel(cfg, dev->regs + GSC_SRCIMG_SIZE);
141 /* Set input cropped size */
142 cfg = GSC_CROPPED_WIDTH(frame->crop.width);
143 cfg |= GSC_CROPPED_HEIGHT(frame->crop.height);
144 writel(cfg, dev->regs + GSC_CROPPED_SIZE);
147 void gsc_hw_set_in_image_rgb(struct gsc_ctx *ctx)
149 struct gsc_dev *dev = ctx->gsc_dev;
150 struct gsc_frame *frame = &ctx->s_frame;
153 cfg = readl(dev->regs + GSC_IN_CON);
154 if (frame->colorspace == V4L2_COLORSPACE_REC709)
155 cfg |= GSC_IN_RGB_HD_WIDE;
157 cfg |= GSC_IN_RGB_SD_WIDE;
159 if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB565X)
160 cfg |= GSC_IN_RGB565;
161 else if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB32)
162 cfg |= GSC_IN_XRGB8888;
164 writel(cfg, dev->regs + GSC_IN_CON);
167 void gsc_hw_set_in_image_format(struct gsc_ctx *ctx)
169 struct gsc_dev *dev = ctx->gsc_dev;
170 struct gsc_frame *frame = &ctx->s_frame;
174 cfg = readl(dev->regs + GSC_IN_CON);
175 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
176 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
177 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE);
178 writel(cfg, dev->regs + GSC_IN_CON);
180 if (is_rgb(frame->fmt->color)) {
181 gsc_hw_set_in_image_rgb(ctx);
184 for (i = 0; i < frame->fmt->num_planes; i++)
185 depth += frame->fmt->depth[i];
187 switch (frame->fmt->num_comp) {
189 cfg |= GSC_IN_YUV422_1P;
190 if (frame->fmt->yorder == GSC_LSB_Y)
191 cfg |= GSC_IN_YUV422_1P_ORDER_LSB_Y;
193 cfg |= GSC_IN_YUV422_1P_OEDER_LSB_C;
194 if (frame->fmt->corder == GSC_CBCR)
195 cfg |= GSC_IN_CHROMA_ORDER_CBCR;
197 cfg |= GSC_IN_CHROMA_ORDER_CRCB;
201 cfg |= GSC_IN_YUV420_2P;
203 cfg |= GSC_IN_YUV422_2P;
204 if (frame->fmt->corder == GSC_CBCR)
205 cfg |= GSC_IN_CHROMA_ORDER_CBCR;
207 cfg |= GSC_IN_CHROMA_ORDER_CRCB;
211 cfg |= GSC_IN_YUV420_3P;
213 cfg |= GSC_IN_YUV422_3P;
217 writel(cfg, dev->regs + GSC_IN_CON);
220 void gsc_hw_set_output_path(struct gsc_ctx *ctx)
222 struct gsc_dev *dev = ctx->gsc_dev;
224 u32 cfg = readl(dev->regs + GSC_OUT_CON);
225 cfg &= ~GSC_OUT_PATH_MASK;
227 if (ctx->out_path == GSC_DMA)
228 cfg |= GSC_OUT_PATH_MEMORY;
230 cfg |= GSC_OUT_PATH_LOCAL;
232 writel(cfg, dev->regs + GSC_OUT_CON);
235 void gsc_hw_set_out_size(struct gsc_ctx *ctx)
237 struct gsc_dev *dev = ctx->gsc_dev;
238 struct gsc_frame *frame = &ctx->d_frame;
241 /* Set output original size */
242 if (ctx->out_path == GSC_DMA) {
243 cfg = GSC_DSTIMG_OFFSET_X(frame->crop.left);
244 cfg |= GSC_DSTIMG_OFFSET_Y(frame->crop.top);
245 writel(cfg, dev->regs + GSC_DSTIMG_OFFSET);
247 cfg = GSC_DSTIMG_WIDTH(frame->f_width);
248 cfg |= GSC_DSTIMG_HEIGHT(frame->f_height);
249 writel(cfg, dev->regs + GSC_DSTIMG_SIZE);
252 /* Set output scaled size */
253 if (ctx->gsc_ctrls.rotate->val == 90 ||
254 ctx->gsc_ctrls.rotate->val == 270) {
255 cfg = GSC_SCALED_WIDTH(frame->crop.height);
256 cfg |= GSC_SCALED_HEIGHT(frame->crop.width);
258 cfg = GSC_SCALED_WIDTH(frame->crop.width);
259 cfg |= GSC_SCALED_HEIGHT(frame->crop.height);
261 writel(cfg, dev->regs + GSC_SCALED_SIZE);
264 void gsc_hw_set_out_image_rgb(struct gsc_ctx *ctx)
266 struct gsc_dev *dev = ctx->gsc_dev;
267 struct gsc_frame *frame = &ctx->d_frame;
270 cfg = readl(dev->regs + GSC_OUT_CON);
271 if (frame->colorspace == V4L2_COLORSPACE_REC709)
272 cfg |= GSC_OUT_RGB_HD_WIDE;
274 cfg |= GSC_OUT_RGB_SD_WIDE;
276 if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB565X)
277 cfg |= GSC_OUT_RGB565;
278 else if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB32)
279 cfg |= GSC_OUT_XRGB8888;
281 writel(cfg, dev->regs + GSC_OUT_CON);
284 void gsc_hw_set_out_image_format(struct gsc_ctx *ctx)
286 struct gsc_dev *dev = ctx->gsc_dev;
287 struct gsc_frame *frame = &ctx->d_frame;
291 cfg = readl(dev->regs + GSC_OUT_CON);
292 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
293 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
294 GSC_OUT_TILE_TYPE_MASK | GSC_OUT_TILE_MODE);
295 writel(cfg, dev->regs + GSC_OUT_CON);
297 if (is_rgb(frame->fmt->color)) {
298 gsc_hw_set_out_image_rgb(ctx);
302 if (ctx->out_path != GSC_DMA) {
303 cfg |= GSC_OUT_YUV444;
307 for (i = 0; i < frame->fmt->num_planes; i++)
308 depth += frame->fmt->depth[i];
310 switch (frame->fmt->num_comp) {
312 cfg |= GSC_OUT_YUV422_1P;
313 if (frame->fmt->yorder == GSC_LSB_Y)
314 cfg |= GSC_OUT_YUV422_1P_ORDER_LSB_Y;
316 cfg |= GSC_OUT_YUV422_1P_OEDER_LSB_C;
317 if (frame->fmt->corder == GSC_CBCR)
318 cfg |= GSC_OUT_CHROMA_ORDER_CBCR;
320 cfg |= GSC_OUT_CHROMA_ORDER_CRCB;
324 cfg |= GSC_OUT_YUV420_2P;
326 cfg |= GSC_OUT_YUV422_2P;
327 if (frame->fmt->corder == GSC_CBCR)
328 cfg |= GSC_OUT_CHROMA_ORDER_CBCR;
330 cfg |= GSC_OUT_CHROMA_ORDER_CRCB;
333 cfg |= GSC_OUT_YUV420_3P;
338 writel(cfg, dev->regs + GSC_OUT_CON);
341 void gsc_hw_set_prescaler(struct gsc_ctx *ctx)
343 struct gsc_dev *dev = ctx->gsc_dev;
344 struct gsc_scaler *sc = &ctx->scaler;
347 cfg = GSC_PRESC_SHFACTOR(sc->pre_shfactor);
348 cfg |= GSC_PRESC_H_RATIO(sc->pre_hratio);
349 cfg |= GSC_PRESC_V_RATIO(sc->pre_vratio);
350 writel(cfg, dev->regs + GSC_PRE_SCALE_RATIO);
353 void gsc_hw_set_mainscaler(struct gsc_ctx *ctx)
355 struct gsc_dev *dev = ctx->gsc_dev;
356 struct gsc_scaler *sc = &ctx->scaler;
359 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
360 writel(cfg, dev->regs + GSC_MAIN_H_RATIO);
362 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
363 writel(cfg, dev->regs + GSC_MAIN_V_RATIO);
366 void gsc_hw_set_rotation(struct gsc_ctx *ctx)
368 struct gsc_dev *dev = ctx->gsc_dev;
371 cfg = readl(dev->regs + GSC_IN_CON);
372 cfg &= ~GSC_IN_ROT_MASK;
374 switch (ctx->gsc_ctrls.rotate->val) {
376 cfg |= GSC_IN_ROT_270;
379 cfg |= GSC_IN_ROT_180;
382 if (ctx->gsc_ctrls.hflip->val)
383 cfg |= GSC_IN_ROT_90_XFLIP;
384 else if (ctx->gsc_ctrls.vflip->val)
385 cfg |= GSC_IN_ROT_90_YFLIP;
387 cfg |= GSC_IN_ROT_90;
390 if (ctx->gsc_ctrls.hflip->val)
391 cfg |= GSC_IN_ROT_XFLIP;
392 else if (ctx->gsc_ctrls.vflip->val)
393 cfg |= GSC_IN_ROT_YFLIP;
396 writel(cfg, dev->regs + GSC_IN_CON);
399 void gsc_hw_set_global_alpha(struct gsc_ctx *ctx)
401 struct gsc_dev *dev = ctx->gsc_dev;
402 struct gsc_frame *frame = &ctx->d_frame;
405 if (!is_rgb(frame->fmt->color)) {
406 pr_debug("Not a RGB format");
410 cfg = readl(dev->regs + GSC_OUT_CON);
411 cfg &= ~GSC_OUT_GLOBAL_ALPHA_MASK;
413 cfg |= GSC_OUT_GLOBAL_ALPHA(ctx->gsc_ctrls.global_alpha->val);
414 writel(cfg, dev->regs + GSC_OUT_CON);
417 void gsc_hw_set_sfr_update(struct gsc_ctx *ctx)
419 struct gsc_dev *dev = ctx->gsc_dev;
422 cfg = readl(dev->regs + GSC_ENABLE);
423 cfg |= GSC_ENABLE_SFR_UPDATE;
424 writel(cfg, dev->regs + GSC_ENABLE);