2 * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
4 * Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/kernel.h>
20 #include <linux/memory.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/videodev2.h>
28 #include <media/v4l2-subdev.h>
29 #include <linux/platform_data/mipi-csis.h>
30 #include "mipi-csis.h"
33 module_param(debug, int, 0644);
34 MODULE_PARM_DESC(debug, "Debug level (0-2)");
36 /* Register map definition */
38 /* CSIS global control */
39 #define S5PCSIS_CTRL 0x00
40 #define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31)
41 #define S5PCSIS_CTRL_DPDN_SWAP (1 << 31)
42 #define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20)
43 #define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16)
44 #define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8)
45 #define S5PCSIS_CTRL_RESET (1 << 4)
46 #define S5PCSIS_CTRL_ENABLE (1 << 0)
49 #define S5PCSIS_DPHYCTRL 0x04
50 #define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27)
51 #define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0)
53 #define S5PCSIS_CONFIG 0x08
54 #define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2)
55 #define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2)
56 #define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2)
57 #define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2)
58 /* User defined formats, x = 1...4 */
59 #define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2)
60 #define S5PCSIS_CFG_FMT_MASK (0x3f << 2)
61 #define S5PCSIS_CFG_NR_LANE_MASK 3
64 #define S5PCSIS_INTMSK 0x10
65 #define S5PCSIS_INTMSK_EN_ALL 0xf000103f
66 #define S5PCSIS_INTMSK_EVEN_BEFORE (1 << 31)
67 #define S5PCSIS_INTMSK_EVEN_AFTER (1 << 30)
68 #define S5PCSIS_INTMSK_ODD_BEFORE (1 << 29)
69 #define S5PCSIS_INTMSK_ODD_AFTER (1 << 28)
70 #define S5PCSIS_INTMSK_ERR_SOT_HS (1 << 12)
71 #define S5PCSIS_INTMSK_ERR_LOST_FS (1 << 5)
72 #define S5PCSIS_INTMSK_ERR_LOST_FE (1 << 4)
73 #define S5PCSIS_INTMSK_ERR_OVER (1 << 3)
74 #define S5PCSIS_INTMSK_ERR_ECC (1 << 2)
75 #define S5PCSIS_INTMSK_ERR_CRC (1 << 1)
76 #define S5PCSIS_INTMSK_ERR_UNKNOWN (1 << 0)
78 /* Interrupt source */
79 #define S5PCSIS_INTSRC 0x14
80 #define S5PCSIS_INTSRC_EVEN_BEFORE (1 << 31)
81 #define S5PCSIS_INTSRC_EVEN_AFTER (1 << 30)
82 #define S5PCSIS_INTSRC_EVEN (0x3 << 30)
83 #define S5PCSIS_INTSRC_ODD_BEFORE (1 << 29)
84 #define S5PCSIS_INTSRC_ODD_AFTER (1 << 28)
85 #define S5PCSIS_INTSRC_ODD (0x3 << 28)
86 #define S5PCSIS_INTSRC_NON_IMAGE_DATA (0xff << 28)
87 #define S5PCSIS_INTSRC_ERR_SOT_HS (0xf << 12)
88 #define S5PCSIS_INTSRC_ERR_LOST_FS (1 << 5)
89 #define S5PCSIS_INTSRC_ERR_LOST_FE (1 << 4)
90 #define S5PCSIS_INTSRC_ERR_OVER (1 << 3)
91 #define S5PCSIS_INTSRC_ERR_ECC (1 << 2)
92 #define S5PCSIS_INTSRC_ERR_CRC (1 << 1)
93 #define S5PCSIS_INTSRC_ERR_UNKNOWN (1 << 0)
94 #define S5PCSIS_INTSRC_ERRORS 0xf03f
96 /* Pixel resolution */
97 #define S5PCSIS_RESOL 0x2c
98 #define CSIS_MAX_PIX_WIDTH 0xffff
99 #define CSIS_MAX_PIX_HEIGHT 0xffff
101 /* Non-image packet data buffers */
102 #define S5PCSIS_PKTDATA_ODD 0x2000
103 #define S5PCSIS_PKTDATA_EVEN 0x3000
104 #define S5PCSIS_PKTDATA_SIZE SZ_4K
111 static char *csi_clock_name[] = {
112 [CSIS_CLK_MUX] = "sclk_csis",
113 [CSIS_CLK_GATE] = "csis",
115 #define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
117 static const char * const csis_supply_name[] = {
118 "vddcore", /* CSIS Core (1.0V, 1.1V or 1.2V) suppply */
119 "vddio", /* CSIS I/O and PLL (1.8V) supply */
121 #define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name)
129 struct s5pcsis_event {
131 const char * const name;
132 unsigned int counter;
135 static const struct s5pcsis_event s5pcsis_events[] = {
137 { S5PCSIS_INTSRC_ERR_SOT_HS, "SOT Error" },
138 { S5PCSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" },
139 { S5PCSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" },
140 { S5PCSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" },
141 { S5PCSIS_INTSRC_ERR_ECC, "ECC Error" },
142 { S5PCSIS_INTSRC_ERR_CRC, "CRC Error" },
143 { S5PCSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" },
144 /* Non-image data receive events */
145 { S5PCSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" },
146 { S5PCSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" },
147 { S5PCSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" },
148 { S5PCSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" },
150 #define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events)
158 * struct csis_state - the driver's internal state data structure
159 * @lock: mutex serializing the subdev and power management operations,
160 * protecting @format and @flags members
161 * @pads: CSIS pads array
162 * @sd: v4l2_subdev associated with CSIS device instance
163 * @index: the hardware instance index
164 * @pdev: CSIS platform device
165 * @regs: mmaped I/O registers memory
166 * @supplies: CSIS regulator supplies
167 * @clock: CSIS clocks
168 * @irq: requested s5p-mipi-csis irq number
169 * @flags: the state variable for power and streaming control
170 * @csis_fmt: current CSIS pixel format
171 * @format: common media bus format for the source and sink pad
172 * @slock: spinlock protecting structure members below
173 * @pkt_buf: the frame embedded (non-image) data buffer
174 * @events: MIPI-CSIS event (error) counters
178 struct media_pad pads[CSIS_PADS_NUM];
179 struct v4l2_subdev sd;
181 struct platform_device *pdev;
183 struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES];
184 struct clk *clock[NUM_CSIS_CLOCKS];
187 const struct csis_pix_format *csis_fmt;
188 struct v4l2_mbus_framefmt format;
190 struct spinlock slock;
191 struct csis_pktbuf pkt_buf;
192 struct s5pcsis_event events[S5PCSIS_NUM_EVENTS];
196 * struct csis_pix_format - CSIS pixel format description
197 * @pix_width_alignment: horizontal pixel alignment, width will be
198 * multiple of 2^pix_width_alignment
199 * @code: corresponding media bus code
200 * @fmt_reg: S5PCSIS_CONFIG register value
201 * @data_alignment: MIPI-CSI data alignment in bits
203 struct csis_pix_format {
204 unsigned int pix_width_alignment;
205 enum v4l2_mbus_pixelcode code;
210 static const struct csis_pix_format s5pcsis_formats[] = {
212 .code = V4L2_MBUS_FMT_VYUY8_2X8,
213 .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
214 .data_alignment = 32,
216 .code = V4L2_MBUS_FMT_JPEG_1X8,
217 .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
218 .data_alignment = 32,
220 .code = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8,
221 .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
222 .data_alignment = 32,
226 #define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
227 #define s5pcsis_read(__csis, __r) readl(__csis->regs + __r)
229 static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev)
231 return container_of(sdev, struct csis_state, sd);
234 static const struct csis_pix_format *find_csis_format(
235 struct v4l2_mbus_framefmt *mf)
239 for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++)
240 if (mf->code == s5pcsis_formats[i].code)
241 return &s5pcsis_formats[i];
245 static void s5pcsis_enable_interrupts(struct csis_state *state, bool on)
247 u32 val = s5pcsis_read(state, S5PCSIS_INTMSK);
249 val = on ? val | S5PCSIS_INTMSK_EN_ALL :
250 val & ~S5PCSIS_INTMSK_EN_ALL;
251 s5pcsis_write(state, S5PCSIS_INTMSK, val);
254 static void s5pcsis_reset(struct csis_state *state)
256 u32 val = s5pcsis_read(state, S5PCSIS_CTRL);
258 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET);
262 static void s5pcsis_system_enable(struct csis_state *state, int on)
266 val = s5pcsis_read(state, S5PCSIS_CTRL);
268 val |= S5PCSIS_CTRL_ENABLE;
270 val &= ~S5PCSIS_CTRL_ENABLE;
271 s5pcsis_write(state, S5PCSIS_CTRL, val);
273 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
275 val |= S5PCSIS_DPHYCTRL_ENABLE;
277 val &= ~S5PCSIS_DPHYCTRL_ENABLE;
278 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
281 /* Called with the state.lock mutex held */
282 static void __s5pcsis_set_format(struct csis_state *state)
284 struct v4l2_mbus_framefmt *mf = &state->format;
287 v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n",
288 mf->code, mf->width, mf->height);
291 val = s5pcsis_read(state, S5PCSIS_CONFIG);
292 val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg;
293 s5pcsis_write(state, S5PCSIS_CONFIG, val);
295 /* Pixel resolution */
296 val = (mf->width << 16) | mf->height;
297 s5pcsis_write(state, S5PCSIS_RESOL, val);
300 static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle)
302 u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
304 val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27);
305 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
308 static void s5pcsis_set_params(struct csis_state *state)
310 struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data;
313 val = s5pcsis_read(state, S5PCSIS_CONFIG);
314 val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (pdata->lanes - 1);
315 s5pcsis_write(state, S5PCSIS_CONFIG, val);
317 __s5pcsis_set_format(state);
318 s5pcsis_set_hsync_settle(state, pdata->hs_settle);
320 val = s5pcsis_read(state, S5PCSIS_CTRL);
321 if (state->csis_fmt->data_alignment == 32)
322 val |= S5PCSIS_CTRL_ALIGN_32BIT;
324 val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
326 val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
327 if (pdata->wclk_source)
328 val |= S5PCSIS_CTRL_WCLK_EXTCLK;
329 s5pcsis_write(state, S5PCSIS_CTRL, val);
331 /* Update the shadow register. */
332 val = s5pcsis_read(state, S5PCSIS_CTRL);
333 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
336 static void s5pcsis_clk_put(struct csis_state *state)
340 for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
341 if (IS_ERR_OR_NULL(state->clock[i]))
343 clk_unprepare(state->clock[i]);
344 clk_put(state->clock[i]);
345 state->clock[i] = NULL;
349 static int s5pcsis_clk_get(struct csis_state *state)
351 struct device *dev = &state->pdev->dev;
354 for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
355 state->clock[i] = clk_get(dev, csi_clock_name[i]);
356 if (IS_ERR(state->clock[i]))
358 ret = clk_prepare(state->clock[i]);
360 clk_put(state->clock[i]);
361 state->clock[i] = NULL;
367 s5pcsis_clk_put(state);
368 dev_err(dev, "failed to get clock: %s\n", csi_clock_name[i]);
372 static void s5pcsis_start_stream(struct csis_state *state)
374 s5pcsis_reset(state);
375 s5pcsis_set_params(state);
376 s5pcsis_system_enable(state, true);
377 s5pcsis_enable_interrupts(state, true);
380 static void s5pcsis_stop_stream(struct csis_state *state)
382 s5pcsis_enable_interrupts(state, false);
383 s5pcsis_system_enable(state, false);
386 static void s5pcsis_clear_counters(struct csis_state *state)
391 spin_lock_irqsave(&state->slock, flags);
392 for (i = 0; i < S5PCSIS_NUM_EVENTS; i++)
393 state->events[i].counter = 0;
394 spin_unlock_irqrestore(&state->slock, flags);
397 static void s5pcsis_log_counters(struct csis_state *state, bool non_errors)
399 int i = non_errors ? S5PCSIS_NUM_EVENTS : S5PCSIS_NUM_EVENTS - 4;
402 spin_lock_irqsave(&state->slock, flags);
404 for (i--; i >= 0; i--)
405 if (state->events[i].counter >= 0)
406 v4l2_info(&state->sd, "%s events: %d\n",
407 state->events[i].name,
408 state->events[i].counter);
410 spin_unlock_irqrestore(&state->slock, flags);
414 * V4L2 subdev operations
416 static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
418 struct csis_state *state = sd_to_csis_state(sd);
419 struct device *dev = &state->pdev->dev;
422 return pm_runtime_get_sync(dev);
424 return pm_runtime_put_sync(dev);
427 static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable)
429 struct csis_state *state = sd_to_csis_state(sd);
432 v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n",
433 __func__, enable, state->flags);
436 s5pcsis_clear_counters(state);
437 ret = pm_runtime_get_sync(&state->pdev->dev);
442 mutex_lock(&state->lock);
444 if (state->flags & ST_SUSPENDED) {
448 s5pcsis_start_stream(state);
449 state->flags |= ST_STREAMING;
451 s5pcsis_stop_stream(state);
452 state->flags &= ~ST_STREAMING;
454 s5pcsis_log_counters(state, true);
457 mutex_unlock(&state->lock);
459 pm_runtime_put(&state->pdev->dev);
461 return ret == 1 ? 0 : ret;
464 static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd,
465 struct v4l2_subdev_fh *fh,
466 struct v4l2_subdev_mbus_code_enum *code)
468 if (code->index >= ARRAY_SIZE(s5pcsis_formats))
471 code->code = s5pcsis_formats[code->index].code;
475 static struct csis_pix_format const *s5pcsis_try_format(
476 struct v4l2_mbus_framefmt *mf)
478 struct csis_pix_format const *csis_fmt;
480 csis_fmt = find_csis_format(mf);
481 if (csis_fmt == NULL)
482 csis_fmt = &s5pcsis_formats[0];
484 mf->code = csis_fmt->code;
485 v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
486 csis_fmt->pix_width_alignment,
487 &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
492 static struct v4l2_mbus_framefmt *__s5pcsis_get_format(
493 struct csis_state *state, struct v4l2_subdev_fh *fh,
494 u32 pad, enum v4l2_subdev_format_whence which)
496 if (which == V4L2_SUBDEV_FORMAT_TRY)
497 return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL;
499 return &state->format;
502 static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
503 struct v4l2_subdev_format *fmt)
505 struct csis_state *state = sd_to_csis_state(sd);
506 struct csis_pix_format const *csis_fmt;
507 struct v4l2_mbus_framefmt *mf;
509 if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
512 mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
514 if (fmt->pad == CSIS_PAD_SOURCE) {
516 mutex_lock(&state->lock);
518 mutex_unlock(&state->lock);
522 csis_fmt = s5pcsis_try_format(&fmt->format);
524 mutex_lock(&state->lock);
526 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
527 state->csis_fmt = csis_fmt;
528 mutex_unlock(&state->lock);
533 static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
534 struct v4l2_subdev_format *fmt)
536 struct csis_state *state = sd_to_csis_state(sd);
537 struct v4l2_mbus_framefmt *mf;
539 if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
542 mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
546 mutex_lock(&state->lock);
548 mutex_unlock(&state->lock);
552 static int s5pcsis_s_rx_buffer(struct v4l2_subdev *sd, void *buf,
555 struct csis_state *state = sd_to_csis_state(sd);
558 *size = min_t(unsigned int, *size, S5PCSIS_PKTDATA_SIZE);
560 spin_lock_irqsave(&state->slock, flags);
561 state->pkt_buf.data = buf;
562 state->pkt_buf.len = *size;
563 spin_unlock_irqrestore(&state->slock, flags);
568 static int s5pcsis_log_status(struct v4l2_subdev *sd)
570 struct csis_state *state = sd_to_csis_state(sd);
572 s5pcsis_log_counters(state, true);
576 static int s5pcsis_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
578 struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0);
580 format->colorspace = V4L2_COLORSPACE_JPEG;
581 format->code = s5pcsis_formats[0].code;
582 format->width = S5PCSIS_DEF_PIX_WIDTH;
583 format->height = S5PCSIS_DEF_PIX_HEIGHT;
584 format->field = V4L2_FIELD_NONE;
589 static const struct v4l2_subdev_internal_ops s5pcsis_sd_internal_ops = {
590 .open = s5pcsis_open,
593 static struct v4l2_subdev_core_ops s5pcsis_core_ops = {
594 .s_power = s5pcsis_s_power,
595 .log_status = s5pcsis_log_status,
598 static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
599 .enum_mbus_code = s5pcsis_enum_mbus_code,
600 .get_fmt = s5pcsis_get_fmt,
601 .set_fmt = s5pcsis_set_fmt,
604 static struct v4l2_subdev_video_ops s5pcsis_video_ops = {
605 .s_rx_buffer = s5pcsis_s_rx_buffer,
606 .s_stream = s5pcsis_s_stream,
609 static struct v4l2_subdev_ops s5pcsis_subdev_ops = {
610 .core = &s5pcsis_core_ops,
611 .pad = &s5pcsis_pad_ops,
612 .video = &s5pcsis_video_ops,
615 static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
617 struct csis_state *state = dev_id;
618 struct csis_pktbuf *pktbuf = &state->pkt_buf;
622 status = s5pcsis_read(state, S5PCSIS_INTSRC);
623 spin_lock_irqsave(&state->slock, flags);
625 if ((status & S5PCSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) {
628 if (status & S5PCSIS_INTSRC_EVEN)
629 offset = S5PCSIS_PKTDATA_EVEN;
631 offset = S5PCSIS_PKTDATA_ODD;
633 memcpy(pktbuf->data, state->regs + offset, pktbuf->len);
638 /* Update the event/error counters */
639 if ((status & S5PCSIS_INTSRC_ERRORS) || debug) {
641 for (i = 0; i < S5PCSIS_NUM_EVENTS; i++) {
642 if (!(status & state->events[i].mask))
644 state->events[i].counter++;
645 v4l2_dbg(2, debug, &state->sd, "%s: %d\n",
646 state->events[i].name,
647 state->events[i].counter);
649 v4l2_dbg(2, debug, &state->sd, "status: %08x\n", status);
651 spin_unlock_irqrestore(&state->slock, flags);
653 s5pcsis_write(state, S5PCSIS_INTSRC, status);
657 static int s5pcsis_probe(struct platform_device *pdev)
659 struct s5p_platform_mipi_csis *pdata;
660 struct resource *mem_res;
661 struct csis_state *state;
665 state = devm_kzalloc(&pdev->dev, sizeof(*state), GFP_KERNEL);
669 mutex_init(&state->lock);
670 spin_lock_init(&state->slock);
673 state->index = max(0, pdev->id);
675 pdata = pdev->dev.platform_data;
677 dev_err(&pdev->dev, "Platform data not fully specified\n");
681 if ((state->index == 1 && pdata->lanes > CSIS1_MAX_LANES) ||
682 pdata->lanes > CSIS0_MAX_LANES) {
683 dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n",
688 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
689 state->regs = devm_request_and_ioremap(&pdev->dev, mem_res);
690 if (state->regs == NULL) {
691 dev_err(&pdev->dev, "Failed to request and remap io memory\n");
695 state->irq = platform_get_irq(pdev, 0);
696 if (state->irq < 0) {
697 dev_err(&pdev->dev, "Failed to get irq\n");
701 for (i = 0; i < CSIS_NUM_SUPPLIES; i++)
702 state->supplies[i].supply = csis_supply_name[i];
704 ret = regulator_bulk_get(&pdev->dev, CSIS_NUM_SUPPLIES,
709 ret = s5pcsis_clk_get(state);
713 clk_enable(state->clock[CSIS_CLK_MUX]);
715 clk_set_rate(state->clock[CSIS_CLK_MUX], pdata->clk_rate);
717 dev_WARN(&pdev->dev, "No clock frequency specified!\n");
719 ret = devm_request_irq(&pdev->dev, state->irq, s5pcsis_irq_handler,
720 0, dev_name(&pdev->dev), state);
722 dev_err(&pdev->dev, "Interrupt request failed\n");
726 v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops);
727 state->sd.owner = THIS_MODULE;
728 strlcpy(state->sd.name, dev_name(&pdev->dev), sizeof(state->sd.name));
729 state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
730 state->csis_fmt = &s5pcsis_formats[0];
732 state->format.code = s5pcsis_formats[0].code;
733 state->format.width = S5PCSIS_DEF_PIX_WIDTH;
734 state->format.height = S5PCSIS_DEF_PIX_HEIGHT;
736 state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
737 state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
738 ret = media_entity_init(&state->sd.entity,
739 CSIS_PADS_NUM, state->pads, 0);
743 /* This allows to retrieve the platform device id by the host driver */
744 v4l2_set_subdevdata(&state->sd, pdev);
746 /* .. and a pointer to the subdev. */
747 platform_set_drvdata(pdev, &state->sd);
749 memcpy(state->events, s5pcsis_events, sizeof(state->events));
751 pm_runtime_enable(&pdev->dev);
755 regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies);
757 clk_disable(state->clock[CSIS_CLK_MUX]);
758 s5pcsis_clk_put(state);
762 static int s5pcsis_pm_suspend(struct device *dev, bool runtime)
764 struct platform_device *pdev = to_platform_device(dev);
765 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
766 struct csis_state *state = sd_to_csis_state(sd);
769 v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
770 __func__, state->flags);
772 mutex_lock(&state->lock);
773 if (state->flags & ST_POWERED) {
774 s5pcsis_stop_stream(state);
775 ret = s5p_csis_phy_enable(state->index, false);
778 ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES,
782 clk_disable(state->clock[CSIS_CLK_GATE]);
783 state->flags &= ~ST_POWERED;
785 state->flags |= ST_SUSPENDED;
788 mutex_unlock(&state->lock);
789 return ret ? -EAGAIN : 0;
792 static int s5pcsis_pm_resume(struct device *dev, bool runtime)
794 struct platform_device *pdev = to_platform_device(dev);
795 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
796 struct csis_state *state = sd_to_csis_state(sd);
799 v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
800 __func__, state->flags);
802 mutex_lock(&state->lock);
803 if (!runtime && !(state->flags & ST_SUSPENDED))
806 if (!(state->flags & ST_POWERED)) {
807 ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES,
811 ret = s5p_csis_phy_enable(state->index, true);
813 state->flags |= ST_POWERED;
815 regulator_bulk_disable(CSIS_NUM_SUPPLIES,
819 clk_enable(state->clock[CSIS_CLK_GATE]);
821 if (state->flags & ST_STREAMING)
822 s5pcsis_start_stream(state);
824 state->flags &= ~ST_SUSPENDED;
826 mutex_unlock(&state->lock);
827 return ret ? -EAGAIN : 0;
830 #ifdef CONFIG_PM_SLEEP
831 static int s5pcsis_suspend(struct device *dev)
833 return s5pcsis_pm_suspend(dev, false);
836 static int s5pcsis_resume(struct device *dev)
838 return s5pcsis_pm_resume(dev, false);
842 #ifdef CONFIG_PM_RUNTIME
843 static int s5pcsis_runtime_suspend(struct device *dev)
845 return s5pcsis_pm_suspend(dev, true);
848 static int s5pcsis_runtime_resume(struct device *dev)
850 return s5pcsis_pm_resume(dev, true);
854 static int s5pcsis_remove(struct platform_device *pdev)
856 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
857 struct csis_state *state = sd_to_csis_state(sd);
859 pm_runtime_disable(&pdev->dev);
860 s5pcsis_pm_suspend(&pdev->dev, false);
861 clk_disable(state->clock[CSIS_CLK_MUX]);
862 pm_runtime_set_suspended(&pdev->dev);
863 s5pcsis_clk_put(state);
864 regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies);
866 media_entity_cleanup(&state->sd.entity);
871 static const struct dev_pm_ops s5pcsis_pm_ops = {
872 SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume,
874 SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume)
877 static struct platform_driver s5pcsis_driver = {
878 .probe = s5pcsis_probe,
879 .remove = s5pcsis_remove,
881 .name = CSIS_DRIVER_NAME,
882 .owner = THIS_MODULE,
883 .pm = &s5pcsis_pm_ops,
887 module_platform_driver(s5pcsis_driver);
889 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
890 MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI-CSI2 receiver driver");
891 MODULE_LICENSE("GPL");