2 * Samsung S5P Multi Format Codec v 5.1
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
25 #include <linux/of_reserved_mem.h>
26 #include <media/videobuf2-v4l2.h>
27 #include "s5p_mfc_common.h"
28 #include "s5p_mfc_ctrl.h"
29 #include "s5p_mfc_debug.h"
30 #include "s5p_mfc_dec.h"
31 #include "s5p_mfc_enc.h"
32 #include "s5p_mfc_intr.h"
33 #include "s5p_mfc_iommu.h"
34 #include "s5p_mfc_opr.h"
35 #include "s5p_mfc_cmd.h"
36 #include "s5p_mfc_pm.h"
38 #define S5P_MFC_NAME "s5p-mfc"
39 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
40 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
43 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
46 /* Helper functions for interrupt processing */
48 /* Remove from hw execution round robin */
49 void clear_work_bit(struct s5p_mfc_ctx *ctx)
51 struct s5p_mfc_dev *dev = ctx->dev;
53 spin_lock(&dev->condlock);
54 __clear_bit(ctx->num, &dev->ctx_work_bits);
55 spin_unlock(&dev->condlock);
58 /* Add to hw execution round robin */
59 void set_work_bit(struct s5p_mfc_ctx *ctx)
61 struct s5p_mfc_dev *dev = ctx->dev;
63 spin_lock(&dev->condlock);
64 __set_bit(ctx->num, &dev->ctx_work_bits);
65 spin_unlock(&dev->condlock);
68 /* Remove from hw execution round robin */
69 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
71 struct s5p_mfc_dev *dev = ctx->dev;
74 spin_lock_irqsave(&dev->condlock, flags);
75 __clear_bit(ctx->num, &dev->ctx_work_bits);
76 spin_unlock_irqrestore(&dev->condlock, flags);
79 /* Add to hw execution round robin */
80 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
82 struct s5p_mfc_dev *dev = ctx->dev;
85 spin_lock_irqsave(&dev->condlock, flags);
86 __set_bit(ctx->num, &dev->ctx_work_bits);
87 spin_unlock_irqrestore(&dev->condlock, flags);
90 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
95 spin_lock_irqsave(&dev->condlock, flags);
98 ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
99 if (ctx == dev->curr_ctx) {
100 if (!test_bit(ctx, &dev->ctx_work_bits))
104 } while (!test_bit(ctx, &dev->ctx_work_bits));
105 spin_unlock_irqrestore(&dev->condlock, flags);
110 /* Wake up context wait_queue */
111 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
115 ctx->int_type = reason;
117 wake_up(&ctx->queue);
120 /* Wake up device wait_queue */
121 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
125 dev->int_type = reason;
127 wake_up(&dev->queue);
130 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
132 struct s5p_mfc_buf *b;
135 while (!list_empty(lh)) {
136 b = list_entry(lh->next, struct s5p_mfc_buf, list);
137 for (i = 0; i < b->b->vb2_buf.num_planes; i++)
138 vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
139 vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
144 static void s5p_mfc_watchdog(unsigned long arg)
146 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
148 if (test_bit(0, &dev->hw_lock))
149 atomic_inc(&dev->watchdog_cnt);
150 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
151 /* This means that hw is busy and no interrupts were
152 * generated by hw for the Nth time of running this
153 * watchdog timer. This usually means a serious hw
154 * error. Now it is time to kill all instances and
156 mfc_err("Time out during waiting for HW\n");
157 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
159 dev->watchdog_timer.expires = jiffies +
160 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
161 add_timer(&dev->watchdog_timer);
164 static void s5p_mfc_watchdog_worker(struct work_struct *work)
166 struct s5p_mfc_dev *dev;
167 struct s5p_mfc_ctx *ctx;
172 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
174 mfc_err("Driver timeout error handling\n");
175 /* Lock the mutex that protects open and release.
176 * This is necessary as they may load and unload firmware. */
177 mutex_locked = mutex_trylock(&dev->mfc_mutex);
179 mfc_err("Error: some instance may be closing/opening\n");
180 spin_lock_irqsave(&dev->irqlock, flags);
184 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
188 ctx->state = MFCINST_ERROR;
189 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
190 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
192 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
194 clear_bit(0, &dev->hw_lock);
195 spin_unlock_irqrestore(&dev->irqlock, flags);
198 s5p_mfc_deinit_hw(dev);
200 /* Double check if there is at least one instance running.
201 * If no instance is in memory than no firmware should be present */
202 if (dev->num_inst > 0) {
203 ret = s5p_mfc_load_firmware(dev);
205 mfc_err("Failed to reload FW\n");
209 ret = s5p_mfc_init_hw(dev);
211 mfc_err("Failed to reinit FW\n");
215 mutex_unlock(&dev->mfc_mutex);
218 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
220 struct s5p_mfc_buf *dst_buf;
221 struct s5p_mfc_dev *dev = ctx->dev;
223 ctx->state = MFCINST_FINISHED;
225 while (!list_empty(&ctx->dst_queue)) {
226 dst_buf = list_entry(ctx->dst_queue.next,
227 struct s5p_mfc_buf, list);
228 mfc_debug(2, "Cleaning up buffer: %d\n",
229 dst_buf->b->vb2_buf.index);
230 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
231 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
232 list_del(&dst_buf->list);
233 dst_buf->flags |= MFC_BUF_FLAG_EOS;
234 ctx->dst_queue_cnt--;
235 dst_buf->b->sequence = (ctx->sequence++);
237 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
238 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
239 dst_buf->b->field = V4L2_FIELD_NONE;
241 dst_buf->b->field = V4L2_FIELD_INTERLACED;
242 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
244 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
245 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
249 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
251 struct s5p_mfc_dev *dev = ctx->dev;
252 struct s5p_mfc_buf *dst_buf, *src_buf;
254 unsigned int frame_type;
256 /* Make sure we actually have a new frame before continuing. */
257 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
258 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
260 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
262 /* Copy timestamp / timecode from decoded src to dst and set
263 appropriate flags. */
264 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
265 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
266 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
268 dst_buf->b->timecode =
269 src_buf->b->timecode;
270 dst_buf->b->vb2_buf.timestamp =
271 src_buf->b->vb2_buf.timestamp;
273 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
276 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
277 switch (frame_type) {
278 case S5P_FIMV_DECODE_FRAME_I_FRAME:
280 V4L2_BUF_FLAG_KEYFRAME;
282 case S5P_FIMV_DECODE_FRAME_P_FRAME:
284 V4L2_BUF_FLAG_PFRAME;
286 case S5P_FIMV_DECODE_FRAME_B_FRAME:
288 V4L2_BUF_FLAG_BFRAME;
291 /* Don't know how to handle
292 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
293 mfc_debug(2, "Unexpected frame type: %d\n",
301 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
303 struct s5p_mfc_dev *dev = ctx->dev;
304 struct s5p_mfc_buf *dst_buf;
306 unsigned int frame_type;
308 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
309 if (IS_MFCV6_PLUS(dev))
310 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
311 get_disp_frame_type, ctx);
313 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
314 get_dec_frame_type, dev);
316 /* If frame is same as previous then skip and do not dequeue */
317 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
318 if (!ctx->after_packed_pb)
320 ctx->after_packed_pb = 0;
324 /* The MFC returns address of the buffer, now we have to
325 * check which videobuf does it correspond to */
326 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
327 /* Check if this is the buffer we're looking for */
328 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
330 list_del(&dst_buf->list);
331 ctx->dst_queue_cnt--;
332 dst_buf->b->sequence = ctx->sequence;
333 if (s5p_mfc_hw_call(dev->mfc_ops,
334 get_pic_type_top, ctx) ==
335 s5p_mfc_hw_call(dev->mfc_ops,
336 get_pic_type_bot, ctx))
337 dst_buf->b->field = V4L2_FIELD_NONE;
340 V4L2_FIELD_INTERLACED;
341 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
343 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
345 clear_bit(dst_buf->b->vb2_buf.index,
348 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
349 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
356 /* Handle frame decoding interrupt */
357 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
358 unsigned int reason, unsigned int err)
360 struct s5p_mfc_dev *dev = ctx->dev;
361 unsigned int dst_frame_status;
362 unsigned int dec_frame_status;
363 struct s5p_mfc_buf *src_buf;
364 unsigned int res_change;
366 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
367 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
368 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
369 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
370 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
371 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
372 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
373 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
374 if (ctx->state == MFCINST_RES_CHANGE_INIT)
375 ctx->state = MFCINST_RES_CHANGE_FLUSH;
376 if (res_change == S5P_FIMV_RES_INCREASE ||
377 res_change == S5P_FIMV_RES_DECREASE) {
378 ctx->state = MFCINST_RES_CHANGE_INIT;
379 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
380 wake_up_ctx(ctx, reason, err);
381 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
383 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
386 if (ctx->dpb_flush_flag)
387 ctx->dpb_flush_flag = 0;
389 /* All frames remaining in the buffer have been extracted */
390 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
391 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
392 static const struct v4l2_event ev_src_ch = {
393 .type = V4L2_EVENT_SOURCE_CHANGE,
394 .u.src_change.changes =
395 V4L2_EVENT_SRC_CH_RESOLUTION,
398 s5p_mfc_handle_frame_all_extracted(ctx);
399 ctx->state = MFCINST_RES_CHANGE_END;
400 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
402 goto leave_handle_frame;
404 s5p_mfc_handle_frame_all_extracted(ctx);
408 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
409 s5p_mfc_handle_frame_copy_time(ctx);
411 /* A frame has been decoded and is in the buffer */
412 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
413 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
414 s5p_mfc_handle_frame_new(ctx, err);
416 mfc_debug(2, "No frame decode\n");
418 /* Mark source buffer as complete */
419 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
420 && !list_empty(&ctx->src_queue)) {
421 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
423 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
424 get_consumed_stream, dev);
425 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
426 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
427 ctx->consumed_stream + STUFF_BYTE <
428 src_buf->b->vb2_buf.planes[0].bytesused) {
429 /* Run MFC again on the same buffer */
430 mfc_debug(2, "Running again the same buffer\n");
431 ctx->after_packed_pb = 1;
433 mfc_debug(2, "MFC needs next buffer\n");
434 ctx->consumed_stream = 0;
435 if (src_buf->flags & MFC_BUF_FLAG_EOS)
436 ctx->state = MFCINST_FINISHING;
437 list_del(&src_buf->list);
438 ctx->src_queue_cnt--;
439 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
440 vb2_buffer_done(&src_buf->b->vb2_buf,
441 VB2_BUF_STATE_ERROR);
443 vb2_buffer_done(&src_buf->b->vb2_buf,
448 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
449 || ctx->dst_queue_cnt < ctx->pb_count)
451 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
452 wake_up_ctx(ctx, reason, err);
453 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
455 /* if suspending, wake up device and do not try_run again*/
456 if (test_bit(0, &dev->enter_suspend))
457 wake_up_dev(dev, reason, err);
459 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
462 /* Error handling for interrupt */
463 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
464 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
466 mfc_err("Interrupt Error: %08x\n", err);
469 /* Error recovery is dependent on the state of context */
470 switch (ctx->state) {
471 case MFCINST_RES_CHANGE_INIT:
472 case MFCINST_RES_CHANGE_FLUSH:
473 case MFCINST_RES_CHANGE_END:
474 case MFCINST_FINISHING:
475 case MFCINST_FINISHED:
476 case MFCINST_RUNNING:
477 /* It is highly probable that an error occurred
478 * while decoding a frame */
480 ctx->state = MFCINST_ERROR;
481 /* Mark all dst buffers as having an error */
482 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
483 /* Mark all src buffers as having an error */
484 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
485 wake_up_ctx(ctx, reason, err);
489 ctx->state = MFCINST_ERROR;
490 wake_up_ctx(ctx, reason, err);
494 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
495 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
497 wake_up_dev(dev, reason, err);
501 /* Header parsing interrupt handling */
502 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
503 unsigned int reason, unsigned int err)
505 struct s5p_mfc_dev *dev;
510 if (ctx->c_ops->post_seq_start) {
511 if (ctx->c_ops->post_seq_start(ctx))
512 mfc_err("post_seq_start() failed\n");
514 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
516 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
519 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
521 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
523 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
525 if (ctx->img_width == 0 || ctx->img_height == 0)
526 ctx->state = MFCINST_ERROR;
528 ctx->state = MFCINST_HEAD_PARSED;
530 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
531 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
532 !list_empty(&ctx->src_queue)) {
533 struct s5p_mfc_buf *src_buf;
534 src_buf = list_entry(ctx->src_queue.next,
535 struct s5p_mfc_buf, list);
536 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
538 src_buf->b->vb2_buf.planes[0].bytesused)
539 ctx->head_processed = 0;
541 ctx->head_processed = 1;
543 ctx->head_processed = 1;
546 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
548 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
550 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
551 wake_up_ctx(ctx, reason, err);
554 /* Header parsing interrupt handling */
555 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
556 unsigned int reason, unsigned int err)
558 struct s5p_mfc_buf *src_buf;
559 struct s5p_mfc_dev *dev;
564 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
565 ctx->int_type = reason;
570 ctx->state = MFCINST_RUNNING;
571 if (!ctx->dpb_flush_flag && ctx->head_processed) {
572 if (!list_empty(&ctx->src_queue)) {
573 src_buf = list_entry(ctx->src_queue.next,
574 struct s5p_mfc_buf, list);
575 list_del(&src_buf->list);
576 ctx->src_queue_cnt--;
577 vb2_buffer_done(&src_buf->b->vb2_buf,
581 ctx->dpb_flush_flag = 0;
583 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
587 wake_up(&ctx->queue);
588 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
590 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
594 wake_up(&ctx->queue);
598 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
600 struct s5p_mfc_dev *dev = ctx->dev;
601 struct s5p_mfc_buf *mb_entry;
603 mfc_debug(2, "Stream completed\n");
605 ctx->state = MFCINST_FINISHED;
607 if (!list_empty(&ctx->dst_queue)) {
608 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
610 list_del(&mb_entry->list);
611 ctx->dst_queue_cnt--;
612 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
613 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
618 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
621 wake_up(&ctx->queue);
622 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
625 /* Interrupt processing */
626 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
628 struct s5p_mfc_dev *dev = priv;
629 struct s5p_mfc_ctx *ctx;
634 /* Reset the timeout watchdog */
635 atomic_set(&dev->watchdog_cnt, 0);
636 spin_lock(&dev->irqlock);
637 ctx = dev->ctx[dev->curr_ctx];
638 /* Get the reason of interrupt and the error code */
639 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
640 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
641 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
643 case S5P_MFC_R2H_CMD_ERR_RET:
644 /* An error has occurred */
645 if (ctx->state == MFCINST_RUNNING &&
646 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
648 s5p_mfc_handle_frame(ctx, reason, err);
650 s5p_mfc_handle_error(dev, ctx, reason, err);
651 clear_bit(0, &dev->enter_suspend);
654 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
655 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
656 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
657 if (ctx->c_ops->post_frame_start) {
658 if (ctx->c_ops->post_frame_start(ctx))
659 mfc_err("post_frame_start() failed\n");
661 if (ctx->state == MFCINST_FINISHING &&
662 list_empty(&ctx->ref_queue)) {
663 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
664 s5p_mfc_handle_stream_complete(ctx);
667 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
668 wake_up_ctx(ctx, reason, err);
669 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
671 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
673 s5p_mfc_handle_frame(ctx, reason, err);
677 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
678 s5p_mfc_handle_seq_done(ctx, reason, err);
681 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
682 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
683 ctx->state = MFCINST_GOT_INST;
685 wake_up(&ctx->queue);
688 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
690 ctx->inst_no = MFC_NO_INSTANCE_SET;
691 ctx->state = MFCINST_FREE;
692 wake_up(&ctx->queue);
695 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
696 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
697 case S5P_MFC_R2H_CMD_SLEEP_RET:
698 case S5P_MFC_R2H_CMD_WAKEUP_RET:
701 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
702 wake_up_dev(dev, reason, err);
703 clear_bit(0, &dev->hw_lock);
704 clear_bit(0, &dev->enter_suspend);
707 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
708 s5p_mfc_handle_init_buffers(ctx, reason, err);
711 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
712 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
713 ctx->int_type = reason;
715 s5p_mfc_handle_stream_complete(ctx);
718 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
720 ctx->state = MFCINST_RUNNING;
721 wake_up(&ctx->queue);
725 mfc_debug(2, "Unknown int reason\n");
726 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
728 spin_unlock(&dev->irqlock);
732 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
733 ctx->int_type = reason;
736 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
737 mfc_err("Failed to unlock hw\n");
741 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
742 spin_unlock(&dev->irqlock);
743 mfc_debug(2, "Exit via irq_cleanup_hw\n");
747 /* Open an MFC node */
748 static int s5p_mfc_open(struct file *file)
750 struct video_device *vdev = video_devdata(file);
751 struct s5p_mfc_dev *dev = video_drvdata(file);
752 struct s5p_mfc_ctx *ctx = NULL;
757 if (mutex_lock_interruptible(&dev->mfc_mutex))
759 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
760 /* Allocate memory for context */
761 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
763 mfc_err("Not enough memory\n");
767 v4l2_fh_init(&ctx->fh, vdev);
768 file->private_data = &ctx->fh;
769 v4l2_fh_add(&ctx->fh);
771 INIT_LIST_HEAD(&ctx->src_queue);
772 INIT_LIST_HEAD(&ctx->dst_queue);
773 ctx->src_queue_cnt = 0;
774 ctx->dst_queue_cnt = 0;
775 /* Get context number */
777 while (dev->ctx[ctx->num]) {
779 if (ctx->num >= MFC_NUM_CONTEXTS) {
780 mfc_err("Too many open contexts\n");
785 /* Mark context as idle */
786 clear_work_bit_irqsave(ctx);
787 dev->ctx[ctx->num] = ctx;
788 if (vdev == dev->vfd_dec) {
789 ctx->type = MFCINST_DECODER;
790 ctx->c_ops = get_dec_codec_ops();
791 s5p_mfc_dec_init(ctx);
792 /* Setup ctrl handler */
793 ret = s5p_mfc_dec_ctrls_setup(ctx);
795 mfc_err("Failed to setup mfc controls\n");
796 goto err_ctrls_setup;
798 } else if (vdev == dev->vfd_enc) {
799 ctx->type = MFCINST_ENCODER;
800 ctx->c_ops = get_enc_codec_ops();
801 /* only for encoder */
802 INIT_LIST_HEAD(&ctx->ref_queue);
803 ctx->ref_queue_cnt = 0;
804 s5p_mfc_enc_init(ctx);
805 /* Setup ctrl handler */
806 ret = s5p_mfc_enc_ctrls_setup(ctx);
808 mfc_err("Failed to setup mfc controls\n");
809 goto err_ctrls_setup;
815 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
816 ctx->inst_no = MFC_NO_INSTANCE_SET;
817 /* Load firmware if this is the first instance */
818 if (dev->num_inst == 1) {
819 dev->watchdog_timer.expires = jiffies +
820 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
821 add_timer(&dev->watchdog_timer);
822 ret = s5p_mfc_power_on();
824 mfc_err("power on failed\n");
828 ret = s5p_mfc_load_firmware(dev);
834 ret = s5p_mfc_init_hw(dev);
839 /* Init videobuf2 queue for CAPTURE */
841 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
842 q->drv_priv = &ctx->fh;
843 q->lock = &dev->mfc_mutex;
844 if (vdev == dev->vfd_dec) {
845 q->io_modes = VB2_MMAP;
846 q->ops = get_dec_queue_ops();
847 } else if (vdev == dev->vfd_enc) {
848 q->io_modes = VB2_MMAP | VB2_USERPTR;
849 q->ops = get_enc_queue_ops();
854 q->mem_ops = &vb2_dma_contig_memops;
855 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
856 ret = vb2_queue_init(q);
858 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
861 /* Init videobuf2 queue for OUTPUT */
863 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
864 q->io_modes = VB2_MMAP;
865 q->drv_priv = &ctx->fh;
866 q->lock = &dev->mfc_mutex;
867 if (vdev == dev->vfd_dec) {
868 q->io_modes = VB2_MMAP;
869 q->ops = get_dec_queue_ops();
870 } else if (vdev == dev->vfd_enc) {
871 q->io_modes = VB2_MMAP | VB2_USERPTR;
872 q->ops = get_enc_queue_ops();
877 /* One way to indicate end-of-stream for MFC is to set the
878 * bytesused == 0. However by default videobuf2 handles bytesused
879 * equal to 0 as a special case and changes its value to the size
880 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
881 * will keep the value of bytesused intact.
883 q->allow_zero_bytesused = 1;
884 q->mem_ops = &vb2_dma_contig_memops;
885 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
886 ret = vb2_queue_init(q);
888 mfc_err("Failed to initialize videobuf2 queue(output)\n");
891 init_waitqueue_head(&ctx->queue);
892 mutex_unlock(&dev->mfc_mutex);
895 /* Deinit when failure occurred */
897 if (dev->num_inst == 1)
898 s5p_mfc_deinit_hw(dev);
902 if (dev->num_inst == 1) {
903 if (s5p_mfc_power_off() < 0)
904 mfc_err("power off failed\n");
905 del_timer_sync(&dev->watchdog_timer);
908 s5p_mfc_dec_ctrls_delete(ctx);
910 dev->ctx[ctx->num] = NULL;
912 v4l2_fh_del(&ctx->fh);
913 v4l2_fh_exit(&ctx->fh);
917 mutex_unlock(&dev->mfc_mutex);
922 /* Release MFC context */
923 static int s5p_mfc_release(struct file *file)
925 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
926 struct s5p_mfc_dev *dev = ctx->dev;
929 mutex_lock(&dev->mfc_mutex);
931 vb2_queue_release(&ctx->vq_src);
932 vb2_queue_release(&ctx->vq_dst);
933 /* Mark context as idle */
934 clear_work_bit_irqsave(ctx);
935 /* If instance was initialised and not yet freed,
936 * return instance and free resources */
937 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
938 mfc_debug(2, "Has to free instance\n");
939 s5p_mfc_close_mfc_inst(dev, ctx);
941 /* hardware locking scheme */
942 if (dev->curr_ctx == ctx->num)
943 clear_bit(0, &dev->hw_lock);
945 if (dev->num_inst == 0) {
946 mfc_debug(2, "Last instance\n");
947 s5p_mfc_deinit_hw(dev);
948 del_timer_sync(&dev->watchdog_timer);
949 if (s5p_mfc_power_off() < 0)
950 mfc_err("Power off failed\n");
952 mfc_debug(2, "Shutting down clock\n");
954 dev->ctx[ctx->num] = NULL;
955 s5p_mfc_dec_ctrls_delete(ctx);
956 v4l2_fh_del(&ctx->fh);
957 v4l2_fh_exit(&ctx->fh);
960 mutex_unlock(&dev->mfc_mutex);
965 static unsigned int s5p_mfc_poll(struct file *file,
966 struct poll_table_struct *wait)
968 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
969 struct s5p_mfc_dev *dev = ctx->dev;
970 struct vb2_queue *src_q, *dst_q;
971 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
975 mutex_lock(&dev->mfc_mutex);
976 src_q = &ctx->vq_src;
977 dst_q = &ctx->vq_dst;
979 * There has to be at least one buffer queued on each queued_list, which
980 * means either in driver already or waiting for driver to claim it
981 * and start processing.
983 if ((!src_q->streaming || list_empty(&src_q->queued_list))
984 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
988 mutex_unlock(&dev->mfc_mutex);
989 poll_wait(file, &ctx->fh.wait, wait);
990 poll_wait(file, &src_q->done_wq, wait);
991 poll_wait(file, &dst_q->done_wq, wait);
992 mutex_lock(&dev->mfc_mutex);
993 if (v4l2_event_pending(&ctx->fh))
995 spin_lock_irqsave(&src_q->done_lock, flags);
996 if (!list_empty(&src_q->done_list))
997 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
999 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1000 || src_vb->state == VB2_BUF_STATE_ERROR))
1001 rc |= POLLOUT | POLLWRNORM;
1002 spin_unlock_irqrestore(&src_q->done_lock, flags);
1003 spin_lock_irqsave(&dst_q->done_lock, flags);
1004 if (!list_empty(&dst_q->done_list))
1005 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1007 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1008 || dst_vb->state == VB2_BUF_STATE_ERROR))
1009 rc |= POLLIN | POLLRDNORM;
1010 spin_unlock_irqrestore(&dst_q->done_lock, flags);
1012 mutex_unlock(&dev->mfc_mutex);
1017 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1019 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1020 struct s5p_mfc_dev *dev = ctx->dev;
1021 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1024 if (mutex_lock_interruptible(&dev->mfc_mutex))
1025 return -ERESTARTSYS;
1026 if (offset < DST_QUEUE_OFF_BASE) {
1027 mfc_debug(2, "mmaping source\n");
1028 ret = vb2_mmap(&ctx->vq_src, vma);
1029 } else { /* capture */
1030 mfc_debug(2, "mmaping destination\n");
1031 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1032 ret = vb2_mmap(&ctx->vq_dst, vma);
1034 mutex_unlock(&dev->mfc_mutex);
1039 static const struct v4l2_file_operations s5p_mfc_fops = {
1040 .owner = THIS_MODULE,
1041 .open = s5p_mfc_open,
1042 .release = s5p_mfc_release,
1043 .poll = s5p_mfc_poll,
1044 .unlocked_ioctl = video_ioctl2,
1045 .mmap = s5p_mfc_mmap,
1048 /* DMA memory related helper functions */
1049 static void s5p_mfc_memdev_release(struct device *dev)
1051 of_reserved_mem_device_release(dev);
1054 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1055 const char *name, unsigned int idx)
1057 struct device *child;
1060 child = devm_kzalloc(dev, sizeof(struct device), GFP_KERNEL);
1064 device_initialize(child);
1065 dev_set_name(child, "%s:%s", dev_name(dev), name);
1066 child->parent = dev;
1067 child->bus = dev->bus;
1068 child->coherent_dma_mask = dev->coherent_dma_mask;
1069 child->dma_mask = dev->dma_mask;
1070 child->release = s5p_mfc_memdev_release;
1072 if (device_add(child) == 0) {
1073 ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1083 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1085 struct device *dev = &mfc_dev->plat_dev->dev;
1088 * When IOMMU is available, we cannot use the default configuration,
1089 * because of MFC firmware requirements: address space limited to
1090 * 256M and non-zero default start address.
1091 * This is still simplified, not optimal configuration, but for now
1092 * IOMMU core doesn't allow to configure device's IOMMUs channel
1095 if (exynos_is_iommu_available(dev)) {
1096 int ret = exynos_configure_iommu(dev, S5P_MFC_IOMMU_DMA_BASE,
1097 S5P_MFC_IOMMU_DMA_SIZE);
1099 mfc_dev->mem_dev_l = mfc_dev->mem_dev_r = dev;
1104 * Create and initialize virtual devices for accessing
1105 * reserved memory regions.
1107 mfc_dev->mem_dev_l = s5p_mfc_alloc_memdev(dev, "left",
1108 MFC_BANK1_ALLOC_CTX);
1109 if (!mfc_dev->mem_dev_l)
1111 mfc_dev->mem_dev_r = s5p_mfc_alloc_memdev(dev, "right",
1112 MFC_BANK2_ALLOC_CTX);
1113 if (!mfc_dev->mem_dev_r) {
1114 device_unregister(mfc_dev->mem_dev_l);
1121 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1123 struct device *dev = &mfc_dev->plat_dev->dev;
1125 if (exynos_is_iommu_available(dev)) {
1126 exynos_unconfigure_iommu(dev);
1130 device_unregister(mfc_dev->mem_dev_l);
1131 device_unregister(mfc_dev->mem_dev_r);
1134 static void *mfc_get_drv_data(struct platform_device *pdev);
1136 /* MFC probe function */
1137 static int s5p_mfc_probe(struct platform_device *pdev)
1139 struct s5p_mfc_dev *dev;
1140 struct video_device *vfd;
1141 struct resource *res;
1144 pr_debug("%s++\n", __func__);
1145 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1147 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1151 spin_lock_init(&dev->irqlock);
1152 spin_lock_init(&dev->condlock);
1153 dev->plat_dev = pdev;
1154 if (!dev->plat_dev) {
1155 dev_err(&pdev->dev, "No platform data specified\n");
1159 dev->variant = mfc_get_drv_data(pdev);
1161 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1163 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1164 if (IS_ERR(dev->regs_base))
1165 return PTR_ERR(dev->regs_base);
1167 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1169 dev_err(&pdev->dev, "failed to get irq resource\n");
1173 dev->irq = res->start;
1174 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1175 0, pdev->name, dev);
1177 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1181 ret = s5p_mfc_configure_dma_memory(dev);
1183 dev_err(&pdev->dev, "failed to configure DMA memory\n");
1187 ret = s5p_mfc_init_pm(dev);
1189 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1193 vb2_dma_contig_set_max_seg_size(dev->mem_dev_l, DMA_BIT_MASK(32));
1194 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1195 if (IS_ERR(dev->alloc_ctx[0])) {
1196 ret = PTR_ERR(dev->alloc_ctx[0]);
1199 vb2_dma_contig_set_max_seg_size(dev->mem_dev_r, DMA_BIT_MASK(32));
1200 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1201 if (IS_ERR(dev->alloc_ctx[1])) {
1202 ret = PTR_ERR(dev->alloc_ctx[1]);
1203 goto err_mem_init_ctx_1;
1206 mutex_init(&dev->mfc_mutex);
1208 ret = s5p_mfc_alloc_firmware(dev);
1212 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1214 goto err_v4l2_dev_reg;
1215 init_waitqueue_head(&dev->queue);
1218 vfd = video_device_alloc();
1220 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1224 vfd->fops = &s5p_mfc_fops;
1225 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1226 vfd->release = video_device_release;
1227 vfd->lock = &dev->mfc_mutex;
1228 vfd->v4l2_dev = &dev->v4l2_dev;
1229 vfd->vfl_dir = VFL_DIR_M2M;
1230 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1232 video_set_drvdata(vfd, dev);
1235 vfd = video_device_alloc();
1237 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1241 vfd->fops = &s5p_mfc_fops;
1242 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1243 vfd->release = video_device_release;
1244 vfd->lock = &dev->mfc_mutex;
1245 vfd->v4l2_dev = &dev->v4l2_dev;
1246 vfd->vfl_dir = VFL_DIR_M2M;
1247 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1249 video_set_drvdata(vfd, dev);
1250 platform_set_drvdata(pdev, dev);
1253 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1254 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1255 atomic_set(&dev->watchdog_cnt, 0);
1256 init_timer(&dev->watchdog_timer);
1257 dev->watchdog_timer.data = (unsigned long)dev;
1258 dev->watchdog_timer.function = s5p_mfc_watchdog;
1260 /* Initialize HW ops and commands based on MFC version */
1261 s5p_mfc_init_hw_ops(dev);
1262 s5p_mfc_init_hw_cmds(dev);
1263 s5p_mfc_init_regs(dev);
1265 /* Register decoder and encoder */
1266 ret = video_register_device(dev->vfd_dec, VFL_TYPE_GRABBER, 0);
1268 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1271 v4l2_info(&dev->v4l2_dev,
1272 "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1274 ret = video_register_device(dev->vfd_enc, VFL_TYPE_GRABBER, 0);
1276 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1279 v4l2_info(&dev->v4l2_dev,
1280 "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1282 pr_debug("%s--\n", __func__);
1285 /* Deinit MFC if probe had failed */
1287 video_unregister_device(dev->vfd_dec);
1289 video_device_release(dev->vfd_enc);
1291 video_device_release(dev->vfd_dec);
1293 v4l2_device_unregister(&dev->v4l2_dev);
1295 s5p_mfc_release_firmware(dev);
1297 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1299 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1301 s5p_mfc_final_pm(dev);
1303 pr_debug("%s-- with error\n", __func__);
1308 /* Remove the driver */
1309 static int s5p_mfc_remove(struct platform_device *pdev)
1311 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1313 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1315 del_timer_sync(&dev->watchdog_timer);
1316 flush_workqueue(dev->watchdog_workqueue);
1317 destroy_workqueue(dev->watchdog_workqueue);
1319 video_unregister_device(dev->vfd_enc);
1320 video_unregister_device(dev->vfd_dec);
1321 v4l2_device_unregister(&dev->v4l2_dev);
1322 s5p_mfc_release_firmware(dev);
1323 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1324 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1325 s5p_mfc_unconfigure_dma_memory(dev);
1326 vb2_dma_contig_clear_max_seg_size(dev->mem_dev_l);
1327 vb2_dma_contig_clear_max_seg_size(dev->mem_dev_r);
1329 s5p_mfc_final_pm(dev);
1333 #ifdef CONFIG_PM_SLEEP
1335 static int s5p_mfc_suspend(struct device *dev)
1337 struct platform_device *pdev = to_platform_device(dev);
1338 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1341 if (m_dev->num_inst == 0)
1344 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1345 mfc_err("Error: going to suspend for a second time\n");
1349 /* Check if we're processing then wait if it necessary. */
1350 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1351 /* Try and lock the HW */
1352 /* Wait on the interrupt waitqueue */
1353 ret = wait_event_interruptible_timeout(m_dev->queue,
1354 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1356 mfc_err("Waiting for hardware to finish timed out\n");
1357 clear_bit(0, &m_dev->enter_suspend);
1362 ret = s5p_mfc_sleep(m_dev);
1364 clear_bit(0, &m_dev->enter_suspend);
1365 clear_bit(0, &m_dev->hw_lock);
1370 static int s5p_mfc_resume(struct device *dev)
1372 struct platform_device *pdev = to_platform_device(dev);
1373 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1375 if (m_dev->num_inst == 0)
1377 return s5p_mfc_wakeup(m_dev);
1382 static int s5p_mfc_runtime_suspend(struct device *dev)
1384 struct platform_device *pdev = to_platform_device(dev);
1385 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1387 atomic_set(&m_dev->pm.power, 0);
1391 static int s5p_mfc_runtime_resume(struct device *dev)
1393 struct platform_device *pdev = to_platform_device(dev);
1394 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1396 atomic_set(&m_dev->pm.power, 1);
1401 /* Power management */
1402 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1403 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1404 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1408 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1409 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1410 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1411 .dsc = DESC_BUF_SIZE,
1412 .shm = SHARED_BUF_SIZE,
1415 static struct s5p_mfc_buf_size buf_size_v5 = {
1417 .cpb = MAX_CPB_SIZE,
1418 .priv = &mfc_buf_size_v5,
1421 static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1422 .base = MFC_BASE_ALIGN_ORDER,
1425 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1426 .version = MFC_VERSION,
1427 .version_bit = MFC_V5_BIT,
1428 .port_num = MFC_NUM_PORTS,
1429 .buf_size = &buf_size_v5,
1430 .buf_align = &mfc_buf_align_v5,
1431 .fw_name[0] = "s5p-mfc.fw",
1434 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1435 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1436 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1437 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1438 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1439 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1442 static struct s5p_mfc_buf_size buf_size_v6 = {
1443 .fw = MAX_FW_SIZE_V6,
1444 .cpb = MAX_CPB_SIZE_V6,
1445 .priv = &mfc_buf_size_v6,
1448 static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1452 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1453 .version = MFC_VERSION_V6,
1454 .version_bit = MFC_V6_BIT,
1455 .port_num = MFC_NUM_PORTS_V6,
1456 .buf_size = &buf_size_v6,
1457 .buf_align = &mfc_buf_align_v6,
1458 .fw_name[0] = "s5p-mfc-v6.fw",
1460 * v6-v2 firmware contains bug fixes and interface change
1461 * for init buffer command
1463 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1466 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1467 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1468 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1469 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1470 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1471 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1474 static struct s5p_mfc_buf_size buf_size_v7 = {
1475 .fw = MAX_FW_SIZE_V7,
1476 .cpb = MAX_CPB_SIZE_V7,
1477 .priv = &mfc_buf_size_v7,
1480 static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1484 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1485 .version = MFC_VERSION_V7,
1486 .version_bit = MFC_V7_BIT,
1487 .port_num = MFC_NUM_PORTS_V7,
1488 .buf_size = &buf_size_v7,
1489 .buf_align = &mfc_buf_align_v7,
1490 .fw_name[0] = "s5p-mfc-v7.fw",
1493 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1494 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1495 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1496 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1497 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1498 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1501 static struct s5p_mfc_buf_size buf_size_v8 = {
1502 .fw = MAX_FW_SIZE_V8,
1503 .cpb = MAX_CPB_SIZE_V8,
1504 .priv = &mfc_buf_size_v8,
1507 static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1511 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1512 .version = MFC_VERSION_V8,
1513 .version_bit = MFC_V8_BIT,
1514 .port_num = MFC_NUM_PORTS_V8,
1515 .buf_size = &buf_size_v8,
1516 .buf_align = &mfc_buf_align_v8,
1517 .fw_name[0] = "s5p-mfc-v8.fw",
1520 static const struct of_device_id exynos_mfc_match[] = {
1522 .compatible = "samsung,mfc-v5",
1523 .data = &mfc_drvdata_v5,
1525 .compatible = "samsung,mfc-v6",
1526 .data = &mfc_drvdata_v6,
1528 .compatible = "samsung,mfc-v7",
1529 .data = &mfc_drvdata_v7,
1531 .compatible = "samsung,mfc-v8",
1532 .data = &mfc_drvdata_v8,
1536 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1538 static void *mfc_get_drv_data(struct platform_device *pdev)
1540 struct s5p_mfc_variant *driver_data = NULL;
1541 const struct of_device_id *match;
1543 match = of_match_node(exynos_mfc_match, pdev->dev.of_node);
1545 driver_data = (struct s5p_mfc_variant *)match->data;
1550 static struct platform_driver s5p_mfc_driver = {
1551 .probe = s5p_mfc_probe,
1552 .remove = s5p_mfc_remove,
1554 .name = S5P_MFC_NAME,
1555 .pm = &s5p_mfc_pm_ops,
1556 .of_match_table = exynos_mfc_match,
1560 module_platform_driver(s5p_mfc_driver);
1562 MODULE_LICENSE("GPL");
1563 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1564 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");