drivers/media/platform/s5p-mfc/s5p_mfc.c

   1 /*
   2  * Samsung S5P Multi Format Codec v 5.1
   3  *
   4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   5  * Kamil Debski, <k.debski@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/videodev2.h>
  22 #include <media/v4l2-event.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/of.h>
  25 #include <media/videobuf2-core.h>
  26 #include "s5p_mfc_common.h"
  27 #include "s5p_mfc_ctrl.h"
  28 #include "s5p_mfc_debug.h"
  29 #include "s5p_mfc_dec.h"
  30 #include "s5p_mfc_enc.h"
  31 #include "s5p_mfc_intr.h"
  32 #include "s5p_mfc_opr.h"
  33 #include "s5p_mfc_cmd.h"
  34 #include "s5p_mfc_pm.h"
  35
  36 #define S5P_MFC_NAME            "s5p-mfc"
  37 #define S5P_MFC_DEC_NAME        "s5p-mfc-dec"
  38 #define S5P_MFC_ENC_NAME        "s5p-mfc-enc"
  39
  40 int mfc_debug_level;
  41 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
  42 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
  43
  44 /* Helper functions for interrupt processing */
  45
  46 /* Remove from hw execution round robin */
  47 void clear_work_bit(struct s5p_mfc_ctx *ctx)
  48 {
  49         struct s5p_mfc_dev *dev = ctx->dev;
  50
  51         spin_lock(&dev->condlock);
  52         __clear_bit(ctx->num, &dev->ctx_work_bits);
  53         spin_unlock(&dev->condlock);
  54 }
  55
  56 /* Add to hw execution round robin */
  57 void set_work_bit(struct s5p_mfc_ctx *ctx)
  58 {
  59         struct s5p_mfc_dev *dev = ctx->dev;
  60
  61         spin_lock(&dev->condlock);
  62         __set_bit(ctx->num, &dev->ctx_work_bits);
  63         spin_unlock(&dev->condlock);
  64 }
  65
  66 /* Remove from hw execution round robin */
  67 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  68 {
  69         struct s5p_mfc_dev *dev = ctx->dev;
  70         unsigned long flags;
  71
  72         spin_lock_irqsave(&dev->condlock, flags);
  73         __clear_bit(ctx->num, &dev->ctx_work_bits);
  74         spin_unlock_irqrestore(&dev->condlock, flags);
  75 }
  76
  77 /* Add to hw execution round robin */
  78 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  79 {
  80         struct s5p_mfc_dev *dev = ctx->dev;
  81         unsigned long flags;
  82
  83         spin_lock_irqsave(&dev->condlock, flags);
  84         __set_bit(ctx->num, &dev->ctx_work_bits);
  85         spin_unlock_irqrestore(&dev->condlock, flags);
  86 }
  87
  88 /* Wake up context wait_queue */
  89 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
  90                         unsigned int err)
  91 {
  92         ctx->int_cond = 1;
  93         ctx->int_type = reason;
  94         ctx->int_err = err;
  95         wake_up(&ctx->queue);
  96 }
  97
  98 /* Wake up device wait_queue */
  99 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
 100                         unsigned int err)
 101 {
 102         dev->int_cond = 1;
 103         dev->int_type = reason;
 104         dev->int_err = err;
 105         wake_up(&dev->queue);
 106 }
 107
 108 static void s5p_mfc_watchdog(unsigned long arg)
 109 {
 110         struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
 111
 112         if (test_bit(0, &dev->hw_lock))
 113                 atomic_inc(&dev->watchdog_cnt);
 114         if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
 115                 /* This means that hw is busy and no interrupts were
 116                  * generated by hw for the Nth time of running this
 117                  * watchdog timer. This usually means a serious hw
 118                  * error. Now it is time to kill all instances and
 119                  * reset the MFC. */
 120                 mfc_err("Time out during waiting for HW\n");
 121                 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
 122         }
 123         dev->watchdog_timer.expires = jiffies +
 124                                         msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
 125         add_timer(&dev->watchdog_timer);
 126 }
 127
 128 static void s5p_mfc_watchdog_worker(struct work_struct *work)
 129 {
 130         struct s5p_mfc_dev *dev;
 131         struct s5p_mfc_ctx *ctx;
 132         unsigned long flags;
 133         int mutex_locked;
 134         int i, ret;
 135
 136         dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
 137
 138         mfc_err("Driver timeout error handling\n");
 139         /* Lock the mutex that protects open and release.
 140          * This is necessary as they may load and unload firmware. */
 141         mutex_locked = mutex_trylock(&dev->mfc_mutex);
 142         if (!mutex_locked)
 143                 mfc_err("Error: some instance may be closing/opening\n");
 144         spin_lock_irqsave(&dev->irqlock, flags);
 145
 146         s5p_mfc_clock_off();
 147
 148         for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
 149                 ctx = dev->ctx[i];
 150                 if (!ctx)
 151                         continue;
 152                 ctx->state = MFCINST_ERROR;
 153                 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 154                                                 &ctx->dst_queue, &ctx->vq_dst);
 155                 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 156                                                 &ctx->src_queue, &ctx->vq_src);
 157                 clear_work_bit(ctx);
 158                 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
 159         }
 160         clear_bit(0, &dev->hw_lock);
 161         spin_unlock_irqrestore(&dev->irqlock, flags);
 162
 163         /* De-init MFC */
 164         s5p_mfc_deinit_hw(dev);
 165
 166         /* Double check if there is at least one instance running.
 167          * If no instance is in memory than no firmware should be present */
 168         if (dev->num_inst > 0) {
 169                 ret = s5p_mfc_load_firmware(dev);
 170                 if (ret) {
 171                         mfc_err("Failed to reload FW\n");
 172                         goto unlock;
 173                 }
 174                 s5p_mfc_clock_on();
 175                 ret = s5p_mfc_init_hw(dev);
 176                 if (ret)
 177                         mfc_err("Failed to reinit FW\n");
 178         }
 179 unlock:
 180         if (mutex_locked)
 181                 mutex_unlock(&dev->mfc_mutex);
 182 }
 183
 184 static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
 185 {
 186         mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
 187         mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
 188         mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
 189 }
 190
 191 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
 192 {
 193         struct s5p_mfc_buf *dst_buf;
 194         struct s5p_mfc_dev *dev = ctx->dev;
 195
 196         ctx->state = MFCINST_FINISHED;
 197         ctx->sequence++;
 198         while (!list_empty(&ctx->dst_queue)) {
 199                 dst_buf = list_entry(ctx->dst_queue.next,
 200                                      struct s5p_mfc_buf, list);
 201                 mfc_debug(2, "Cleaning up buffer: %d\n",
 202                                           dst_buf->b->v4l2_buf.index);
 203                 vb2_set_plane_payload(dst_buf->b, 0, 0);
 204                 vb2_set_plane_payload(dst_buf->b, 1, 0);
 205                 list_del(&dst_buf->list);
 206                 ctx->dst_queue_cnt--;
 207                 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
 208
 209                 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
 210                         s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
 211                         dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
 212                 else
 213                         dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
 214                 dst_buf->b->v4l2_buf.flags |= V4L2_BUF_FLAG_LAST;
 215
 216                 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
 217                 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
 218         }
 219 }
 220
 221 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
 222 {
 223         struct s5p_mfc_dev *dev = ctx->dev;
 224         struct s5p_mfc_buf  *dst_buf, *src_buf;
 225         size_t dec_y_addr;
 226         unsigned int frame_type;
 227
 228         /* Make sure we actually have a new frame before continuing. */
 229         frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
 230         if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
 231                 return;
 232         dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
 233
 234         /* Copy timestamp / timecode from decoded src to dst and set
 235            appropriate flags. */
 236         src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
 237         list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
 238                 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
 239                         dst_buf->b->v4l2_buf.timecode =
 240                                                 src_buf->b->v4l2_buf.timecode;
 241                         dst_buf->b->v4l2_buf.timestamp =
 242                                                 src_buf->b->v4l2_buf.timestamp;
 243                         dst_buf->b->v4l2_buf.flags &=
 244                                 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
 245                         dst_buf->b->v4l2_buf.flags |=
 246                                 src_buf->b->v4l2_buf.flags
 247                                 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
 248                         switch (frame_type) {
 249                         case S5P_FIMV_DECODE_FRAME_I_FRAME:
 250                                 dst_buf->b->v4l2_buf.flags |=
 251                                                 V4L2_BUF_FLAG_KEYFRAME;
 252                                 break;
 253                         case S5P_FIMV_DECODE_FRAME_P_FRAME:
 254                                 dst_buf->b->v4l2_buf.flags |=
 255                                                 V4L2_BUF_FLAG_PFRAME;
 256                                 break;
 257                         case S5P_FIMV_DECODE_FRAME_B_FRAME:
 258                                 dst_buf->b->v4l2_buf.flags |=
 259                                                 V4L2_BUF_FLAG_BFRAME;
 260                                 break;
 261                         default:
 262                                 /* Don't know how to handle
 263                                    S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
 264                                 mfc_debug(2, "Unexpected frame type: %d\n",
 265                                                 frame_type);
 266                         }
 267                         break;
 268                 }
 269         }
 270 }
 271
 272 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
 273 {
 274         struct s5p_mfc_dev *dev = ctx->dev;
 275         struct s5p_mfc_buf  *dst_buf;
 276         size_t dspl_y_addr;
 277         unsigned int frame_type;
 278
 279         dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
 280         if (IS_MFCV6_PLUS(dev))
 281                 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
 282                         get_disp_frame_type, ctx);
 283         else
 284                 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
 285                         get_dec_frame_type, dev);
 286
 287         /* If frame is same as previous then skip and do not dequeue */
 288         if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
 289                 if (!ctx->after_packed_pb)
 290                         ctx->sequence++;
 291                 ctx->after_packed_pb = 0;
 292                 return;
 293         }
 294         ctx->sequence++;
 295         /* The MFC returns address of the buffer, now we have to
 296          * check which videobuf does it correspond to */
 297         list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
 298                 /* Check if this is the buffer we're looking for */
 299                 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
 300                         list_del(&dst_buf->list);
 301                         ctx->dst_queue_cnt--;
 302                         dst_buf->b->v4l2_buf.sequence = ctx->sequence;
 303                         if (s5p_mfc_hw_call(dev->mfc_ops,
 304                                         get_pic_type_top, ctx) ==
 305                                 s5p_mfc_hw_call(dev->mfc_ops,
 306                                         get_pic_type_bot, ctx))
 307                                 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
 308                         else
 309                                 dst_buf->b->v4l2_buf.field =
 310                                                         V4L2_FIELD_INTERLACED;
 311                         vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
 312                         vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
 313                         clear_bit(dst_buf->b->v4l2_buf.index,
 314                                                         &ctx->dec_dst_flag);
 315
 316                         vb2_buffer_done(dst_buf->b,
 317                                 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
 318
 319                         break;
 320                 }
 321         }
 322 }
 323
 324 /* Handle frame decoding interrupt */
 325 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
 326                                         unsigned int reason, unsigned int err)
 327 {
 328         struct s5p_mfc_dev *dev = ctx->dev;
 329         unsigned int dst_frame_status;
 330         unsigned int dec_frame_status;
 331         struct s5p_mfc_buf *src_buf;
 332         unsigned long flags;
 333         unsigned int res_change;
 334
 335         dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
 336                                 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
 337         dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
 338                                 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
 339         res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
 340                                 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
 341                                 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
 342         mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
 343         if (ctx->state == MFCINST_RES_CHANGE_INIT)
 344                 ctx->state = MFCINST_RES_CHANGE_FLUSH;
 345         if (res_change == S5P_FIMV_RES_INCREASE ||
 346                 res_change == S5P_FIMV_RES_DECREASE) {
 347                 ctx->state = MFCINST_RES_CHANGE_INIT;
 348                 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 349                 wake_up_ctx(ctx, reason, err);
 350                 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 351                 s5p_mfc_clock_off();
 352                 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 353                 return;
 354         }
 355         if (ctx->dpb_flush_flag)
 356                 ctx->dpb_flush_flag = 0;
 357
 358         spin_lock_irqsave(&dev->irqlock, flags);
 359         /* All frames remaining in the buffer have been extracted  */
 360         if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
 361                 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
 362                         static const struct v4l2_event ev_src_ch = {
 363                                 .type = V4L2_EVENT_SOURCE_CHANGE,
 364                                 .u.src_change.changes =
 365                                         V4L2_EVENT_SRC_CH_RESOLUTION,
 366                         };
 367
 368                         s5p_mfc_handle_frame_all_extracted(ctx);
 369                         ctx->state = MFCINST_RES_CHANGE_END;
 370                         v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
 371
 372                         goto leave_handle_frame;
 373                 } else {
 374                         s5p_mfc_handle_frame_all_extracted(ctx);
 375                 }
 376         }
 377
 378         if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
 379                 s5p_mfc_handle_frame_copy_time(ctx);
 380
 381         /* A frame has been decoded and is in the buffer  */
 382         if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
 383             dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
 384                 s5p_mfc_handle_frame_new(ctx, err);
 385         } else {
 386                 mfc_debug(2, "No frame decode\n");
 387         }
 388         /* Mark source buffer as complete */
 389         if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
 390                 && !list_empty(&ctx->src_queue)) {
 391                 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
 392                                                                 list);
 393                 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
 394                                                 get_consumed_stream, dev);
 395                 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
 396                         ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
 397                         ctx->consumed_stream + STUFF_BYTE <
 398                         src_buf->b->v4l2_planes[0].bytesused) {
 399                         /* Run MFC again on the same buffer */
 400                         mfc_debug(2, "Running again the same buffer\n");
 401                         ctx->after_packed_pb = 1;
 402                 } else {
 403                         mfc_debug(2, "MFC needs next buffer\n");
 404                         ctx->consumed_stream = 0;
 405                         if (src_buf->flags & MFC_BUF_FLAG_EOS)
 406                                 ctx->state = MFCINST_FINISHING;
 407                         list_del(&src_buf->list);
 408                         ctx->src_queue_cnt--;
 409                         if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
 410                                 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
 411                         else
 412                                 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
 413                 }
 414         }
 415 leave_handle_frame:
 416         spin_unlock_irqrestore(&dev->irqlock, flags);
 417         if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
 418                                     || ctx->dst_queue_cnt < ctx->pb_count)
 419                 clear_work_bit(ctx);
 420         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 421         wake_up_ctx(ctx, reason, err);
 422         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 423         s5p_mfc_clock_off();
 424         /* if suspending, wake up device and do not try_run again*/
 425         if (test_bit(0, &dev->enter_suspend))
 426                 wake_up_dev(dev, reason, err);
 427         else
 428                 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 429 }
 430
 431 /* Error handling for interrupt */
 432 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
 433                 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
 434 {
 435         unsigned long flags;
 436
 437         mfc_err("Interrupt Error: %08x\n", err);
 438
 439         if (ctx != NULL) {
 440                 /* Error recovery is dependent on the state of context */
 441                 switch (ctx->state) {
 442                 case MFCINST_RES_CHANGE_INIT:
 443                 case MFCINST_RES_CHANGE_FLUSH:
 444                 case MFCINST_RES_CHANGE_END:
 445                 case MFCINST_FINISHING:
 446                 case MFCINST_FINISHED:
 447                 case MFCINST_RUNNING:
 448                         /* It is highly probable that an error occurred
 449                          * while decoding a frame */
 450                         clear_work_bit(ctx);
 451                         ctx->state = MFCINST_ERROR;
 452                         /* Mark all dst buffers as having an error */
 453                         spin_lock_irqsave(&dev->irqlock, flags);
 454                         s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 455                                                 &ctx->dst_queue, &ctx->vq_dst);
 456                         /* Mark all src buffers as having an error */
 457                         s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 458                                                 &ctx->src_queue, &ctx->vq_src);
 459                         spin_unlock_irqrestore(&dev->irqlock, flags);
 460                         wake_up_ctx(ctx, reason, err);
 461                         break;
 462                 default:
 463                         clear_work_bit(ctx);
 464                         ctx->state = MFCINST_ERROR;
 465                         wake_up_ctx(ctx, reason, err);
 466                         break;
 467                 }
 468         }
 469         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 470         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 471         s5p_mfc_clock_off();
 472         wake_up_dev(dev, reason, err);
 473         return;
 474 }
 475
 476 /* Header parsing interrupt handling */
 477 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
 478                                  unsigned int reason, unsigned int err)
 479 {
 480         struct s5p_mfc_dev *dev;
 481
 482         if (ctx == NULL)
 483                 return;
 484         dev = ctx->dev;
 485         if (ctx->c_ops->post_seq_start) {
 486                 if (ctx->c_ops->post_seq_start(ctx))
 487                         mfc_err("post_seq_start() failed\n");
 488         } else {
 489                 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
 490                                 dev);
 491                 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
 492                                 dev);
 493
 494                 s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx);
 495
 496                 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
 497                                 dev);
 498                 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
 499                                 dev);
 500                 if (ctx->img_width == 0 || ctx->img_height == 0)
 501                         ctx->state = MFCINST_ERROR;
 502                 else
 503                         ctx->state = MFCINST_HEAD_PARSED;
 504
 505                 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 506                         ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
 507                                 !list_empty(&ctx->src_queue)) {
 508                         struct s5p_mfc_buf *src_buf;
 509                         src_buf = list_entry(ctx->src_queue.next,
 510                                         struct s5p_mfc_buf, list);
 511                         if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
 512                                                 dev) <
 513                                         src_buf->b->v4l2_planes[0].bytesused)
 514                                 ctx->head_processed = 0;
 515                         else
 516                                 ctx->head_processed = 1;
 517                 } else {
 518                         ctx->head_processed = 1;
 519                 }
 520         }
 521         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 522         clear_work_bit(ctx);
 523         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 524         s5p_mfc_clock_off();
 525         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 526         wake_up_ctx(ctx, reason, err);
 527 }
 528
 529 /* Header parsing interrupt handling */
 530 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
 531                                  unsigned int reason, unsigned int err)
 532 {
 533         struct s5p_mfc_buf *src_buf;
 534         struct s5p_mfc_dev *dev;
 535         unsigned long flags;
 536
 537         if (ctx == NULL)
 538                 return;
 539         dev = ctx->dev;
 540         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 541         ctx->int_type = reason;
 542         ctx->int_err = err;
 543         ctx->int_cond = 1;
 544         clear_work_bit(ctx);
 545         if (err == 0) {
 546                 ctx->state = MFCINST_RUNNING;
 547                 if (!ctx->dpb_flush_flag && ctx->head_processed) {
 548                         spin_lock_irqsave(&dev->irqlock, flags);
 549                         if (!list_empty(&ctx->src_queue)) {
 550                                 src_buf = list_entry(ctx->src_queue.next,
 551                                              struct s5p_mfc_buf, list);
 552                                 list_del(&src_buf->list);
 553                                 ctx->src_queue_cnt--;
 554                                 vb2_buffer_done(src_buf->b,
 555                                                 VB2_BUF_STATE_DONE);
 556                         }
 557                         spin_unlock_irqrestore(&dev->irqlock, flags);
 558                 } else {
 559                         ctx->dpb_flush_flag = 0;
 560                 }
 561                 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 562
 563                 s5p_mfc_clock_off();
 564
 565                 wake_up(&ctx->queue);
 566                 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 567         } else {
 568                 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 569
 570                 s5p_mfc_clock_off();
 571
 572                 wake_up(&ctx->queue);
 573         }
 574 }
 575
 576 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
 577                                  unsigned int reason, unsigned int err)
 578 {
 579         struct s5p_mfc_dev *dev = ctx->dev;
 580         struct s5p_mfc_buf *mb_entry;
 581
 582         mfc_debug(2, "Stream completed\n");
 583
 584         s5p_mfc_clear_int_flags(dev);
 585         ctx->int_type = reason;
 586         ctx->int_err = err;
 587         ctx->state = MFCINST_FINISHED;
 588
 589         spin_lock(&dev->irqlock);
 590         if (!list_empty(&ctx->dst_queue)) {
 591                 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
 592                                                                         list);
 593                 list_del(&mb_entry->list);
 594                 ctx->dst_queue_cnt--;
 595                 vb2_set_plane_payload(mb_entry->b, 0, 0);
 596                 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
 597         }
 598         spin_unlock(&dev->irqlock);
 599
 600         clear_work_bit(ctx);
 601
 602         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 603
 604         s5p_mfc_clock_off();
 605         wake_up(&ctx->queue);
 606         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 607 }
 608
 609 /* Interrupt processing */
 610 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
 611 {
 612         struct s5p_mfc_dev *dev = priv;
 613         struct s5p_mfc_ctx *ctx;
 614         unsigned int reason;
 615         unsigned int err;
 616
 617         mfc_debug_enter();
 618         /* Reset the timeout watchdog */
 619         atomic_set(&dev->watchdog_cnt, 0);
 620         ctx = dev->ctx[dev->curr_ctx];
 621         /* Get the reason of interrupt and the error code */
 622         reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
 623         err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
 624         mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
 625         switch (reason) {
 626         case S5P_MFC_R2H_CMD_ERR_RET:
 627                 /* An error has occurred */
 628                 if (ctx->state == MFCINST_RUNNING &&
 629                         s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
 630                                 dev->warn_start)
 631                         s5p_mfc_handle_frame(ctx, reason, err);
 632                 else
 633                         s5p_mfc_handle_error(dev, ctx, reason, err);
 634                 clear_bit(0, &dev->enter_suspend);
 635                 break;
 636
 637         case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
 638         case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
 639         case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
 640                 if (ctx->c_ops->post_frame_start) {
 641                         if (ctx->c_ops->post_frame_start(ctx))
 642                                 mfc_err("post_frame_start() failed\n");
 643                         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 644                         wake_up_ctx(ctx, reason, err);
 645                         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 646                         s5p_mfc_clock_off();
 647                         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 648                 } else {
 649                         s5p_mfc_handle_frame(ctx, reason, err);
 650                 }
 651                 break;
 652
 653         case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
 654                 s5p_mfc_handle_seq_done(ctx, reason, err);
 655                 break;
 656
 657         case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
 658                 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
 659                 ctx->state = MFCINST_GOT_INST;
 660                 clear_work_bit(ctx);
 661                 wake_up(&ctx->queue);
 662                 goto irq_cleanup_hw;
 663
 664         case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
 665                 clear_work_bit(ctx);
 666                 ctx->inst_no = MFC_NO_INSTANCE_SET;
 667                 ctx->state = MFCINST_FREE;
 668                 wake_up(&ctx->queue);
 669                 goto irq_cleanup_hw;
 670
 671         case S5P_MFC_R2H_CMD_SYS_INIT_RET:
 672         case S5P_MFC_R2H_CMD_FW_STATUS_RET:
 673         case S5P_MFC_R2H_CMD_SLEEP_RET:
 674         case S5P_MFC_R2H_CMD_WAKEUP_RET:
 675                 if (ctx)
 676                         clear_work_bit(ctx);
 677                 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 678                 wake_up_dev(dev, reason, err);
 679                 clear_bit(0, &dev->hw_lock);
 680                 clear_bit(0, &dev->enter_suspend);
 681                 break;
 682
 683         case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
 684                 s5p_mfc_handle_init_buffers(ctx, reason, err);
 685                 break;
 686
 687         case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
 688                 s5p_mfc_handle_stream_complete(ctx, reason, err);
 689                 break;
 690
 691         case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
 692                 clear_work_bit(ctx);
 693                 ctx->state = MFCINST_RUNNING;
 694                 wake_up(&ctx->queue);
 695                 goto irq_cleanup_hw;
 696
 697         default:
 698                 mfc_debug(2, "Unknown int reason\n");
 699                 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 700         }
 701         mfc_debug_leave();
 702         return IRQ_HANDLED;
 703 irq_cleanup_hw:
 704         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 705         ctx->int_type = reason;
 706         ctx->int_err = err;
 707         ctx->int_cond = 1;
 708         if (test_and_clear_bit(0, &dev->hw_lock) == 0)
 709                 mfc_err("Failed to unlock hw\n");
 710
 711         s5p_mfc_clock_off();
 712
 713         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 714         mfc_debug(2, "Exit via irq_cleanup_hw\n");
 715         return IRQ_HANDLED;
 716 }
 717
 718 /* Open an MFC node */
 719 static int s5p_mfc_open(struct file *file)
 720 {
 721         struct video_device *vdev = video_devdata(file);
 722         struct s5p_mfc_dev *dev = video_drvdata(file);
 723         struct s5p_mfc_ctx *ctx = NULL;
 724         struct vb2_queue *q;
 725         int ret = 0;
 726
 727         mfc_debug_enter();
 728         if (mutex_lock_interruptible(&dev->mfc_mutex))
 729                 return -ERESTARTSYS;
 730         dev->num_inst++;        /* It is guarded by mfc_mutex in vfd */
 731         /* Allocate memory for context */
 732         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 733         if (!ctx) {
 734                 mfc_err("Not enough memory\n");
 735                 ret = -ENOMEM;
 736                 goto err_alloc;
 737         }
 738         v4l2_fh_init(&ctx->fh, vdev);
 739         file->private_data = &ctx->fh;
 740         v4l2_fh_add(&ctx->fh);
 741         ctx->dev = dev;
 742         INIT_LIST_HEAD(&ctx->src_queue);
 743         INIT_LIST_HEAD(&ctx->dst_queue);
 744         ctx->src_queue_cnt = 0;
 745         ctx->dst_queue_cnt = 0;
 746         /* Get context number */
 747         ctx->num = 0;
 748         while (dev->ctx[ctx->num]) {
 749                 ctx->num++;
 750                 if (ctx->num >= MFC_NUM_CONTEXTS) {
 751                         mfc_err("Too many open contexts\n");
 752                         ret = -EBUSY;
 753                         goto err_no_ctx;
 754                 }
 755         }
 756         /* Mark context as idle */
 757         clear_work_bit_irqsave(ctx);
 758         dev->ctx[ctx->num] = ctx;
 759         if (vdev == dev->vfd_dec) {
 760                 ctx->type = MFCINST_DECODER;
 761                 ctx->c_ops = get_dec_codec_ops();
 762                 s5p_mfc_dec_init(ctx);
 763                 /* Setup ctrl handler */
 764                 ret = s5p_mfc_dec_ctrls_setup(ctx);
 765                 if (ret) {
 766                         mfc_err("Failed to setup mfc controls\n");
 767                         goto err_ctrls_setup;
 768                 }
 769         } else if (vdev == dev->vfd_enc) {
 770                 ctx->type = MFCINST_ENCODER;
 771                 ctx->c_ops = get_enc_codec_ops();
 772                 /* only for encoder */
 773                 INIT_LIST_HEAD(&ctx->ref_queue);
 774                 ctx->ref_queue_cnt = 0;
 775                 s5p_mfc_enc_init(ctx);
 776                 /* Setup ctrl handler */
 777                 ret = s5p_mfc_enc_ctrls_setup(ctx);
 778                 if (ret) {
 779                         mfc_err("Failed to setup mfc controls\n");
 780                         goto err_ctrls_setup;
 781                 }
 782         } else {
 783                 ret = -ENOENT;
 784                 goto err_bad_node;
 785         }
 786         ctx->fh.ctrl_handler = &ctx->ctrl_handler;
 787         ctx->inst_no = MFC_NO_INSTANCE_SET;
 788         /* Load firmware if this is the first instance */
 789         if (dev->num_inst == 1) {
 790                 dev->watchdog_timer.expires = jiffies +
 791                                         msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
 792                 add_timer(&dev->watchdog_timer);
 793                 ret = s5p_mfc_power_on();
 794                 if (ret < 0) {
 795                         mfc_err("power on failed\n");
 796                         goto err_pwr_enable;
 797                 }
 798                 s5p_mfc_clock_on();
 799                 ret = s5p_mfc_load_firmware(dev);
 800                 if (ret) {
 801                         s5p_mfc_clock_off();
 802                         goto err_load_fw;
 803                 }
 804                 /* Init the FW */
 805                 ret = s5p_mfc_init_hw(dev);
 806                 s5p_mfc_clock_off();
 807                 if (ret)
 808                         goto err_init_hw;
 809         }
 810         /* Init videobuf2 queue for CAPTURE */
 811         q = &ctx->vq_dst;
 812         q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
 813         q->drv_priv = &ctx->fh;
 814         q->lock = &dev->mfc_mutex;
 815         if (vdev == dev->vfd_dec) {
 816                 q->io_modes = VB2_MMAP;
 817                 q->ops = get_dec_queue_ops();
 818         } else if (vdev == dev->vfd_enc) {
 819                 q->io_modes = VB2_MMAP | VB2_USERPTR;
 820                 q->ops = get_enc_queue_ops();
 821         } else {
 822                 ret = -ENOENT;
 823                 goto err_queue_init;
 824         }
 825         q->mem_ops = &vb2_dma_contig_memops;
 826         q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 827         ret = vb2_queue_init(q);
 828         if (ret) {
 829                 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
 830                 goto err_queue_init;
 831         }
 832         /* Init videobuf2 queue for OUTPUT */
 833         q = &ctx->vq_src;
 834         q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
 835         q->io_modes = VB2_MMAP;
 836         q->drv_priv = &ctx->fh;
 837         q->lock = &dev->mfc_mutex;
 838         if (vdev == dev->vfd_dec) {
 839                 q->io_modes = VB2_MMAP;
 840                 q->ops = get_dec_queue_ops();
 841         } else if (vdev == dev->vfd_enc) {
 842                 q->io_modes = VB2_MMAP | VB2_USERPTR;
 843                 q->ops = get_enc_queue_ops();
 844         } else {
 845                 ret = -ENOENT;
 846                 goto err_queue_init;
 847         }
 848         /* One way to indicate end-of-stream for MFC is to set the
 849          * bytesused == 0. However by default videobuf2 handles bytesused
 850          * equal to 0 as a special case and changes its value to the size
 851          * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
 852          * will keep the value of bytesused intact.
 853          */
 854         q->allow_zero_bytesused = 1;
 855         q->mem_ops = &vb2_dma_contig_memops;
 856         q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 857         ret = vb2_queue_init(q);
 858         if (ret) {
 859                 mfc_err("Failed to initialize videobuf2 queue(output)\n");
 860                 goto err_queue_init;
 861         }
 862         init_waitqueue_head(&ctx->queue);
 863         mutex_unlock(&dev->mfc_mutex);
 864         mfc_debug_leave();
 865         return ret;
 866         /* Deinit when failure occurred */
 867 err_queue_init:
 868         if (dev->num_inst == 1)
 869                 s5p_mfc_deinit_hw(dev);
 870 err_init_hw:
 871 err_load_fw:
 872 err_pwr_enable:
 873         if (dev->num_inst == 1) {
 874                 if (s5p_mfc_power_off() < 0)
 875                         mfc_err("power off failed\n");
 876                 del_timer_sync(&dev->watchdog_timer);
 877         }
 878 err_ctrls_setup:
 879         s5p_mfc_dec_ctrls_delete(ctx);
 880 err_bad_node:
 881         dev->ctx[ctx->num] = NULL;
 882 err_no_ctx:
 883         v4l2_fh_del(&ctx->fh);
 884         v4l2_fh_exit(&ctx->fh);
 885         kfree(ctx);
 886 err_alloc:
 887         dev->num_inst--;
 888         mutex_unlock(&dev->mfc_mutex);
 889         mfc_debug_leave();
 890         return ret;
 891 }
 892
 893 /* Release MFC context */
 894 static int s5p_mfc_release(struct file *file)
 895 {
 896         struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
 897         struct s5p_mfc_dev *dev = ctx->dev;
 898
 899         mfc_debug_enter();
 900         mutex_lock(&dev->mfc_mutex);
 901         s5p_mfc_clock_on();
 902         vb2_queue_release(&ctx->vq_src);
 903         vb2_queue_release(&ctx->vq_dst);
 904         /* Mark context as idle */
 905         clear_work_bit_irqsave(ctx);
 906         /* If instance was initialised and not yet freed,
 907          * return instance and free resources */
 908         if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
 909                 mfc_debug(2, "Has to free instance\n");
 910                 s5p_mfc_close_mfc_inst(dev, ctx);
 911         }
 912         /* hardware locking scheme */
 913         if (dev->curr_ctx == ctx->num)
 914                 clear_bit(0, &dev->hw_lock);
 915         dev->num_inst--;
 916         if (dev->num_inst == 0) {
 917                 mfc_debug(2, "Last instance\n");
 918                 s5p_mfc_deinit_hw(dev);
 919                 del_timer_sync(&dev->watchdog_timer);
 920                 if (s5p_mfc_power_off() < 0)
 921                         mfc_err("Power off failed\n");
 922         }
 923         mfc_debug(2, "Shutting down clock\n");
 924         s5p_mfc_clock_off();
 925         dev->ctx[ctx->num] = NULL;
 926         s5p_mfc_dec_ctrls_delete(ctx);
 927         v4l2_fh_del(&ctx->fh);
 928         v4l2_fh_exit(&ctx->fh);
 929         kfree(ctx);
 930         mfc_debug_leave();
 931         mutex_unlock(&dev->mfc_mutex);
 932         return 0;
 933 }
 934
 935 /* Poll */
 936 static unsigned int s5p_mfc_poll(struct file *file,
 937                                  struct poll_table_struct *wait)
 938 {
 939         struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
 940         struct s5p_mfc_dev *dev = ctx->dev;
 941         struct vb2_queue *src_q, *dst_q;
 942         struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
 943         unsigned int rc = 0;
 944         unsigned long flags;
 945
 946         mutex_lock(&dev->mfc_mutex);
 947         src_q = &ctx->vq_src;
 948         dst_q = &ctx->vq_dst;
 949         /*
 950          * There has to be at least one buffer queued on each queued_list, which
 951          * means either in driver already or waiting for driver to claim it
 952          * and start processing.
 953          */
 954         if ((!src_q->streaming || list_empty(&src_q->queued_list))
 955                 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
 956                 rc = POLLERR;
 957                 goto end;
 958         }
 959         mutex_unlock(&dev->mfc_mutex);
 960         poll_wait(file, &ctx->fh.wait, wait);
 961         poll_wait(file, &src_q->done_wq, wait);
 962         poll_wait(file, &dst_q->done_wq, wait);
 963         mutex_lock(&dev->mfc_mutex);
 964         if (v4l2_event_pending(&ctx->fh))
 965                 rc |= POLLPRI;
 966         spin_lock_irqsave(&src_q->done_lock, flags);
 967         if (!list_empty(&src_q->done_list))
 968                 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
 969                                                                 done_entry);
 970         if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
 971                                 || src_vb->state == VB2_BUF_STATE_ERROR))
 972                 rc |= POLLOUT | POLLWRNORM;
 973         spin_unlock_irqrestore(&src_q->done_lock, flags);
 974         spin_lock_irqsave(&dst_q->done_lock, flags);
 975         if (!list_empty(&dst_q->done_list))
 976                 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
 977                                                                 done_entry);
 978         if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
 979                                 || dst_vb->state == VB2_BUF_STATE_ERROR))
 980                 rc |= POLLIN | POLLRDNORM;
 981         spin_unlock_irqrestore(&dst_q->done_lock, flags);
 982 end:
 983         mutex_unlock(&dev->mfc_mutex);
 984         return rc;
 985 }
 986
 987 /* Mmap */
 988 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
 989 {
 990         struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
 991         struct s5p_mfc_dev *dev = ctx->dev;
 992         unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
 993         int ret;
 994
 995         if (mutex_lock_interruptible(&dev->mfc_mutex))
 996                 return -ERESTARTSYS;
 997         if (offset < DST_QUEUE_OFF_BASE) {
 998                 mfc_debug(2, "mmaping source\n");
 999                 ret = vb2_mmap(&ctx->vq_src, vma);
1000         } else {                /* capture */
1001                 mfc_debug(2, "mmaping destination\n");
1002                 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1003                 ret = vb2_mmap(&ctx->vq_dst, vma);
1004         }
1005         mutex_unlock(&dev->mfc_mutex);
1006         return ret;
1007 }
1008
1009 /* v4l2 ops */
1010 static const struct v4l2_file_operations s5p_mfc_fops = {
1011         .owner = THIS_MODULE,
1012         .open = s5p_mfc_open,
1013         .release = s5p_mfc_release,
1014         .poll = s5p_mfc_poll,
1015         .unlocked_ioctl = video_ioctl2,
1016         .mmap = s5p_mfc_mmap,
1017 };
1018
1019 static int match_child(struct device *dev, void *data)
1020 {
1021         if (!dev_name(dev))
1022                 return 0;
1023         return !strcmp(dev_name(dev), (char *)data);
1024 }
1025
1026 static void *mfc_get_drv_data(struct platform_device *pdev);
1027
1028 static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1029 {
1030         unsigned int mem_info[2] = { };
1031
1032         dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1033                         sizeof(struct device), GFP_KERNEL);
1034         if (!dev->mem_dev_l) {
1035                 mfc_err("Not enough memory\n");
1036                 return -ENOMEM;
1037         }
1038         device_initialize(dev->mem_dev_l);
1039         of_property_read_u32_array(dev->plat_dev->dev.of_node,
1040                         "samsung,mfc-l", mem_info, 2);
1041         if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1042                                 mem_info[0], mem_info[1],
1043                                 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1044                 mfc_err("Failed to declare coherent memory for\n"
1045                 "MFC device\n");
1046                 return -ENOMEM;
1047         }
1048
1049         dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1050                         sizeof(struct device), GFP_KERNEL);
1051         if (!dev->mem_dev_r) {
1052                 mfc_err("Not enough memory\n");
1053                 return -ENOMEM;
1054         }
1055         device_initialize(dev->mem_dev_r);
1056         of_property_read_u32_array(dev->plat_dev->dev.of_node,
1057                         "samsung,mfc-r", mem_info, 2);
1058         if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1059                                 mem_info[0], mem_info[1],
1060                                 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1061                 pr_err("Failed to declare coherent memory for\n"
1062                 "MFC device\n");
1063                 return -ENOMEM;
1064         }
1065         return 0;
1066 }
1067
1068 /* MFC probe function */
1069 static int s5p_mfc_probe(struct platform_device *pdev)
1070 {
1071         struct s5p_mfc_dev *dev;
1072         struct video_device *vfd;
1073         struct resource *res;
1074         int ret;
1075
1076         pr_debug("%s++\n", __func__);
1077         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1078         if (!dev) {
1079                 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1080                 return -ENOMEM;
1081         }
1082
1083         spin_lock_init(&dev->irqlock);
1084         spin_lock_init(&dev->condlock);
1085         dev->plat_dev = pdev;
1086         if (!dev->plat_dev) {
1087                 dev_err(&pdev->dev, "No platform data specified\n");
1088                 return -ENODEV;
1089         }
1090
1091         dev->variant = mfc_get_drv_data(pdev);
1092
1093         ret = s5p_mfc_init_pm(dev);
1094         if (ret < 0) {
1095                 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1096                 return ret;
1097         }
1098
1099         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1100
1101         dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1102         if (IS_ERR(dev->regs_base))
1103                 return PTR_ERR(dev->regs_base);
1104
1105         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1106         if (res == NULL) {
1107                 dev_err(&pdev->dev, "failed to get irq resource\n");
1108                 ret = -ENOENT;
1109                 goto err_res;
1110         }
1111         dev->irq = res->start;
1112         ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1113                                         0, pdev->name, dev);
1114         if (ret) {
1115                 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1116                 goto err_res;
1117         }
1118
1119         if (pdev->dev.of_node) {
1120                 ret = s5p_mfc_alloc_memdevs(dev);
1121                 if (ret < 0)
1122                         goto err_res;
1123         } else {
1124                 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1125                                 "s5p-mfc-l", match_child);
1126                 if (!dev->mem_dev_l) {
1127                         mfc_err("Mem child (L) device get failed\n");
1128                         ret = -ENODEV;
1129                         goto err_res;
1130                 }
1131                 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1132                                 "s5p-mfc-r", match_child);
1133                 if (!dev->mem_dev_r) {
1134                         mfc_err("Mem child (R) device get failed\n");
1135                         ret = -ENODEV;
1136                         goto err_res;
1137                 }
1138         }
1139
1140         dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1141         if (IS_ERR(dev->alloc_ctx[0])) {
1142                 ret = PTR_ERR(dev->alloc_ctx[0]);
1143                 goto err_res;
1144         }
1145         dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1146         if (IS_ERR(dev->alloc_ctx[1])) {
1147                 ret = PTR_ERR(dev->alloc_ctx[1]);
1148                 goto err_mem_init_ctx_1;
1149         }
1150
1151         mutex_init(&dev->mfc_mutex);
1152
1153         ret = s5p_mfc_alloc_firmware(dev);
1154         if (ret)
1155                 goto err_alloc_fw;
1156
1157         ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1158         if (ret)
1159                 goto err_v4l2_dev_reg;
1160         init_waitqueue_head(&dev->queue);
1161
1162         /* decoder */
1163         vfd = video_device_alloc();
1164         if (!vfd) {
1165                 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1166                 ret = -ENOMEM;
1167                 goto err_dec_alloc;
1168         }
1169         vfd->fops       = &s5p_mfc_fops;
1170         vfd->ioctl_ops  = get_dec_v4l2_ioctl_ops();
1171         vfd->release    = video_device_release;
1172         vfd->lock       = &dev->mfc_mutex;
1173         vfd->v4l2_dev   = &dev->v4l2_dev;
1174         vfd->vfl_dir    = VFL_DIR_M2M;
1175         snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1176         dev->vfd_dec    = vfd;
1177         ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1178         if (ret) {
1179                 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1180                 video_device_release(vfd);
1181                 goto err_dec_reg;
1182         }
1183         v4l2_info(&dev->v4l2_dev,
1184                   "decoder registered as /dev/video%d\n", vfd->num);
1185         video_set_drvdata(vfd, dev);
1186
1187         /* encoder */
1188         vfd = video_device_alloc();
1189         if (!vfd) {
1190                 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1191                 ret = -ENOMEM;
1192                 goto err_enc_alloc;
1193         }
1194         vfd->fops       = &s5p_mfc_fops;
1195         vfd->ioctl_ops  = get_enc_v4l2_ioctl_ops();
1196         vfd->release    = video_device_release;
1197         vfd->lock       = &dev->mfc_mutex;
1198         vfd->v4l2_dev   = &dev->v4l2_dev;
1199         vfd->vfl_dir    = VFL_DIR_M2M;
1200         snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1201         dev->vfd_enc    = vfd;
1202         ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1203         if (ret) {
1204                 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1205                 video_device_release(vfd);
1206                 goto err_enc_reg;
1207         }
1208         v4l2_info(&dev->v4l2_dev,
1209                   "encoder registered as /dev/video%d\n", vfd->num);
1210         video_set_drvdata(vfd, dev);
1211         platform_set_drvdata(pdev, dev);
1212
1213         dev->hw_lock = 0;
1214         dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1215         INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1216         atomic_set(&dev->watchdog_cnt, 0);
1217         init_timer(&dev->watchdog_timer);
1218         dev->watchdog_timer.data = (unsigned long)dev;
1219         dev->watchdog_timer.function = s5p_mfc_watchdog;
1220
1221         /* Initialize HW ops and commands based on MFC version */
1222         s5p_mfc_init_hw_ops(dev);
1223         s5p_mfc_init_hw_cmds(dev);
1224         s5p_mfc_init_regs(dev);
1225
1226         pr_debug("%s--\n", __func__);
1227         return 0;
1228
1229 /* Deinit MFC if probe had failed */
1230 err_enc_reg:
1231         video_device_release(dev->vfd_enc);
1232 err_enc_alloc:
1233         video_unregister_device(dev->vfd_dec);
1234 err_dec_reg:
1235         video_device_release(dev->vfd_dec);
1236 err_dec_alloc:
1237         v4l2_device_unregister(&dev->v4l2_dev);
1238 err_v4l2_dev_reg:
1239         s5p_mfc_release_firmware(dev);
1240 err_alloc_fw:
1241         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1242 err_mem_init_ctx_1:
1243         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1244 err_res:
1245         s5p_mfc_final_pm(dev);
1246
1247         pr_debug("%s-- with error\n", __func__);
1248         return ret;
1249
1250 }
1251
1252 /* Remove the driver */
1253 static int s5p_mfc_remove(struct platform_device *pdev)
1254 {
1255         struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1256
1257         v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1258
1259         del_timer_sync(&dev->watchdog_timer);
1260         flush_workqueue(dev->watchdog_workqueue);
1261         destroy_workqueue(dev->watchdog_workqueue);
1262
1263         video_unregister_device(dev->vfd_enc);
1264         video_unregister_device(dev->vfd_dec);
1265         v4l2_device_unregister(&dev->v4l2_dev);
1266         s5p_mfc_release_firmware(dev);
1267         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1268         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1269         if (pdev->dev.of_node) {
1270                 put_device(dev->mem_dev_l);
1271                 put_device(dev->mem_dev_r);
1272         }
1273
1274         s5p_mfc_final_pm(dev);
1275         return 0;
1276 }
1277
1278 #ifdef CONFIG_PM_SLEEP
1279
1280 static int s5p_mfc_suspend(struct device *dev)
1281 {
1282         struct platform_device *pdev = to_platform_device(dev);
1283         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1284         int ret;
1285
1286         if (m_dev->num_inst == 0)
1287                 return 0;
1288
1289         if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1290                 mfc_err("Error: going to suspend for a second time\n");
1291                 return -EIO;
1292         }
1293
1294         /* Check if we're processing then wait if it necessary. */
1295         while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1296                 /* Try and lock the HW */
1297                 /* Wait on the interrupt waitqueue */
1298                 ret = wait_event_interruptible_timeout(m_dev->queue,
1299                         m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1300                 if (ret == 0) {
1301                         mfc_err("Waiting for hardware to finish timed out\n");
1302                         clear_bit(0, &m_dev->enter_suspend);
1303                         return -EIO;
1304                 }
1305         }
1306
1307         ret = s5p_mfc_sleep(m_dev);
1308         if (ret) {
1309                 clear_bit(0, &m_dev->enter_suspend);
1310                 clear_bit(0, &m_dev->hw_lock);
1311         }
1312         return ret;
1313 }
1314
1315 static int s5p_mfc_resume(struct device *dev)
1316 {
1317         struct platform_device *pdev = to_platform_device(dev);
1318         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1319
1320         if (m_dev->num_inst == 0)
1321                 return 0;
1322         return s5p_mfc_wakeup(m_dev);
1323 }
1324 #endif
1325
1326 #ifdef CONFIG_PM
1327 static int s5p_mfc_runtime_suspend(struct device *dev)
1328 {
1329         struct platform_device *pdev = to_platform_device(dev);
1330         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1331
1332         atomic_set(&m_dev->pm.power, 0);
1333         return 0;
1334 }
1335
1336 static int s5p_mfc_runtime_resume(struct device *dev)
1337 {
1338         struct platform_device *pdev = to_platform_device(dev);
1339         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1340
1341         atomic_set(&m_dev->pm.power, 1);
1342         return 0;
1343 }
1344 #endif
1345
1346 /* Power management */
1347 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1348         SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1349         SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1350                            NULL)
1351 };
1352
1353 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1354         .h264_ctx       = MFC_H264_CTX_BUF_SIZE,
1355         .non_h264_ctx   = MFC_CTX_BUF_SIZE,
1356         .dsc            = DESC_BUF_SIZE,
1357         .shm            = SHARED_BUF_SIZE,
1358 };
1359
1360 static struct s5p_mfc_buf_size buf_size_v5 = {
1361         .fw     = MAX_FW_SIZE,
1362         .cpb    = MAX_CPB_SIZE,
1363         .priv   = &mfc_buf_size_v5,
1364 };
1365
1366 static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1367         .base = MFC_BASE_ALIGN_ORDER,
1368 };
1369
1370 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1371         .version        = MFC_VERSION,
1372         .version_bit    = MFC_V5_BIT,
1373         .port_num       = MFC_NUM_PORTS,
1374         .buf_size       = &buf_size_v5,
1375         .buf_align      = &mfc_buf_align_v5,
1376         .fw_name[0]     = "s5p-mfc.fw",
1377 };
1378
1379 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1380         .dev_ctx        = MFC_CTX_BUF_SIZE_V6,
1381         .h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1382         .other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1383         .h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1384         .other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1385 };
1386
1387 static struct s5p_mfc_buf_size buf_size_v6 = {
1388         .fw     = MAX_FW_SIZE_V6,
1389         .cpb    = MAX_CPB_SIZE_V6,
1390         .priv   = &mfc_buf_size_v6,
1391 };
1392
1393 static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1394         .base = 0,
1395 };
1396
1397 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1398         .version        = MFC_VERSION_V6,
1399         .version_bit    = MFC_V6_BIT,
1400         .port_num       = MFC_NUM_PORTS_V6,
1401         .buf_size       = &buf_size_v6,
1402         .buf_align      = &mfc_buf_align_v6,
1403         .fw_name[0]     = "s5p-mfc-v6.fw",
1404         /*
1405          * v6-v2 firmware contains bug fixes and interface change
1406          * for init buffer command
1407          */
1408         .fw_name[1]     = "s5p-mfc-v6-v2.fw",
1409 };
1410
1411 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1412         .dev_ctx        = MFC_CTX_BUF_SIZE_V7,
1413         .h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1414         .other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1415         .h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1416         .other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1417 };
1418
1419 static struct s5p_mfc_buf_size buf_size_v7 = {
1420         .fw     = MAX_FW_SIZE_V7,
1421         .cpb    = MAX_CPB_SIZE_V7,
1422         .priv   = &mfc_buf_size_v7,
1423 };
1424
1425 static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1426         .base = 0,
1427 };
1428
1429 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1430         .version        = MFC_VERSION_V7,
1431         .version_bit    = MFC_V7_BIT,
1432         .port_num       = MFC_NUM_PORTS_V7,
1433         .buf_size       = &buf_size_v7,
1434         .buf_align      = &mfc_buf_align_v7,
1435         .fw_name[0]     = "s5p-mfc-v7.fw",
1436 };
1437
1438 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1439         .dev_ctx        = MFC_CTX_BUF_SIZE_V8,
1440         .h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1441         .other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1442         .h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1443         .other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1444 };
1445
1446 static struct s5p_mfc_buf_size buf_size_v8 = {
1447         .fw     = MAX_FW_SIZE_V8,
1448         .cpb    = MAX_CPB_SIZE_V8,
1449         .priv   = &mfc_buf_size_v8,
1450 };
1451
1452 static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1453         .base = 0,
1454 };
1455
1456 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1457         .version        = MFC_VERSION_V8,
1458         .version_bit    = MFC_V8_BIT,
1459         .port_num       = MFC_NUM_PORTS_V8,
1460         .buf_size       = &buf_size_v8,
1461         .buf_align      = &mfc_buf_align_v8,
1462         .fw_name[0]     = "s5p-mfc-v8.fw",
1463 };
1464
1465 static const struct platform_device_id mfc_driver_ids[] = {
1466         {
1467                 .name = "s5p-mfc",
1468                 .driver_data = (unsigned long)&mfc_drvdata_v5,
1469         }, {
1470                 .name = "s5p-mfc-v5",
1471                 .driver_data = (unsigned long)&mfc_drvdata_v5,
1472         }, {
1473                 .name = "s5p-mfc-v6",
1474                 .driver_data = (unsigned long)&mfc_drvdata_v6,
1475         }, {
1476                 .name = "s5p-mfc-v7",
1477                 .driver_data = (unsigned long)&mfc_drvdata_v7,
1478         }, {
1479                 .name = "s5p-mfc-v8",
1480                 .driver_data = (unsigned long)&mfc_drvdata_v8,
1481         },
1482         {},
1483 };
1484 MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1485
1486 static const struct of_device_id exynos_mfc_match[] = {
1487         {
1488                 .compatible = "samsung,mfc-v5",
1489                 .data = &mfc_drvdata_v5,
1490         }, {
1491                 .compatible = "samsung,mfc-v6",
1492                 .data = &mfc_drvdata_v6,
1493         }, {
1494                 .compatible = "samsung,mfc-v7",
1495                 .data = &mfc_drvdata_v7,
1496         }, {
1497                 .compatible = "samsung,mfc-v8",
1498                 .data = &mfc_drvdata_v8,
1499         },
1500         {},
1501 };
1502 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1503
1504 static void *mfc_get_drv_data(struct platform_device *pdev)
1505 {
1506         struct s5p_mfc_variant *driver_data = NULL;
1507
1508         if (pdev->dev.of_node) {
1509                 const struct of_device_id *match;
1510                 match = of_match_node(exynos_mfc_match,
1511                                 pdev->dev.of_node);
1512                 if (match)
1513                         driver_data = (struct s5p_mfc_variant *)match->data;
1514         } else {
1515                 driver_data = (struct s5p_mfc_variant *)
1516                         platform_get_device_id(pdev)->driver_data;
1517         }
1518         return driver_data;
1519 }
1520
1521 static struct platform_driver s5p_mfc_driver = {
1522         .probe          = s5p_mfc_probe,
1523         .remove         = s5p_mfc_remove,
1524         .id_table       = mfc_driver_ids,
1525         .driver = {
1526                 .name   = S5P_MFC_NAME,
1527                 .pm     = &s5p_mfc_pm_ops,
1528                 .of_match_table = exynos_mfc_match,
1529         },
1530 };
1531
1532 module_platform_driver(s5p_mfc_driver);
1533
1534 MODULE_LICENSE("GPL");
1535 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1536 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1537