2 * linux/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/firmware.h>
16 #include <linux/jiffies.h>
17 #include <linux/sched.h>
18 #include "s5p_mfc_cmd.h"
19 #include "s5p_mfc_common.h"
20 #include "s5p_mfc_debug.h"
21 #include "s5p_mfc_intr.h"
22 #include "s5p_mfc_opr.h"
23 #include "s5p_mfc_pm.h"
25 static void *s5p_mfc_bitproc_buf;
26 static size_t s5p_mfc_bitproc_phys;
27 static unsigned char *s5p_mfc_bitproc_virt;
29 /* Allocate and load firmware */
30 int s5p_mfc_alloc_and_load_firmware(struct s5p_mfc_dev *dev)
32 struct firmware *fw_blob;
33 size_t bank2_base_phys;
37 /* Firmare has to be present as a separate file or compiled
41 err = request_firmware((const struct firmware **)&fw_blob,
42 dev->variant->fw_name, dev->v4l2_dev.dev);
44 mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
47 dev->fw_size = dev->variant->buf_size->fw;
48 if (fw_blob->size > dev->fw_size) {
49 mfc_err("MFC firmware is too big to be loaded\n");
50 release_firmware(fw_blob);
53 if (s5p_mfc_bitproc_buf) {
54 mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
55 release_firmware(fw_blob);
58 s5p_mfc_bitproc_buf = vb2_dma_contig_memops.alloc(
59 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], dev->fw_size);
60 if (IS_ERR(s5p_mfc_bitproc_buf)) {
61 s5p_mfc_bitproc_buf = NULL;
62 mfc_err("Allocating bitprocessor buffer failed\n");
63 release_firmware(fw_blob);
66 s5p_mfc_bitproc_phys = s5p_mfc_mem_cookie(
67 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], s5p_mfc_bitproc_buf);
68 if (s5p_mfc_bitproc_phys & ((1 << MFC_BASE_ALIGN_ORDER) - 1)) {
69 mfc_err("The base memory for bank 1 is not aligned to 128KB\n");
70 vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
71 s5p_mfc_bitproc_phys = 0;
72 s5p_mfc_bitproc_buf = NULL;
73 release_firmware(fw_blob);
76 s5p_mfc_bitproc_virt = vb2_dma_contig_memops.vaddr(s5p_mfc_bitproc_buf);
77 if (!s5p_mfc_bitproc_virt) {
78 mfc_err("Bitprocessor memory remap failed\n");
79 vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
80 s5p_mfc_bitproc_phys = 0;
81 s5p_mfc_bitproc_buf = NULL;
82 release_firmware(fw_blob);
85 dev->bank1 = s5p_mfc_bitproc_phys;
86 if (HAS_PORTNUM(dev) && IS_TWOPORT(dev)) {
87 b_base = vb2_dma_contig_memops.alloc(
88 dev->alloc_ctx[MFC_BANK2_ALLOC_CTX],
89 1 << MFC_BASE_ALIGN_ORDER);
91 vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
92 s5p_mfc_bitproc_phys = 0;
93 s5p_mfc_bitproc_buf = NULL;
94 mfc_err("Allocating bank2 base failed\n");
95 release_firmware(fw_blob);
98 bank2_base_phys = s5p_mfc_mem_cookie(
99 dev->alloc_ctx[MFC_BANK2_ALLOC_CTX], b_base);
100 vb2_dma_contig_memops.put(b_base);
101 if (bank2_base_phys & ((1 << MFC_BASE_ALIGN_ORDER) - 1)) {
102 mfc_err("The base memory for bank 2 is not aligned to 128KB\n");
103 vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
104 s5p_mfc_bitproc_phys = 0;
105 s5p_mfc_bitproc_buf = NULL;
106 release_firmware(fw_blob);
109 /* Valid buffers passed to MFC encoder with LAST_FRAME command
110 * should not have address of bank2 - MFC will treat it as a null frame.
111 * To avoid such situation we set bank2 address below the pool address.
113 dev->bank2 = bank2_base_phys - (1 << MFC_BASE_ALIGN_ORDER);
115 dev->bank2 = dev->bank1;
117 memcpy(s5p_mfc_bitproc_virt, fw_blob->data, fw_blob->size);
119 release_firmware(fw_blob);
124 /* Reload firmware to MFC */
125 int s5p_mfc_reload_firmware(struct s5p_mfc_dev *dev)
127 struct firmware *fw_blob;
130 /* Firmare has to be present as a separate file or compiled
134 err = request_firmware((const struct firmware **)&fw_blob,
135 dev->variant->fw_name, dev->v4l2_dev.dev);
137 mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
140 if (fw_blob->size > dev->fw_size) {
141 mfc_err("MFC firmware is too big to be loaded\n");
142 release_firmware(fw_blob);
145 if (s5p_mfc_bitproc_buf == NULL || s5p_mfc_bitproc_phys == 0) {
146 mfc_err("MFC firmware is not allocated or was not mapped correctly\n");
147 release_firmware(fw_blob);
150 memcpy(s5p_mfc_bitproc_virt, fw_blob->data, fw_blob->size);
152 release_firmware(fw_blob);
157 /* Release firmware memory */
158 int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
160 /* Before calling this function one has to make sure
161 * that MFC is no longer processing */
162 if (!s5p_mfc_bitproc_buf)
164 vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
165 s5p_mfc_bitproc_virt = NULL;
166 s5p_mfc_bitproc_phys = 0;
167 s5p_mfc_bitproc_buf = NULL;
171 /* Reset the device */
172 int s5p_mfc_reset(struct s5p_mfc_dev *dev)
174 unsigned int mc_status;
175 unsigned long timeout;
182 /* except RISC, reset */
183 mfc_write(dev, 0xFEE, S5P_FIMV_MFC_RESET_V6);
185 mfc_write(dev, 0x0, S5P_FIMV_MFC_RESET_V6);
187 /* Zero Initialization of MFC registers */
188 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
189 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
190 mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
192 for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++)
193 mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
196 mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
197 mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
198 mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
202 mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
203 /* All reset except for MC */
204 mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
207 timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
208 /* Check MC status */
210 if (time_after(jiffies, timeout)) {
211 mfc_err("Timeout while resetting MFC\n");
215 mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
217 } while (mc_status & 0x3);
219 mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
220 mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
227 static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
230 mfc_write(dev, dev->bank1, S5P_FIMV_RISC_BASE_ADDRESS_V6);
231 mfc_debug(2, "Base Address : %08x\n", dev->bank1);
233 mfc_write(dev, dev->bank1, S5P_FIMV_MC_DRAMBASE_ADR_A);
234 mfc_write(dev, dev->bank2, S5P_FIMV_MC_DRAMBASE_ADR_B);
235 mfc_debug(2, "Bank1: %08x, Bank2: %08x\n",
236 dev->bank1, dev->bank2);
240 static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
243 /* Zero initialization should be done before RESET.
244 * Nothing to do here. */
246 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
247 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
248 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
249 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
253 /* Initialize hardware */
254 int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
260 if (!s5p_mfc_bitproc_buf)
264 mfc_debug(2, "MFC reset..\n");
266 ret = s5p_mfc_reset(dev);
268 mfc_err("Failed to reset MFC - timeout\n");
271 mfc_debug(2, "Done MFC reset..\n");
272 /* 1. Set DRAM base Addr */
273 s5p_mfc_init_memctrl(dev);
274 /* 2. Initialize registers of channel I/F */
275 s5p_mfc_clear_cmds(dev);
276 /* 3. Release reset signal to the RISC */
277 s5p_mfc_clean_dev_int_flags(dev);
279 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
281 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
282 mfc_debug(2, "Will now wait for completion of firmware transfer\n");
283 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
284 mfc_err("Failed to load firmware\n");
289 s5p_mfc_clean_dev_int_flags(dev);
290 /* 4. Initialize firmware */
291 ret = s5p_mfc_hw_call(dev->mfc_cmds, sys_init_cmd, dev);
293 mfc_err("Failed to send command to MFC - timeout\n");
298 mfc_debug(2, "Ok, now will write a command to init the system\n");
299 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) {
300 mfc_err("Failed to load firmware\n");
306 if (dev->int_err != 0 || dev->int_type !=
307 S5P_MFC_R2H_CMD_SYS_INIT_RET) {
309 mfc_err("Failed to init firmware - error: %d int: %d\n",
310 dev->int_err, dev->int_type);
316 ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6);
318 ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
320 mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n",
321 (ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF);
328 /* Deinitialize hardware */
329 void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
334 s5p_mfc_hw_call(dev->mfc_ops, release_dev_context_buffer, dev);
339 int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
345 s5p_mfc_clean_dev_int_flags(dev);
346 ret = s5p_mfc_hw_call(dev->mfc_cmds, sleep_cmd, dev);
348 mfc_err("Failed to send command to MFC - timeout\n");
351 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SLEEP_RET)) {
352 mfc_err("Failed to sleep\n");
357 if (dev->int_err != 0 || dev->int_type !=
358 S5P_MFC_R2H_CMD_SLEEP_RET) {
360 mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
368 int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
374 mfc_debug(2, "MFC reset..\n");
376 ret = s5p_mfc_reset(dev);
378 mfc_err("Failed to reset MFC - timeout\n");
381 mfc_debug(2, "Done MFC reset..\n");
382 /* 1. Set DRAM base Addr */
383 s5p_mfc_init_memctrl(dev);
384 /* 2. Initialize registers of channel I/F */
385 s5p_mfc_clear_cmds(dev);
386 s5p_mfc_clean_dev_int_flags(dev);
387 /* 3. Initialize firmware */
388 ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
390 mfc_err("Failed to send command to MFC - timeout\n");
393 /* 4. Release reset signal to the RISC */
395 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
397 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
398 mfc_debug(2, "Ok, now will write a command to wakeup the system\n");
399 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
400 mfc_err("Failed to load firmware\n");
405 if (dev->int_err != 0 || dev->int_type !=
406 S5P_MFC_R2H_CMD_WAKEUP_RET) {
408 mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,