2 * vsp1_dl.h -- R-Car VSP1 Display List
4 * Copyright (C) 2015 Renesas Corporation
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/gfp.h>
17 #include <linux/slab.h>
21 #include "vsp1_pipe.h"
26 * - Display-related interrupts (can be used for vblank evasion ?)
27 * - Display-list enable
28 * - Header-less for WPF0
32 #define VSP1_DL_BODY_SIZE (2 * 4 * 256)
33 #define VSP1_DL_NUM_LISTS 3
35 struct vsp1_dl_entry {
38 } __attribute__((__packed__));
46 struct vsp1_dl_entry *body;
51 * struct vsp1_dl - Display List manager
52 * @vsp1: the VSP1 device
53 * @lock: protects the active, queued and pending lists
54 * @lists.all: array of all allocate display lists
55 * @lists.active: list currently being processed (loaded) by hardware
56 * @lists.queued: list queued to the hardware (written to the DL registers)
57 * @lists.pending: list waiting to be queued to the hardware
58 * @lists.write: list being written to by software
61 struct vsp1_device *vsp1;
70 struct vsp1_dl_list all[VSP1_DL_NUM_LISTS];
72 struct vsp1_dl_list *active;
73 struct vsp1_dl_list *queued;
74 struct vsp1_dl_list *pending;
75 struct vsp1_dl_list *write;
79 /* -----------------------------------------------------------------------------
80 * Display List Transaction Management
83 static void vsp1_dl_free_list(struct vsp1_dl_list *list)
91 void vsp1_dl_reset(struct vsp1_dl *dl)
95 dl->lists.active = NULL;
96 dl->lists.queued = NULL;
97 dl->lists.pending = NULL;
98 dl->lists.write = NULL;
100 for (i = 0; i < ARRAY_SIZE(dl->lists.all); ++i)
101 dl->lists.all[i].in_use = false;
104 void vsp1_dl_begin(struct vsp1_dl *dl)
106 struct vsp1_dl_list *list = NULL;
110 spin_lock_irqsave(&dl->lock, flags);
112 for (i = 0; i < ARRAY_SIZE(dl->lists.all); ++i) {
113 if (!dl->lists.all[i].in_use) {
114 list = &dl->lists.all[i];
120 list = dl->lists.pending;
121 dl->lists.pending = NULL;
124 spin_unlock_irqrestore(&dl->lock, flags);
126 dl->lists.write = list;
132 void vsp1_dl_add(struct vsp1_entity *e, u32 reg, u32 data)
134 struct vsp1_pipeline *pipe = to_vsp1_pipeline(&e->subdev.entity);
135 struct vsp1_dl *dl = pipe->dl;
136 struct vsp1_dl_list *list = dl->lists.write;
138 list->body[list->reg_count].addr = reg;
139 list->body[list->reg_count].data = data;
143 void vsp1_dl_commit(struct vsp1_dl *dl)
145 struct vsp1_device *vsp1 = dl->vsp1;
146 struct vsp1_dl_list *list;
150 list = dl->lists.write;
151 dl->lists.write = NULL;
153 spin_lock_irqsave(&dl->lock, flags);
155 /* Once the UPD bit has been set the hardware can start processing the
156 * display list at any time and we can't touch the address and size
157 * registers. In that case mark the update as pending, it will be
158 * queued up to the hardware by the frame end interrupt handler.
160 update = !!(vsp1_read(vsp1, VI6_DL_BODY_SIZE) & VI6_DL_BODY_SIZE_UPD);
162 vsp1_dl_free_list(dl->lists.pending);
163 dl->lists.pending = list;
167 /* Program the hardware with the display list body address and size.
168 * The UPD bit will be cleared by the device when the display list is
171 vsp1_write(vsp1, VI6_DL_HDR_ADDR(0), list->dma);
172 vsp1_write(vsp1, VI6_DL_BODY_SIZE, VI6_DL_BODY_SIZE_UPD |
173 (list->reg_count * 8));
175 vsp1_dl_free_list(dl->lists.queued);
176 dl->lists.queued = list;
179 spin_unlock_irqrestore(&dl->lock, flags);
182 /* -----------------------------------------------------------------------------
186 void vsp1_dl_irq_display_start(struct vsp1_dl *dl)
188 spin_lock(&dl->lock);
190 /* The display start interrupt signals the end of the display list
191 * processing by the device. The active display list, if any, won't be
192 * accessed anymore and can be reused.
194 if (dl->lists.active) {
195 vsp1_dl_free_list(dl->lists.active);
196 dl->lists.active = NULL;
199 spin_unlock(&dl->lock);
202 void vsp1_dl_irq_frame_end(struct vsp1_dl *dl)
204 struct vsp1_device *vsp1 = dl->vsp1;
206 spin_lock(&dl->lock);
208 /* The UPD bit set indicates that the commit operation raced with the
209 * interrupt and occurred after the frame end event and UPD clear but
210 * before interrupt processing. The hardware hasn't taken the update
211 * into account yet, we'll thus skip one frame and retry.
213 if (vsp1_read(vsp1, VI6_DL_BODY_SIZE) & VI6_DL_BODY_SIZE_UPD)
216 /* The device starts processing the queued display list right after the
217 * frame end interrupt. The display list thus becomes active.
219 if (dl->lists.queued) {
220 WARN_ON(dl->lists.active);
221 dl->lists.active = dl->lists.queued;
222 dl->lists.queued = NULL;
225 /* Now that the UPD bit has been cleared we can queue the next display
226 * list to the hardware if one has been prepared.
228 if (dl->lists.pending) {
229 struct vsp1_dl_list *list = dl->lists.pending;
231 vsp1_write(vsp1, VI6_DL_HDR_ADDR(0), list->dma);
232 vsp1_write(vsp1, VI6_DL_BODY_SIZE, VI6_DL_BODY_SIZE_UPD |
233 (list->reg_count * 8));
235 dl->lists.queued = list;
236 dl->lists.pending = NULL;
240 spin_unlock(&dl->lock);
243 /* -----------------------------------------------------------------------------
247 void vsp1_dl_setup(struct vsp1_device *vsp1)
249 u32 ctrl = (256 << VI6_DL_CTRL_AR_WAIT_SHIFT)
250 | VI6_DL_CTRL_DC2 | VI6_DL_CTRL_DC1 | VI6_DL_CTRL_DC0
253 /* The DRM pipeline operates with header-less display lists in
254 * Continuous Frame Mode.
257 ctrl |= VI6_DL_CTRL_CFM0 | VI6_DL_CTRL_NH0;
259 vsp1_write(vsp1, VI6_DL_CTRL, ctrl);
260 vsp1_write(vsp1, VI6_DL_SWAP, VI6_DL_SWAP_LWS);
263 /* -----------------------------------------------------------------------------
264 * Initialization and Cleanup
267 struct vsp1_dl *vsp1_dl_create(struct vsp1_device *vsp1)
272 dl = kzalloc(sizeof(*dl), GFP_KERNEL);
276 spin_lock_init(&dl->lock);
279 dl->size = VSP1_DL_BODY_SIZE * ARRAY_SIZE(dl->lists.all);
281 dl->mem = dma_alloc_wc(vsp1->dev, dl->size, &dl->dma,
288 for (i = 0; i < ARRAY_SIZE(dl->lists.all); ++i) {
289 struct vsp1_dl_list *list = &dl->lists.all[i];
291 list->size = VSP1_DL_BODY_SIZE;
293 list->in_use = false;
294 list->dma = dl->dma + VSP1_DL_BODY_SIZE * i;
295 list->body = dl->mem + VSP1_DL_BODY_SIZE * i;
301 void vsp1_dl_destroy(struct vsp1_dl *dl)
303 dma_free_wc(dl->vsp1->dev, dl->size, dl->mem, dl->dma);