2 * Elonics E4000 silicon tuner driver
4 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "e4000_priv.h"
22 #include <linux/math64.h>
24 /* write multiple registers */
25 static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
29 struct i2c_msg msg[1] = {
31 .addr = priv->cfg->i2c_addr,
39 memcpy(&buf[1], val, len);
41 ret = i2c_transfer(priv->i2c, msg, 1);
45 dev_warn(&priv->i2c->dev,
46 "%s: i2c wr failed=%d reg=%02x len=%d\n",
47 KBUILD_MODNAME, ret, reg, len);
53 /* read multiple registers */
54 static int e4000_rd_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
58 struct i2c_msg msg[2] = {
60 .addr = priv->cfg->i2c_addr,
65 .addr = priv->cfg->i2c_addr,
72 ret = i2c_transfer(priv->i2c, msg, 2);
74 memcpy(val, buf, len);
77 dev_warn(&priv->i2c->dev,
78 "%s: i2c rd failed=%d reg=%02x len=%d\n",
79 KBUILD_MODNAME, ret, reg, len);
86 /* write single register */
87 static int e4000_wr_reg(struct e4000_priv *priv, u8 reg, u8 val)
89 return e4000_wr_regs(priv, reg, &val, 1);
92 /* read single register */
93 static int e4000_rd_reg(struct e4000_priv *priv, u8 reg, u8 *val)
95 return e4000_rd_regs(priv, reg, val, 1);
98 static int e4000_init(struct dvb_frontend *fe)
100 struct e4000_priv *priv = fe->tuner_priv;
103 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
105 if (fe->ops.i2c_gate_ctrl)
106 fe->ops.i2c_gate_ctrl(fe, 1);
108 /* dummy I2C to ensure I2C wakes up */
109 ret = e4000_wr_reg(priv, 0x02, 0x40);
112 ret = e4000_wr_reg(priv, 0x00, 0x01);
116 /* disable output clock */
117 ret = e4000_wr_reg(priv, 0x06, 0x00);
121 ret = e4000_wr_reg(priv, 0x7a, 0x96);
125 /* configure gains */
126 ret = e4000_wr_regs(priv, 0x7e, "\x01\xfe", 2);
130 ret = e4000_wr_reg(priv, 0x82, 0x00);
134 ret = e4000_wr_reg(priv, 0x24, 0x05);
138 ret = e4000_wr_regs(priv, 0x87, "\x20\x01", 2);
142 ret = e4000_wr_regs(priv, 0x9f, "\x7f\x07", 2);
146 /* DC offset control */
147 ret = e4000_wr_reg(priv, 0x2d, 0x1f);
151 ret = e4000_wr_regs(priv, 0x70, "\x01\x01", 2);
156 ret = e4000_wr_reg(priv, 0x1a, 0x17);
160 ret = e4000_wr_reg(priv, 0x1f, 0x1a);
164 if (fe->ops.i2c_gate_ctrl)
165 fe->ops.i2c_gate_ctrl(fe, 0);
169 if (fe->ops.i2c_gate_ctrl)
170 fe->ops.i2c_gate_ctrl(fe, 0);
172 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
176 static int e4000_sleep(struct dvb_frontend *fe)
178 struct e4000_priv *priv = fe->tuner_priv;
181 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
183 if (fe->ops.i2c_gate_ctrl)
184 fe->ops.i2c_gate_ctrl(fe, 1);
186 ret = e4000_wr_reg(priv, 0x00, 0x00);
190 if (fe->ops.i2c_gate_ctrl)
191 fe->ops.i2c_gate_ctrl(fe, 0);
195 if (fe->ops.i2c_gate_ctrl)
196 fe->ops.i2c_gate_ctrl(fe, 0);
198 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
202 static int e4000_set_params(struct dvb_frontend *fe)
204 struct e4000_priv *priv = fe->tuner_priv;
205 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
206 int ret, i, sigma_delta;
208 u8 buf[5], i_data[4], q_data[4];
210 dev_dbg(&priv->i2c->dev,
211 "%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
212 __func__, c->delivery_system, c->frequency,
215 if (fe->ops.i2c_gate_ctrl)
216 fe->ops.i2c_gate_ctrl(fe, 1);
218 /* gain control manual */
219 ret = e4000_wr_reg(priv, 0x1a, 0x00);
224 for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
225 if (c->frequency <= e4000_pll_lut[i].freq)
229 if (i == ARRAY_SIZE(e4000_pll_lut))
233 * Note: Currently f_vco overflows when c->frequency is 1 073 741 824 Hz
236 f_vco = c->frequency * e4000_pll_lut[i].mul;
237 sigma_delta = div_u64(0x10000ULL * (f_vco % priv->cfg->clock), priv->cfg->clock);
238 buf[0] = f_vco / priv->cfg->clock;
239 buf[1] = (sigma_delta >> 0) & 0xff;
240 buf[2] = (sigma_delta >> 8) & 0xff;
242 buf[4] = e4000_pll_lut[i].div;
244 dev_dbg(&priv->i2c->dev, "%s: f_vco=%u pll div=%d sigma_delta=%04x\n",
245 __func__, f_vco, buf[0], sigma_delta);
247 ret = e4000_wr_regs(priv, 0x09, buf, 5);
251 /* LNA filter (RF filter) */
252 for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) {
253 if (c->frequency <= e400_lna_filter_lut[i].freq)
257 if (i == ARRAY_SIZE(e400_lna_filter_lut))
260 ret = e4000_wr_reg(priv, 0x10, e400_lna_filter_lut[i].val);
265 for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) {
266 if (c->bandwidth_hz <= e4000_if_filter_lut[i].freq)
270 if (i == ARRAY_SIZE(e4000_if_filter_lut))
273 buf[0] = e4000_if_filter_lut[i].reg11_val;
274 buf[1] = e4000_if_filter_lut[i].reg12_val;
276 ret = e4000_wr_regs(priv, 0x11, buf, 2);
281 for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) {
282 if (c->frequency <= e4000_band_lut[i].freq)
286 if (i == ARRAY_SIZE(e4000_band_lut))
289 ret = e4000_wr_reg(priv, 0x07, e4000_band_lut[i].reg07_val);
293 ret = e4000_wr_reg(priv, 0x78, e4000_band_lut[i].reg78_val);
298 for (i = 0; i < 4; i++) {
300 ret = e4000_wr_regs(priv, 0x15, "\x00\x7e\x24", 3);
302 ret = e4000_wr_regs(priv, 0x15, "\x00\x7f", 2);
304 ret = e4000_wr_regs(priv, 0x15, "\x01", 1);
306 ret = e4000_wr_regs(priv, 0x16, "\x7e", 1);
311 ret = e4000_wr_reg(priv, 0x29, 0x01);
315 ret = e4000_rd_regs(priv, 0x2a, buf, 3);
319 i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f);
320 q_data[i] = (((buf[2] >> 4) & 0x3) << 6) | (buf[1] & 0x3f);
323 swap(q_data[2], q_data[3]);
324 swap(i_data[2], i_data[3]);
326 ret = e4000_wr_regs(priv, 0x50, q_data, 4);
330 ret = e4000_wr_regs(priv, 0x60, i_data, 4);
334 /* gain control auto */
335 ret = e4000_wr_reg(priv, 0x1a, 0x17);
339 if (fe->ops.i2c_gate_ctrl)
340 fe->ops.i2c_gate_ctrl(fe, 0);
344 if (fe->ops.i2c_gate_ctrl)
345 fe->ops.i2c_gate_ctrl(fe, 0);
347 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
351 static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
353 struct e4000_priv *priv = fe->tuner_priv;
355 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
357 *frequency = 0; /* Zero-IF */
362 static int e4000_release(struct dvb_frontend *fe)
364 struct e4000_priv *priv = fe->tuner_priv;
366 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
368 kfree(fe->tuner_priv);
373 static const struct dvb_tuner_ops e4000_tuner_ops = {
375 .name = "Elonics E4000",
376 .frequency_min = 174000000,
377 .frequency_max = 862000000,
380 .release = e4000_release,
383 .sleep = e4000_sleep,
384 .set_params = e4000_set_params,
386 .get_if_frequency = e4000_get_if_frequency,
389 struct dvb_frontend *e4000_attach(struct dvb_frontend *fe,
390 struct i2c_adapter *i2c, const struct e4000_config *cfg)
392 struct e4000_priv *priv;
396 if (fe->ops.i2c_gate_ctrl)
397 fe->ops.i2c_gate_ctrl(fe, 1);
399 priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL);
402 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
409 /* check if the tuner is there */
410 ret = e4000_rd_reg(priv, 0x02, &chip_id);
414 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
419 /* put sleep as chip seems to be in normal mode by default */
420 ret = e4000_wr_reg(priv, 0x00, 0x00);
424 dev_info(&priv->i2c->dev,
425 "%s: Elonics E4000 successfully identified\n",
428 fe->tuner_priv = priv;
429 memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops,
430 sizeof(struct dvb_tuner_ops));
432 if (fe->ops.i2c_gate_ctrl)
433 fe->ops.i2c_gate_ctrl(fe, 0);
437 if (fe->ops.i2c_gate_ctrl)
438 fe->ops.i2c_gate_ctrl(fe, 0);
440 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
444 EXPORT_SYMBOL(e4000_attach);
446 MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver");
447 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
448 MODULE_LICENSE("GPL");