2 * Elonics E4000 silicon tuner driver
4 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "e4000_priv.h"
23 /* write multiple registers */
24 static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
28 struct i2c_msg msg[1] = {
30 .addr = priv->cfg->i2c_addr,
38 memcpy(&buf[1], val, len);
40 ret = i2c_transfer(priv->i2c, msg, 1);
44 dev_warn(&priv->i2c->dev,
45 "%s: i2c wr failed=%d reg=%02x len=%d\n",
46 KBUILD_MODNAME, ret, reg, len);
52 /* read multiple registers */
53 static int e4000_rd_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
57 struct i2c_msg msg[2] = {
59 .addr = priv->cfg->i2c_addr,
64 .addr = priv->cfg->i2c_addr,
71 ret = i2c_transfer(priv->i2c, msg, 2);
73 memcpy(val, buf, len);
76 dev_warn(&priv->i2c->dev,
77 "%s: i2c rd failed=%d reg=%02x len=%d\n",
78 KBUILD_MODNAME, ret, reg, len);
85 /* write single register */
86 static int e4000_wr_reg(struct e4000_priv *priv, u8 reg, u8 val)
88 return e4000_wr_regs(priv, reg, &val, 1);
91 /* read single register */
92 static int e4000_rd_reg(struct e4000_priv *priv, u8 reg, u8 *val)
94 return e4000_rd_regs(priv, reg, val, 1);
97 static int e4000_init(struct dvb_frontend *fe)
99 struct e4000_priv *priv = fe->tuner_priv;
102 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
104 if (fe->ops.i2c_gate_ctrl)
105 fe->ops.i2c_gate_ctrl(fe, 1);
107 /* dummy I2C to ensure I2C wakes up */
108 ret = e4000_wr_reg(priv, 0x02, 0x40);
111 ret = e4000_wr_reg(priv, 0x00, 0x01);
115 /* disable output clock */
116 ret = e4000_wr_reg(priv, 0x06, 0x00);
120 ret = e4000_wr_reg(priv, 0x7a, 0x96);
124 /* configure gains */
125 ret = e4000_wr_regs(priv, 0x7e, "\x01\xfe", 2);
129 ret = e4000_wr_reg(priv, 0x82, 0x00);
133 ret = e4000_wr_reg(priv, 0x24, 0x05);
137 ret = e4000_wr_regs(priv, 0x87, "\x20\x01", 2);
141 ret = e4000_wr_regs(priv, 0x9f, "\x7f\x07", 2);
145 /* DC offset control */
146 ret = e4000_wr_reg(priv, 0x2d, 0x1f);
150 ret = e4000_wr_regs(priv, 0x70, "\x01\x01", 2);
155 ret = e4000_wr_reg(priv, 0x1a, 0x17);
159 ret = e4000_wr_reg(priv, 0x1f, 0x1a);
163 if (fe->ops.i2c_gate_ctrl)
164 fe->ops.i2c_gate_ctrl(fe, 0);
168 if (fe->ops.i2c_gate_ctrl)
169 fe->ops.i2c_gate_ctrl(fe, 0);
171 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
175 static int e4000_sleep(struct dvb_frontend *fe)
177 struct e4000_priv *priv = fe->tuner_priv;
180 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
182 if (fe->ops.i2c_gate_ctrl)
183 fe->ops.i2c_gate_ctrl(fe, 1);
185 ret = e4000_wr_reg(priv, 0x00, 0x00);
189 if (fe->ops.i2c_gate_ctrl)
190 fe->ops.i2c_gate_ctrl(fe, 0);
194 if (fe->ops.i2c_gate_ctrl)
195 fe->ops.i2c_gate_ctrl(fe, 0);
197 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
201 static int e4000_set_params(struct dvb_frontend *fe)
203 struct e4000_priv *priv = fe->tuner_priv;
204 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
205 int ret, i, sigma_delta;
207 u8 buf[5], i_data[4], q_data[4];
209 dev_dbg(&priv->i2c->dev,
210 "%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
211 __func__, c->delivery_system, c->frequency,
214 if (fe->ops.i2c_gate_ctrl)
215 fe->ops.i2c_gate_ctrl(fe, 1);
217 /* gain control manual */
218 ret = e4000_wr_reg(priv, 0x1a, 0x00);
223 for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
224 if (c->frequency <= e4000_pll_lut[i].freq)
228 if (i == ARRAY_SIZE(e4000_pll_lut))
232 * Note: Currently f_vco overflows when c->frequency is 1 073 741 824 Hz
235 f_vco = c->frequency * e4000_pll_lut[i].mul;
236 sigma_delta = 0x10000UL * (f_vco % priv->cfg->clock) / priv->cfg->clock;
237 buf[0] = f_vco / priv->cfg->clock;
238 buf[1] = (sigma_delta >> 0) & 0xff;
239 buf[2] = (sigma_delta >> 8) & 0xff;
241 buf[4] = e4000_pll_lut[i].div;
243 dev_dbg(&priv->i2c->dev, "%s: f_vco=%u pll div=%d sigma_delta=%04x\n",
244 __func__, f_vco, buf[0], sigma_delta);
246 ret = e4000_wr_regs(priv, 0x09, buf, 5);
250 /* LNA filter (RF filter) */
251 for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) {
252 if (c->frequency <= e400_lna_filter_lut[i].freq)
256 if (i == ARRAY_SIZE(e400_lna_filter_lut))
259 ret = e4000_wr_reg(priv, 0x10, e400_lna_filter_lut[i].val);
264 for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) {
265 if (c->bandwidth_hz <= e4000_if_filter_lut[i].freq)
269 if (i == ARRAY_SIZE(e4000_if_filter_lut))
272 buf[0] = e4000_if_filter_lut[i].reg11_val;
273 buf[1] = e4000_if_filter_lut[i].reg12_val;
275 ret = e4000_wr_regs(priv, 0x11, buf, 2);
280 for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) {
281 if (c->frequency <= e4000_band_lut[i].freq)
285 if (i == ARRAY_SIZE(e4000_band_lut))
288 ret = e4000_wr_reg(priv, 0x07, e4000_band_lut[i].reg07_val);
292 ret = e4000_wr_reg(priv, 0x78, e4000_band_lut[i].reg78_val);
297 for (i = 0; i < 4; i++) {
299 ret = e4000_wr_regs(priv, 0x15, "\x00\x7e\x24", 3);
301 ret = e4000_wr_regs(priv, 0x15, "\x00\x7f", 2);
303 ret = e4000_wr_regs(priv, 0x15, "\x01", 1);
305 ret = e4000_wr_regs(priv, 0x16, "\x7e", 1);
310 ret = e4000_wr_reg(priv, 0x29, 0x01);
314 ret = e4000_rd_regs(priv, 0x2a, buf, 3);
318 i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f);
319 q_data[i] = (((buf[2] >> 4) & 0x3) << 6) | (buf[1] & 0x3f);
322 swap(q_data[2], q_data[3]);
323 swap(i_data[2], i_data[3]);
325 ret = e4000_wr_regs(priv, 0x50, q_data, 4);
329 ret = e4000_wr_regs(priv, 0x60, i_data, 4);
333 /* gain control auto */
334 ret = e4000_wr_reg(priv, 0x1a, 0x17);
338 if (fe->ops.i2c_gate_ctrl)
339 fe->ops.i2c_gate_ctrl(fe, 0);
343 if (fe->ops.i2c_gate_ctrl)
344 fe->ops.i2c_gate_ctrl(fe, 0);
346 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
350 static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
352 struct e4000_priv *priv = fe->tuner_priv;
354 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
356 *frequency = 0; /* Zero-IF */
361 static int e4000_release(struct dvb_frontend *fe)
363 struct e4000_priv *priv = fe->tuner_priv;
365 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
367 kfree(fe->tuner_priv);
372 static const struct dvb_tuner_ops e4000_tuner_ops = {
374 .name = "Elonics E4000",
375 .frequency_min = 174000000,
376 .frequency_max = 862000000,
379 .release = e4000_release,
382 .sleep = e4000_sleep,
383 .set_params = e4000_set_params,
385 .get_if_frequency = e4000_get_if_frequency,
388 struct dvb_frontend *e4000_attach(struct dvb_frontend *fe,
389 struct i2c_adapter *i2c, const struct e4000_config *cfg)
391 struct e4000_priv *priv;
395 if (fe->ops.i2c_gate_ctrl)
396 fe->ops.i2c_gate_ctrl(fe, 1);
398 priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL);
401 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
408 /* check if the tuner is there */
409 ret = e4000_rd_reg(priv, 0x02, &chip_id);
413 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
418 /* put sleep as chip seems to be in normal mode by default */
419 ret = e4000_wr_reg(priv, 0x00, 0x00);
423 dev_info(&priv->i2c->dev,
424 "%s: Elonics E4000 successfully identified\n",
427 fe->tuner_priv = priv;
428 memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops,
429 sizeof(struct dvb_tuner_ops));
431 if (fe->ops.i2c_gate_ctrl)
432 fe->ops.i2c_gate_ctrl(fe, 0);
436 if (fe->ops.i2c_gate_ctrl)
437 fe->ops.i2c_gate_ctrl(fe, 0);
439 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
443 EXPORT_SYMBOL(e4000_attach);
445 MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver");
446 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
447 MODULE_LICENSE("GPL");