2 * FCI FC2580 silicon tuner driver
4 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "fc2580_priv.h"
25 * I2C write and read works only for one single register. Multiple registers
26 * could not be accessed using normal register address auto-increment.
27 * There could be (very likely) register to change that behavior....
29 * Due to that limitation functions:
32 * could not be used for accessing more than one register at once.
35 * Currently it blind writes bunch of static registers from the
36 * fc2580_freq_regs_lut[] when fc2580_set_params() is called. Add some
37 * logic to reduce unneeded register writes.
40 /* write multiple registers */
41 static int fc2580_wr_regs(struct fc2580_priv *priv, u8 reg, u8 *val, int len)
45 struct i2c_msg msg[1] = {
47 .addr = priv->cfg->i2c_addr,
55 memcpy(&buf[1], val, len);
57 ret = i2c_transfer(priv->i2c, msg, 1);
61 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \
62 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
68 /* read multiple registers */
69 static int fc2580_rd_regs(struct fc2580_priv *priv, u8 reg, u8 *val, int len)
73 struct i2c_msg msg[2] = {
75 .addr = priv->cfg->i2c_addr,
80 .addr = priv->cfg->i2c_addr,
87 ret = i2c_transfer(priv->i2c, msg, 2);
89 memcpy(val, buf, len);
92 dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \
93 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
100 /* write single register */
101 static int fc2580_wr_reg(struct fc2580_priv *priv, u8 reg, u8 val)
103 return fc2580_wr_regs(priv, reg, &val, 1);
106 /* read single register */
107 static int fc2580_rd_reg(struct fc2580_priv *priv, u8 reg, u8 *val)
109 return fc2580_rd_regs(priv, reg, val, 1);
112 /* write single register conditionally only when value differs from 0xff
113 * XXX: This is special routine meant only for writing fc2580_freq_regs_lut[]
114 * values. Do not use for the other purposes. */
115 static int fc2580_wr_reg_ff(struct fc2580_priv *priv, u8 reg, u8 val)
120 return fc2580_wr_regs(priv, reg, &val, 1);
123 static int fc2580_set_params(struct dvb_frontend *fe)
125 struct fc2580_priv *priv = fe->tuner_priv;
126 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
128 unsigned int r_val, n_val, k_val, k_val_reg, f_ref;
133 * Fractional-N synthesizer/PLL.
134 * Most likely all those PLL calculations are not correct. I am not
135 * sure, but it looks like it is divider based Fractional-N synthesizer.
136 * There is divider for reference clock too?
137 * Anyhow, synthesizer calculation results seems to be quite correct.
140 dev_dbg(&priv->i2c->dev, "%s: delivery_system=%d frequency=%d " \
141 "bandwidth_hz=%d\n", __func__,
142 c->delivery_system, c->frequency, c->bandwidth_hz);
144 if (fe->ops.i2c_gate_ctrl)
145 fe->ops.i2c_gate_ctrl(fe, 1);
148 for (i = 0; i < ARRAY_SIZE(fc2580_pll_lut); i++) {
149 if (c->frequency <= fc2580_pll_lut[i].freq)
153 if (i == ARRAY_SIZE(fc2580_pll_lut))
156 f_vco = c->frequency;
157 f_vco *= fc2580_pll_lut[i].div;
159 if (f_vco >= 2600000000UL)
160 tmp_val = 0x0e | fc2580_pll_lut[i].band;
162 tmp_val = 0x06 | fc2580_pll_lut[i].band;
164 ret = fc2580_wr_reg(priv, 0x02, tmp_val);
168 if (f_vco >= 2UL * 76 * priv->cfg->clock) {
171 } else if (f_vco >= 1UL * 76 * priv->cfg->clock) {
179 f_ref = 2UL * priv->cfg->clock / r_val;
180 n_val = div_u64_rem(f_vco, f_ref, &k_val);
181 k_val_reg = 1UL * k_val * (1 << 20) / f_ref;
183 ret = fc2580_wr_reg(priv, 0x18, r18_val | ((k_val_reg >> 16) & 0xff));
187 ret = fc2580_wr_reg(priv, 0x1a, (k_val_reg >> 8) & 0xff);
191 ret = fc2580_wr_reg(priv, 0x1b, (k_val_reg >> 0) & 0xff);
195 ret = fc2580_wr_reg(priv, 0x1c, n_val);
199 if (priv->cfg->clock >= 28000000) {
200 ret = fc2580_wr_reg(priv, 0x4b, 0x22);
205 if (fc2580_pll_lut[i].band == 0x00) {
206 if (c->frequency <= 794000000)
211 ret = fc2580_wr_reg(priv, 0x2d, tmp_val);
217 for (i = 0; i < ARRAY_SIZE(fc2580_freq_regs_lut); i++) {
218 if (c->frequency <= fc2580_freq_regs_lut[i].freq)
222 if (i == ARRAY_SIZE(fc2580_freq_regs_lut))
225 ret = fc2580_wr_reg_ff(priv, 0x25, fc2580_freq_regs_lut[i].r25_val);
229 ret = fc2580_wr_reg_ff(priv, 0x27, fc2580_freq_regs_lut[i].r27_val);
233 ret = fc2580_wr_reg_ff(priv, 0x28, fc2580_freq_regs_lut[i].r28_val);
237 ret = fc2580_wr_reg_ff(priv, 0x29, fc2580_freq_regs_lut[i].r29_val);
241 ret = fc2580_wr_reg_ff(priv, 0x2b, fc2580_freq_regs_lut[i].r2b_val);
245 ret = fc2580_wr_reg_ff(priv, 0x2c, fc2580_freq_regs_lut[i].r2c_val);
249 ret = fc2580_wr_reg_ff(priv, 0x2d, fc2580_freq_regs_lut[i].r2d_val);
253 ret = fc2580_wr_reg_ff(priv, 0x30, fc2580_freq_regs_lut[i].r30_val);
257 ret = fc2580_wr_reg_ff(priv, 0x44, fc2580_freq_regs_lut[i].r44_val);
261 ret = fc2580_wr_reg_ff(priv, 0x50, fc2580_freq_regs_lut[i].r50_val);
265 ret = fc2580_wr_reg_ff(priv, 0x53, fc2580_freq_regs_lut[i].r53_val);
269 ret = fc2580_wr_reg_ff(priv, 0x5f, fc2580_freq_regs_lut[i].r5f_val);
273 ret = fc2580_wr_reg_ff(priv, 0x61, fc2580_freq_regs_lut[i].r61_val);
277 ret = fc2580_wr_reg_ff(priv, 0x62, fc2580_freq_regs_lut[i].r62_val);
281 ret = fc2580_wr_reg_ff(priv, 0x63, fc2580_freq_regs_lut[i].r63_val);
285 ret = fc2580_wr_reg_ff(priv, 0x67, fc2580_freq_regs_lut[i].r67_val);
289 ret = fc2580_wr_reg_ff(priv, 0x68, fc2580_freq_regs_lut[i].r68_val);
293 ret = fc2580_wr_reg_ff(priv, 0x69, fc2580_freq_regs_lut[i].r69_val);
297 ret = fc2580_wr_reg_ff(priv, 0x6a, fc2580_freq_regs_lut[i].r6a_val);
301 ret = fc2580_wr_reg_ff(priv, 0x6b, fc2580_freq_regs_lut[i].r6b_val);
305 ret = fc2580_wr_reg_ff(priv, 0x6c, fc2580_freq_regs_lut[i].r6c_val);
309 ret = fc2580_wr_reg_ff(priv, 0x6d, fc2580_freq_regs_lut[i].r6d_val);
313 ret = fc2580_wr_reg_ff(priv, 0x6e, fc2580_freq_regs_lut[i].r6e_val);
317 ret = fc2580_wr_reg_ff(priv, 0x6f, fc2580_freq_regs_lut[i].r6f_val);
322 for (i = 0; i < ARRAY_SIZE(fc2580_if_filter_lut); i++) {
323 if (c->bandwidth_hz <= fc2580_if_filter_lut[i].freq)
327 if (i == ARRAY_SIZE(fc2580_if_filter_lut))
330 ret = fc2580_wr_reg(priv, 0x36, fc2580_if_filter_lut[i].r36_val);
334 ret = fc2580_wr_reg(priv, 0x37, 1UL * priv->cfg->clock * \
335 fc2580_if_filter_lut[i].mul / 1000000000);
339 ret = fc2580_wr_reg(priv, 0x39, fc2580_if_filter_lut[i].r39_val);
344 ret = fc2580_wr_reg(priv, 0x2e, 0x09);
348 for (i = 0; i < 5; i++) {
349 ret = fc2580_rd_reg(priv, 0x2f, &tmp_val);
353 /* done when [7:6] are set */
354 if ((tmp_val & 0xc0) == 0xc0)
357 ret = fc2580_wr_reg(priv, 0x2e, 0x01);
361 ret = fc2580_wr_reg(priv, 0x2e, 0x09);
365 usleep_range(5000, 25000);
368 dev_dbg(&priv->i2c->dev, "%s: loop=%i\n", __func__, i);
370 ret = fc2580_wr_reg(priv, 0x2e, 0x01);
374 if (fe->ops.i2c_gate_ctrl)
375 fe->ops.i2c_gate_ctrl(fe, 0);
379 if (fe->ops.i2c_gate_ctrl)
380 fe->ops.i2c_gate_ctrl(fe, 0);
382 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
386 static int fc2580_init(struct dvb_frontend *fe)
388 struct fc2580_priv *priv = fe->tuner_priv;
391 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
393 if (fe->ops.i2c_gate_ctrl)
394 fe->ops.i2c_gate_ctrl(fe, 1);
396 for (i = 0; i < ARRAY_SIZE(fc2580_init_reg_vals); i++) {
397 ret = fc2580_wr_reg(priv, fc2580_init_reg_vals[i].reg,
398 fc2580_init_reg_vals[i].val);
403 if (fe->ops.i2c_gate_ctrl)
404 fe->ops.i2c_gate_ctrl(fe, 0);
408 if (fe->ops.i2c_gate_ctrl)
409 fe->ops.i2c_gate_ctrl(fe, 0);
411 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
415 static int fc2580_sleep(struct dvb_frontend *fe)
417 struct fc2580_priv *priv = fe->tuner_priv;
420 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
422 if (fe->ops.i2c_gate_ctrl)
423 fe->ops.i2c_gate_ctrl(fe, 1);
425 ret = fc2580_wr_reg(priv, 0x02, 0x0a);
429 if (fe->ops.i2c_gate_ctrl)
430 fe->ops.i2c_gate_ctrl(fe, 0);
434 if (fe->ops.i2c_gate_ctrl)
435 fe->ops.i2c_gate_ctrl(fe, 0);
437 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
441 static int fc2580_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
443 struct fc2580_priv *priv = fe->tuner_priv;
445 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
447 *frequency = 0; /* Zero-IF */
452 static int fc2580_release(struct dvb_frontend *fe)
454 struct fc2580_priv *priv = fe->tuner_priv;
456 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
458 kfree(fe->tuner_priv);
463 static const struct dvb_tuner_ops fc2580_tuner_ops = {
465 .name = "FCI FC2580",
466 .frequency_min = 174000000,
467 .frequency_max = 862000000,
470 .release = fc2580_release,
473 .sleep = fc2580_sleep,
474 .set_params = fc2580_set_params,
476 .get_if_frequency = fc2580_get_if_frequency,
479 struct dvb_frontend *fc2580_attach(struct dvb_frontend *fe,
480 struct i2c_adapter *i2c, const struct fc2580_config *cfg)
482 struct fc2580_priv *priv;
486 if (fe->ops.i2c_gate_ctrl)
487 fe->ops.i2c_gate_ctrl(fe, 1);
489 priv = kzalloc(sizeof(struct fc2580_priv), GFP_KERNEL);
492 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
499 /* check if the tuner is there */
500 ret = fc2580_rd_reg(priv, 0x01, &chip_id);
504 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
514 dev_info(&priv->i2c->dev,
515 "%s: FCI FC2580 successfully identified\n",
518 fe->tuner_priv = priv;
519 memcpy(&fe->ops.tuner_ops, &fc2580_tuner_ops,
520 sizeof(struct dvb_tuner_ops));
522 if (fe->ops.i2c_gate_ctrl)
523 fe->ops.i2c_gate_ctrl(fe, 0);
527 if (fe->ops.i2c_gate_ctrl)
528 fe->ops.i2c_gate_ctrl(fe, 0);
530 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
534 EXPORT_SYMBOL(fc2580_attach);
536 MODULE_DESCRIPTION("FCI FC2580 silicon tuner driver");
537 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
538 MODULE_LICENSE("GPL");