2 * Montage M88TS2022 silicon tuner driver
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * Some calculations are taken from existing TS2020 driver.
19 #include "m88ts2022_priv.h"
21 static int m88ts2022_cmd(struct m88ts2022_dev *dev, int op, int sleep, u8 reg,
22 u8 mask, u8 val, u8 *reg_val)
26 struct m88ts2022_reg_val reg_vals[] = {
33 for (i = 0; i < 2; i++) {
34 dev_dbg(&dev->client->dev,
35 "i=%d op=%02x reg=%02x mask=%02x val=%02x\n",
36 i, op, reg, mask, val);
38 for (i = 0; i < ARRAY_SIZE(reg_vals); i++) {
39 ret = regmap_write(dev->regmap, reg_vals[i].reg,
45 usleep_range(sleep * 1000, sleep * 10000);
47 ret = regmap_read(dev->regmap, reg, &utmp);
51 if ((utmp & mask) != val)
61 static int m88ts2022_set_params(struct dvb_frontend *fe)
63 struct m88ts2022_dev *dev = fe->tuner_priv;
64 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
66 unsigned int utmp, frequency_khz, frequency_offset_khz, f_3db_hz;
67 unsigned int f_ref_khz, f_vco_khz, div_ref, div_out, pll_n, gdiv28;
68 u8 buf[3], u8tmp, cap_code, lpf_gm, lpf_mxdiv, div_max, div_min;
71 dev_dbg(&dev->client->dev,
72 "frequency=%d symbol_rate=%d rolloff=%d\n",
73 c->frequency, c->symbol_rate, c->rolloff);
75 * Integer-N PLL synthesizer
76 * kHz is used for all calculations to keep calculations within 32-bit
78 f_ref_khz = DIV_ROUND_CLOSEST(dev->cfg.clock, 1000);
79 div_ref = DIV_ROUND_CLOSEST(f_ref_khz, 2000);
81 if (c->symbol_rate < 5000000)
82 frequency_offset_khz = 3000; /* 3 MHz */
84 frequency_offset_khz = 0;
86 frequency_khz = c->frequency + frequency_offset_khz;
88 if (frequency_khz < 1103000) {
98 ret = regmap_bulk_write(dev->regmap, 0x10, buf, 2);
102 f_vco_khz = frequency_khz * div_out;
103 pll_n = f_vco_khz * div_ref / f_ref_khz;
105 dev->frequency_khz = pll_n * f_ref_khz / div_ref / div_out;
108 u16tmp = pll_n - 1024;
109 else if (pll_n < 6143)
110 u16tmp = pll_n + 1024;
112 u16tmp = pll_n + 3072;
114 buf[0] = (u16tmp >> 8) & 0x3f;
115 buf[1] = (u16tmp >> 0) & 0xff;
116 buf[2] = div_ref - 8;
117 ret = regmap_bulk_write(dev->regmap, 0x01, buf, 3);
121 dev_dbg(&dev->client->dev,
122 "frequency=%u offset=%d f_vco_khz=%u pll_n=%u div_ref=%u div_out=%u\n",
123 dev->frequency_khz, dev->frequency_khz - c->frequency,
124 f_vco_khz, pll_n, div_ref, div_out);
126 ret = m88ts2022_cmd(dev, 0x10, 5, 0x15, 0x40, 0x00, NULL);
130 ret = regmap_read(dev->regmap, 0x14, &utmp);
136 ret = regmap_update_bits(dev->regmap, 0x10, 0x80, 0x80);
140 ret = regmap_write(dev->regmap, 0x11, 0x6f);
144 ret = m88ts2022_cmd(dev, 0x10, 5, 0x15, 0x40, 0x00, NULL);
149 ret = regmap_read(dev->regmap, 0x14, &utmp);
155 ret = regmap_update_bits(dev->regmap, 0x10, 0x02, 0x00);
160 ret = m88ts2022_cmd(dev, 0x08, 5, 0x3c, 0xff, 0x00, NULL);
164 ret = regmap_write(dev->regmap, 0x25, 0x00);
168 ret = regmap_write(dev->regmap, 0x27, 0x70);
172 ret = regmap_write(dev->regmap, 0x41, 0x09);
176 ret = regmap_write(dev->regmap, 0x08, 0x0b);
181 gdiv28 = DIV_ROUND_CLOSEST(f_ref_khz * 1694U, 1000000U);
183 ret = regmap_write(dev->regmap, 0x04, gdiv28);
187 ret = m88ts2022_cmd(dev, 0x04, 2, 0x26, 0xff, 0x00, &u8tmp);
191 cap_code = u8tmp & 0x3f;
193 ret = regmap_write(dev->regmap, 0x41, 0x0d);
197 ret = m88ts2022_cmd(dev, 0x04, 2, 0x26, 0xff, 0x00, &u8tmp);
202 cap_code = (cap_code + u8tmp) / 2;
203 gdiv28 = gdiv28 * 207 / (cap_code * 2 + 151);
204 div_max = gdiv28 * 135 / 100;
205 div_min = gdiv28 * 78 / 100;
206 div_max = clamp_val(div_max, 0U, 63U);
208 f_3db_hz = mult_frac(c->symbol_rate, 135, 200);
209 f_3db_hz += 2000000U + (frequency_offset_khz * 1000U);
210 f_3db_hz = clamp(f_3db_hz, 7000000U, 40000000U);
212 #define LPF_COEFF 3200U
213 lpf_gm = DIV_ROUND_CLOSEST(f_3db_hz * gdiv28, LPF_COEFF * f_ref_khz);
214 lpf_gm = clamp_val(lpf_gm, 1U, 23U);
216 lpf_mxdiv = DIV_ROUND_CLOSEST(lpf_gm * LPF_COEFF * f_ref_khz, f_3db_hz);
217 if (lpf_mxdiv < div_min)
218 lpf_mxdiv = DIV_ROUND_CLOSEST(++lpf_gm * LPF_COEFF * f_ref_khz, f_3db_hz);
219 lpf_mxdiv = clamp_val(lpf_mxdiv, 0U, div_max);
221 ret = regmap_write(dev->regmap, 0x04, lpf_mxdiv);
225 ret = regmap_write(dev->regmap, 0x06, lpf_gm);
229 ret = m88ts2022_cmd(dev, 0x04, 2, 0x26, 0xff, 0x00, &u8tmp);
233 cap_code = u8tmp & 0x3f;
235 ret = regmap_write(dev->regmap, 0x41, 0x09);
239 ret = m88ts2022_cmd(dev, 0x04, 2, 0x26, 0xff, 0x00, &u8tmp);
244 cap_code = (cap_code + u8tmp) / 2;
246 u8tmp = cap_code | 0x80;
247 ret = regmap_write(dev->regmap, 0x25, u8tmp);
251 ret = regmap_write(dev->regmap, 0x27, 0x30);
255 ret = regmap_write(dev->regmap, 0x08, 0x09);
259 ret = m88ts2022_cmd(dev, 0x01, 20, 0x21, 0xff, 0x00, NULL);
264 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
269 static int m88ts2022_init(struct dvb_frontend *fe)
271 struct m88ts2022_dev *dev = fe->tuner_priv;
274 static const struct m88ts2022_reg_val reg_vals[] = {
288 dev_dbg(&dev->client->dev, "\n");
290 ret = regmap_write(dev->regmap, 0x00, 0x01);
294 ret = regmap_write(dev->regmap, 0x00, 0x03);
298 switch (dev->cfg.clock_out) {
299 case M88TS2022_CLOCK_OUT_DISABLED:
302 case M88TS2022_CLOCK_OUT_ENABLED:
304 ret = regmap_write(dev->regmap, 0x05, dev->cfg.clock_out_div);
308 case M88TS2022_CLOCK_OUT_ENABLED_XTALOUT:
315 ret = regmap_write(dev->regmap, 0x42, u8tmp);
319 if (dev->cfg.loop_through)
324 ret = regmap_write(dev->regmap, 0x62, u8tmp);
328 for (i = 0; i < ARRAY_SIZE(reg_vals); i++) {
329 ret = regmap_write(dev->regmap, reg_vals[i].reg, reg_vals[i].val);
335 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
339 static int m88ts2022_sleep(struct dvb_frontend *fe)
341 struct m88ts2022_dev *dev = fe->tuner_priv;
344 dev_dbg(&dev->client->dev, "\n");
346 ret = regmap_write(dev->regmap, 0x00, 0x00);
351 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
355 static int m88ts2022_get_frequency(struct dvb_frontend *fe, u32 *frequency)
357 struct m88ts2022_dev *dev = fe->tuner_priv;
359 dev_dbg(&dev->client->dev, "\n");
361 *frequency = dev->frequency_khz;
365 static int m88ts2022_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
367 struct m88ts2022_dev *dev = fe->tuner_priv;
369 dev_dbg(&dev->client->dev, "\n");
371 *frequency = 0; /* Zero-IF */
375 static int m88ts2022_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
377 struct m88ts2022_dev *dev = fe->tuner_priv;
380 unsigned int utmp, gain1, gain2, gain3;
382 ret = regmap_read(dev->regmap, 0x3d, &utmp);
386 gain1 = (utmp >> 0) & 0x1f;
387 gain1 = clamp(gain1, 0U, 15U);
389 ret = regmap_read(dev->regmap, 0x21, &utmp);
393 gain2 = (utmp >> 0) & 0x1f;
394 gain2 = clamp(gain2, 2U, 16U);
396 ret = regmap_read(dev->regmap, 0x66, &utmp);
400 gain3 = (utmp >> 3) & 0x07;
401 gain3 = clamp(gain3, 0U, 6U);
403 gain = gain1 * 265 + gain2 * 338 + gain3 * 285;
405 /* scale value to 0x0000-0xffff */
406 u16tmp = (0xffff - gain);
407 u16tmp = clamp_val(u16tmp, 59000U, 61500U);
409 *strength = (u16tmp - 59000) * 0xffff / (61500 - 59000);
412 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
416 static const struct dvb_tuner_ops m88ts2022_tuner_ops = {
418 .name = "Montage M88TS2022",
419 .frequency_min = 950000,
420 .frequency_max = 2150000,
423 .init = m88ts2022_init,
424 .sleep = m88ts2022_sleep,
425 .set_params = m88ts2022_set_params,
427 .get_frequency = m88ts2022_get_frequency,
428 .get_if_frequency = m88ts2022_get_if_frequency,
429 .get_rf_strength = m88ts2022_get_rf_strength,
432 static int m88ts2022_probe(struct i2c_client *client,
433 const struct i2c_device_id *id)
435 struct m88ts2022_config *cfg = client->dev.platform_data;
436 struct dvb_frontend *fe = cfg->fe;
437 struct m88ts2022_dev *dev;
441 static const struct regmap_config regmap_config = {
446 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
449 dev_err(&client->dev, "kzalloc() failed\n");
453 memcpy(&dev->cfg, cfg, sizeof(struct m88ts2022_config));
454 dev->client = client;
455 dev->regmap = devm_regmap_init_i2c(client, ®map_config);
456 if (IS_ERR(dev->regmap)) {
457 ret = PTR_ERR(dev->regmap);
461 /* check if the tuner is there */
462 ret = regmap_read(dev->regmap, 0x00, &utmp);
466 if ((utmp & 0x03) == 0x00) {
467 ret = regmap_write(dev->regmap, 0x00, 0x01);
471 usleep_range(2000, 50000);
474 ret = regmap_write(dev->regmap, 0x00, 0x03);
478 usleep_range(2000, 50000);
480 ret = regmap_read(dev->regmap, 0x00, &utmp);
484 dev_dbg(&dev->client->dev, "chip_id=%02x\n", utmp);
495 switch (dev->cfg.clock_out) {
496 case M88TS2022_CLOCK_OUT_DISABLED:
499 case M88TS2022_CLOCK_OUT_ENABLED:
501 ret = regmap_write(dev->regmap, 0x05, dev->cfg.clock_out_div);
505 case M88TS2022_CLOCK_OUT_ENABLED_XTALOUT:
513 ret = regmap_write(dev->regmap, 0x42, u8tmp);
517 if (dev->cfg.loop_through)
522 ret = regmap_write(dev->regmap, 0x62, u8tmp);
527 ret = regmap_write(dev->regmap, 0x00, 0x00);
531 dev_info(&dev->client->dev, "Montage M88TS2022 successfully identified\n");
533 fe->tuner_priv = dev;
534 memcpy(&fe->ops.tuner_ops, &m88ts2022_tuner_ops,
535 sizeof(struct dvb_tuner_ops));
537 i2c_set_clientdata(client, dev);
540 dev_dbg(&client->dev, "failed=%d\n", ret);
545 static int m88ts2022_remove(struct i2c_client *client)
547 struct m88ts2022_dev *dev = i2c_get_clientdata(client);
548 struct dvb_frontend *fe = dev->cfg.fe;
550 dev_dbg(&client->dev, "\n");
552 memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
553 fe->tuner_priv = NULL;
559 static const struct i2c_device_id m88ts2022_id[] = {
563 MODULE_DEVICE_TABLE(i2c, m88ts2022_id);
565 static struct i2c_driver m88ts2022_driver = {
567 .owner = THIS_MODULE,
570 .probe = m88ts2022_probe,
571 .remove = m88ts2022_remove,
572 .id_table = m88ts2022_id,
575 module_i2c_driver(m88ts2022_driver);
577 MODULE_DESCRIPTION("Montage M88TS2022 silicon tuner driver");
578 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
579 MODULE_LICENSE("GPL");