drivers/media/tuners/r820t.c

   1 /*
   2  * Rafael Micro R820T driver
   3  *
   4  * Copyright (C) 2013 Mauro Carvalho Chehab <mchehab@redhat.com>
   5  *
   6  * This driver was written from scratch, based on an existing driver
   7  * that it is part of rtl-sdr git tree, released under GPLv2:
   8  *      https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
   9  *      https://github.com/n1gp/gr-baz
  10  *
  11  * From what I understood from the threads, the original driver was converted
  12  * to userspace from a Realtek tree. I couldn't find the original tree.
  13  * However, the original driver look awkward on my eyes. So, I decided to
  14  * write a new version from it from the scratch, while trying to reproduce
  15  * everything found there.
  16  *
  17  * TODO:
  18  *      After locking, the original driver seems to have some routines to
  19  *              improve reception. This was not implemented here yet.
  20  *
  21  *      RF Gain set/get is not implemented.
  22  *
  23  *    This program is free software; you can redistribute it and/or modify
  24  *    it under the terms of the GNU General Public License as published by
  25  *    the Free Software Foundation; either version 2 of the License, or
  26  *    (at your option) any later version.
  27  *
  28  *    This program is distributed in the hope that it will be useful,
  29  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  30  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  31  *    GNU General Public License for more details.
  32  *
  33  */
  34
  35 #include <linux/videodev2.h>
  36 #include <linux/mutex.h>
  37 #include <linux/slab.h>
  38 #include <linux/bitrev.h>
  39 #include <asm/div64.h>
  40
  41 #include "tuner-i2c.h"
  42 #include "r820t.h"
  43
  44 /*
  45  * FIXME: I think that there are only 32 registers, but better safe than
  46  *        sorry. After finishing the driver, we may review it.
  47  */
  48 #define REG_SHADOW_START        5
  49 #define NUM_REGS                27
  50 #define NUM_IMR                 5
  51 #define IMR_TRIAL               9
  52
  53 #define VER_NUM  49
  54
  55 static int debug;
  56 module_param(debug, int, 0644);
  57 MODULE_PARM_DESC(debug, "enable verbose debug messages");
  58
  59 static int no_imr_cal;
  60 module_param(no_imr_cal, int, 0444);
  61 MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init");
  62
  63
  64 /*
  65  * enums and structures
  66  */
  67
  68 enum xtal_cap_value {
  69         XTAL_LOW_CAP_30P = 0,
  70         XTAL_LOW_CAP_20P,
  71         XTAL_LOW_CAP_10P,
  72         XTAL_LOW_CAP_0P,
  73         XTAL_HIGH_CAP_0P
  74 };
  75
  76 struct r820t_sect_type {
  77         u8      phase_y;
  78         u8      gain_x;
  79         u16     value;
  80 };
  81
  82 struct r820t_priv {
  83         struct list_head                hybrid_tuner_instance_list;
  84         const struct r820t_config       *cfg;
  85         struct tuner_i2c_props          i2c_props;
  86         struct mutex                    lock;
  87
  88         u8                              regs[NUM_REGS];
  89         u8                              buf[NUM_REGS + 1];
  90         enum xtal_cap_value             xtal_cap_sel;
  91         u16                             pll;    /* kHz */
  92         u32                             int_freq;
  93         u8                              fil_cal_code;
  94         bool                            imr_done;
  95         bool                            has_lock;
  96         bool                            init_done;
  97         struct r820t_sect_type          imr_data[NUM_IMR];
  98
  99         /* Store current mode */
 100         u32                             delsys;
 101         enum v4l2_tuner_type            type;
 102         v4l2_std_id                     std;
 103         u32                             bw;     /* in MHz */
 104 };
 105
 106 struct r820t_freq_range {
 107         u32     freq;
 108         u8      open_d;
 109         u8      rf_mux_ploy;
 110         u8      tf_c;
 111         u8      xtal_cap20p;
 112         u8      xtal_cap10p;
 113         u8      xtal_cap0p;
 114         u8      imr_mem;                /* Not used, currently */
 115 };
 116
 117 #define VCO_POWER_REF   0x02
 118 #define DIP_FREQ        32000000
 119
 120 /*
 121  * Static constants
 122  */
 123
 124 static LIST_HEAD(hybrid_tuner_instance_list);
 125 static DEFINE_MUTEX(r820t_list_mutex);
 126
 127 /* Those initial values start from REG_SHADOW_START */
 128 static const u8 r820t_init_array[NUM_REGS] = {
 129         0x83, 0x32, 0x75,                       /* 05 to 07 */
 130         0xc0, 0x40, 0xd6, 0x6c,                 /* 08 to 0b */
 131         0xf5, 0x63, 0x75, 0x68,                 /* 0c to 0f */
 132         0x6c, 0x83, 0x80, 0x00,                 /* 10 to 13 */
 133         0x0f, 0x00, 0xc0, 0x30,                 /* 14 to 17 */
 134         0x48, 0xcc, 0x60, 0x00,                 /* 18 to 1b */
 135         0x54, 0xae, 0x4a, 0xc0                  /* 1c to 1f */
 136 };
 137
 138 /* Tuner frequency ranges */
 139 static const struct r820t_freq_range freq_ranges[] = {
 140         {
 141                 .freq = 0,
 142                 .open_d = 0x08,         /* low */
 143                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 144                 .tf_c = 0xdf,           /* R27[7:0]  band2,band0 */
 145                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 146                 .xtal_cap10p = 0x01,
 147                 .xtal_cap0p = 0x00,
 148                 .imr_mem = 0,
 149         }, {
 150                 .freq = 50,             /* Start freq, in MHz */
 151                 .open_d = 0x08,         /* low */
 152                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 153                 .tf_c = 0xbe,           /* R27[7:0]  band4,band1  */
 154                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 155                 .xtal_cap10p = 0x01,
 156                 .xtal_cap0p = 0x00,
 157                 .imr_mem = 0,
 158         }, {
 159                 .freq = 55,             /* Start freq, in MHz */
 160                 .open_d = 0x08,         /* low */
 161                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 162                 .tf_c = 0x8b,           /* R27[7:0]  band7,band4 */
 163                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 164                 .xtal_cap10p = 0x01,
 165                 .xtal_cap0p = 0x00,
 166                 .imr_mem = 0,
 167         }, {
 168                 .freq = 60,             /* Start freq, in MHz */
 169                 .open_d = 0x08,         /* low */
 170                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 171                 .tf_c = 0x7b,           /* R27[7:0]  band8,band4 */
 172                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 173                 .xtal_cap10p = 0x01,
 174                 .xtal_cap0p = 0x00,
 175                 .imr_mem = 0,
 176         }, {
 177                 .freq = 65,             /* Start freq, in MHz */
 178                 .open_d = 0x08,         /* low */
 179                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 180                 .tf_c = 0x69,           /* R27[7:0]  band9,band6 */
 181                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 182                 .xtal_cap10p = 0x01,
 183                 .xtal_cap0p = 0x00,
 184                 .imr_mem = 0,
 185         }, {
 186                 .freq = 70,             /* Start freq, in MHz */
 187                 .open_d = 0x08,         /* low */
 188                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 189                 .tf_c = 0x58,           /* R27[7:0]  band10,band7 */
 190                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 191                 .xtal_cap10p = 0x01,
 192                 .xtal_cap0p = 0x00,
 193                 .imr_mem = 0,
 194         }, {
 195                 .freq = 75,             /* Start freq, in MHz */
 196                 .open_d = 0x00,         /* high */
 197                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 198                 .tf_c = 0x44,           /* R27[7:0]  band11,band11 */
 199                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 200                 .xtal_cap10p = 0x01,
 201                 .xtal_cap0p = 0x00,
 202                 .imr_mem = 0,
 203         }, {
 204                 .freq = 80,             /* Start freq, in MHz */
 205                 .open_d = 0x00,         /* high */
 206                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 207                 .tf_c = 0x44,           /* R27[7:0]  band11,band11 */
 208                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 209                 .xtal_cap10p = 0x01,
 210                 .xtal_cap0p = 0x00,
 211                 .imr_mem = 0,
 212         }, {
 213                 .freq = 90,             /* Start freq, in MHz */
 214                 .open_d = 0x00,         /* high */
 215                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 216                 .tf_c = 0x34,           /* R27[7:0]  band12,band11 */
 217                 .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
 218                 .xtal_cap10p = 0x01,
 219                 .xtal_cap0p = 0x00,
 220                 .imr_mem = 0,
 221         }, {
 222                 .freq = 100,            /* Start freq, in MHz */
 223                 .open_d = 0x00,         /* high */
 224                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 225                 .tf_c = 0x34,           /* R27[7:0]  band12,band11 */
 226                 .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)    */
 227                 .xtal_cap10p = 0x01,
 228                 .xtal_cap0p = 0x00,
 229                 .imr_mem = 0,
 230         }, {
 231                 .freq = 110,            /* Start freq, in MHz */
 232                 .open_d = 0x00,         /* high */
 233                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 234                 .tf_c = 0x24,           /* R27[7:0]  band13,band11 */
 235                 .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
 236                 .xtal_cap10p = 0x01,
 237                 .xtal_cap0p = 0x00,
 238                 .imr_mem = 1,
 239         }, {
 240                 .freq = 120,            /* Start freq, in MHz */
 241                 .open_d = 0x00,         /* high */
 242                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 243                 .tf_c = 0x24,           /* R27[7:0]  band13,band11 */
 244                 .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
 245                 .xtal_cap10p = 0x01,
 246                 .xtal_cap0p = 0x00,
 247                 .imr_mem = 1,
 248         }, {
 249                 .freq = 140,            /* Start freq, in MHz */
 250                 .open_d = 0x00,         /* high */
 251                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 252                 .tf_c = 0x14,           /* R27[7:0]  band14,band11 */
 253                 .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
 254                 .xtal_cap10p = 0x01,
 255                 .xtal_cap0p = 0x00,
 256                 .imr_mem = 1,
 257         }, {
 258                 .freq = 180,            /* Start freq, in MHz */
 259                 .open_d = 0x00,         /* high */
 260                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 261                 .tf_c = 0x13,           /* R27[7:0]  band14,band12 */
 262                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 263                 .xtal_cap10p = 0x00,
 264                 .xtal_cap0p = 0x00,
 265                 .imr_mem = 1,
 266         }, {
 267                 .freq = 220,            /* Start freq, in MHz */
 268                 .open_d = 0x00,         /* high */
 269                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 270                 .tf_c = 0x13,           /* R27[7:0]  band14,band12 */
 271                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 272                 .xtal_cap10p = 0x00,
 273                 .xtal_cap0p = 0x00,
 274                 .imr_mem = 2,
 275         }, {
 276                 .freq = 250,            /* Start freq, in MHz */
 277                 .open_d = 0x00,         /* high */
 278                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 279                 .tf_c = 0x11,           /* R27[7:0]  highest,highest */
 280                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 281                 .xtal_cap10p = 0x00,
 282                 .xtal_cap0p = 0x00,
 283                 .imr_mem = 2,
 284         }, {
 285                 .freq = 280,            /* Start freq, in MHz */
 286                 .open_d = 0x00,         /* high */
 287                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 288                 .tf_c = 0x00,           /* R27[7:0]  highest,highest */
 289                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 290                 .xtal_cap10p = 0x00,
 291                 .xtal_cap0p = 0x00,
 292                 .imr_mem = 2,
 293         }, {
 294                 .freq = 310,            /* Start freq, in MHz */
 295                 .open_d = 0x00,         /* high */
 296                 .rf_mux_ploy = 0x41,    /* R26[7:6]=1 (bypass)  R26[1:0]=1 (middle) */
 297                 .tf_c = 0x00,           /* R27[7:0]  highest,highest */
 298                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 299                 .xtal_cap10p = 0x00,
 300                 .xtal_cap0p = 0x00,
 301                 .imr_mem = 2,
 302         }, {
 303                 .freq = 450,            /* Start freq, in MHz */
 304                 .open_d = 0x00,         /* high */
 305                 .rf_mux_ploy = 0x41,    /* R26[7:6]=1 (bypass)  R26[1:0]=1 (middle) */
 306                 .tf_c = 0x00,           /* R27[7:0]  highest,highest */
 307                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 308                 .xtal_cap10p = 0x00,
 309                 .xtal_cap0p = 0x00,
 310                 .imr_mem = 3,
 311         }, {
 312                 .freq = 588,            /* Start freq, in MHz */
 313                 .open_d = 0x00,         /* high */
 314                 .rf_mux_ploy = 0x40,    /* R26[7:6]=1 (bypass)  R26[1:0]=0 (highest) */
 315                 .tf_c = 0x00,           /* R27[7:0]  highest,highest */
 316                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 317                 .xtal_cap10p = 0x00,
 318                 .xtal_cap0p = 0x00,
 319                 .imr_mem = 3,
 320         }, {
 321                 .freq = 650,            /* Start freq, in MHz */
 322                 .open_d = 0x00,         /* high */
 323                 .rf_mux_ploy = 0x40,    /* R26[7:6]=1 (bypass)  R26[1:0]=0 (highest) */
 324                 .tf_c = 0x00,           /* R27[7:0]  highest,highest */
 325                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 326                 .xtal_cap10p = 0x00,
 327                 .xtal_cap0p = 0x00,
 328                 .imr_mem = 4,
 329         }
 330 };
 331
 332 static int r820t_xtal_capacitor[][2] = {
 333         { 0x0b, XTAL_LOW_CAP_30P },
 334         { 0x02, XTAL_LOW_CAP_20P },
 335         { 0x01, XTAL_LOW_CAP_10P },
 336         { 0x00, XTAL_LOW_CAP_0P  },
 337         { 0x10, XTAL_HIGH_CAP_0P },
 338 };
 339
 340 /*
 341  * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
 342  * input power, for raw results see:
 343  *      http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
 344  */
 345
 346 static const int r820t_lna_gain_steps[]  = {
 347         0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
 348 };
 349
 350 static const int r820t_mixer_gain_steps[]  = {
 351         0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
 352 };
 353
 354 /*
 355  * I2C read/write code and shadow registers logic
 356  */
 357 static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
 358                          int len)
 359 {
 360         int r = reg - REG_SHADOW_START;
 361
 362         if (r < 0) {
 363                 len += r;
 364                 r = 0;
 365         }
 366         if (len <= 0)
 367                 return;
 368         if (len > NUM_REGS)
 369                 len = NUM_REGS;
 370
 371         tuner_dbg("%s: prev  reg=%02x len=%d: %*ph\n",
 372                   __func__, r + REG_SHADOW_START, len, len, val);
 373
 374         memcpy(&priv->regs[r], val, len);
 375 }
 376
 377 static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
 378                        int len)
 379 {
 380         int rc, size, pos = 0;
 381
 382         /* Store the shadow registers */
 383         shadow_store(priv, reg, val, len);
 384
 385         do {
 386                 if (len > priv->cfg->max_i2c_msg_len - 1)
 387                         size = priv->cfg->max_i2c_msg_len - 1;
 388                 else
 389                         size = len;
 390
 391                 /* Fill I2C buffer */
 392                 priv->buf[0] = reg;
 393                 memcpy(&priv->buf[1], &val[pos], size);
 394
 395                 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
 396                 if (rc != size + 1) {
 397                         tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
 398                                    __func__, rc, reg, size, size, &priv->buf[1]);
 399                         if (rc < 0)
 400                                 return rc;
 401                         return -EREMOTEIO;
 402                 }
 403                 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
 404                           __func__, reg, size, size, &priv->buf[1]);
 405
 406                 reg += size;
 407                 len -= size;
 408                 pos += size;
 409         } while (len > 0);
 410
 411         return 0;
 412 }
 413
 414 static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
 415 {
 416         return r820t_write(priv, reg, &val, 1);
 417 }
 418
 419 static int r820t_read_cache_reg(struct r820t_priv *priv, int reg)
 420 {
 421         reg -= REG_SHADOW_START;
 422
 423         if (reg >= 0 && reg < NUM_REGS)
 424                 return priv->regs[reg];
 425         else
 426                 return -EINVAL;
 427 }
 428
 429 static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
 430                                 u8 bit_mask)
 431 {
 432         int rc = r820t_read_cache_reg(priv, reg);
 433
 434         if (rc < 0)
 435                 return rc;
 436
 437         val = (rc & ~bit_mask) | (val & bit_mask);
 438
 439         return r820t_write(priv, reg, &val, 1);
 440 }
 441
 442 static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
 443 {
 444         int rc, i;
 445         u8 *p = &priv->buf[1];
 446
 447         priv->buf[0] = reg;
 448
 449         rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
 450         if (rc != len) {
 451                 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
 452                            __func__, rc, reg, len, len, p);
 453                 if (rc < 0)
 454                         return rc;
 455                 return -EREMOTEIO;
 456         }
 457
 458         /* Copy data to the output buffer */
 459         for (i = 0; i < len; i++)
 460                 val[i] = bitrev8(p[i]);
 461
 462         tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
 463                   __func__, reg, len, len, val);
 464
 465         return 0;
 466 }
 467
 468 /*
 469  * r820t tuning logic
 470  */
 471
 472 static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
 473 {
 474         const struct r820t_freq_range *range;
 475         int i, rc;
 476         u8 val, reg08, reg09;
 477
 478         /* Get the proper frequency range */
 479         freq = freq / 1000000;
 480         for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
 481                 if (freq < freq_ranges[i + 1].freq)
 482                         break;
 483         }
 484         range = &freq_ranges[i];
 485
 486         tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
 487
 488         /* Open Drain */
 489         rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
 490         if (rc < 0)
 491                 return rc;
 492
 493         /* RF_MUX,Polymux */
 494         rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
 495         if (rc < 0)
 496                 return rc;
 497
 498         /* TF BAND */
 499         rc = r820t_write_reg(priv, 0x1b, range->tf_c);
 500         if (rc < 0)
 501                 return rc;
 502
 503         /* XTAL CAP & Drive */
 504         switch (priv->xtal_cap_sel) {
 505         case XTAL_LOW_CAP_30P:
 506         case XTAL_LOW_CAP_20P:
 507                 val = range->xtal_cap20p | 0x08;
 508                 break;
 509         case XTAL_LOW_CAP_10P:
 510                 val = range->xtal_cap10p | 0x08;
 511                 break;
 512         case XTAL_HIGH_CAP_0P:
 513                 val = range->xtal_cap0p | 0x00;
 514                 break;
 515         default:
 516         case XTAL_LOW_CAP_0P:
 517                 val = range->xtal_cap0p | 0x08;
 518                 break;
 519         }
 520         rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
 521         if (rc < 0)
 522                 return rc;
 523
 524         if (priv->imr_done) {
 525                 reg08 = priv->imr_data[range->imr_mem].gain_x;
 526                 reg09 = priv->imr_data[range->imr_mem].phase_y;
 527         } else {
 528                 reg08 = 0;
 529                 reg09 = 0;
 530         }
 531         rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f);
 532         if (rc < 0)
 533                 return rc;
 534
 535         rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f);
 536
 537         return rc;
 538 }
 539
 540 static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,
 541                          u32 freq)
 542 {
 543         u64 tmp64, vco_freq;
 544         int rc, i;
 545         unsigned sleep_time = 10000;
 546         u32 vco_fra;            /* VCO contribution by SDM (kHz) */
 547         u32 vco_min  = 1770000;
 548         u32 vco_max  = vco_min * 2;
 549         u32 pll_ref;
 550         u16 n_sdm = 2;
 551         u16 sdm = 0;
 552         u8 mix_div = 2;
 553         u8 div_buf = 0;
 554         u8 div_num = 0;
 555         u8 refdiv2 = 0;
 556         u8 ni, si, nint, vco_fine_tune, val;
 557         u8 data[5];
 558
 559         /* Frequency in kHz */
 560         freq = freq / 1000;
 561         pll_ref = priv->cfg->xtal / 1000;
 562
 563         if ((priv->cfg->rafael_chip == CHIP_R620D) ||
 564            (priv->cfg->rafael_chip == CHIP_R828D) ||
 565            (priv->cfg->rafael_chip == CHIP_R828)) {
 566                 /* ref set refdiv2, reffreq = Xtal/2 on ATV application */
 567                 if (type != V4L2_TUNER_DIGITAL_TV) {
 568                         pll_ref /= 2;
 569                         refdiv2 = 0x10;
 570                         sleep_time = 20000;
 571                 }
 572         } else {
 573                 if (priv->cfg->xtal > 24000000) {
 574                         pll_ref /= 2;
 575                         refdiv2 = 0x10;
 576                 }
 577         }
 578
 579         tuner_dbg("set r820t pll for frequency %d kHz = %d%s\n",
 580                   freq, pll_ref, refdiv2 ? " / 2" : "");
 581
 582         rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10);
 583         if (rc < 0)
 584                 return rc;
 585
 586         /* set pll autotune = 128kHz */
 587         rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
 588         if (rc < 0)
 589                 return rc;
 590
 591         /* set VCO current = 100 */
 592         rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
 593         if (rc < 0)
 594                 return rc;
 595
 596         /* Calculate divider */
 597         while (mix_div <= 64) {
 598                 if (((freq * mix_div) >= vco_min) &&
 599                    ((freq * mix_div) < vco_max)) {
 600                         div_buf = mix_div;
 601                         while (div_buf > 2) {
 602                                 div_buf = div_buf >> 1;
 603                                 div_num++;
 604                         }
 605                         break;
 606                 }
 607                 mix_div = mix_div << 1;
 608         }
 609
 610         rc = r820t_read(priv, 0x00, data, sizeof(data));
 611         if (rc < 0)
 612                 return rc;
 613
 614         vco_fine_tune = (data[4] & 0x30) >> 4;
 615
 616         if (vco_fine_tune > VCO_POWER_REF)
 617                 div_num = div_num - 1;
 618         else if (vco_fine_tune < VCO_POWER_REF)
 619                 div_num = div_num + 1;
 620
 621         rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
 622         if (rc < 0)
 623                 return rc;
 624
 625         vco_freq = (u64)(freq * (u64)mix_div);
 626
 627         tmp64 = vco_freq;
 628         do_div(tmp64, 2 * pll_ref);
 629         nint = (u8)tmp64;
 630
 631         tmp64 = vco_freq - ((u64)2) * pll_ref * nint;
 632         do_div(tmp64, 1000);
 633         vco_fra  = (u16)(tmp64);
 634
 635         /* boundary spur prevention */
 636         if (vco_fra < pll_ref / 64) {
 637                 vco_fra = 0;
 638         } else if (vco_fra > pll_ref * 127 / 64) {
 639                 vco_fra = 0;
 640                 nint++;
 641         } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
 642                 vco_fra = pll_ref * 127 / 128;
 643         } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
 644                 vco_fra = pll_ref * 129 / 128;
 645         }
 646
 647         if (nint > 63) {
 648                 tuner_info("No valid PLL values for %u kHz!\n", freq);
 649                 return -EINVAL;
 650         }
 651
 652         ni = (nint - 13) / 4;
 653         si = nint - 4 * ni - 13;
 654
 655         rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
 656         if (rc < 0)
 657                 return rc;
 658
 659         /* pw_sdm */
 660         if (!vco_fra)
 661                 val = 0x08;
 662         else
 663                 val = 0x00;
 664
 665         rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
 666         if (rc < 0)
 667                 return rc;
 668
 669         /* sdm calculator */
 670         while (vco_fra > 1) {
 671                 if (vco_fra > (2 * pll_ref / n_sdm)) {
 672                         sdm = sdm + 32768 / (n_sdm / 2);
 673                         vco_fra = vco_fra - 2 * pll_ref / n_sdm;
 674                         if (n_sdm >= 0x8000)
 675                                 break;
 676                 }
 677                 n_sdm = n_sdm << 1;
 678         }
 679
 680         rc = r820t_write_reg_mask(priv, 0x16, sdm >> 8, 0x08);
 681         if (rc < 0)
 682                 return rc;
 683         rc = r820t_write_reg_mask(priv, 0x15, sdm & 0xff, 0x08);
 684         if (rc < 0)
 685                 return rc;
 686
 687         for (i = 0; i < 2; i++) {
 688                 usleep_range(sleep_time, sleep_time + 1000);
 689
 690                 /* Check if PLL has locked */
 691                 rc = r820t_read(priv, 0x00, data, 3);
 692                 if (rc < 0)
 693                         return rc;
 694                 if (data[2] & 0x40)
 695                         break;
 696
 697                 if (!i) {
 698                         /* Didn't lock. Increase VCO current */
 699                         rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
 700                         if (rc < 0)
 701                                 return rc;
 702                 }
 703         }
 704
 705         if (!(data[2] & 0x40)) {
 706                 priv->has_lock = false;
 707                 return 0;
 708         }
 709
 710         priv->has_lock = true;
 711         tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
 712
 713         /* set pll autotune = 8kHz */
 714         rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
 715
 716         return rc;
 717 }
 718
 719 static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
 720                              enum v4l2_tuner_type type,
 721                              v4l2_std_id std,
 722                              u32 delsys)
 723 {
 724         int rc;
 725         u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
 726         u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
 727
 728         tuner_dbg("adjusting tuner parameters for the standard\n");
 729
 730         switch (delsys) {
 731         case SYS_DVBT:
 732                 if ((freq == 506000000) || (freq == 666000000) ||
 733                    (freq == 818000000)) {
 734                         mixer_top = 0x14;       /* mixer top:14 , top-1, low-discharge */
 735                         lna_top = 0xe5;         /* detect bw 3, lna top:4, predet top:2 */
 736                         cp_cur = 0x28;          /* 101, 0.2 */
 737                         div_buf_cur = 0x20;     /* 10, 200u */
 738                 } else {
 739                         mixer_top = 0x24;       /* mixer top:13 , top-1, low-discharge */
 740                         lna_top = 0xe5;         /* detect bw 3, lna top:4, predet top:2 */
 741                         cp_cur = 0x38;          /* 111, auto */
 742                         div_buf_cur = 0x30;     /* 11, 150u */
 743                 }
 744                 lna_vth_l = 0x53;               /* lna vth 0.84 ,  vtl 0.64 */
 745                 mixer_vth_l = 0x75;             /* mixer vth 1.04, vtl 0.84 */
 746                 air_cable1_in = 0x00;
 747                 cable2_in = 0x00;
 748                 pre_dect = 0x40;
 749                 lna_discharge = 14;
 750                 filter_cur = 0x40;              /* 10, low */
 751                 break;
 752         case SYS_DVBT2:
 753                 mixer_top = 0x24;       /* mixer top:13 , top-1, low-discharge */
 754                 lna_top = 0xe5;         /* detect bw 3, lna top:4, predet top:2 */
 755                 lna_vth_l = 0x53;       /* lna vth 0.84 ,  vtl 0.64 */
 756                 mixer_vth_l = 0x75;     /* mixer vth 1.04, vtl 0.84 */
 757                 air_cable1_in = 0x00;
 758                 cable2_in = 0x00;
 759                 pre_dect = 0x40;
 760                 lna_discharge = 14;
 761                 cp_cur = 0x38;          /* 111, auto */
 762                 div_buf_cur = 0x30;     /* 11, 150u */
 763                 filter_cur = 0x40;      /* 10, low */
 764                 break;
 765         case SYS_ISDBT:
 766                 mixer_top = 0x24;       /* mixer top:13 , top-1, low-discharge */
 767                 lna_top = 0xe5;         /* detect bw 3, lna top:4, predet top:2 */
 768                 lna_vth_l = 0x75;       /* lna vth 1.04 ,  vtl 0.84 */
 769                 mixer_vth_l = 0x75;     /* mixer vth 1.04, vtl 0.84 */
 770                 air_cable1_in = 0x00;
 771                 cable2_in = 0x00;
 772                 pre_dect = 0x40;
 773                 lna_discharge = 14;
 774                 cp_cur = 0x38;          /* 111, auto */
 775                 div_buf_cur = 0x30;     /* 11, 150u */
 776                 filter_cur = 0x40;      /* 10, low */
 777                 break;
 778         default: /* DVB-T 8M */
 779                 mixer_top = 0x24;       /* mixer top:13 , top-1, low-discharge */
 780                 lna_top = 0xe5;         /* detect bw 3, lna top:4, predet top:2 */
 781                 lna_vth_l = 0x53;       /* lna vth 0.84 ,  vtl 0.64 */
 782                 mixer_vth_l = 0x75;     /* mixer vth 1.04, vtl 0.84 */
 783                 air_cable1_in = 0x00;
 784                 cable2_in = 0x00;
 785                 pre_dect = 0x40;
 786                 lna_discharge = 14;
 787                 cp_cur = 0x38;          /* 111, auto */
 788                 div_buf_cur = 0x30;     /* 11, 150u */
 789                 filter_cur = 0x40;      /* 10, low */
 790                 break;
 791         }
 792
 793         if (priv->cfg->use_diplexer &&
 794            ((priv->cfg->rafael_chip == CHIP_R820T) ||
 795            (priv->cfg->rafael_chip == CHIP_R828S) ||
 796            (priv->cfg->rafael_chip == CHIP_R820C))) {
 797                 if (freq > DIP_FREQ)
 798                         air_cable1_in = 0x00;
 799                 else
 800                         air_cable1_in = 0x60;
 801                 cable2_in = 0x00;
 802         }
 803
 804         rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
 805         if (rc < 0)
 806                 return rc;
 807         rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
 808         if (rc < 0)
 809                 return rc;
 810         rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
 811         if (rc < 0)
 812                 return rc;
 813         rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
 814         if (rc < 0)
 815                 return rc;
 816
 817         /* Air-IN only for Astrometa */
 818         rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
 819         if (rc < 0)
 820                 return rc;
 821         rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
 822         if (rc < 0)
 823                 return rc;
 824
 825         rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
 826         if (rc < 0)
 827                 return rc;
 828         rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
 829         if (rc < 0)
 830                 return rc;
 831         rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
 832         if (rc < 0)
 833                 return rc;
 834         /*
 835          * Original driver initializes regs 0x05 and 0x06 with the
 836          * same value again on this point. Probably, it is just an
 837          * error there
 838          */
 839
 840         /*
 841          * Set LNA
 842          */
 843
 844         tuner_dbg("adjusting LNA parameters\n");
 845         if (type != V4L2_TUNER_ANALOG_TV) {
 846                 /* LNA TOP: lowest */
 847                 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
 848                 if (rc < 0)
 849                         return rc;
 850
 851                 /* 0: normal mode */
 852                 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
 853                 if (rc < 0)
 854                         return rc;
 855
 856                 /* 0: PRE_DECT off */
 857                 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
 858                 if (rc < 0)
 859                         return rc;
 860
 861                 /* agc clk 250hz */
 862                 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
 863                 if (rc < 0)
 864                         return rc;
 865
 866                 msleep(250);
 867
 868                 /* write LNA TOP = 3 */
 869                 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
 870                 if (rc < 0)
 871                         return rc;
 872
 873                 /*
 874                  * write discharge mode
 875                  * FIXME: IMHO, the mask here is wrong, but it matches
 876                  * what's there at the original driver
 877                  */
 878                 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
 879                 if (rc < 0)
 880                         return rc;
 881
 882                 /* LNA discharge current */
 883                 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
 884                 if (rc < 0)
 885                         return rc;
 886
 887                 /* agc clk 60hz */
 888                 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
 889                 if (rc < 0)
 890                         return rc;
 891         } else {
 892                 /* PRE_DECT off */
 893                 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
 894                 if (rc < 0)
 895                         return rc;
 896
 897                 /* write LNA TOP */
 898                 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
 899                 if (rc < 0)
 900                         return rc;
 901
 902                 /*
 903                  * write discharge mode
 904                  * FIXME: IMHO, the mask here is wrong, but it matches
 905                  * what's there at the original driver
 906                  */
 907                 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
 908                 if (rc < 0)
 909                         return rc;
 910
 911                 /* LNA discharge current */
 912                 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
 913                 if (rc < 0)
 914                         return rc;
 915
 916                 /* agc clk 1Khz, external det1 cap 1u */
 917                 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
 918                 if (rc < 0)
 919                         return rc;
 920
 921                 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
 922                 if (rc < 0)
 923                         return rc;
 924          }
 925          return 0;
 926 }
 927
 928 static int r820t_set_tv_standard(struct r820t_priv *priv,
 929                                  unsigned bw,
 930                                  enum v4l2_tuner_type type,
 931                                  v4l2_std_id std, u32 delsys)
 932
 933 {
 934         int rc, i;
 935         u32 if_khz, filt_cal_lo;
 936         u8 data[5], val;
 937         u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
 938         u8 lt_att, flt_ext_widest, polyfil_cur;
 939         bool need_calibration;
 940
 941         tuner_dbg("selecting the delivery system\n");
 942
 943         if (delsys == SYS_ISDBT) {
 944                 if_khz = 4063;
 945                 filt_cal_lo = 59000;
 946                 filt_gain = 0x10;       /* +3db, 6mhz on */
 947                 img_r = 0x00;           /* image negative */
 948                 filt_q = 0x10;          /* r10[4]:low q(1'b1) */
 949                 hp_cor = 0x6a;          /* 1.7m disable, +2cap, 1.25mhz */
 950                 ext_enable = 0x40;      /* r30[6], ext enable; r30[5]:0 ext at lna max */
 951                 loop_through = 0x00;    /* r5[7], lt on */
 952                 lt_att = 0x00;          /* r31[7], lt att enable */
 953                 flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
 954                 polyfil_cur = 0x60;     /* r25[6:5]:min */
 955         } else {
 956                 if (bw <= 6) {
 957                         if_khz = 3570;
 958                         filt_cal_lo = 56000;    /* 52000->56000 */
 959                         filt_gain = 0x10;       /* +3db, 6mhz on */
 960                         img_r = 0x00;           /* image negative */
 961                         filt_q = 0x10;          /* r10[4]:low q(1'b1) */
 962                         hp_cor = 0x6b;          /* 1.7m disable, +2cap, 1.0mhz */
 963                         ext_enable = 0x60;      /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
 964                         loop_through = 0x00;    /* r5[7], lt on */
 965                         lt_att = 0x00;          /* r31[7], lt att enable */
 966                         flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
 967                         polyfil_cur = 0x60;     /* r25[6:5]:min */
 968                 } else if (bw == 7) {
 969 #if 0
 970                         /*
 971                          * There are two 7 MHz tables defined on the original
 972                          * driver, but just the second one seems to be visible
 973                          * by rtl2832. Keep this one here commented, as it
 974                          * might be needed in the future
 975                          */
 976
 977                         if_khz = 4070;
 978                         filt_cal_lo = 60000;
 979                         filt_gain = 0x10;       /* +3db, 6mhz on */
 980                         img_r = 0x00;           /* image negative */
 981                         filt_q = 0x10;          /* r10[4]:low q(1'b1) */
 982                         hp_cor = 0x2b;          /* 1.7m disable, +1cap, 1.0mhz */
 983                         ext_enable = 0x60;      /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
 984                         loop_through = 0x00;    /* r5[7], lt on */
 985                         lt_att = 0x00;          /* r31[7], lt att enable */
 986                         flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
 987                         polyfil_cur = 0x60;     /* r25[6:5]:min */
 988 #endif
 989                         /* 7 MHz, second table */
 990                         if_khz = 4570;
 991                         filt_cal_lo = 63000;
 992                         filt_gain = 0x10;       /* +3db, 6mhz on */
 993                         img_r = 0x00;           /* image negative */
 994                         filt_q = 0x10;          /* r10[4]:low q(1'b1) */
 995                         hp_cor = 0x2a;          /* 1.7m disable, +1cap, 1.25mhz */
 996                         ext_enable = 0x60;      /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
 997                         loop_through = 0x00;    /* r5[7], lt on */
 998                         lt_att = 0x00;          /* r31[7], lt att enable */
 999                         flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
1000                         polyfil_cur = 0x60;     /* r25[6:5]:min */
1001                 } else {
1002                         if_khz = 4570;
1003                         filt_cal_lo = 68500;
1004                         filt_gain = 0x10;       /* +3db, 6mhz on */
1005                         img_r = 0x00;           /* image negative */
1006                         filt_q = 0x10;          /* r10[4]:low q(1'b1) */
1007                         hp_cor = 0x0b;          /* 1.7m disable, +0cap, 1.0mhz */
1008                         ext_enable = 0x60;      /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1009                         loop_through = 0x00;    /* r5[7], lt on */
1010                         lt_att = 0x00;          /* r31[7], lt att enable */
1011                         flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
1012                         polyfil_cur = 0x60;     /* r25[6:5]:min */
1013                 }
1014         }
1015
1016         /* Initialize the shadow registers */
1017         memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1018
1019         /* Init Flag & Xtal_check Result */
1020         if (priv->imr_done)
1021                 val = 1 | priv->xtal_cap_sel << 1;
1022         else
1023                 val = 0;
1024         rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
1025         if (rc < 0)
1026                 return rc;
1027
1028         /* version */
1029         rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
1030         if (rc < 0)
1031                 return rc;
1032
1033         /* for LT Gain test */
1034         if (type != V4L2_TUNER_ANALOG_TV) {
1035                 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
1036                 if (rc < 0)
1037                         return rc;
1038                 usleep_range(1000, 2000);
1039         }
1040         priv->int_freq = if_khz * 1000;
1041
1042         /* Check if standard changed. If so, filter calibration is needed */
1043         if (type != priv->type)
1044                 need_calibration = true;
1045         else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
1046                 need_calibration = true;
1047         else if ((type == V4L2_TUNER_DIGITAL_TV) &&
1048                  ((delsys != priv->delsys) || bw != priv->bw))
1049                 need_calibration = true;
1050         else
1051                 need_calibration = false;
1052
1053         if (need_calibration) {
1054                 tuner_dbg("calibrating the tuner\n");
1055                 for (i = 0; i < 2; i++) {
1056                         /* Set filt_cap */
1057                         rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
1058                         if (rc < 0)
1059                                 return rc;
1060
1061                         /* set cali clk =on */
1062                         rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
1063                         if (rc < 0)
1064                                 return rc;
1065
1066                         /* X'tal cap 0pF for PLL */
1067                         rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
1068                         if (rc < 0)
1069                                 return rc;
1070
1071                         rc = r820t_set_pll(priv, type, filt_cal_lo);
1072                         if (rc < 0 || !priv->has_lock)
1073                                 return rc;
1074
1075                         /* Start Trigger */
1076                         rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
1077                         if (rc < 0)
1078                                 return rc;
1079
1080                         usleep_range(1000, 2000);
1081
1082                         /* Stop Trigger */
1083                         rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
1084                         if (rc < 0)
1085                                 return rc;
1086
1087                         /* set cali clk =off */
1088                         rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
1089                         if (rc < 0)
1090                                 return rc;
1091
1092                         /* Check if calibration worked */
1093                         rc = r820t_read(priv, 0x00, data, sizeof(data));
1094                         if (rc < 0)
1095                                 return rc;
1096
1097                         priv->fil_cal_code = data[4] & 0x0f;
1098                         if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
1099                                 break;
1100                 }
1101                 /* narrowest */
1102                 if (priv->fil_cal_code == 0x0f)
1103                         priv->fil_cal_code = 0;
1104         }
1105
1106         rc = r820t_write_reg_mask(priv, 0x0a,
1107                                   filt_q | priv->fil_cal_code, 0x1f);
1108         if (rc < 0)
1109                 return rc;
1110
1111         /* Set BW, Filter_gain, & HP corner */
1112         rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x10);
1113         if (rc < 0)
1114                 return rc;
1115
1116
1117         /* Set Img_R */
1118         rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
1119         if (rc < 0)
1120                 return rc;
1121
1122         /* Set filt_3dB, V6MHz */
1123         rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
1124         if (rc < 0)
1125                 return rc;
1126
1127         /* channel filter extension */
1128         rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
1129         if (rc < 0)
1130                 return rc;
1131
1132         /* Loop through */
1133         rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
1134         if (rc < 0)
1135                 return rc;
1136
1137         /* Loop through attenuation */
1138         rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
1139         if (rc < 0)
1140                 return rc;
1141
1142         /* filter extension widest */
1143         rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
1144         if (rc < 0)
1145                 return rc;
1146
1147         /* RF poly filter current */
1148         rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
1149         if (rc < 0)
1150                 return rc;
1151
1152         /* Store current standard. If it changes, re-calibrate the tuner */
1153         priv->delsys = delsys;
1154         priv->type = type;
1155         priv->std = std;
1156         priv->bw = bw;
1157
1158         return 0;
1159 }
1160
1161 static int r820t_read_gain(struct r820t_priv *priv)
1162 {
1163         u8 data[4];
1164         int rc;
1165
1166         rc = r820t_read(priv, 0x00, data, sizeof(data));
1167         if (rc < 0)
1168                 return rc;
1169
1170         return ((data[3] & 0x0f) << 1) + ((data[3] & 0xf0) >> 4);
1171 }
1172
1173 static int r820t_set_gain_mode(struct r820t_priv *priv,
1174                                bool set_manual_gain,
1175                                int gain)
1176 {
1177         int rc;
1178
1179         if (set_manual_gain) {
1180                 int i, total_gain = 0;
1181                 uint8_t mix_index = 0, lna_index = 0;
1182                 u8 data[4];
1183
1184                 /* LNA auto off */
1185                 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
1186                 if (rc < 0)
1187                         return rc;
1188
1189                  /* Mixer auto off */
1190                 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1191                 if (rc < 0)
1192                         return rc;
1193
1194                 rc = r820t_read(priv, 0x00, data, sizeof(data));
1195                 if (rc < 0)
1196                         return rc;
1197
1198                 /* set fixed VGA gain for now (16.3 dB) */
1199                 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
1200                 if (rc < 0)
1201                         return rc;
1202
1203                 for (i = 0; i < 15; i++) {
1204                         if (total_gain >= gain)
1205                                 break;
1206
1207                         total_gain += r820t_lna_gain_steps[++lna_index];
1208
1209                         if (total_gain >= gain)
1210                                 break;
1211
1212                         total_gain += r820t_mixer_gain_steps[++mix_index];
1213                 }
1214
1215                 /* set LNA gain */
1216                 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
1217                 if (rc < 0)
1218                         return rc;
1219
1220                 /* set Mixer gain */
1221                 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
1222                 if (rc < 0)
1223                         return rc;
1224         } else {
1225                 /* LNA */
1226                 rc = r820t_write_reg_mask(priv, 0x05, 0, 0xef);
1227                 if (rc < 0)
1228                         return rc;
1229
1230                 /* Mixer */
1231                 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0xef);
1232                 if (rc < 0)
1233                         return rc;
1234
1235                 /* set fixed VGA gain for now (26.5 dB) */
1236                 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1237                 if (rc < 0)
1238                         return rc;
1239         }
1240
1241         return 0;
1242 }
1243
1244
1245 static int generic_set_freq(struct dvb_frontend *fe,
1246                             u32 freq /* in HZ */,
1247                             unsigned bw,
1248                             enum v4l2_tuner_type type,
1249                             v4l2_std_id std, u32 delsys)
1250 {
1251         struct r820t_priv               *priv = fe->tuner_priv;
1252         int                             rc = -EINVAL;
1253         u32                             lo_freq;
1254
1255         tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1256                   freq / 1000, bw);
1257
1258         rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
1259         if (rc < 0)
1260                 goto err;
1261
1262         if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
1263                 lo_freq = freq - priv->int_freq;
1264          else
1265                 lo_freq = freq + priv->int_freq;
1266
1267         rc = r820t_set_mux(priv, lo_freq);
1268         if (rc < 0)
1269                 goto err;
1270
1271         rc = r820t_set_gain_mode(priv, true, 0);
1272         if (rc < 0)
1273                 goto err;
1274
1275         rc = r820t_set_pll(priv, type, lo_freq);
1276         if (rc < 0 || !priv->has_lock)
1277                 goto err;
1278
1279         rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
1280         if (rc < 0)
1281                 goto err;
1282
1283         tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1284                   __func__, freq, r820t_read_gain(priv));
1285
1286 err:
1287
1288         if (rc < 0)
1289                 tuner_dbg("%s: failed=%d\n", __func__, rc);
1290         return rc;
1291 }
1292
1293 /*
1294  * r820t standby logic
1295  */
1296
1297 static int r820t_standby(struct r820t_priv *priv)
1298 {
1299         int rc;
1300
1301         rc = r820t_write_reg(priv, 0x06, 0xb1);
1302         if (rc < 0)
1303                 return rc;
1304         rc = r820t_write_reg(priv, 0x05, 0x03);
1305         if (rc < 0)
1306                 return rc;
1307         rc = r820t_write_reg(priv, 0x07, 0x3a);
1308         if (rc < 0)
1309                 return rc;
1310         rc = r820t_write_reg(priv, 0x08, 0x40);
1311         if (rc < 0)
1312                 return rc;
1313         rc = r820t_write_reg(priv, 0x09, 0xc0);
1314         if (rc < 0)
1315                 return rc;
1316         rc = r820t_write_reg(priv, 0x0a, 0x36);
1317         if (rc < 0)
1318                 return rc;
1319         rc = r820t_write_reg(priv, 0x0c, 0x35);
1320         if (rc < 0)
1321                 return rc;
1322         rc = r820t_write_reg(priv, 0x0f, 0x68);
1323         if (rc < 0)
1324                 return rc;
1325         rc = r820t_write_reg(priv, 0x11, 0x03);
1326         if (rc < 0)
1327                 return rc;
1328         rc = r820t_write_reg(priv, 0x17, 0xf4);
1329         if (rc < 0)
1330                 return rc;
1331         rc = r820t_write_reg(priv, 0x19, 0x0c);
1332
1333         /* Force initial calibration */
1334         priv->type = -1;
1335
1336         return rc;
1337 }
1338
1339 /*
1340  * r820t device init logic
1341  */
1342
1343 static int r820t_xtal_check(struct r820t_priv *priv)
1344 {
1345         int rc, i;
1346         u8 data[3], val;
1347
1348         /* Initialize the shadow registers */
1349         memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1350
1351         /* cap 30pF & Drive Low */
1352         rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
1353         if (rc < 0)
1354                 return rc;
1355
1356         /* set pll autotune = 128kHz */
1357         rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
1358         if (rc < 0)
1359                 return rc;
1360
1361         /* set manual initial reg = 111111;  */
1362         rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
1363         if (rc < 0)
1364                 return rc;
1365
1366         /* set auto */
1367         rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
1368         if (rc < 0)
1369                 return rc;
1370
1371         /* Try several xtal capacitor alternatives */
1372         for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
1373                 rc = r820t_write_reg_mask(priv, 0x10,
1374                                           r820t_xtal_capacitor[i][0], 0x1b);
1375                 if (rc < 0)
1376                         return rc;
1377
1378                 usleep_range(5000, 6000);
1379
1380                 rc = r820t_read(priv, 0x00, data, sizeof(data));
1381                 if (rc < 0)
1382                         return rc;
1383                 if ((!data[2]) & 0x40)
1384                         continue;
1385
1386                 val = data[2] & 0x3f;
1387
1388                 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
1389                         break;
1390
1391                 if (val != 0x3f)
1392                         break;
1393         }
1394
1395         if (i == ARRAY_SIZE(r820t_xtal_capacitor))
1396                 return -EINVAL;
1397
1398         return r820t_xtal_capacitor[i][1];
1399 }
1400
1401 static int r820t_imr_prepare(struct r820t_priv *priv)
1402 {
1403         int rc;
1404
1405         /* Initialize the shadow registers */
1406         memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1407
1408         /* lna off (air-in off) */
1409         rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20);
1410         if (rc < 0)
1411                 return rc;
1412
1413         /* mixer gain mode = manual */
1414         rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1415         if (rc < 0)
1416                 return rc;
1417
1418         /* filter corner = lowest */
1419         rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f);
1420         if (rc < 0)
1421                 return rc;
1422
1423         /* filter bw=+2cap, hp=5M */
1424         rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f);
1425         if (rc < 0)
1426                 return rc;
1427
1428         /* adc=on, vga code mode, gain = 26.5dB   */
1429         rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1430         if (rc < 0)
1431                 return rc;
1432
1433         /* ring clk = on */
1434         rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08);
1435         if (rc < 0)
1436                 return rc;
1437
1438         /* ring power = on */
1439         rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10);
1440         if (rc < 0)
1441                 return rc;
1442
1443         /* from ring = ring pll in */
1444         rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02);
1445         if (rc < 0)
1446                 return rc;
1447
1448         /* sw_pdect = det3 */
1449         rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80);
1450         if (rc < 0)
1451                 return rc;
1452
1453         /* Set filt_3dB */
1454         rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20);
1455
1456         return rc;
1457 }
1458
1459 static int r820t_multi_read(struct r820t_priv *priv)
1460 {
1461         int rc, i;
1462         u8 data[2], min = 0, max = 255, sum = 0;
1463
1464         usleep_range(5000, 6000);
1465
1466         for (i = 0; i < 6; i++) {
1467                 rc = r820t_read(priv, 0x00, data, sizeof(data));
1468                 if (rc < 0)
1469                         return rc;
1470
1471                 sum += data[1];
1472
1473                 if (data[1] < min)
1474                         min = data[1];
1475
1476                 if (data[1] > max)
1477                         max = data[1];
1478         }
1479         rc = sum - max - min;
1480
1481         return rc;
1482 }
1483
1484 static int r820t_imr_cross(struct r820t_priv *priv,
1485                            struct r820t_sect_type iq_point[3],
1486                            u8 *x_direct)
1487 {
1488         struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
1489         struct r820t_sect_type tmp;
1490         int i, rc;
1491         u8 reg08, reg09;
1492
1493         reg08 = r820t_read_cache_reg(priv, 8) & 0xc0;
1494         reg09 = r820t_read_cache_reg(priv, 9) & 0xc0;
1495
1496         tmp.gain_x = 0;
1497         tmp.phase_y = 0;
1498         tmp.value = 255;
1499
1500         for (i = 0; i < 5; i++) {
1501                 switch (i) {
1502                 case 0:
1503                         cross[i].gain_x  = reg08;
1504                         cross[i].phase_y = reg09;
1505                         break;
1506                 case 1:
1507                         cross[i].gain_x  = reg08;               /* 0 */
1508                         cross[i].phase_y = reg09 + 1;           /* Q-1 */
1509                         break;
1510                 case 2:
1511                         cross[i].gain_x  = reg08;               /* 0 */
1512                         cross[i].phase_y = (reg09 | 0x20) + 1;  /* I-1 */
1513                         break;
1514                 case 3:
1515                         cross[i].gain_x  = reg08 + 1;           /* Q-1 */
1516                         cross[i].phase_y = reg09;
1517                         break;
1518                 default:
1519                         cross[i].gain_x  = (reg08 | 0x20) + 1;  /* I-1 */
1520                         cross[i].phase_y = reg09;
1521                 }
1522
1523                 rc = r820t_write_reg(priv, 0x08, cross[i].gain_x);
1524                 if (rc < 0)
1525                         return rc;
1526
1527                 rc = r820t_write_reg(priv, 0x09, cross[i].phase_y);
1528                 if (rc < 0)
1529                         return rc;
1530
1531                 rc = r820t_multi_read(priv);
1532                 if (rc < 0)
1533                         return rc;
1534
1535                 cross[i].value = rc;
1536
1537                 if (cross[i].value < tmp.value)
1538                         memcpy(&tmp, &cross[i], sizeof(tmp));
1539         }
1540
1541         if ((tmp.phase_y & 0x1f) == 1) {        /* y-direction */
1542                 *x_direct = 0;
1543
1544                 iq_point[0] = cross[0];
1545                 iq_point[1] = cross[1];
1546                 iq_point[2] = cross[2];
1547         } else {                                /* (0,0) or x-direction */
1548                 *x_direct = 1;
1549
1550                 iq_point[0] = cross[0];
1551                 iq_point[1] = cross[3];
1552                 iq_point[2] = cross[4];
1553         }
1554         return 0;
1555 }
1556
1557 static void r820t_compre_cor(struct r820t_sect_type iq[3])
1558 {
1559         int i;
1560
1561         for (i = 3; i > 0; i--) {
1562                 if (iq[0].value > iq[i - 1].value)
1563                         swap(iq[0], iq[i - 1]);
1564         }
1565 }
1566
1567 static int r820t_compre_step(struct r820t_priv *priv,
1568                              struct r820t_sect_type iq[3], u8 reg)
1569 {
1570         int rc;
1571         struct r820t_sect_type tmp;
1572
1573         /*
1574          * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
1575          * with min value:
1576          *  new < min => update to min and continue
1577          *  new > min => Exit
1578          */
1579
1580         /* min value already saved in iq[0] */
1581         tmp.phase_y = iq[0].phase_y;
1582         tmp.gain_x  = iq[0].gain_x;
1583
1584         while (((tmp.gain_x & 0x1f) < IMR_TRIAL) &&
1585               ((tmp.phase_y & 0x1f) < IMR_TRIAL)) {
1586                 if (reg == 0x08)
1587                         tmp.gain_x++;
1588                 else
1589                         tmp.phase_y++;
1590
1591                 rc = r820t_write_reg(priv, 0x08, tmp.gain_x);
1592                 if (rc < 0)
1593                         return rc;
1594
1595                 rc = r820t_write_reg(priv, 0x09, tmp.phase_y);
1596                 if (rc < 0)
1597                         return rc;
1598
1599                 rc = r820t_multi_read(priv);
1600                 if (rc < 0)
1601                         return rc;
1602                 tmp.value = rc;
1603
1604                 if (tmp.value <= iq[0].value) {
1605                         iq[0].gain_x  = tmp.gain_x;
1606                         iq[0].phase_y = tmp.phase_y;
1607                         iq[0].value   = tmp.value;
1608                 } else {
1609                         return 0;
1610                 }
1611
1612         }
1613
1614         return 0;
1615 }
1616
1617 static int r820t_iq_tree(struct r820t_priv *priv,
1618                          struct r820t_sect_type iq[3],
1619                          u8 fix_val, u8 var_val, u8 fix_reg)
1620 {
1621         int rc, i;
1622         u8 tmp, var_reg;
1623
1624         /*
1625          * record IMC results by input gain/phase location then adjust
1626          * gain or phase positive 1 step and negtive 1 step,
1627          * both record results
1628          */
1629
1630         if (fix_reg == 0x08)
1631                 var_reg = 0x09;
1632         else
1633                 var_reg = 0x08;
1634
1635         for (i = 0; i < 3; i++) {
1636                 rc = r820t_write_reg(priv, fix_reg, fix_val);
1637                 if (rc < 0)
1638                         return rc;
1639
1640                 rc = r820t_write_reg(priv, var_reg, var_val);
1641                 if (rc < 0)
1642                         return rc;
1643
1644                 rc = r820t_multi_read(priv);
1645                 if (rc < 0)
1646                         return rc;
1647                 iq[i].value = rc;
1648
1649                 if (fix_reg == 0x08) {
1650                         iq[i].gain_x  = fix_val;
1651                         iq[i].phase_y = var_val;
1652                 } else {
1653                         iq[i].phase_y = fix_val;
1654                         iq[i].gain_x  = var_val;
1655                 }
1656
1657                 if (i == 0) {  /* try right-side point */
1658                         var_val++;
1659                 } else if (i == 1) { /* try left-side point */
1660                          /* if absolute location is 1, change I/Q direction */
1661                         if ((var_val & 0x1f) < 0x02) {
1662                                 tmp = 2 - (var_val & 0x1f);
1663
1664                                 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */
1665                                 if (var_val & 0x20) {
1666                                         var_val &= 0xc0;
1667                                         var_val |= tmp;
1668                                 } else {
1669                                         var_val |= 0x20 | tmp;
1670                                 }
1671                         } else {
1672                                 var_val -= 2;
1673                         }
1674                 }
1675         }
1676
1677         return 0;
1678 }
1679
1680 static int r820t_section(struct r820t_priv *priv,
1681                          struct r820t_sect_type *iq_point)
1682 {
1683         int rc;
1684         struct r820t_sect_type compare_iq[3], compare_bet[3];
1685
1686         /* Try X-1 column and save min result to compare_bet[0] */
1687         if (!(iq_point->gain_x & 0x1f))
1688                 compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1;  /* Q-path, Gain=1 */
1689         else
1690                 compare_iq[0].gain_x  = iq_point->gain_x - 1;  /* left point */
1691         compare_iq[0].phase_y = iq_point->phase_y;
1692
1693         /* y-direction */
1694         rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1695                         compare_iq[0].phase_y, 0x08);
1696         if (rc < 0)
1697                 return rc;
1698
1699         r820t_compre_cor(compare_iq);
1700
1701         compare_bet[0] = compare_iq[0];
1702
1703         /* Try X column and save min result to compare_bet[1] */
1704         compare_iq[0].gain_x  = iq_point->gain_x;
1705         compare_iq[0].phase_y = iq_point->phase_y;
1706
1707         rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1708                            compare_iq[0].phase_y, 0x08);
1709         if (rc < 0)
1710                 return rc;
1711
1712         r820t_compre_cor(compare_iq);
1713
1714         compare_bet[1] = compare_iq[0];
1715
1716         /* Try X+1 column and save min result to compare_bet[2] */
1717         if ((iq_point->gain_x & 0x1f) == 0x00)
1718                 compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1;  /* I-path, Gain=1 */
1719         else
1720                 compare_iq[0].gain_x = iq_point->gain_x + 1;
1721         compare_iq[0].phase_y = iq_point->phase_y;
1722
1723         rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1724                            compare_iq[0].phase_y, 0x08);
1725         if (rc < 0)
1726                 return rc;
1727
1728         r820t_compre_cor(compare_iq);
1729
1730         compare_bet[2] = compare_iq[0];
1731
1732         r820t_compre_cor(compare_bet);
1733
1734         *iq_point = compare_bet[0];
1735
1736         return 0;
1737 }
1738
1739 static int r820t_vga_adjust(struct r820t_priv *priv)
1740 {
1741         int rc;
1742         u8 vga_count;
1743
1744         /* increase vga power to let image significant */
1745         for (vga_count = 12; vga_count < 16; vga_count++) {
1746                 rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f);
1747                 if (rc < 0)
1748                         return rc;
1749
1750                 usleep_range(10000, 11000);
1751
1752                 rc = r820t_multi_read(priv);
1753                 if (rc < 0)
1754                         return rc;
1755
1756                 if (rc > 40 * 4)
1757                         break;
1758         }
1759
1760         return 0;
1761 }
1762
1763 static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1764 {
1765         struct r820t_sect_type compare_iq[3];
1766         int rc;
1767         u8 x_direction = 0;  /* 1:x, 0:y */
1768         u8 dir_reg, other_reg;
1769
1770         r820t_vga_adjust(priv);
1771
1772         rc = r820t_imr_cross(priv, compare_iq, &x_direction);
1773         if (rc < 0)
1774                 return rc;
1775
1776         if (x_direction == 1) {
1777                 dir_reg   = 0x08;
1778                 other_reg = 0x09;
1779         } else {
1780                 dir_reg   = 0x09;
1781                 other_reg = 0x08;
1782         }
1783
1784         /* compare and find min of 3 points. determine i/q direction */
1785         r820t_compre_cor(compare_iq);
1786
1787         /* increase step to find min value of this direction */
1788         rc = r820t_compre_step(priv, compare_iq, dir_reg);
1789         if (rc < 0)
1790                 return rc;
1791
1792         /* the other direction */
1793         rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1794                                 compare_iq[0].phase_y, dir_reg);
1795         if (rc < 0)
1796                 return rc;
1797
1798         /* compare and find min of 3 points. determine i/q direction */
1799         r820t_compre_cor(compare_iq);
1800
1801         /* increase step to find min value on this direction */
1802         rc = r820t_compre_step(priv, compare_iq, other_reg);
1803         if (rc < 0)
1804                 return rc;
1805
1806         /* check 3 points again */
1807         rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1808                                 compare_iq[0].phase_y, other_reg);
1809         if (rc < 0)
1810                 return rc;
1811
1812         r820t_compre_cor(compare_iq);
1813
1814         /* section-9 check */
1815         rc = r820t_section(priv, compare_iq);
1816
1817         *iq_pont = compare_iq[0];
1818
1819         /* reset gain/phase control setting */
1820         rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
1821         if (rc < 0)
1822                 return rc;
1823
1824         rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
1825
1826         return rc;
1827 }
1828
1829 static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1830 {
1831         int rc;
1832
1833         r820t_vga_adjust(priv);
1834
1835         /*
1836          * search surrounding points from previous point
1837          * try (x-1), (x), (x+1) columns, and find min IMR result point
1838          */
1839         rc = r820t_section(priv, iq_pont);
1840         if (rc < 0)
1841                 return rc;
1842
1843         return 0;
1844 }
1845
1846 static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag)
1847 {
1848         struct r820t_sect_type imr_point;
1849         int rc;
1850         u32 ring_vco, ring_freq, ring_ref;
1851         u8 n_ring, n;
1852         int reg18, reg19, reg1f;
1853
1854         if (priv->cfg->xtal > 24000000)
1855                 ring_ref = priv->cfg->xtal / 2;
1856         else
1857                 ring_ref = priv->cfg->xtal;
1858
1859         for (n = 0; n < 16; n++) {
1860                 if ((16 + n) * 8 * ring_ref >= 3100000) {
1861                         n_ring = n;
1862                         break;
1863                 }
1864
1865                 /* n_ring not found */
1866                 if (n == 15)
1867                         n_ring = n;
1868         }
1869
1870         reg18 = r820t_read_cache_reg(priv, 0x18);
1871         reg19 = r820t_read_cache_reg(priv, 0x19);
1872         reg1f = r820t_read_cache_reg(priv, 0x1f);
1873
1874         reg18 &= 0xf0;      /* set ring[3:0] */
1875         reg18 |= n_ring;
1876
1877         ring_vco = (16 + n_ring) * 8 * ring_ref;
1878
1879         reg18 &= 0xdf;   /* clear ring_se23 */
1880         reg19 &= 0xfc;   /* clear ring_seldiv */
1881         reg1f &= 0xfc;   /* clear ring_att */
1882
1883         switch (imr_mem) {
1884         case 0:
1885                 ring_freq = ring_vco / 48;
1886                 reg18 |= 0x20;  /* ring_se23 = 1 */
1887                 reg19 |= 0x03;  /* ring_seldiv = 3 */
1888                 reg1f |= 0x02;  /* ring_att 10 */
1889                 break;
1890         case 1:
1891                 ring_freq = ring_vco / 16;
1892                 reg18 |= 0x00;  /* ring_se23 = 0 */
1893                 reg19 |= 0x02;  /* ring_seldiv = 2 */
1894                 reg1f |= 0x00;  /* pw_ring 00 */
1895                 break;
1896         case 2:
1897                 ring_freq = ring_vco / 8;
1898                 reg18 |= 0x00;  /* ring_se23 = 0 */
1899                 reg19 |= 0x01;  /* ring_seldiv = 1 */
1900                 reg1f |= 0x03;  /* pw_ring 11 */
1901                 break;
1902         case 3:
1903                 ring_freq = ring_vco / 6;
1904                 reg18 |= 0x20;  /* ring_se23 = 1 */
1905                 reg19 |= 0x00;  /* ring_seldiv = 0 */
1906                 reg1f |= 0x03;  /* pw_ring 11 */
1907                 break;
1908         case 4:
1909                 ring_freq = ring_vco / 4;
1910                 reg18 |= 0x00;  /* ring_se23 = 0 */
1911                 reg19 |= 0x00;  /* ring_seldiv = 0 */
1912                 reg1f |= 0x01;  /* pw_ring 01 */
1913                 break;
1914         default:
1915                 ring_freq = ring_vco / 4;
1916                 reg18 |= 0x00;  /* ring_se23 = 0 */
1917                 reg19 |= 0x00;  /* ring_seldiv = 0 */
1918                 reg1f |= 0x01;  /* pw_ring 01 */
1919                 break;
1920         }
1921
1922
1923         /* write pw_ring, n_ring, ringdiv2 registers */
1924
1925         /* n_ring, ring_se23 */
1926         rc = r820t_write_reg(priv, 0x18, reg18);
1927         if (rc < 0)
1928                 return rc;
1929
1930         /* ring_sediv */
1931         rc = r820t_write_reg(priv, 0x19, reg19);
1932         if (rc < 0)
1933                 return rc;
1934
1935         /* pw_ring */
1936         rc = r820t_write_reg(priv, 0x1f, reg1f);
1937         if (rc < 0)
1938                 return rc;
1939
1940         /* mux input freq ~ rf_in freq */
1941         rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000);
1942         if (rc < 0)
1943                 return rc;
1944
1945         rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV,
1946                            (ring_freq - 5300) * 1000);
1947         if (!priv->has_lock)
1948                 rc = -EINVAL;
1949         if (rc < 0)
1950                 return rc;
1951
1952         if (im_flag) {
1953                 rc = r820t_iq(priv, &imr_point);
1954         } else {
1955                 imr_point.gain_x  = priv->imr_data[3].gain_x;
1956                 imr_point.phase_y = priv->imr_data[3].phase_y;
1957                 imr_point.value   = priv->imr_data[3].value;
1958
1959                 rc = r820t_f_imr(priv, &imr_point);
1960         }
1961         if (rc < 0)
1962                 return rc;
1963
1964         /* save IMR value */
1965         switch (imr_mem) {
1966         case 0:
1967                 priv->imr_data[0].gain_x  = imr_point.gain_x;
1968                 priv->imr_data[0].phase_y = imr_point.phase_y;
1969                 priv->imr_data[0].value   = imr_point.value;
1970                 break;
1971         case 1:
1972                 priv->imr_data[1].gain_x  = imr_point.gain_x;
1973                 priv->imr_data[1].phase_y = imr_point.phase_y;
1974                 priv->imr_data[1].value   = imr_point.value;
1975                 break;
1976         case 2:
1977                 priv->imr_data[2].gain_x  = imr_point.gain_x;
1978                 priv->imr_data[2].phase_y = imr_point.phase_y;
1979                 priv->imr_data[2].value   = imr_point.value;
1980                 break;
1981         case 3:
1982                 priv->imr_data[3].gain_x  = imr_point.gain_x;
1983                 priv->imr_data[3].phase_y = imr_point.phase_y;
1984                 priv->imr_data[3].value   = imr_point.value;
1985                 break;
1986         case 4:
1987                 priv->imr_data[4].gain_x  = imr_point.gain_x;
1988                 priv->imr_data[4].phase_y = imr_point.phase_y;
1989                 priv->imr_data[4].value   = imr_point.value;
1990                 break;
1991         default:
1992                 priv->imr_data[4].gain_x  = imr_point.gain_x;
1993                 priv->imr_data[4].phase_y = imr_point.phase_y;
1994                 priv->imr_data[4].value   = imr_point.value;
1995                 break;
1996         }
1997
1998         return 0;
1999 }
2000
2001 static int r820t_imr_callibrate(struct r820t_priv *priv)
2002 {
2003         int rc, i;
2004         int xtal_cap = 0;
2005
2006         if (priv->init_done)
2007                 return 0;
2008
2009         /* Initialize registers */
2010         rc = r820t_write(priv, 0x05,
2011                          r820t_init_array, sizeof(r820t_init_array));
2012         if (rc < 0)
2013                 return rc;
2014
2015         /* Detect Xtal capacitance */
2016         if ((priv->cfg->rafael_chip == CHIP_R820T) ||
2017             (priv->cfg->rafael_chip == CHIP_R828S) ||
2018             (priv->cfg->rafael_chip == CHIP_R820C)) {
2019                 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
2020         } else {
2021                 for (i = 0; i < 3; i++) {
2022                         rc = r820t_xtal_check(priv);
2023                         if (rc < 0)
2024                                 return rc;
2025                         if (!i || rc > xtal_cap)
2026                                 xtal_cap = rc;
2027                 }
2028                 priv->xtal_cap_sel = xtal_cap;
2029         }
2030
2031         /*
2032          * Disables IMR callibration. That emulates the same behaviour
2033          * as what is done by rtl-sdr userspace library. Useful for testing
2034          */
2035         if (no_imr_cal) {
2036                 priv->init_done = true;
2037
2038                 return 0;
2039         }
2040
2041         /* Initialize registers */
2042         rc = r820t_write(priv, 0x05,
2043                          r820t_init_array, sizeof(r820t_init_array));
2044         if (rc < 0)
2045                 return rc;
2046
2047         rc = r820t_imr_prepare(priv);
2048         if (rc < 0)
2049                 return rc;
2050
2051         rc = r820t_imr(priv, 3, true);
2052         if (rc < 0)
2053                 return rc;
2054         rc = r820t_imr(priv, 1, false);
2055         if (rc < 0)
2056                 return rc;
2057         rc = r820t_imr(priv, 0, false);
2058         if (rc < 0)
2059                 return rc;
2060         rc = r820t_imr(priv, 2, false);
2061         if (rc < 0)
2062                 return rc;
2063         rc = r820t_imr(priv, 4, false);
2064         if (rc < 0)
2065                 return rc;
2066
2067         priv->init_done = true;
2068         priv->imr_done = true;
2069
2070         return 0;
2071 }
2072
2073 #if 0
2074 /* Not used, for now */
2075 static int r820t_gpio(struct r820t_priv *priv, bool enable)
2076 {
2077         return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01);
2078 }
2079 #endif
2080
2081 /*
2082  *  r820t frontend operations and tuner attach code
2083  *
2084  * All driver locks and i2c control are only in this part of the code
2085  */
2086
2087 static int r820t_init(struct dvb_frontend *fe)
2088 {
2089         struct r820t_priv *priv = fe->tuner_priv;
2090         int rc;
2091
2092         tuner_dbg("%s:\n", __func__);
2093
2094         mutex_lock(&priv->lock);
2095         if (fe->ops.i2c_gate_ctrl)
2096                 fe->ops.i2c_gate_ctrl(fe, 1);
2097
2098         rc = r820t_imr_callibrate(priv);
2099         if (rc < 0)
2100                 goto err;
2101
2102         /* Initialize registers */
2103         rc = r820t_write(priv, 0x05,
2104                          r820t_init_array, sizeof(r820t_init_array));
2105
2106 err:
2107         if (fe->ops.i2c_gate_ctrl)
2108                 fe->ops.i2c_gate_ctrl(fe, 0);
2109         mutex_unlock(&priv->lock);
2110
2111         if (rc < 0)
2112                 tuner_dbg("%s: failed=%d\n", __func__, rc);
2113         return rc;
2114 }
2115
2116 static int r820t_sleep(struct dvb_frontend *fe)
2117 {
2118         struct r820t_priv *priv = fe->tuner_priv;
2119         int rc;
2120
2121         tuner_dbg("%s:\n", __func__);
2122
2123         mutex_lock(&priv->lock);
2124         if (fe->ops.i2c_gate_ctrl)
2125                 fe->ops.i2c_gate_ctrl(fe, 1);
2126
2127         rc = r820t_standby(priv);
2128
2129         if (fe->ops.i2c_gate_ctrl)
2130                 fe->ops.i2c_gate_ctrl(fe, 0);
2131         mutex_unlock(&priv->lock);
2132
2133         tuner_dbg("%s: failed=%d\n", __func__, rc);
2134         return rc;
2135 }
2136
2137 static int r820t_set_analog_freq(struct dvb_frontend *fe,
2138                                  struct analog_parameters *p)
2139 {
2140         struct r820t_priv *priv = fe->tuner_priv;
2141         unsigned bw;
2142         int rc;
2143
2144         tuner_dbg("%s called\n", __func__);
2145
2146         /* if std is not defined, choose one */
2147         if (!p->std)
2148                 p->std = V4L2_STD_MN;
2149
2150         if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
2151                 bw = 6;
2152         else
2153                 bw = 8;
2154
2155         mutex_lock(&priv->lock);
2156         if (fe->ops.i2c_gate_ctrl)
2157                 fe->ops.i2c_gate_ctrl(fe, 1);
2158
2159         rc = generic_set_freq(fe, 62500l * p->frequency, bw,
2160                               V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
2161
2162         if (fe->ops.i2c_gate_ctrl)
2163                 fe->ops.i2c_gate_ctrl(fe, 0);
2164         mutex_unlock(&priv->lock);
2165
2166         return rc;
2167 }
2168
2169 static int r820t_set_params(struct dvb_frontend *fe)
2170 {
2171         struct r820t_priv *priv = fe->tuner_priv;
2172         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2173         int rc;
2174         unsigned bw;
2175
2176         tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
2177                 __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
2178
2179         mutex_lock(&priv->lock);
2180         if (fe->ops.i2c_gate_ctrl)
2181                 fe->ops.i2c_gate_ctrl(fe, 1);
2182
2183         bw = (c->bandwidth_hz + 500000) / 1000000;
2184         if (!bw)
2185                 bw = 8;
2186
2187         rc = generic_set_freq(fe, c->frequency, bw,
2188                               V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
2189
2190         if (fe->ops.i2c_gate_ctrl)
2191                 fe->ops.i2c_gate_ctrl(fe, 0);
2192         mutex_unlock(&priv->lock);
2193
2194         if (rc)
2195                 tuner_dbg("%s: failed=%d\n", __func__, rc);
2196         return rc;
2197 }
2198
2199 static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
2200 {
2201         struct r820t_priv *priv = fe->tuner_priv;
2202         int rc = 0;
2203
2204         mutex_lock(&priv->lock);
2205         if (fe->ops.i2c_gate_ctrl)
2206                 fe->ops.i2c_gate_ctrl(fe, 1);
2207
2208         if (priv->has_lock) {
2209                 rc = r820t_read_gain(priv);
2210                 if (rc < 0)
2211                         goto err;
2212
2213                 /* A higher gain at LNA means a lower signal strength */
2214                 *strength = (45 - rc) << 4 | 0xff;
2215                 if (*strength == 0xff)
2216                         *strength = 0;
2217         } else {
2218                 *strength = 0;
2219         }
2220
2221 err:
2222         if (fe->ops.i2c_gate_ctrl)
2223                 fe->ops.i2c_gate_ctrl(fe, 0);
2224         mutex_unlock(&priv->lock);
2225
2226         tuner_dbg("%s: %s, gain=%d strength=%d\n",
2227                   __func__,
2228                   priv->has_lock ? "PLL locked" : "no signal",
2229                   rc, *strength);
2230
2231         return 0;
2232 }
2233
2234 static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
2235 {
2236         struct r820t_priv *priv = fe->tuner_priv;
2237
2238         tuner_dbg("%s:\n", __func__);
2239
2240         *frequency = priv->int_freq;
2241
2242         return 0;
2243 }
2244
2245 static int r820t_release(struct dvb_frontend *fe)
2246 {
2247         struct r820t_priv *priv = fe->tuner_priv;
2248
2249         tuner_dbg("%s:\n", __func__);
2250
2251         mutex_lock(&r820t_list_mutex);
2252
2253         if (priv)
2254                 hybrid_tuner_release_state(priv);
2255
2256         mutex_unlock(&r820t_list_mutex);
2257
2258         fe->tuner_priv = NULL;
2259
2260         kfree(fe->tuner_priv);
2261
2262         return 0;
2263 }
2264
2265 static const struct dvb_tuner_ops r820t_tuner_ops = {
2266         .info = {
2267                 .name           = "Rafael Micro R820T",
2268                 .frequency_min  =   42000000,
2269                 .frequency_max  = 1002000000,
2270         },
2271         .init = r820t_init,
2272         .release = r820t_release,
2273         .sleep = r820t_sleep,
2274         .set_params = r820t_set_params,
2275         .set_analog_params = r820t_set_analog_freq,
2276         .get_if_frequency = r820t_get_if_frequency,
2277         .get_rf_strength = r820t_signal,
2278 };
2279
2280 struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
2281                                   struct i2c_adapter *i2c,
2282                                   const struct r820t_config *cfg)
2283 {
2284         struct r820t_priv *priv;
2285         int rc = -ENODEV;
2286         u8 data[5];
2287         int instance;
2288
2289         mutex_lock(&r820t_list_mutex);
2290
2291         instance = hybrid_tuner_request_state(struct r820t_priv, priv,
2292                                               hybrid_tuner_instance_list,
2293                                               i2c, cfg->i2c_addr,
2294                                               "r820t");
2295         switch (instance) {
2296         case 0:
2297                 /* memory allocation failure */
2298                 goto err_no_gate;
2299                 break;
2300         case 1:
2301                 /* new tuner instance */
2302                 priv->cfg = cfg;
2303
2304                 mutex_init(&priv->lock);
2305
2306                 fe->tuner_priv = priv;
2307                 break;
2308         case 2:
2309                 /* existing tuner instance */
2310                 fe->tuner_priv = priv;
2311                 break;
2312         }
2313
2314         memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops, sizeof(r820t_tuner_ops));
2315
2316         if (fe->ops.i2c_gate_ctrl)
2317                 fe->ops.i2c_gate_ctrl(fe, 1);
2318
2319         /* check if the tuner is there */
2320         rc = r820t_read(priv, 0x00, data, sizeof(data));
2321         if (rc < 0)
2322                 goto err;
2323
2324         rc = r820t_sleep(fe);
2325         if (rc < 0)
2326                 goto err;
2327
2328         tuner_info("Rafael Micro r820t successfully identified\n");
2329
2330         fe->tuner_priv = priv;
2331         memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
2332                         sizeof(struct dvb_tuner_ops));
2333
2334         if (fe->ops.i2c_gate_ctrl)
2335                 fe->ops.i2c_gate_ctrl(fe, 0);
2336
2337         mutex_unlock(&r820t_list_mutex);
2338
2339         return fe;
2340 err:
2341         if (fe->ops.i2c_gate_ctrl)
2342                 fe->ops.i2c_gate_ctrl(fe, 0);
2343
2344 err_no_gate:
2345         mutex_unlock(&r820t_list_mutex);
2346
2347         tuner_info("%s: failed=%d\n", __func__, rc);
2348         r820t_release(fe);
2349         return NULL;
2350 }
2351 EXPORT_SYMBOL_GPL(r820t_attach);
2352
2353 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
2354 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2355 MODULE_LICENSE("GPL");