2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
7 This program contains the specific code to control the avdecoder chip and
8 other related usb control functions for cx231xx based chipset.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/bitmap.h>
30 #include <linux/usb.h>
31 #include <linux/i2c.h>
33 #include <linux/mutex.h>
34 #include <media/tuner.h>
36 #include <media/v4l2-common.h>
37 #include <media/v4l2-ioctl.h>
38 #include <media/v4l2-chip-ident.h>
41 #include "cx231xx-dif.h"
43 #define TUNER_MODE_FM_RADIO 0
44 /******************************************************************************
45 -: BLOCK ARRANGEMENT :-
46 I2S block ----------------------|
49 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
50 [video & audio] | [Audio]
55 *******************************************************************************/
56 /******************************************************************************
59 ******************************************************************************/
60 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
62 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
66 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
71 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
76 void initGPIO(struct cx231xx *dev)
78 u32 _gpio_direction = 0;
82 _gpio_direction = _gpio_direction & 0xFC0003FF;
83 _gpio_direction = _gpio_direction | 0x03FDFC00;
84 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
86 verve_read_byte(dev, 0x07, &val);
87 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
88 verve_write_byte(dev, 0x07, 0xF4);
89 verve_read_byte(dev, 0x07, &val);
90 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
92 cx231xx_capture_start(dev, 1, 2);
94 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
95 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
98 void uninitGPIO(struct cx231xx *dev)
100 u8 value[4] = { 0, 0, 0, 0 };
102 cx231xx_capture_start(dev, 0, 2);
103 verve_write_byte(dev, 0x07, 0x14);
104 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
108 /******************************************************************************
109 * A F E - B L O C K C O N T R O L functions *
110 * [ANALOG FRONT END] *
111 ******************************************************************************/
112 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
114 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
118 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
123 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
129 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
133 u8 afe_power_status = 0;
136 /* super block initialize */
137 temp = (u8) (ref_count & 0xff);
138 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
142 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
146 temp = (u8) ((ref_count & 0x300) >> 8);
148 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
152 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
157 while (afe_power_status != 0x18) {
158 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
161 ": Init Super Block failed in send cmd\n");
165 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
166 afe_power_status &= 0xff;
169 ": Init Super Block failed in receive cmd\n");
175 ": Init Super Block force break in loop !!!!\n");
184 /* start tuning filter */
185 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
192 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
197 int cx231xx_afe_init_channels(struct cx231xx *dev)
201 /* power up all 3 channels, clear pd_buffer */
202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
204 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
206 /* Enable quantizer calibration */
207 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
209 /* channel initialize, force modulator (fb) reset */
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
214 /* start quantilizer calibration */
215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
217 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
220 /* exit modulator (fb) reset */
221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
223 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
225 /* enable the pre_clamp in each channel for single-ended input */
226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
228 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
230 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
231 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
232 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
233 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
234 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
235 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
236 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
238 /* dynamic element matching off */
239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
241 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
246 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
251 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
252 c_value &= (~(0x50));
253 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
259 The Analog Front End in Cx231xx has 3 channels. These
260 channels are used to share between different inputs
261 like tuner, s-video and composite inputs.
263 channel 1 ----- pin 1 to pin4(in reg is 1-4)
264 channel 2 ----- pin 5 to pin8(in reg is 5-8)
265 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
267 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
269 u8 ch1_setting = (u8) input_mux;
270 u8 ch2_setting = (u8) (input_mux >> 8);
271 u8 ch3_setting = (u8) (input_mux >> 16);
275 if (ch1_setting != 0) {
276 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
277 value &= (!INPUT_SEL_MASK);
278 value |= (ch1_setting - 1) << 4;
280 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
283 if (ch2_setting != 0) {
284 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
285 value &= (!INPUT_SEL_MASK);
286 value |= (ch2_setting - 1) << 4;
288 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
291 /* For ch3_setting, the value to put in the register is
292 7 less than the input number */
293 if (ch3_setting != 0) {
294 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
295 value &= (!INPUT_SEL_MASK);
296 value |= (ch3_setting - 1) << 4;
298 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
304 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
309 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
310 * Currently, only baseband works.
314 case AFE_MODE_LOW_IF:
315 cx231xx_Setup_AFE_for_LowIF(dev);
317 case AFE_MODE_BASEBAND:
318 status = cx231xx_afe_setup_AFE_for_baseband(dev);
320 case AFE_MODE_EU_HI_IF:
321 /* SetupAFEforEuHiIF(); */
323 case AFE_MODE_US_HI_IF:
324 /* SetupAFEforUsHiIF(); */
326 case AFE_MODE_JAPAN_HI_IF:
327 /* SetupAFEforJapanHiIF(); */
331 if ((mode != dev->afe_mode) &&
332 (dev->video_input == CX231XX_VMUX_TELEVISION))
333 status = cx231xx_afe_adjust_ref_count(dev,
334 CX231XX_VMUX_TELEVISION);
336 dev->afe_mode = mode;
341 int cx231xx_afe_update_power_control(struct cx231xx *dev,
344 u8 afe_power_status = 0;
347 switch (dev->model) {
348 case CX231XX_BOARD_CNXT_CARRAERA:
349 case CX231XX_BOARD_CNXT_RDE_250:
350 case CX231XX_BOARD_CNXT_SHELBY:
351 case CX231XX_BOARD_CNXT_RDU_250:
352 case CX231XX_BOARD_CNXT_RDE_253S:
353 case CX231XX_BOARD_CNXT_RDU_253S:
354 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
355 case CX231XX_BOARD_HAUPPAUGE_EXETER:
356 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
357 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
358 FLD_PWRDN_ENABLE_PLL)) {
359 status = afe_write_byte(dev, SUP_BLK_PWRDN,
360 FLD_PWRDN_TUNING_BIAS |
361 FLD_PWRDN_ENABLE_PLL);
362 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
368 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
370 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
372 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
374 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
375 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
377 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
379 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
382 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
384 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
387 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
389 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
390 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
391 FLD_PWRDN_ENABLE_PLL)) {
392 status = afe_write_byte(dev, SUP_BLK_PWRDN,
393 FLD_PWRDN_TUNING_BIAS |
394 FLD_PWRDN_ENABLE_PLL);
395 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
401 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
403 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
405 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
408 cx231xx_info("Invalid AV mode input\n");
413 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
414 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
415 FLD_PWRDN_ENABLE_PLL)) {
416 status = afe_write_byte(dev, SUP_BLK_PWRDN,
417 FLD_PWRDN_TUNING_BIAS |
418 FLD_PWRDN_ENABLE_PLL);
419 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
425 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
427 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
429 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
431 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
432 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
434 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
436 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
439 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
441 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
444 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
446 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
447 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
448 FLD_PWRDN_ENABLE_PLL)) {
449 status = afe_write_byte(dev, SUP_BLK_PWRDN,
450 FLD_PWRDN_TUNING_BIAS |
451 FLD_PWRDN_ENABLE_PLL);
452 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
458 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
460 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
462 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
465 cx231xx_info("Invalid AV mode input\n");
473 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
479 dev->video_input = video_input;
481 if (video_input == CX231XX_VMUX_TELEVISION) {
482 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
483 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
486 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
487 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
491 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
493 switch (input_mode) {
495 dev->afe_ref_count = 0x23C;
498 dev->afe_ref_count = 0x24C;
501 dev->afe_ref_count = 0x258;
504 dev->afe_ref_count = 0x260;
510 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
515 /******************************************************************************
516 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
517 ******************************************************************************/
518 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
520 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
524 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
529 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
535 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
537 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
541 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
543 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
546 int cx231xx_check_fw(struct cx231xx *dev)
550 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
558 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
562 switch (INPUT(input)->type) {
563 case CX231XX_VMUX_COMPOSITE1:
564 case CX231XX_VMUX_SVIDEO:
565 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
566 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
568 status = cx231xx_set_power_mode(dev,
569 POLARIS_AVMODE_ENXTERNAL_AV);
571 cx231xx_errdev("%s: set_power_mode : Failed to"
572 " set Power - errCode [%d]!\n",
577 status = cx231xx_set_decoder_video_input(dev,
581 case CX231XX_VMUX_TELEVISION:
582 case CX231XX_VMUX_CABLE:
583 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
584 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
586 status = cx231xx_set_power_mode(dev,
587 POLARIS_AVMODE_ANALOGT_TV);
589 cx231xx_errdev("%s: set_power_mode:Failed"
590 " to set Power - errCode [%d]!\n",
595 if (dev->tuner_type == TUNER_NXP_TDA18271)
596 status = cx231xx_set_decoder_video_input(dev,
597 CX231XX_VMUX_TELEVISION,
600 status = cx231xx_set_decoder_video_input(dev,
601 CX231XX_VMUX_COMPOSITE1,
606 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
607 __func__, INPUT(input)->type);
611 /* save the selection */
612 dev->video_input = input;
617 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
618 u8 pin_type, u8 input)
623 if (pin_type != dev->video_input) {
624 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
626 cx231xx_errdev("%s: adjust_ref_count :Failed to set"
627 "AFE input mux - errCode [%d]!\n",
633 /* call afe block to set video inputs */
634 status = cx231xx_afe_set_input_mux(dev, input);
636 cx231xx_errdev("%s: set_input_mux :Failed to set"
637 " AFE input mux - errCode [%d]!\n",
643 case CX231XX_VMUX_COMPOSITE1:
644 status = vid_blk_read_word(dev, AFE_CTRL, &value);
645 value |= (0 << 13) | (1 << 4);
648 /* set [24:23] [22:15] to 0 */
649 value &= (~(0x1ff8000));
650 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
652 status = vid_blk_write_word(dev, AFE_CTRL, value);
654 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
656 status = vid_blk_write_word(dev, OUT_CTRL1, value);
658 /* Set vip 1.1 output mode */
659 status = cx231xx_read_modify_write_i2c_dword(dev,
665 /* Tell DIF object to go to baseband mode */
666 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
668 cx231xx_errdev("%s: cx231xx_dif set to By pass"
669 " mode- errCode [%d]!\n",
674 /* Read the DFE_CTRL1 register */
675 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
677 /* enable the VBI_GATE_EN */
678 value |= FLD_VBI_GATE_EN;
680 /* Enable the auto-VGA enable */
681 value |= FLD_VGA_AUTO_EN;
684 status = vid_blk_write_word(dev, DFE_CTRL1, value);
686 /* Disable auto config of registers */
687 status = cx231xx_read_modify_write_i2c_dword(dev,
689 MODE_CTRL, FLD_ACFG_DIS,
690 cx231xx_set_field(FLD_ACFG_DIS, 1));
692 /* Set CVBS input mode */
693 status = cx231xx_read_modify_write_i2c_dword(dev,
695 MODE_CTRL, FLD_INPUT_MODE,
696 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
698 case CX231XX_VMUX_SVIDEO:
699 /* Disable the use of DIF */
701 status = vid_blk_read_word(dev, AFE_CTRL, &value);
703 /* set [24:23] [22:15] to 0 */
704 value &= (~(0x1ff8000));
705 /* set FUNC_MODE[24:23] = 2
706 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
708 status = vid_blk_write_word(dev, AFE_CTRL, value);
710 /* Tell DIF object to go to baseband mode */
711 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
713 cx231xx_errdev("%s: cx231xx_dif set to By pass"
714 " mode- errCode [%d]!\n",
719 /* Read the DFE_CTRL1 register */
720 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
722 /* enable the VBI_GATE_EN */
723 value |= FLD_VBI_GATE_EN;
725 /* Enable the auto-VGA enable */
726 value |= FLD_VGA_AUTO_EN;
729 status = vid_blk_write_word(dev, DFE_CTRL1, value);
731 /* Disable auto config of registers */
732 status = cx231xx_read_modify_write_i2c_dword(dev,
734 MODE_CTRL, FLD_ACFG_DIS,
735 cx231xx_set_field(FLD_ACFG_DIS, 1));
737 /* Set YC input mode */
738 status = cx231xx_read_modify_write_i2c_dword(dev,
742 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
745 status = vid_blk_read_word(dev, AFE_CTRL, &value);
746 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
748 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
749 This sets them to use video
750 rather than audio. Only one of the two will be in use. */
751 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
753 status = vid_blk_write_word(dev, AFE_CTRL, value);
755 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
757 case CX231XX_VMUX_TELEVISION:
758 case CX231XX_VMUX_CABLE:
760 switch (dev->model) {
761 case CX231XX_BOARD_CNXT_CARRAERA:
762 case CX231XX_BOARD_CNXT_RDE_250:
763 case CX231XX_BOARD_CNXT_SHELBY:
764 case CX231XX_BOARD_CNXT_RDU_250:
765 /* Disable the use of DIF */
767 status = vid_blk_read_word(dev, AFE_CTRL, &value);
768 value |= (0 << 13) | (1 << 4);
771 /* set [24:23] [22:15] to 0 */
772 value &= (~(0x1FF8000));
773 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
775 status = vid_blk_write_word(dev, AFE_CTRL, value);
777 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
779 status = vid_blk_write_word(dev, OUT_CTRL1, value);
781 /* Set vip 1.1 output mode */
782 status = cx231xx_read_modify_write_i2c_dword(dev,
784 OUT_CTRL1, FLD_OUT_MODE,
787 /* Tell DIF object to go to baseband mode */
788 status = cx231xx_dif_set_standard(dev,
791 cx231xx_errdev("%s: cx231xx_dif set to By pass"
792 " mode- errCode [%d]!\n",
797 /* Read the DFE_CTRL1 register */
798 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
800 /* enable the VBI_GATE_EN */
801 value |= FLD_VBI_GATE_EN;
803 /* Enable the auto-VGA enable */
804 value |= FLD_VGA_AUTO_EN;
807 status = vid_blk_write_word(dev, DFE_CTRL1, value);
809 /* Disable auto config of registers */
810 status = cx231xx_read_modify_write_i2c_dword(dev,
812 MODE_CTRL, FLD_ACFG_DIS,
813 cx231xx_set_field(FLD_ACFG_DIS, 1));
815 /* Set CVBS input mode */
816 status = cx231xx_read_modify_write_i2c_dword(dev,
818 MODE_CTRL, FLD_INPUT_MODE,
819 cx231xx_set_field(FLD_INPUT_MODE,
823 /* Enable the DIF for the tuner */
825 /* Reinitialize the DIF */
826 status = cx231xx_dif_set_standard(dev, dev->norm);
828 cx231xx_errdev("%s: cx231xx_dif set to By pass"
829 " mode- errCode [%d]!\n",
834 /* Make sure bypass is cleared */
835 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
837 /* Clear the bypass bit */
838 value &= ~FLD_DIF_DIF_BYPASS;
840 /* Enable the use of the DIF block */
841 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
843 /* Read the DFE_CTRL1 register */
844 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
846 /* Disable the VBI_GATE_EN */
847 value &= ~FLD_VBI_GATE_EN;
849 /* Enable the auto-VGA enable, AGC, and
850 set the skip count to 2 */
851 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
854 status = vid_blk_write_word(dev, DFE_CTRL1, value);
856 /* Wait until AGC locks up */
859 /* Disable the auto-VGA enable AGC */
860 value &= ~(FLD_VGA_AUTO_EN);
863 status = vid_blk_write_word(dev, DFE_CTRL1, value);
865 /* Enable Polaris B0 AGC output */
866 status = vid_blk_read_word(dev, PIN_CTRL, &value);
867 value |= (FLD_OEF_AGC_RF) |
868 (FLD_OEF_AGC_IFVGA) |
870 status = vid_blk_write_word(dev, PIN_CTRL, value);
872 /* Set vip 1.1 output mode */
873 status = cx231xx_read_modify_write_i2c_dword(dev,
875 OUT_CTRL1, FLD_OUT_MODE,
878 /* Disable auto config of registers */
879 status = cx231xx_read_modify_write_i2c_dword(dev,
881 MODE_CTRL, FLD_ACFG_DIS,
882 cx231xx_set_field(FLD_ACFG_DIS, 1));
884 /* Set CVBS input mode */
885 status = cx231xx_read_modify_write_i2c_dword(dev,
887 MODE_CTRL, FLD_INPUT_MODE,
888 cx231xx_set_field(FLD_INPUT_MODE,
891 /* Set some bits in AFE_CTRL so that channel 2 or 3
892 * is ready to receive audio */
893 /* Clear clamp for channels 2 and 3 (bit 16-17) */
894 /* Clear droop comp (bit 19-20) */
895 /* Set VGA_SEL (for audio control) (bit 7-8) */
896 status = vid_blk_read_word(dev, AFE_CTRL, &value);
898 /*Set Func mode:01-DIF 10-baseband 11-YUV*/
899 value &= (~(FLD_FUNC_MODE));
902 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
904 status = vid_blk_write_word(dev, AFE_CTRL, value);
906 if (dev->tuner_type == TUNER_NXP_TDA18271) {
907 status = vid_blk_read_word(dev, PIN_CTRL,
909 status = vid_blk_write_word(dev, PIN_CTRL,
910 (value & 0xFFFFFFEF));
919 /* Set raw VBI mode */
920 status = cx231xx_read_modify_write_i2c_dword(dev,
922 OUT_CTRL1, FLD_VBIHACTRAW_EN,
923 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
925 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
928 status = vid_blk_write_word(dev, OUT_CTRL1, value);
934 void cx231xx_enable656(struct cx231xx *dev)
938 /*enable TS1 data[0:7] as output to export 656*/
940 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
942 /*enable TS1 clock as output to export 656*/
944 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
947 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
950 EXPORT_SYMBOL_GPL(cx231xx_enable656);
952 void cx231xx_disable656(struct cx231xx *dev)
958 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
960 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
963 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
965 EXPORT_SYMBOL_GPL(cx231xx_disable656);
968 * Handle any video-mode specific overrides that are different
969 * on a per video standards basis after touching the MODE_CTRL
970 * register which resets many values for autodetect
972 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
976 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
977 (unsigned int)dev->norm);
979 /* Change the DFE_CTRL3 bp_percent to fix flagging */
980 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
982 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
983 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
985 /* Move the close caption lines out of active video,
986 adjust the active video start point */
987 status = cx231xx_read_modify_write_i2c_dword(dev,
990 FLD_VBLANK_CNT, 0x18);
991 status = cx231xx_read_modify_write_i2c_dword(dev,
996 status = cx231xx_read_modify_write_i2c_dword(dev,
1002 status = cx231xx_read_modify_write_i2c_dword(dev,
1003 VID_BLK_I2C_ADDRESS,
1007 (FLD_HBLANK_CNT, 0x79));
1009 } else if (dev->norm & V4L2_STD_SECAM) {
1010 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1011 status = cx231xx_read_modify_write_i2c_dword(dev,
1012 VID_BLK_I2C_ADDRESS,
1014 FLD_VBLANK_CNT, 0x24);
1015 status = cx231xx_read_modify_write_i2c_dword(dev,
1016 VID_BLK_I2C_ADDRESS,
1022 /* Adjust the active video horizontal start point */
1023 status = cx231xx_read_modify_write_i2c_dword(dev,
1024 VID_BLK_I2C_ADDRESS,
1028 (FLD_HBLANK_CNT, 0x85));
1030 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1031 status = cx231xx_read_modify_write_i2c_dword(dev,
1032 VID_BLK_I2C_ADDRESS,
1034 FLD_VBLANK_CNT, 0x24);
1035 status = cx231xx_read_modify_write_i2c_dword(dev,
1036 VID_BLK_I2C_ADDRESS,
1042 /* Adjust the active video horizontal start point */
1043 status = cx231xx_read_modify_write_i2c_dword(dev,
1044 VID_BLK_I2C_ADDRESS,
1048 (FLD_HBLANK_CNT, 0x85));
1055 int cx231xx_unmute_audio(struct cx231xx *dev)
1057 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1059 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1061 int stopAudioFirmware(struct cx231xx *dev)
1063 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1066 int restartAudioFirmware(struct cx231xx *dev)
1068 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1071 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1074 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1076 switch (INPUT(input)->amux) {
1077 case CX231XX_AMUX_VIDEO:
1078 ainput = AUDIO_INPUT_TUNER_TV;
1080 case CX231XX_AMUX_LINE_IN:
1081 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1082 ainput = AUDIO_INPUT_LINE;
1088 status = cx231xx_set_audio_decoder_input(dev, ainput);
1093 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1094 enum AUDIO_INPUT audio_input)
1101 /* Put it in soft reset */
1102 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1104 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1106 switch (audio_input) {
1107 case AUDIO_INPUT_LINE:
1108 /* setup AUD_IO control from Merlin paralle output */
1109 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1110 AUD_CHAN_SRC_PARALLEL);
1111 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1113 /* setup input to Merlin, SRC2 connect to AC97
1114 bypass upsample-by-2, slave mode, sony mode, left justify
1115 adr 091c, dat 01000000 */
1116 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1118 status = vid_blk_write_word(dev, AC97_CTL,
1119 (dwval | FLD_AC97_UP2X_BYPASS));
1121 /* select the parallel1 and SRC3 */
1122 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1123 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1124 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1125 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1127 /* unmute all, AC97 in, independence mode
1128 adr 08d0, data 0x00063073 */
1129 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1130 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1132 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1133 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1134 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1135 (dwval | FLD_PATH1_AVC_THRESHOLD));
1137 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1138 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1139 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1140 (dwval | FLD_PATH1_SC_THRESHOLD));
1143 case AUDIO_INPUT_TUNER_TV:
1145 status = stopAudioFirmware(dev);
1146 /* Setup SRC sources and clocks */
1147 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1148 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1149 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1150 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
1151 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
1152 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
1153 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
1154 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
1155 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1156 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1157 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1158 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1159 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1160 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1162 /* Setup the AUD_IO control */
1163 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1164 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1165 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1166 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1167 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1168 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1170 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1172 /* setAudioStandard(_audio_standard); */
1173 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1175 status = restartAudioFirmware(dev);
1177 switch (dev->model) {
1178 case CX231XX_BOARD_CNXT_CARRAERA:
1179 case CX231XX_BOARD_CNXT_RDE_250:
1180 case CX231XX_BOARD_CNXT_SHELBY:
1181 case CX231XX_BOARD_CNXT_RDU_250:
1182 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1183 status = cx231xx_read_modify_write_i2c_dword(dev,
1184 VID_BLK_I2C_ADDRESS,
1187 cx231xx_set_field(FLD_SIF_EN, 1));
1189 case CX231XX_BOARD_CNXT_RDE_253S:
1190 case CX231XX_BOARD_CNXT_RDU_253S:
1191 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1192 status = cx231xx_read_modify_write_i2c_dword(dev,
1193 VID_BLK_I2C_ADDRESS,
1196 cx231xx_set_field(FLD_SIF_EN, 0));
1203 case AUDIO_INPUT_TUNER_FM:
1204 /* use SIF for FM radio
1206 setAudioStandard(_audio_standard);
1210 case AUDIO_INPUT_MUTE:
1211 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1215 /* Take it out of soft reset */
1216 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1218 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1223 /******************************************************************************
1224 * C H I P Specific C O N T R O L functions *
1225 ******************************************************************************/
1226 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1231 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1232 value |= (~dev->board.ctl_pin_status_mask);
1233 status = vid_blk_write_word(dev, PIN_CTRL, value);
1238 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1239 u8 analog_or_digital)
1243 /* first set the direction to output */
1244 status = cx231xx_set_gpio_direction(dev,
1246 agc_analog_digital_select_gpio, 1);
1248 /* 0 - demod ; 1 - Analog mode */
1249 status = cx231xx_set_gpio_value(dev,
1250 dev->board.agc_analog_digital_select_gpio,
1256 int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1258 u8 value[4] = { 0, 0, 0, 0 };
1261 cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1263 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1264 PWR_CTL_EN, value, 4);
1268 if (I2CIndex == I2C_1) {
1269 if (value[0] & I2C_DEMOD_EN) {
1270 value[0] &= ~I2C_DEMOD_EN;
1271 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1272 PWR_CTL_EN, value, 4);
1275 if (!(value[0] & I2C_DEMOD_EN)) {
1276 value[0] |= I2C_DEMOD_EN;
1277 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1278 PWR_CTL_EN, value, 4);
1285 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_for_tuner);
1286 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1292 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1293 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1294 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1296 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1297 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1298 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1302 void cx231xx_dump_HH_reg(struct cx231xx *dev)
1309 status = vid_blk_write_word(dev, 0x104, value);
1311 for (i = 0x100; i < 0x140; i++) {
1312 status = vid_blk_read_word(dev, i, &value);
1313 cx231xx_info("reg0x%x=0x%x\n", i, value);
1317 for (i = 0x300; i < 0x400; i++) {
1318 status = vid_blk_read_word(dev, i, &value);
1319 cx231xx_info("reg0x%x=0x%x\n", i, value);
1323 for (i = 0x400; i < 0x440; i++) {
1324 status = vid_blk_read_word(dev, i, &value);
1325 cx231xx_info("reg0x%x=0x%x\n", i, value);
1329 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1330 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1331 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1332 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1333 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1336 void cx231xx_dump_SC_reg(struct cx231xx *dev)
1338 u8 value[4] = { 0, 0, 0, 0 };
1340 cx231xx_info("cx231xx_dump_SC_reg %s!\n", __TIME__);
1342 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1344 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1345 value[1], value[2], value[3]);
1346 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1348 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1349 value[1], value[2], value[3]);
1350 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1352 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1353 value[1], value[2], value[3]);
1354 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1356 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1357 value[1], value[2], value[3]);
1359 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1361 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1362 value[1], value[2], value[3]);
1363 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1365 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1366 value[1], value[2], value[3]);
1367 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1369 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1370 value[1], value[2], value[3]);
1371 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1373 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1374 value[1], value[2], value[3]);
1376 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1378 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1379 value[1], value[2], value[3]);
1380 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1382 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1383 value[1], value[2], value[3]);
1384 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1386 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1387 value[1], value[2], value[3]);
1388 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1390 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1391 value[1], value[2], value[3]);
1393 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1395 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1396 value[1], value[2], value[3]);
1397 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1399 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1400 value[1], value[2], value[3]);
1401 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1403 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1404 value[1], value[2], value[3]);
1405 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1407 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1408 value[1], value[2], value[3]);
1410 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1412 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1413 value[1], value[2], value[3]);
1414 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1416 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1417 value[1], value[2], value[3]);
1422 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1430 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1431 value = (value & 0xFE)|0x01;
1432 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1434 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1435 value = (value & 0xFE)|0x00;
1436 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1440 config colibri to lo-if mode
1442 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1443 the diff IF input by half,
1445 for low-if agc defect
1448 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1449 value = (value & 0xFC)|0x00;
1450 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1452 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
1453 value = (value & 0xF9)|0x02;
1454 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
1456 status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1457 value = (value & 0xFB)|0x04;
1458 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1460 status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1461 value = (value & 0xFC)|0x03;
1462 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1464 status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1465 value = (value & 0xFB)|0x04;
1466 status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1468 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1469 value = (value & 0xF8)|0x06;
1470 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1472 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1473 value = (value & 0x8F)|0x40;
1474 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1476 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1477 value = (value & 0xDF)|0x20;
1478 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1481 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1482 u8 spectral_invert, u32 mode)
1485 u32 colibri_carrier_offset = 0;
1489 u8 value[4] = { 0, 0, 0, 0 };
1491 switch (dev->model) {
1492 case CX231XX_BOARD_CNXT_CARRAERA:
1493 case CX231XX_BOARD_CNXT_RDE_250:
1494 case CX231XX_BOARD_CNXT_SHELBY:
1495 case CX231XX_BOARD_CNXT_RDU_250:
1496 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1499 case CX231XX_BOARD_CNXT_RDE_253S:
1500 case CX231XX_BOARD_CNXT_RDU_253S:
1508 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
1509 value[0] = (u8) 0x6F;
1510 value[1] = (u8) 0x6F;
1511 value[2] = (u8) 0x6F;
1512 value[3] = (u8) 0x6F;
1513 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1514 PWR_CTL_EN, value, 4);
1517 /*Set colibri for low IF*/
1518 status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1521 /* Set C2HH for low IF operation.*/
1522 standard = dev->norm;
1523 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1524 func_mode, standard);
1527 /* Get colibri offsets.*/
1528 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1531 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
1532 colibri_carrier_offset, standard);
1534 /* Set the band Pass filter for DIF*/
1535 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset)
1536 , spectral_invert, mode);
1540 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1542 u32 colibri_carrier_offset = 0;
1545 if (mode == TUNER_MODE_FM_RADIO) {
1546 colibri_carrier_offset = 1100000;
1547 } else if (standerd & (V4L2_STD_NTSC | V4L2_STD_NTSC_M_JP)) {
1548 colibri_carrier_offset = 4832000; /*4.83MHz */
1549 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1550 colibri_carrier_offset = 2700000; /*2.70MHz */
1551 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1552 | V4L2_STD_SECAM)) {
1553 colibri_carrier_offset = 2100000; /*2.10MHz */
1557 return colibri_carrier_offset;
1560 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1561 u8 spectral_invert, u32 mode)
1564 unsigned long pll_freq_word;
1566 u32 dif_misc_ctrl_value = 0;
1567 u64 pll_freq_u64 = 0;
1571 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1572 if_freq, spectral_invert, mode);
1575 if (mode == TUNER_MODE_FM_RADIO) {
1576 pll_freq_word = 0x905A1CAC;
1577 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1579 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1580 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1581 pll_freq_word = if_freq;
1582 pll_freq_u64 = (u64)pll_freq_word << 28L;
1583 do_div(pll_freq_u64, 50000000);
1584 pll_freq_word = (u32)pll_freq_u64;
1585 /*pll_freq_word = 0x3463497;*/
1586 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1588 if (spectral_invert) {
1590 /* Enable Spectral Invert*/
1591 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1592 &dif_misc_ctrl_value);
1593 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1594 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1595 dif_misc_ctrl_value);
1598 /* Disable Spectral Invert*/
1599 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1600 &dif_misc_ctrl_value);
1601 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1602 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1603 dif_misc_ctrl_value);
1606 if_freq = (if_freq/100000)*100000;
1608 if (if_freq < 3000000)
1611 if (if_freq > 16000000)
1615 cx231xx_info("Enter IF=%d\n",
1616 sizeof(Dif_set_array)/sizeof(struct dif_settings));
1617 for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
1618 if (Dif_set_array[i].if_freq == if_freq) {
1619 status = vid_blk_write_word(dev,
1620 Dif_set_array[i].register_address, Dif_set_array[i].value);
1626 /******************************************************************************
1627 * D I F - B L O C K C O N T R O L functions *
1628 ******************************************************************************/
1629 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1630 u32 function_mode, u32 standard)
1635 if (mode == V4L2_TUNER_RADIO) {
1637 /* lo if big signal */
1638 status = cx231xx_reg_mask_write(dev,
1639 VID_BLK_I2C_ADDRESS, 32,
1640 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1641 /* FUNC_MODE = DIF */
1642 status = cx231xx_reg_mask_write(dev,
1643 VID_BLK_I2C_ADDRESS, 32,
1644 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1646 status = cx231xx_reg_mask_write(dev,
1647 VID_BLK_I2C_ADDRESS, 32,
1648 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1650 status = cx231xx_reg_mask_write(dev,
1651 VID_BLK_I2C_ADDRESS, 32,
1652 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1653 } else if (standard != DIF_USE_BASEBAND) {
1654 if (standard & V4L2_STD_MN) {
1655 /* lo if big signal */
1656 status = cx231xx_reg_mask_write(dev,
1657 VID_BLK_I2C_ADDRESS, 32,
1658 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1659 /* FUNC_MODE = DIF */
1660 status = cx231xx_reg_mask_write(dev,
1661 VID_BLK_I2C_ADDRESS, 32,
1662 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1665 status = cx231xx_reg_mask_write(dev,
1666 VID_BLK_I2C_ADDRESS, 32,
1667 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1669 status = cx231xx_reg_mask_write(dev,
1670 VID_BLK_I2C_ADDRESS, 32,
1671 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1672 /* 0x124, AUD_CHAN1_SRC = 0x3 */
1673 status = cx231xx_reg_mask_write(dev,
1674 VID_BLK_I2C_ADDRESS, 32,
1675 AUD_IO_CTRL, 0, 31, 0x00000003);
1676 } else if ((standard == V4L2_STD_PAL_I) |
1677 (standard & V4L2_STD_PAL_D) |
1678 (standard & V4L2_STD_SECAM)) {
1680 /* lo if big signal */
1681 status = cx231xx_reg_mask_write(dev,
1682 VID_BLK_I2C_ADDRESS, 32,
1683 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1684 /* FUNC_MODE = DIF */
1685 status = cx231xx_reg_mask_write(dev,
1686 VID_BLK_I2C_ADDRESS, 32,
1687 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1690 status = cx231xx_reg_mask_write(dev,
1691 VID_BLK_I2C_ADDRESS, 32,
1692 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1694 status = cx231xx_reg_mask_write(dev,
1695 VID_BLK_I2C_ADDRESS, 32,
1696 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1698 /* default PAL BG */
1700 /* lo if big signal */
1701 status = cx231xx_reg_mask_write(dev,
1702 VID_BLK_I2C_ADDRESS, 32,
1703 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1704 /* FUNC_MODE = DIF */
1705 status = cx231xx_reg_mask_write(dev,
1706 VID_BLK_I2C_ADDRESS, 32,
1707 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1710 status = cx231xx_reg_mask_write(dev,
1711 VID_BLK_I2C_ADDRESS, 32,
1712 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1714 status = cx231xx_reg_mask_write(dev,
1715 VID_BLK_I2C_ADDRESS, 32,
1716 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1723 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1726 u32 dif_misc_ctrl_value = 0;
1729 cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1731 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1732 if (standard != DIF_USE_BASEBAND)
1733 dev->norm = standard;
1735 switch (dev->model) {
1736 case CX231XX_BOARD_CNXT_CARRAERA:
1737 case CX231XX_BOARD_CNXT_RDE_250:
1738 case CX231XX_BOARD_CNXT_SHELBY:
1739 case CX231XX_BOARD_CNXT_RDU_250:
1740 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1741 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1744 case CX231XX_BOARD_CNXT_RDE_253S:
1745 case CX231XX_BOARD_CNXT_RDU_253S:
1752 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1753 func_mode, standard);
1755 if (standard == DIF_USE_BASEBAND) { /* base band */
1756 /* There is a different SRC_PHASE_INC value
1757 for baseband vs. DIF */
1758 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1759 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1760 &dif_misc_ctrl_value);
1761 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1762 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1763 dif_misc_ctrl_value);
1764 } else if (standard & V4L2_STD_PAL_D) {
1765 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1766 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1767 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1768 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1769 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1770 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1771 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1772 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1773 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1774 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1775 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1776 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1777 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1778 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1779 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1780 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1781 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1782 DIF_AGC_IF_INT_CURRENT, 0, 31,
1784 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1785 DIF_AGC_RF_CURRENT, 0, 31,
1787 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1788 DIF_VIDEO_AGC_CTRL, 0, 31,
1790 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1791 DIF_VID_AUD_OVERRIDE, 0, 31,
1793 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1794 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1796 DIF_COMP_FLT_CTRL, 0, 31,
1798 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1799 DIF_SRC_PHASE_INC, 0, 31,
1801 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1802 DIF_SRC_GAIN_CONTROL, 0, 31,
1804 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1805 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1806 /* Save the Spec Inversion value */
1807 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1808 dif_misc_ctrl_value |= 0x3a023F11;
1809 } else if (standard & V4L2_STD_PAL_I) {
1810 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1811 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1812 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1813 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1814 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1815 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1816 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1817 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1818 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1819 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1820 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1821 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1822 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1823 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1824 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1825 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1826 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1827 DIF_AGC_IF_INT_CURRENT, 0, 31,
1829 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1830 DIF_AGC_RF_CURRENT, 0, 31,
1832 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1833 DIF_VIDEO_AGC_CTRL, 0, 31,
1835 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1836 DIF_VID_AUD_OVERRIDE, 0, 31,
1838 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1839 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1840 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1841 DIF_COMP_FLT_CTRL, 0, 31,
1843 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1844 DIF_SRC_PHASE_INC, 0, 31,
1846 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1847 DIF_SRC_GAIN_CONTROL, 0, 31,
1849 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1850 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1851 /* Save the Spec Inversion value */
1852 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1853 dif_misc_ctrl_value |= 0x3a033F11;
1854 } else if (standard & V4L2_STD_PAL_M) {
1855 /* improved Low Frequency Phase Noise */
1856 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1857 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1858 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1859 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1860 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1861 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1863 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1865 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1867 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1869 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1870 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1872 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1874 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1876 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1878 /* Save the Spec Inversion value */
1879 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1880 dif_misc_ctrl_value |= 0x3A0A3F10;
1881 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1882 /* improved Low Frequency Phase Noise */
1883 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1884 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1885 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1886 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1887 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1888 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1890 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1892 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1894 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1896 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1898 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1900 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1902 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1904 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1906 /* Save the Spec Inversion value */
1907 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1908 dif_misc_ctrl_value = 0x3A093F10;
1909 } else if (standard &
1910 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1911 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1913 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1914 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1915 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1916 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1917 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1918 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1919 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1920 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1921 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1922 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1923 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1924 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1925 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1926 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1927 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1928 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1929 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1930 DIF_AGC_IF_INT_CURRENT, 0, 31,
1932 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1933 DIF_AGC_RF_CURRENT, 0, 31,
1935 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1936 DIF_VID_AUD_OVERRIDE, 0, 31,
1938 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1939 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1940 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1941 DIF_COMP_FLT_CTRL, 0, 31,
1943 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1944 DIF_SRC_PHASE_INC, 0, 31,
1946 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1947 DIF_SRC_GAIN_CONTROL, 0, 31,
1949 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1950 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1951 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1952 DIF_VIDEO_AGC_CTRL, 0, 31,
1955 /* Save the Spec Inversion value */
1956 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1957 dif_misc_ctrl_value |= 0x3a023F11;
1958 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1959 /* Is it SECAM_L1? */
1960 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1961 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1962 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1963 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1964 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1965 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1966 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1967 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1968 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1969 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1970 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1971 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1972 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1973 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1974 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1975 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1976 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1977 DIF_AGC_IF_INT_CURRENT, 0, 31,
1979 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1980 DIF_AGC_RF_CURRENT, 0, 31,
1982 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1983 DIF_VID_AUD_OVERRIDE, 0, 31,
1985 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1986 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1987 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1988 DIF_COMP_FLT_CTRL, 0, 31,
1990 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1991 DIF_SRC_PHASE_INC, 0, 31,
1993 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1994 DIF_SRC_GAIN_CONTROL, 0, 31,
1996 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1997 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1998 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1999 DIF_VIDEO_AGC_CTRL, 0, 31,
2002 /* Save the Spec Inversion value */
2003 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2004 dif_misc_ctrl_value |= 0x3a023F11;
2006 } else if (standard & V4L2_STD_NTSC_M) {
2007 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
2008 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
2010 /* For NTSC the centre frequency of video coming out of
2011 sidewinder is around 7.1MHz or 3.6MHz depending on the
2012 spectral inversion. so for a non spectrally inverted channel
2013 the pll freq word is 0x03420c49
2016 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2017 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2018 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2019 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2020 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2021 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2023 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2025 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2027 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2029 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2031 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2033 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2035 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2038 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2039 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2041 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2043 /* Save the Spec Inversion value */
2044 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2045 dif_misc_ctrl_value |= 0x3a003F10;
2047 /* default PAL BG */
2048 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2049 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
2050 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2051 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
2052 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2053 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
2054 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2055 DIF_PLL_CTRL3, 0, 31, 0x00008800);
2056 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2057 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
2058 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2059 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
2060 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2061 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
2062 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2063 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
2064 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2065 DIF_AGC_IF_INT_CURRENT, 0, 31,
2067 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2068 DIF_AGC_RF_CURRENT, 0, 31,
2070 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2071 DIF_VIDEO_AGC_CTRL, 0, 31,
2073 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2074 DIF_VID_AUD_OVERRIDE, 0, 31,
2076 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2077 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
2078 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2079 DIF_COMP_FLT_CTRL, 0, 31,
2081 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2082 DIF_SRC_PHASE_INC, 0, 31,
2084 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2085 DIF_SRC_GAIN_CONTROL, 0, 31,
2087 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2088 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2089 /* Save the Spec Inversion value */
2090 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2091 dif_misc_ctrl_value |= 0x3a013F11;
2094 /* The AGC values should be the same for all standards,
2095 AUD_SRC_SEL[19] should always be disabled */
2096 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2098 /* It is still possible to get Set Standard calls even when we
2100 This is done to override the value for FM. */
2101 if (dev->active_mode == V4L2_TUNER_RADIO)
2102 dif_misc_ctrl_value = 0x7a080000;
2104 /* Write the calculated value for misc ontrol register */
2105 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2110 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2115 /* Set the RF and IF k_agc values to 3 */
2116 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2117 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2118 dwval |= 0x33000000;
2120 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2125 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2129 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n",
2131 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2132 * SECAM L/B/D standards */
2133 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2134 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2136 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2137 V4L2_STD_SECAM_D)) {
2138 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2139 dwval &= ~FLD_DIF_IF_REF;
2140 dwval |= 0x88000300;
2142 dwval |= 0x88000000;
2144 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2145 dwval &= ~FLD_DIF_IF_REF;
2146 dwval |= 0xCC000300;
2148 dwval |= 0x44000000;
2151 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2156 /******************************************************************************
2157 * I 2 S - B L O C K C O N T R O L functions *
2158 ******************************************************************************/
2159 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2164 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2165 CH_PWR_CTRL1, 1, &value, 1);
2166 /* enables clock to delta-sigma and decimation filter */
2168 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2169 CH_PWR_CTRL1, 1, value, 1);
2170 /* power up all channel */
2171 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2172 CH_PWR_CTRL2, 1, 0x00, 1);
2177 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2178 enum AV_MODE avmode)
2183 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2184 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2185 CH_PWR_CTRL2, 1, &value, 1);
2187 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2188 CH_PWR_CTRL2, 1, value, 1);
2190 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2191 CH_PWR_CTRL2, 1, 0x00, 1);
2197 /* set i2s_blk for audio input types */
2198 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2202 switch (audio_input) {
2203 case CX231XX_AMUX_LINE_IN:
2204 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2205 CH_PWR_CTRL2, 1, 0x00, 1);
2206 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2207 CH_PWR_CTRL1, 1, 0x80, 1);
2209 case CX231XX_AMUX_VIDEO:
2214 dev->ctl_ainput = audio_input;
2219 /******************************************************************************
2220 * P O W E R C O N T R O L functions *
2221 ******************************************************************************/
2222 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2224 u8 value[4] = { 0, 0, 0, 0 };
2228 if (dev->power_mode != mode)
2229 dev->power_mode = mode;
2231 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
2236 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2241 tmp = *((u32 *) value);
2244 case POLARIS_AVMODE_ENXTERNAL_AV:
2246 tmp &= (~PWR_MODE_MASK);
2249 value[0] = (u8) tmp;
2250 value[1] = (u8) (tmp >> 8);
2251 value[2] = (u8) (tmp >> 16);
2252 value[3] = (u8) (tmp >> 24);
2253 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2254 PWR_CTL_EN, value, 4);
2255 msleep(PWR_SLEEP_INTERVAL);
2258 value[0] = (u8) tmp;
2259 value[1] = (u8) (tmp >> 8);
2260 value[2] = (u8) (tmp >> 16);
2261 value[3] = (u8) (tmp >> 24);
2263 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2265 msleep(PWR_SLEEP_INTERVAL);
2267 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2268 value[0] = (u8) tmp;
2269 value[1] = (u8) (tmp >> 8);
2270 value[2] = (u8) (tmp >> 16);
2271 value[3] = (u8) (tmp >> 24);
2272 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2273 PWR_CTL_EN, value, 4);
2275 /* reset state of xceive tuner */
2276 dev->xc_fw_load_done = 0;
2279 case POLARIS_AVMODE_ANALOGT_TV:
2281 tmp |= PWR_DEMOD_EN;
2282 tmp |= (I2C_DEMOD_EN);
2283 value[0] = (u8) tmp;
2284 value[1] = (u8) (tmp >> 8);
2285 value[2] = (u8) (tmp >> 16);
2286 value[3] = (u8) (tmp >> 24);
2287 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2288 PWR_CTL_EN, value, 4);
2289 msleep(PWR_SLEEP_INTERVAL);
2291 if (!(tmp & PWR_TUNER_EN)) {
2292 tmp |= (PWR_TUNER_EN);
2293 value[0] = (u8) tmp;
2294 value[1] = (u8) (tmp >> 8);
2295 value[2] = (u8) (tmp >> 16);
2296 value[3] = (u8) (tmp >> 24);
2297 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2298 PWR_CTL_EN, value, 4);
2299 msleep(PWR_SLEEP_INTERVAL);
2302 if (!(tmp & PWR_AV_EN)) {
2304 value[0] = (u8) tmp;
2305 value[1] = (u8) (tmp >> 8);
2306 value[2] = (u8) (tmp >> 16);
2307 value[3] = (u8) (tmp >> 24);
2308 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2309 PWR_CTL_EN, value, 4);
2310 msleep(PWR_SLEEP_INTERVAL);
2312 if (!(tmp & PWR_ISO_EN)) {
2314 value[0] = (u8) tmp;
2315 value[1] = (u8) (tmp >> 8);
2316 value[2] = (u8) (tmp >> 16);
2317 value[3] = (u8) (tmp >> 24);
2318 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2319 PWR_CTL_EN, value, 4);
2320 msleep(PWR_SLEEP_INTERVAL);
2323 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2324 tmp |= POLARIS_AVMODE_ANALOGT_TV;
2325 value[0] = (u8) tmp;
2326 value[1] = (u8) (tmp >> 8);
2327 value[2] = (u8) (tmp >> 16);
2328 value[3] = (u8) (tmp >> 24);
2329 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2330 PWR_CTL_EN, value, 4);
2331 msleep(PWR_SLEEP_INTERVAL);
2334 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2335 (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2336 (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2337 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2338 /* tuner path to channel 1 from port 3 */
2339 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2341 /* reset the Tuner */
2342 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2344 if (dev->cx231xx_reset_analog_tuner)
2345 dev->cx231xx_reset_analog_tuner(dev);
2346 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2347 (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2348 (dev->model == CX231XX_BOARD_CNXT_RDU_253S) ||
2349 (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER)) {
2350 /* tuner path to channel 1 from port 3 */
2351 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2352 if (dev->cx231xx_reset_analog_tuner)
2353 dev->cx231xx_reset_analog_tuner(dev);
2358 case POLARIS_AVMODE_DIGITAL:
2359 if (!(tmp & PWR_TUNER_EN)) {
2360 tmp |= (PWR_TUNER_EN);
2361 value[0] = (u8) tmp;
2362 value[1] = (u8) (tmp >> 8);
2363 value[2] = (u8) (tmp >> 16);
2364 value[3] = (u8) (tmp >> 24);
2365 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2366 PWR_CTL_EN, value, 4);
2367 msleep(PWR_SLEEP_INTERVAL);
2369 if (!(tmp & PWR_AV_EN)) {
2371 value[0] = (u8) tmp;
2372 value[1] = (u8) (tmp >> 8);
2373 value[2] = (u8) (tmp >> 16);
2374 value[3] = (u8) (tmp >> 24);
2375 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2376 PWR_CTL_EN, value, 4);
2377 msleep(PWR_SLEEP_INTERVAL);
2379 if (!(tmp & PWR_ISO_EN)) {
2381 value[0] = (u8) tmp;
2382 value[1] = (u8) (tmp >> 8);
2383 value[2] = (u8) (tmp >> 16);
2384 value[3] = (u8) (tmp >> 24);
2385 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2386 PWR_CTL_EN, value, 4);
2387 msleep(PWR_SLEEP_INTERVAL);
2390 tmp &= (~PWR_AV_MODE);
2391 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
2392 value[0] = (u8) tmp;
2393 value[1] = (u8) (tmp >> 8);
2394 value[2] = (u8) (tmp >> 16);
2395 value[3] = (u8) (tmp >> 24);
2396 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2397 PWR_CTL_EN, value, 4);
2398 msleep(PWR_SLEEP_INTERVAL);
2400 if (!(tmp & PWR_DEMOD_EN)) {
2401 tmp |= PWR_DEMOD_EN;
2402 value[0] = (u8) tmp;
2403 value[1] = (u8) (tmp >> 8);
2404 value[2] = (u8) (tmp >> 16);
2405 value[3] = (u8) (tmp >> 24);
2406 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2407 PWR_CTL_EN, value, 4);
2408 msleep(PWR_SLEEP_INTERVAL);
2411 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2412 (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2413 (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2414 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2415 /* tuner path to channel 1 from port 3 */
2416 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2418 /* reset the Tuner */
2419 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2421 if (dev->cx231xx_reset_analog_tuner)
2422 dev->cx231xx_reset_analog_tuner(dev);
2423 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2424 (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2425 (dev->model == CX231XX_BOARD_CNXT_RDU_253S)) {
2426 /* tuner path to channel 1 from port 3 */
2427 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2428 if (dev->cx231xx_reset_analog_tuner)
2429 dev->cx231xx_reset_analog_tuner(dev);
2430 } else if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) {
2431 /* tuner path to channel 1 from port 1 ?? */
2432 cx231xx_enable_i2c_for_tuner(dev, I2C_1);
2434 if (dev->cx231xx_reset_analog_tuner)
2435 dev->cx231xx_reset_analog_tuner(dev);
2444 msleep(PWR_SLEEP_INTERVAL);
2446 /* For power saving, only enable Pwr_resetout_n
2447 when digital TV is selected. */
2448 if (mode == POLARIS_AVMODE_DIGITAL) {
2449 tmp |= PWR_RESETOUT_EN;
2450 value[0] = (u8) tmp;
2451 value[1] = (u8) (tmp >> 8);
2452 value[2] = (u8) (tmp >> 16);
2453 value[3] = (u8) (tmp >> 24);
2454 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2455 PWR_CTL_EN, value, 4);
2456 msleep(PWR_SLEEP_INTERVAL);
2459 /* update power control for afe */
2460 status = cx231xx_afe_update_power_control(dev, mode);
2462 /* update power control for i2s_blk */
2463 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2465 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2471 int cx231xx_power_suspend(struct cx231xx *dev)
2473 u8 value[4] = { 0, 0, 0, 0 };
2477 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2482 tmp = *((u32 *) value);
2483 tmp &= (~PWR_MODE_MASK);
2485 value[0] = (u8) tmp;
2486 value[1] = (u8) (tmp >> 8);
2487 value[2] = (u8) (tmp >> 16);
2488 value[3] = (u8) (tmp >> 24);
2489 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2495 /******************************************************************************
2496 * S T R E A M C O N T R O L functions *
2497 ******************************************************************************/
2498 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2500 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2504 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2505 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2510 tmp = *((u32 *) value);
2512 value[0] = (u8) tmp;
2513 value[1] = (u8) (tmp >> 8);
2514 value[2] = (u8) (tmp >> 16);
2515 value[3] = (u8) (tmp >> 24);
2517 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2523 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2525 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2529 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2531 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2535 tmp = *((u32 *) value);
2537 value[0] = (u8) tmp;
2538 value[1] = (u8) (tmp >> 8);
2539 value[2] = (u8) (tmp >> 16);
2540 value[3] = (u8) (tmp >> 24);
2542 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2548 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2552 u8 val[4] = { 0, 0, 0, 0 };
2554 if (dev->udev->speed == USB_SPEED_HIGH) {
2555 switch (media_type) {
2556 case 81: /* audio */
2557 cx231xx_info("%s: Audio enter HANC\n", __func__);
2559 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2563 cx231xx_info("%s: set vanc registers\n", __func__);
2564 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2567 case 3: /* sliced cc */
2568 cx231xx_info("%s: set hanc registers\n", __func__);
2570 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2574 cx231xx_info("%s: set video registers\n", __func__);
2575 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2579 cx231xx_info("%s: set ts1 registers", __func__);
2581 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
2582 cx231xx_info(" MPEG\n");
2583 value &= 0xFFFFFFFC;
2586 status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2592 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2593 TS1_CFG_REG, val, 4);
2599 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2600 TS1_LENGTH_REG, val, 4);
2603 cx231xx_info(" BDA\n");
2604 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2605 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2609 case 6: /* ts1 parallel mode */
2610 cx231xx_info("%s: set ts1 parrallel mode registers\n",
2612 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2613 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2617 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2623 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2627 struct pcb_config *pcb_config;
2629 /* get EP for media type */
2630 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2632 if (pcb_config->config_num == 1) {
2633 switch (media_type) {
2635 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2638 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2641 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2643 case 3: /* Sliced_cc */
2644 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2647 case 6: /* ts1 parallel mode */
2648 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2651 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2655 } else if (pcb_config->config_num > 1) {
2656 switch (media_type) {
2658 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2661 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2664 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2666 case 3: /* Sliced_cc */
2667 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2670 case 6: /* ts1 parallel mode */
2671 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2674 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2681 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2686 /* enable video capture */
2688 rc = cx231xx_start_stream(dev, ep_mask);
2690 /* disable video capture */
2692 rc = cx231xx_stop_stream(dev, ep_mask);
2695 if (dev->mode == CX231XX_ANALOG_MODE)
2696 ;/* do any in Analog mode */
2698 ;/* do any in digital mode */
2702 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2704 /*****************************************************************************
2705 * G P I O B I T control functions *
2706 ******************************************************************************/
2707 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2711 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2716 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2720 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2726 * cx231xx_set_gpio_direction
2727 * Sets the direction of the GPIO pin to input or output
2730 * pin_number : The GPIO Pin number to program the direction for
2732 * pin_value : The Direction of the GPIO Pin under reference.
2733 * 0 = Input direction
2734 * 1 = Output direction
2736 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2737 int pin_number, int pin_value)
2742 /* Check for valid pin_number - if 32 , bail out */
2743 if (pin_number >= 32)
2748 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
2750 value = dev->gpio_dir | (1 << pin_number);
2752 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2754 /* cache the value for future */
2755 dev->gpio_dir = value;
2761 * cx231xx_set_gpio_value
2762 * Sets the value of the GPIO pin to Logic high or low. The Pin under
2763 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2766 * pin_number : The GPIO Pin number to program the direction for
2767 * pin_value : The value of the GPIO Pin under reference.
2771 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2776 /* Check for valid pin_number - if 0xFF , bail out */
2777 if (pin_number >= 32)
2780 /* first do a sanity check - if the Pin is not output, make it output */
2781 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2782 /* It was in input mode */
2783 value = dev->gpio_dir | (1 << pin_number);
2784 dev->gpio_dir = value;
2785 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2786 (u8 *) &dev->gpio_val);
2791 value = dev->gpio_val & (~(1 << pin_number));
2793 value = dev->gpio_val | (1 << pin_number);
2795 /* store the value */
2796 dev->gpio_val = value;
2798 /* toggle bit0 of GP_IO */
2799 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2804 /*****************************************************************************
2805 * G P I O I2C related functions *
2806 ******************************************************************************/
2807 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2811 /* set SCL to output 1 ; set SDA to output 1 */
2812 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2813 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2814 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2815 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2817 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2821 /* set SCL to output 1; set SDA to output 0 */
2822 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2823 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2825 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2829 /* set SCL to output 0; set SDA to output 0 */
2830 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2831 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2833 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2840 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2844 /* set SCL to output 0; set SDA to output 0 */
2845 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2846 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2848 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2849 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2851 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2855 /* set SCL to output 1; set SDA to output 0 */
2856 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2857 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2859 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2863 /* set SCL to input ,release SCL cable control
2864 set SDA to input ,release SDA cable control */
2865 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2866 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2869 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2876 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2881 /* set SCL to output ; set SDA to output */
2882 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2883 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2885 for (i = 0; i < 8; i++) {
2886 if (((data << i) & 0x80) == 0) {
2887 /* set SCL to output 0; set SDA to output 0 */
2888 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2889 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2890 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2891 (u8 *)&dev->gpio_val);
2893 /* set SCL to output 1; set SDA to output 0 */
2894 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2895 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2896 (u8 *)&dev->gpio_val);
2898 /* set SCL to output 0; set SDA to output 0 */
2899 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2900 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2901 (u8 *)&dev->gpio_val);
2903 /* set SCL to output 0; set SDA to output 1 */
2904 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2905 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2906 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2907 (u8 *)&dev->gpio_val);
2909 /* set SCL to output 1; set SDA to output 1 */
2910 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2911 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2912 (u8 *)&dev->gpio_val);
2914 /* set SCL to output 0; set SDA to output 1 */
2915 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2916 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2917 (u8 *)&dev->gpio_val);
2923 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2927 u32 gpio_logic_value = 0;
2931 for (i = 0; i < 8; i++) { /* send write I2c addr */
2933 /* set SCL to output 0; set SDA to input */
2934 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2935 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2936 (u8 *)&dev->gpio_val);
2938 /* set SCL to output 1; set SDA to input */
2939 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2940 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2941 (u8 *)&dev->gpio_val);
2943 /* get SDA data bit */
2944 gpio_logic_value = dev->gpio_val;
2945 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2946 (u8 *)&dev->gpio_val);
2947 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2948 value |= (1 << (8 - i - 1));
2950 dev->gpio_val = gpio_logic_value;
2953 /* set SCL to output 0,finish the read latest SCL signal.
2954 !!!set SDA to input, never to modify SDA direction at
2956 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2957 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2959 /* store the value */
2960 *buf = value & 0xff;
2965 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2968 u32 gpio_logic_value = 0;
2972 /* clock stretch; set SCL to input; set SDA to input;
2973 get SCL value till SCL = 1 */
2974 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2975 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2977 gpio_logic_value = dev->gpio_val;
2978 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2982 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2983 (u8 *)&dev->gpio_val);
2985 } while (((dev->gpio_val &
2986 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2990 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2995 * through clock stretch, slave has given a SCL signal,
2996 * so the SDA data can be directly read.
2998 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3000 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
3001 dev->gpio_val = gpio_logic_value;
3002 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3005 dev->gpio_val = gpio_logic_value;
3006 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
3009 /* read SDA end, set the SCL to output 0, after this operation,
3010 SDA direction can be changed. */
3011 dev->gpio_val = gpio_logic_value;
3012 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
3013 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3014 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3019 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
3023 /* set SDA to ouput */
3024 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
3025 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3027 /* set SCL = 0 (output); set SDA = 0 (output) */
3028 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3029 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3030 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3032 /* set SCL = 1 (output); set SDA = 0 (output) */
3033 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3034 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3036 /* set SCL = 0 (output); set SDA = 0 (output) */
3037 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3038 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3040 /* set SDA to input,and then the slave will read data from SDA. */
3041 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3042 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3047 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
3051 /* set scl to output ; set sda to input */
3052 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
3053 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3054 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3056 /* set scl to output 0; set sda to input */
3057 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3058 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3060 /* set scl to output 1; set sda to input */
3061 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3062 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3067 /*****************************************************************************
3068 * G P I O I2C related functions *
3069 ******************************************************************************/
3070 /* cx231xx_gpio_i2c_read
3071 * Function to read data from gpio based I2C interface
3073 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3079 mutex_lock(&dev->gpio_i2c_lock);
3082 status = cx231xx_gpio_i2c_start(dev);
3084 /* write dev_addr */
3085 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3088 status = cx231xx_gpio_i2c_read_ack(dev);
3091 for (i = 0; i < len; i++) {
3094 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3096 if ((i + 1) != len) {
3097 /* only do write ack if we more length */
3098 status = cx231xx_gpio_i2c_write_ack(dev);
3102 /* write NAK - inform reads are complete */
3103 status = cx231xx_gpio_i2c_write_nak(dev);
3106 status = cx231xx_gpio_i2c_end(dev);
3108 /* release the lock */
3109 mutex_unlock(&dev->gpio_i2c_lock);
3114 /* cx231xx_gpio_i2c_write
3115 * Function to write data to gpio based I2C interface
3117 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3123 mutex_lock(&dev->gpio_i2c_lock);
3126 status = cx231xx_gpio_i2c_start(dev);
3128 /* write dev_addr */
3129 status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3132 status = cx231xx_gpio_i2c_read_ack(dev);
3134 for (i = 0; i < len; i++) {
3136 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3139 status = cx231xx_gpio_i2c_read_ack(dev);
3143 status = cx231xx_gpio_i2c_end(dev);
3145 /* release the lock */
3146 mutex_unlock(&dev->gpio_i2c_lock);