drivers/media/video/cx231xx/cx231xx-avcore.c

   1 /*
   2    cx231xx_avcore.c - driver for Conexant Cx23100/101/102
   3                       USB video capture devices
   4
   5    Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
   6
   7    This program contains the specific code to control the avdecoder chip and
   8    other related usb control functions for cx231xx based chipset.
   9
  10    This program is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2 of the License, or
  13    (at your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/list.h>
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/bitmap.h>
  30 #include <linux/usb.h>
  31 #include <linux/i2c.h>
  32 #include <linux/mm.h>
  33 #include <linux/mutex.h>
  34 #include <media/tuner.h>
  35
  36 #include <media/v4l2-common.h>
  37 #include <media/v4l2-ioctl.h>
  38 #include <media/v4l2-chip-ident.h>
  39
  40 #include "cx231xx.h"
  41 #include "cx231xx-dif.h"
  42
  43 #define TUNER_MODE_FM_RADIO 0
  44 /******************************************************************************
  45                         -: BLOCK ARRANGEMENT :-
  46         I2S block ----------------------|
  47         [I2S audio]                     |
  48                                         |
  49         Analog Front End --> Direct IF -|-> Cx25840 --> Audio
  50         [video & audio]                 |   [Audio]
  51                                         |
  52                                         |-> Cx25840 --> Video
  53                                             [Video]
  54
  55 *******************************************************************************/
  56 /******************************************************************************
  57  *                    VERVE REGISTER                                          *
  58         *                                                                     *
  59  ******************************************************************************/
  60 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
  61 {
  62         return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
  63                                         saddr, 1, data, 1);
  64 }
  65
  66 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
  67 {
  68         int status;
  69         u32 temp = 0;
  70
  71         status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
  72                                         saddr, 1, &temp, 1);
  73         *data = (u8) temp;
  74         return status;
  75 }
  76 void initGPIO(struct cx231xx *dev)
  77 {
  78         u32 _gpio_direction = 0;
  79         u32 value = 0;
  80         u8 val = 0;
  81
  82         _gpio_direction = _gpio_direction & 0xFC0003FF;
  83         _gpio_direction = _gpio_direction | 0x03FDFC00;
  84         cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
  85
  86         verve_read_byte(dev, 0x07, &val);
  87         cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
  88         verve_write_byte(dev, 0x07, 0xF4);
  89         verve_read_byte(dev, 0x07, &val);
  90         cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
  91
  92         cx231xx_capture_start(dev, 1, 2);
  93
  94         cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
  95         cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
  96
  97 }
  98 void uninitGPIO(struct cx231xx *dev)
  99 {
 100         u8 value[4] = { 0, 0, 0, 0 };
 101
 102         cx231xx_capture_start(dev, 0, 2);
 103         verve_write_byte(dev, 0x07, 0x14);
 104         cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
 105                         0x68, value, 4);
 106 }
 107
 108 /******************************************************************************
 109  *                    A F E - B L O C K    C O N T R O L   functions          *
 110  *                              [ANALOG FRONT END]                            *
 111  ******************************************************************************/
 112 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
 113 {
 114         return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
 115                                         saddr, 2, data, 1);
 116 }
 117
 118 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
 119 {
 120         int status;
 121         u32 temp = 0;
 122
 123         status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
 124                                         saddr, 2, &temp, 1);
 125         *data = (u8) temp;
 126         return status;
 127 }
 128
 129 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
 130 {
 131         int status = 0;
 132         u8 temp = 0;
 133         u8 afe_power_status = 0;
 134         int i = 0;
 135
 136         /* super block initialize */
 137         temp = (u8) (ref_count & 0xff);
 138         status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
 139         if (status < 0)
 140                 return status;
 141
 142         status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
 143         if (status < 0)
 144                 return status;
 145
 146         temp = (u8) ((ref_count & 0x300) >> 8);
 147         temp |= 0x40;
 148         status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
 149         if (status < 0)
 150                 return status;
 151
 152         status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
 153         if (status < 0)
 154                 return status;
 155
 156         /* enable pll     */
 157         while (afe_power_status != 0x18) {
 158                 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
 159                 if (status < 0) {
 160                         cx231xx_info(
 161                         ": Init Super Block failed in send cmd\n");
 162                         break;
 163                 }
 164
 165                 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
 166                 afe_power_status &= 0xff;
 167                 if (status < 0) {
 168                         cx231xx_info(
 169                         ": Init Super Block failed in receive cmd\n");
 170                         break;
 171                 }
 172                 i++;
 173                 if (i == 10) {
 174                         cx231xx_info(
 175                         ": Init Super Block force break in loop !!!!\n");
 176                         status = -1;
 177                         break;
 178                 }
 179         }
 180
 181         if (status < 0)
 182                 return status;
 183
 184         /* start tuning filter */
 185         status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
 186         if (status < 0)
 187                 return status;
 188
 189         msleep(5);
 190
 191         /* exit tuning */
 192         status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
 193
 194         return status;
 195 }
 196
 197 int cx231xx_afe_init_channels(struct cx231xx *dev)
 198 {
 199         int status = 0;
 200
 201         /* power up all 3 channels, clear pd_buffer */
 202         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
 203         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
 204         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
 205
 206         /* Enable quantizer calibration */
 207         status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
 208
 209         /* channel initialize, force modulator (fb) reset */
 210         status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
 211         status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
 212         status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
 213
 214         /* start quantilizer calibration  */
 215         status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
 216         status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
 217         status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
 218         msleep(5);
 219
 220         /* exit modulator (fb) reset */
 221         status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
 222         status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
 223         status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
 224
 225         /* enable the pre_clamp in each channel for single-ended input */
 226         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
 227         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
 228         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
 229
 230         /* use diode instead of resistor, so set term_en to 0, res_en to 0  */
 231         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 232                                    ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
 233         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 234                                    ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
 235         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 236                                    ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
 237
 238         /* dynamic element matching off */
 239         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
 240         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
 241         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
 242
 243         return status;
 244 }
 245
 246 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
 247 {
 248         u8 c_value = 0;
 249         int status = 0;
 250
 251         status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
 252         c_value &= (~(0x50));
 253         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
 254
 255         return status;
 256 }
 257
 258 /*
 259         The Analog Front End in Cx231xx has 3 channels. These
 260         channels are used to share between different inputs
 261         like tuner, s-video and composite inputs.
 262
 263         channel 1 ----- pin 1  to pin4(in reg is 1-4)
 264         channel 2 ----- pin 5  to pin8(in reg is 5-8)
 265         channel 3 ----- pin 9 to pin 12(in reg is 9-11)
 266 */
 267 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
 268 {
 269         u8 ch1_setting = (u8) input_mux;
 270         u8 ch2_setting = (u8) (input_mux >> 8);
 271         u8 ch3_setting = (u8) (input_mux >> 16);
 272         int status = 0;
 273         u8 value = 0;
 274
 275         if (ch1_setting != 0) {
 276                 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
 277                 value &= (!INPUT_SEL_MASK);
 278                 value |= (ch1_setting - 1) << 4;
 279                 value &= 0xff;
 280                 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
 281         }
 282
 283         if (ch2_setting != 0) {
 284                 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
 285                 value &= (!INPUT_SEL_MASK);
 286                 value |= (ch2_setting - 1) << 4;
 287                 value &= 0xff;
 288                 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
 289         }
 290
 291         /* For ch3_setting, the value to put in the register is
 292            7 less than the input number */
 293         if (ch3_setting != 0) {
 294                 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
 295                 value &= (!INPUT_SEL_MASK);
 296                 value |= (ch3_setting - 1) << 4;
 297                 value &= 0xff;
 298                 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
 299         }
 300
 301         return status;
 302 }
 303
 304 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
 305 {
 306         int status = 0;
 307
 308         /*
 309         * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
 310         * Currently, only baseband works.
 311         */
 312
 313         switch (mode) {
 314         case AFE_MODE_LOW_IF:
 315                 cx231xx_Setup_AFE_for_LowIF(dev);
 316                 break;
 317         case AFE_MODE_BASEBAND:
 318                 status = cx231xx_afe_setup_AFE_for_baseband(dev);
 319                 break;
 320         case AFE_MODE_EU_HI_IF:
 321                 /* SetupAFEforEuHiIF(); */
 322                 break;
 323         case AFE_MODE_US_HI_IF:
 324                 /* SetupAFEforUsHiIF(); */
 325                 break;
 326         case AFE_MODE_JAPAN_HI_IF:
 327                 /* SetupAFEforJapanHiIF(); */
 328                 break;
 329         }
 330
 331         if ((mode != dev->afe_mode) &&
 332                 (dev->video_input == CX231XX_VMUX_TELEVISION))
 333                 status = cx231xx_afe_adjust_ref_count(dev,
 334                                                      CX231XX_VMUX_TELEVISION);
 335
 336         dev->afe_mode = mode;
 337
 338         return status;
 339 }
 340
 341 int cx231xx_afe_update_power_control(struct cx231xx *dev,
 342                                         enum AV_MODE avmode)
 343 {
 344         u8 afe_power_status = 0;
 345         int status = 0;
 346
 347         switch (dev->model) {
 348         case CX231XX_BOARD_CNXT_CARRAERA:
 349         case CX231XX_BOARD_CNXT_RDE_250:
 350         case CX231XX_BOARD_CNXT_SHELBY:
 351         case CX231XX_BOARD_CNXT_RDU_250:
 352         case CX231XX_BOARD_CNXT_RDE_253S:
 353         case CX231XX_BOARD_CNXT_RDU_253S:
 354         case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
 355         case CX231XX_BOARD_HAUPPAUGE_EXETER:
 356                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 357                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 358                                                 FLD_PWRDN_ENABLE_PLL)) {
 359                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 360                                                         FLD_PWRDN_TUNING_BIAS |
 361                                                         FLD_PWRDN_ENABLE_PLL);
 362                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 363                                                         &afe_power_status);
 364                                 if (status < 0)
 365                                         break;
 366                         }
 367
 368                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 369                                                         0x00);
 370                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 371                                                         0x00);
 372                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 373                                                         0x00);
 374                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 375                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 376                                                         0x70);
 377                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 378                                                         0x70);
 379                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 380                                                         0x70);
 381
 382                         status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 383                                                   &afe_power_status);
 384                         afe_power_status |= FLD_PWRDN_PD_BANDGAP |
 385                                                 FLD_PWRDN_PD_BIAS |
 386                                                 FLD_PWRDN_PD_TUNECK;
 387                         status |= afe_write_byte(dev, SUP_BLK_PWRDN,
 388                                                    afe_power_status);
 389                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 390                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 391                                                 FLD_PWRDN_ENABLE_PLL)) {
 392                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 393                                                         FLD_PWRDN_TUNING_BIAS |
 394                                                         FLD_PWRDN_ENABLE_PLL);
 395                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 396                                                         &afe_power_status);
 397                                 if (status < 0)
 398                                         break;
 399                         }
 400
 401                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 402                                                 0x00);
 403                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 404                                                 0x00);
 405                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 406                                                 0x00);
 407                 } else {
 408                         cx231xx_info("Invalid AV mode input\n");
 409                         status = -1;
 410                 }
 411                 break;
 412         default:
 413                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 414                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 415                                                 FLD_PWRDN_ENABLE_PLL)) {
 416                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 417                                                         FLD_PWRDN_TUNING_BIAS |
 418                                                         FLD_PWRDN_ENABLE_PLL);
 419                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 420                                                         &afe_power_status);
 421                                 if (status < 0)
 422                                         break;
 423                         }
 424
 425                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 426                                                         0x40);
 427                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 428                                                         0x40);
 429                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 430                                                         0x00);
 431                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 432                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 433                                                         0x70);
 434                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 435                                                         0x70);
 436                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 437                                                         0x70);
 438
 439                         status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 440                                                        &afe_power_status);
 441                         afe_power_status |= FLD_PWRDN_PD_BANDGAP |
 442                                                 FLD_PWRDN_PD_BIAS |
 443                                                 FLD_PWRDN_PD_TUNECK;
 444                         status |= afe_write_byte(dev, SUP_BLK_PWRDN,
 445                                                         afe_power_status);
 446                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 447                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 448                                                 FLD_PWRDN_ENABLE_PLL)) {
 449                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 450                                                         FLD_PWRDN_TUNING_BIAS |
 451                                                         FLD_PWRDN_ENABLE_PLL);
 452                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 453                                                         &afe_power_status);
 454                                 if (status < 0)
 455                                         break;
 456                         }
 457
 458                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 459                                                         0x00);
 460                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 461                                                         0x00);
 462                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 463                                                         0x40);
 464                 } else {
 465                         cx231xx_info("Invalid AV mode input\n");
 466                         status = -1;
 467                 }
 468         }                       /* switch  */
 469
 470         return status;
 471 }
 472
 473 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
 474 {
 475         u8 input_mode = 0;
 476         u8 ntf_mode = 0;
 477         int status = 0;
 478
 479         dev->video_input = video_input;
 480
 481         if (video_input == CX231XX_VMUX_TELEVISION) {
 482                 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
 483                 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
 484                                         &ntf_mode);
 485         } else {
 486                 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
 487                 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
 488                                         &ntf_mode);
 489         }
 490
 491         input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
 492
 493         switch (input_mode) {
 494         case SINGLE_ENDED:
 495                 dev->afe_ref_count = 0x23C;
 496                 break;
 497         case LOW_IF:
 498                 dev->afe_ref_count = 0x24C;
 499                 break;
 500         case EU_IF:
 501                 dev->afe_ref_count = 0x258;
 502                 break;
 503         case US_IF:
 504                 dev->afe_ref_count = 0x260;
 505                 break;
 506         default:
 507                 break;
 508         }
 509
 510         status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
 511
 512         return status;
 513 }
 514
 515 /******************************************************************************
 516  *     V I D E O / A U D I O    D E C O D E R    C O N T R O L   functions    *
 517  ******************************************************************************/
 518 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
 519 {
 520         return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 521                                         saddr, 2, data, 1);
 522 }
 523
 524 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
 525 {
 526         int status;
 527         u32 temp = 0;
 528
 529         status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 530                                         saddr, 2, &temp, 1);
 531         *data = (u8) temp;
 532         return status;
 533 }
 534
 535 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
 536 {
 537         return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 538                                         saddr, 2, data, 4);
 539 }
 540
 541 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
 542 {
 543         return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 544                                         saddr, 2, data, 4);
 545 }
 546 int cx231xx_check_fw(struct cx231xx *dev)
 547 {
 548         u8 temp = 0;
 549         int status = 0;
 550         status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
 551         if (status < 0)
 552                 return status;
 553         else
 554                 return temp;
 555
 556 }
 557
 558 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
 559 {
 560         int status = 0;
 561
 562         switch (INPUT(input)->type) {
 563         case CX231XX_VMUX_COMPOSITE1:
 564         case CX231XX_VMUX_SVIDEO:
 565                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 566                     (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
 567                         /* External AV */
 568                         status = cx231xx_set_power_mode(dev,
 569                                         POLARIS_AVMODE_ENXTERNAL_AV);
 570                         if (status < 0) {
 571                                 cx231xx_errdev("%s: set_power_mode : Failed to"
 572                                                 " set Power - errCode [%d]!\n",
 573                                                 __func__, status);
 574                                 return status;
 575                         }
 576                 }
 577                 status = cx231xx_set_decoder_video_input(dev,
 578                                                          INPUT(input)->type,
 579                                                          INPUT(input)->vmux);
 580                 break;
 581         case CX231XX_VMUX_TELEVISION:
 582         case CX231XX_VMUX_CABLE:
 583                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 584                     (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
 585                         /* Tuner */
 586                         status = cx231xx_set_power_mode(dev,
 587                                                 POLARIS_AVMODE_ANALOGT_TV);
 588                         if (status < 0) {
 589                                 cx231xx_errdev("%s: set_power_mode:Failed"
 590                                         " to set Power - errCode [%d]!\n",
 591                                         __func__, status);
 592                                 return status;
 593                         }
 594                 }
 595                 if (dev->tuner_type == TUNER_NXP_TDA18271)
 596                         status = cx231xx_set_decoder_video_input(dev,
 597                                                         CX231XX_VMUX_TELEVISION,
 598                                                         INPUT(input)->vmux);
 599                 else
 600                         status = cx231xx_set_decoder_video_input(dev,
 601                                                         CX231XX_VMUX_COMPOSITE1,
 602                                                         INPUT(input)->vmux);
 603
 604                 break;
 605         default:
 606                 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
 607                      __func__, INPUT(input)->type);
 608                 break;
 609         }
 610
 611         /* save the selection */
 612         dev->video_input = input;
 613
 614         return status;
 615 }
 616
 617 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
 618                                 u8 pin_type, u8 input)
 619 {
 620         int status = 0;
 621         u32 value = 0;
 622
 623         if (pin_type != dev->video_input) {
 624                 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
 625                 if (status < 0) {
 626                         cx231xx_errdev("%s: adjust_ref_count :Failed to set"
 627                                 "AFE input mux - errCode [%d]!\n",
 628                                 __func__, status);
 629                         return status;
 630                 }
 631         }
 632
 633         /* call afe block to set video inputs */
 634         status = cx231xx_afe_set_input_mux(dev, input);
 635         if (status < 0) {
 636                 cx231xx_errdev("%s: set_input_mux :Failed to set"
 637                                 " AFE input mux - errCode [%d]!\n",
 638                                 __func__, status);
 639                 return status;
 640         }
 641
 642         switch (pin_type) {
 643         case CX231XX_VMUX_COMPOSITE1:
 644                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 645                 value |= (0 << 13) | (1 << 4);
 646                 value &= ~(1 << 5);
 647
 648                 /* set [24:23] [22:15] to 0  */
 649                 value &= (~(0x1ff8000));
 650                 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0  */
 651                 value |= 0x1000000;
 652                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 653
 654                 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 655                 value |= (1 << 7);
 656                 status = vid_blk_write_word(dev, OUT_CTRL1, value);
 657
 658                 /* Set vip 1.1 output mode */
 659                 status = cx231xx_read_modify_write_i2c_dword(dev,
 660                                                         VID_BLK_I2C_ADDRESS,
 661                                                         OUT_CTRL1,
 662                                                         FLD_OUT_MODE,
 663                                                         OUT_MODE_VIP11);
 664
 665                 /* Tell DIF object to go to baseband mode  */
 666                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 667                 if (status < 0) {
 668                         cx231xx_errdev("%s: cx231xx_dif set to By pass"
 669                                                    " mode- errCode [%d]!\n",
 670                                 __func__, status);
 671                         return status;
 672                 }
 673
 674                 /* Read the DFE_CTRL1 register */
 675                 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 676
 677                 /* enable the VBI_GATE_EN */
 678                 value |= FLD_VBI_GATE_EN;
 679
 680                 /* Enable the auto-VGA enable */
 681                 value |= FLD_VGA_AUTO_EN;
 682
 683                 /* Write it back */
 684                 status = vid_blk_write_word(dev, DFE_CTRL1, value);
 685
 686                 /* Disable auto config of registers */
 687                 status = cx231xx_read_modify_write_i2c_dword(dev,
 688                                         VID_BLK_I2C_ADDRESS,
 689                                         MODE_CTRL, FLD_ACFG_DIS,
 690                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 691
 692                 /* Set CVBS input mode */
 693                 status = cx231xx_read_modify_write_i2c_dword(dev,
 694                         VID_BLK_I2C_ADDRESS,
 695                         MODE_CTRL, FLD_INPUT_MODE,
 696                         cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
 697                 break;
 698         case CX231XX_VMUX_SVIDEO:
 699                 /* Disable the use of  DIF */
 700
 701                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 702
 703                 /* set [24:23] [22:15] to 0 */
 704                 value &= (~(0x1ff8000));
 705                 /* set FUNC_MODE[24:23] = 2
 706                 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
 707                 value |= 0x1000010;
 708                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 709
 710                 /* Tell DIF object to go to baseband mode */
 711                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 712                 if (status < 0) {
 713                         cx231xx_errdev("%s: cx231xx_dif set to By pass"
 714                                                    " mode- errCode [%d]!\n",
 715                                 __func__, status);
 716                         return status;
 717                 }
 718
 719                 /* Read the DFE_CTRL1 register */
 720                 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 721
 722                 /* enable the VBI_GATE_EN */
 723                 value |= FLD_VBI_GATE_EN;
 724
 725                 /* Enable the auto-VGA enable */
 726                 value |= FLD_VGA_AUTO_EN;
 727
 728                 /* Write it back */
 729                 status = vid_blk_write_word(dev, DFE_CTRL1, value);
 730
 731                 /* Disable auto config of registers  */
 732                 status =  cx231xx_read_modify_write_i2c_dword(dev,
 733                                         VID_BLK_I2C_ADDRESS,
 734                                         MODE_CTRL, FLD_ACFG_DIS,
 735                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 736
 737                 /* Set YC input mode */
 738                 status = cx231xx_read_modify_write_i2c_dword(dev,
 739                         VID_BLK_I2C_ADDRESS,
 740                         MODE_CTRL,
 741                         FLD_INPUT_MODE,
 742                         cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
 743
 744                 /* Chroma to ADC2 */
 745                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 746                 value |= FLD_CHROMA_IN_SEL;     /* set the chroma in select */
 747
 748                 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
 749                    This sets them to use video
 750                    rather than audio.  Only one of the two will be in use. */
 751                 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
 752
 753                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 754
 755                 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
 756                 break;
 757         case CX231XX_VMUX_TELEVISION:
 758         case CX231XX_VMUX_CABLE:
 759         default:
 760                 switch (dev->model) {
 761                 case CX231XX_BOARD_CNXT_CARRAERA:
 762                 case CX231XX_BOARD_CNXT_RDE_250:
 763                 case CX231XX_BOARD_CNXT_SHELBY:
 764                 case CX231XX_BOARD_CNXT_RDU_250:
 765                         /* Disable the use of  DIF   */
 766
 767                         status = vid_blk_read_word(dev, AFE_CTRL, &value);
 768                         value |= (0 << 13) | (1 << 4);
 769                         value &= ~(1 << 5);
 770
 771                         /* set [24:23] [22:15] to 0 */
 772                         value &= (~(0x1FF8000));
 773                         /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
 774                         value |= 0x1000000;
 775                         status = vid_blk_write_word(dev, AFE_CTRL, value);
 776
 777                         status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 778                         value |= (1 << 7);
 779                         status = vid_blk_write_word(dev, OUT_CTRL1, value);
 780
 781                         /* Set vip 1.1 output mode */
 782                         status = cx231xx_read_modify_write_i2c_dword(dev,
 783                                                         VID_BLK_I2C_ADDRESS,
 784                                                         OUT_CTRL1, FLD_OUT_MODE,
 785                                                         OUT_MODE_VIP11);
 786
 787                         /* Tell DIF object to go to baseband mode */
 788                         status = cx231xx_dif_set_standard(dev,
 789                                                           DIF_USE_BASEBAND);
 790                         if (status < 0) {
 791                                 cx231xx_errdev("%s: cx231xx_dif set to By pass"
 792                                                 " mode- errCode [%d]!\n",
 793                                                 __func__, status);
 794                                 return status;
 795                         }
 796
 797                         /* Read the DFE_CTRL1 register */
 798                         status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 799
 800                         /* enable the VBI_GATE_EN */
 801                         value |= FLD_VBI_GATE_EN;
 802
 803                         /* Enable the auto-VGA enable */
 804                         value |= FLD_VGA_AUTO_EN;
 805
 806                         /* Write it back */
 807                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 808
 809                         /* Disable auto config of registers */
 810                         status = cx231xx_read_modify_write_i2c_dword(dev,
 811                                         VID_BLK_I2C_ADDRESS,
 812                                         MODE_CTRL, FLD_ACFG_DIS,
 813                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 814
 815                         /* Set CVBS input mode */
 816                         status = cx231xx_read_modify_write_i2c_dword(dev,
 817                                 VID_BLK_I2C_ADDRESS,
 818                                 MODE_CTRL, FLD_INPUT_MODE,
 819                                 cx231xx_set_field(FLD_INPUT_MODE,
 820                                                 INPUT_MODE_CVBS_0));
 821                         break;
 822                 default:
 823                         /* Enable the DIF for the tuner */
 824
 825                         /* Reinitialize the DIF */
 826                         status = cx231xx_dif_set_standard(dev, dev->norm);
 827                         if (status < 0) {
 828                                 cx231xx_errdev("%s: cx231xx_dif set to By pass"
 829                                                 " mode- errCode [%d]!\n",
 830                                                 __func__, status);
 831                                 return status;
 832                         }
 833
 834                         /* Make sure bypass is cleared */
 835                         status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
 836
 837                         /* Clear the bypass bit */
 838                         value &= ~FLD_DIF_DIF_BYPASS;
 839
 840                         /* Enable the use of the DIF block */
 841                         status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
 842
 843                         /* Read the DFE_CTRL1 register */
 844                         status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 845
 846                         /* Disable the VBI_GATE_EN */
 847                         value &= ~FLD_VBI_GATE_EN;
 848
 849                         /* Enable the auto-VGA enable, AGC, and
 850                            set the skip count to 2 */
 851                         value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
 852
 853                         /* Write it back */
 854                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 855
 856                         /* Wait until AGC locks up */
 857                         msleep(1);
 858
 859                         /* Disable the auto-VGA enable AGC */
 860                         value &= ~(FLD_VGA_AUTO_EN);
 861
 862                         /* Write it back */
 863                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 864
 865                         /* Enable Polaris B0 AGC output */
 866                         status = vid_blk_read_word(dev, PIN_CTRL, &value);
 867                         value |= (FLD_OEF_AGC_RF) |
 868                                  (FLD_OEF_AGC_IFVGA) |
 869                                  (FLD_OEF_AGC_IF);
 870                         status = vid_blk_write_word(dev, PIN_CTRL, value);
 871
 872                         /* Set vip 1.1 output mode */
 873                         status = cx231xx_read_modify_write_i2c_dword(dev,
 874                                                 VID_BLK_I2C_ADDRESS,
 875                                                 OUT_CTRL1, FLD_OUT_MODE,
 876                                                 OUT_MODE_VIP11);
 877
 878                         /* Disable auto config of registers */
 879                         status = cx231xx_read_modify_write_i2c_dword(dev,
 880                                         VID_BLK_I2C_ADDRESS,
 881                                         MODE_CTRL, FLD_ACFG_DIS,
 882                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 883
 884                         /* Set CVBS input mode */
 885                         status = cx231xx_read_modify_write_i2c_dword(dev,
 886                                 VID_BLK_I2C_ADDRESS,
 887                                 MODE_CTRL, FLD_INPUT_MODE,
 888                                 cx231xx_set_field(FLD_INPUT_MODE,
 889                                                 INPUT_MODE_CVBS_0));
 890
 891                         /* Set some bits in AFE_CTRL so that channel 2 or 3
 892                          * is ready to receive audio */
 893                         /* Clear clamp for channels 2 and 3      (bit 16-17) */
 894                         /* Clear droop comp                      (bit 19-20) */
 895                         /* Set VGA_SEL (for audio control)       (bit 7-8) */
 896                         status = vid_blk_read_word(dev, AFE_CTRL, &value);
 897
 898                         /*Set Func mode:01-DIF 10-baseband 11-YUV*/
 899                         value &= (~(FLD_FUNC_MODE));
 900                         value |= 0x800000;
 901
 902                         value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
 903
 904                         status = vid_blk_write_word(dev, AFE_CTRL, value);
 905
 906                         if (dev->tuner_type == TUNER_NXP_TDA18271) {
 907                                 status = vid_blk_read_word(dev, PIN_CTRL,
 908                                  &value);
 909                                 status = vid_blk_write_word(dev, PIN_CTRL,
 910                                  (value & 0xFFFFFFEF));
 911                         }
 912
 913                         break;
 914
 915                 }
 916                 break;
 917         }
 918
 919         /* Set raw VBI mode */
 920         status = cx231xx_read_modify_write_i2c_dword(dev,
 921                                 VID_BLK_I2C_ADDRESS,
 922                                 OUT_CTRL1, FLD_VBIHACTRAW_EN,
 923                                 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
 924
 925         status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 926         if (value & 0x02) {
 927                 value |= (1 << 19);
 928                 status = vid_blk_write_word(dev, OUT_CTRL1, value);
 929         }
 930
 931         return status;
 932 }
 933
 934 void cx231xx_enable656(struct cx231xx *dev)
 935 {
 936         u8 temp = 0;
 937         int status;
 938     /*enable TS1 data[0:7] as output to export 656*/
 939
 940         status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
 941
 942     /*enable TS1 clock as output to export 656*/
 943
 944         status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
 945         temp = temp|0x04;
 946
 947         status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
 948
 949 }
 950 EXPORT_SYMBOL_GPL(cx231xx_enable656);
 951
 952 void cx231xx_disable656(struct cx231xx *dev)
 953 {
 954         u8 temp = 0;
 955         int status;
 956
 957
 958         status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
 959
 960         status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
 961         temp = temp&0xFB;
 962
 963         status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
 964 }
 965 EXPORT_SYMBOL_GPL(cx231xx_disable656);
 966
 967 /*
 968  * Handle any video-mode specific overrides that are different
 969  * on a per video standards basis after touching the MODE_CTRL
 970  * register which resets many values for autodetect
 971  */
 972 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
 973 {
 974         int status = 0;
 975
 976         cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
 977                      (unsigned int)dev->norm);
 978
 979         /* Change the DFE_CTRL3 bp_percent to fix flagging */
 980         status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
 981
 982         if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
 983                 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
 984
 985                 /* Move the close caption lines out of active video,
 986                    adjust the active video start point */
 987                 status = cx231xx_read_modify_write_i2c_dword(dev,
 988                                                         VID_BLK_I2C_ADDRESS,
 989                                                         VERT_TIM_CTRL,
 990                                                         FLD_VBLANK_CNT, 0x18);
 991                 status = cx231xx_read_modify_write_i2c_dword(dev,
 992                                                         VID_BLK_I2C_ADDRESS,
 993                                                         VERT_TIM_CTRL,
 994                                                         FLD_VACTIVE_CNT,
 995                                                         0x1E7000);
 996                 status = cx231xx_read_modify_write_i2c_dword(dev,
 997                                                         VID_BLK_I2C_ADDRESS,
 998                                                         VERT_TIM_CTRL,
 999                                                         FLD_V656BLANK_CNT,
1000                                                         0x1C000000);
1001
1002                 status = cx231xx_read_modify_write_i2c_dword(dev,
1003                                                         VID_BLK_I2C_ADDRESS,
1004                                                         HORIZ_TIM_CTRL,
1005                                                         FLD_HBLANK_CNT,
1006                                                         cx231xx_set_field
1007                                                         (FLD_HBLANK_CNT, 0x79));
1008
1009         } else if (dev->norm & V4L2_STD_SECAM) {
1010                 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1011                 status =  cx231xx_read_modify_write_i2c_dword(dev,
1012                                                         VID_BLK_I2C_ADDRESS,
1013                                                         VERT_TIM_CTRL,
1014                                                         FLD_VBLANK_CNT, 0x24);
1015                 status = cx231xx_read_modify_write_i2c_dword(dev,
1016                                                         VID_BLK_I2C_ADDRESS,
1017                                                         VERT_TIM_CTRL,
1018                                                         FLD_V656BLANK_CNT,
1019                                                         cx231xx_set_field
1020                                                         (FLD_V656BLANK_CNT,
1021                                                         0x28));
1022                 /* Adjust the active video horizontal start point */
1023                 status = cx231xx_read_modify_write_i2c_dword(dev,
1024                                                         VID_BLK_I2C_ADDRESS,
1025                                                         HORIZ_TIM_CTRL,
1026                                                         FLD_HBLANK_CNT,
1027                                                         cx231xx_set_field
1028                                                         (FLD_HBLANK_CNT, 0x85));
1029         } else {
1030                 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1031                 status = cx231xx_read_modify_write_i2c_dword(dev,
1032                                                         VID_BLK_I2C_ADDRESS,
1033                                                         VERT_TIM_CTRL,
1034                                                         FLD_VBLANK_CNT, 0x24);
1035                 status = cx231xx_read_modify_write_i2c_dword(dev,
1036                                                         VID_BLK_I2C_ADDRESS,
1037                                                         VERT_TIM_CTRL,
1038                                                         FLD_V656BLANK_CNT,
1039                                                         cx231xx_set_field
1040                                                         (FLD_V656BLANK_CNT,
1041                                                         0x28));
1042                 /* Adjust the active video horizontal start point */
1043                 status = cx231xx_read_modify_write_i2c_dword(dev,
1044                                                         VID_BLK_I2C_ADDRESS,
1045                                                         HORIZ_TIM_CTRL,
1046                                                         FLD_HBLANK_CNT,
1047                                                         cx231xx_set_field
1048                                                         (FLD_HBLANK_CNT, 0x85));
1049
1050         }
1051
1052         return status;
1053 }
1054
1055 int cx231xx_unmute_audio(struct cx231xx *dev)
1056 {
1057         return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1058 }
1059 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1060
1061 int stopAudioFirmware(struct cx231xx *dev)
1062 {
1063         return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1064 }
1065
1066 int restartAudioFirmware(struct cx231xx *dev)
1067 {
1068         return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1069 }
1070
1071 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1072 {
1073         int status = 0;
1074         enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1075
1076         switch (INPUT(input)->amux) {
1077         case CX231XX_AMUX_VIDEO:
1078                 ainput = AUDIO_INPUT_TUNER_TV;
1079                 break;
1080         case CX231XX_AMUX_LINE_IN:
1081                 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1082                 ainput = AUDIO_INPUT_LINE;
1083                 break;
1084         default:
1085                 break;
1086         }
1087
1088         status = cx231xx_set_audio_decoder_input(dev, ainput);
1089
1090         return status;
1091 }
1092
1093 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1094                                     enum AUDIO_INPUT audio_input)
1095 {
1096         u32 dwval;
1097         int status;
1098         u8 gen_ctrl;
1099         u32 value = 0;
1100
1101         /* Put it in soft reset   */
1102         status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1103         gen_ctrl |= 1;
1104         status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1105
1106         switch (audio_input) {
1107         case AUDIO_INPUT_LINE:
1108                 /* setup AUD_IO control from Merlin paralle output */
1109                 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1110                                           AUD_CHAN_SRC_PARALLEL);
1111                 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1112
1113                 /* setup input to Merlin, SRC2 connect to AC97
1114                    bypass upsample-by-2, slave mode, sony mode, left justify
1115                    adr 091c, dat 01000000 */
1116                 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1117
1118                 status = vid_blk_write_word(dev, AC97_CTL,
1119                                            (dwval | FLD_AC97_UP2X_BYPASS));
1120
1121                 /* select the parallel1 and SRC3 */
1122                 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1123                                 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1124                                 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1125                                 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1126
1127                 /* unmute all, AC97 in, independence mode
1128                    adr 08d0, data 0x00063073 */
1129                 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1130                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1131
1132                 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1133                 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1134                 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1135                                            (dwval | FLD_PATH1_AVC_THRESHOLD));
1136
1137                 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1138                 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1139                 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1140                                            (dwval | FLD_PATH1_SC_THRESHOLD));
1141                 break;
1142
1143         case AUDIO_INPUT_TUNER_TV:
1144         default:
1145                 status = stopAudioFirmware(dev);
1146                 /* Setup SRC sources and clocks */
1147                 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1148                         cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00)         |
1149                         cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01)        |
1150                         cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00)         |
1151                         cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02)        |
1152                         cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02)         |
1153                         cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03)        |
1154                         cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00)         |
1155                         cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00)        |
1156                         cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1157                         cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03)        |
1158                         cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00)         |
1159                         cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02)   |
1160                         cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1161
1162                 /* Setup the AUD_IO control */
1163                 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1164                         cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00)  |
1165                         cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00)   |
1166                         cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1167                         cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1168                         cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1169
1170                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1171
1172                 /* setAudioStandard(_audio_standard); */
1173                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1174
1175                 status = restartAudioFirmware(dev);
1176
1177                 switch (dev->model) {
1178                 case CX231XX_BOARD_CNXT_CARRAERA:
1179                 case CX231XX_BOARD_CNXT_RDE_250:
1180                 case CX231XX_BOARD_CNXT_SHELBY:
1181                 case CX231XX_BOARD_CNXT_RDU_250:
1182                 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1183                         status = cx231xx_read_modify_write_i2c_dword(dev,
1184                                         VID_BLK_I2C_ADDRESS,
1185                                         CHIP_CTRL,
1186                                         FLD_SIF_EN,
1187                                         cx231xx_set_field(FLD_SIF_EN, 1));
1188                         break;
1189                 case CX231XX_BOARD_CNXT_RDE_253S:
1190                 case CX231XX_BOARD_CNXT_RDU_253S:
1191                 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1192                         status = cx231xx_read_modify_write_i2c_dword(dev,
1193                                         VID_BLK_I2C_ADDRESS,
1194                                         CHIP_CTRL,
1195                                         FLD_SIF_EN,
1196                                         cx231xx_set_field(FLD_SIF_EN, 0));
1197                         break;
1198                 default:
1199                         break;
1200                 }
1201                 break;
1202
1203         case AUDIO_INPUT_TUNER_FM:
1204                 /*  use SIF for FM radio
1205                    setupFM();
1206                    setAudioStandard(_audio_standard);
1207                  */
1208                 break;
1209
1210         case AUDIO_INPUT_MUTE:
1211                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1212                 break;
1213         }
1214
1215         /* Take it out of soft reset */
1216         status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1217         gen_ctrl &= ~1;
1218         status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1219
1220         return status;
1221 }
1222
1223 /******************************************************************************
1224  *                    C H I P Specific  C O N T R O L   functions             *
1225  ******************************************************************************/
1226 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1227 {
1228         u32 value;
1229         int status = 0;
1230
1231         status = vid_blk_read_word(dev, PIN_CTRL, &value);
1232         value |= (~dev->board.ctl_pin_status_mask);
1233         status = vid_blk_write_word(dev, PIN_CTRL, value);
1234
1235         return status;
1236 }
1237
1238 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1239                                               u8 analog_or_digital)
1240 {
1241         int status = 0;
1242
1243         /* first set the direction to output */
1244         status = cx231xx_set_gpio_direction(dev,
1245                                             dev->board.
1246                                             agc_analog_digital_select_gpio, 1);
1247
1248         /* 0 - demod ; 1 - Analog mode */
1249         status = cx231xx_set_gpio_value(dev,
1250                                    dev->board.agc_analog_digital_select_gpio,
1251                                    analog_or_digital);
1252
1253         return status;
1254 }
1255
1256 int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1257 {
1258         u8 value[4] = { 0, 0, 0, 0 };
1259         int status = 0;
1260
1261         cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1262
1263         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1264                                        PWR_CTL_EN, value, 4);
1265         if (status < 0)
1266                 return status;
1267
1268         if (I2CIndex == I2C_1) {
1269                 if (value[0] & I2C_DEMOD_EN) {
1270                         value[0] &= ~I2C_DEMOD_EN;
1271                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1272                                                    PWR_CTL_EN, value, 4);
1273                 }
1274         } else {
1275                 if (!(value[0] & I2C_DEMOD_EN)) {
1276                         value[0] |= I2C_DEMOD_EN;
1277                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1278                                                    PWR_CTL_EN, value, 4);
1279                 }
1280         }
1281
1282         return status;
1283
1284 }
1285 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_for_tuner);
1286 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1287 {
1288 /*
1289         u8 status = 0;
1290         u32 value = 0;
1291
1292         vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1293         vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1294         vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1295
1296         status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1297         vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1298         status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL,  &value);
1299 */
1300 }
1301
1302 void cx231xx_dump_HH_reg(struct cx231xx *dev)
1303 {
1304         u8 status = 0;
1305         u32 value = 0;
1306         u16  i = 0;
1307
1308         value = 0x45005390;
1309         status = vid_blk_write_word(dev, 0x104, value);
1310
1311         for (i = 0x100; i < 0x140; i++) {
1312                 status = vid_blk_read_word(dev, i, &value);
1313                 cx231xx_info("reg0x%x=0x%x\n", i, value);
1314                 i = i+3;
1315         }
1316
1317         for (i = 0x300; i < 0x400; i++) {
1318                 status = vid_blk_read_word(dev, i, &value);
1319                 cx231xx_info("reg0x%x=0x%x\n", i, value);
1320                 i = i+3;
1321         }
1322
1323         for (i = 0x400; i < 0x440; i++) {
1324                 status = vid_blk_read_word(dev, i,  &value);
1325                 cx231xx_info("reg0x%x=0x%x\n", i, value);
1326                 i = i+3;
1327         }
1328
1329    status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1330    cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1331    vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1332    status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1333    cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1334
1335 }
1336 void cx231xx_dump_SC_reg(struct cx231xx *dev)
1337 {
1338         u8 value[4] = { 0, 0, 0, 0 };
1339         int status = 0;
1340         cx231xx_info("cx231xx_dump_SC_reg %s!\n", __TIME__);
1341
1342         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1343                                  value, 4);
1344         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1345                                  value[1], value[2], value[3]);
1346         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1347                                  value, 4);
1348         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1349                                  value[1], value[2], value[3]);
1350         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1351                                  value, 4);
1352         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1353                                  value[1], value[2], value[3]);
1354         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1355                                  value, 4);
1356         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1357                                  value[1], value[2], value[3]);
1358
1359         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1360                                  value, 4);
1361         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1362                                  value[1], value[2], value[3]);
1363         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1364                                  value, 4);
1365         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1366                                  value[1], value[2], value[3]);
1367         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1368                                  value, 4);
1369         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1370                                  value[1], value[2], value[3]);
1371         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1372                                  value, 4);
1373         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1374                                  value[1], value[2], value[3]);
1375
1376         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1377                                  value, 4);
1378         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1379                                  value[1], value[2], value[3]);
1380         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1381                                  value, 4);
1382         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1383                                  value[1], value[2], value[3]);
1384         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1385                                  value, 4);
1386         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1387                                  value[1], value[2], value[3]);
1388         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1389                                  value, 4);
1390         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1391                                  value[1], value[2], value[3]);
1392
1393         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1394                                  value, 4);
1395         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1396                                  value[1], value[2], value[3]);
1397         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1398                                  value, 4);
1399         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1400                                  value[1], value[2], value[3]);
1401         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1402                                  value, 4);
1403         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1404                                  value[1], value[2], value[3]);
1405         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1406                                  value, 4);
1407         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1408                                  value[1], value[2], value[3]);
1409
1410         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1411                                  value, 4);
1412         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1413                                  value[1], value[2], value[3]);
1414         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1415                                  value, 4);
1416         cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1417                                  value[1], value[2], value[3]);
1418
1419
1420 }
1421
1422 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1423
1424 {
1425         u8 status = 0;
1426         u8 value = 0;
1427
1428
1429
1430         status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1431         value = (value & 0xFE)|0x01;
1432         status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1433
1434         status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1435         value = (value & 0xFE)|0x00;
1436         status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1437
1438
1439 /*
1440      config colibri to lo-if mode
1441
1442      FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1443          the diff IF input by half,
1444
1445             for low-if agc defect
1446 */
1447
1448         status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1449         value = (value & 0xFC)|0x00;
1450         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1451
1452         status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
1453         value = (value & 0xF9)|0x02;
1454         status = afe_write_byte(dev, ADC_INPUT_CH3, value);
1455
1456         status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1457         value = (value & 0xFB)|0x04;
1458         status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1459
1460         status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1461         value = (value & 0xFC)|0x03;
1462         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1463
1464         status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1465         value = (value & 0xFB)|0x04;
1466         status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1467
1468         status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1469         value = (value & 0xF8)|0x06;
1470         status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1471
1472         status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1473         value = (value & 0x8F)|0x40;
1474         status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1475
1476         status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1477         value = (value & 0xDF)|0x20;
1478         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1479 }
1480
1481 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1482                  u8 spectral_invert, u32 mode)
1483 {
1484
1485     u32 colibri_carrier_offset = 0;
1486     u8 status = 0;
1487     u32 func_mode = 0;
1488     u32 standard = 0;
1489         u8 value[4] = { 0, 0, 0, 0 };
1490
1491         switch (dev->model) {
1492         case CX231XX_BOARD_CNXT_CARRAERA:
1493         case CX231XX_BOARD_CNXT_RDE_250:
1494         case CX231XX_BOARD_CNXT_SHELBY:
1495         case CX231XX_BOARD_CNXT_RDU_250:
1496         case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1497                 func_mode = 0x03;
1498                 break;
1499         case CX231XX_BOARD_CNXT_RDE_253S:
1500         case CX231XX_BOARD_CNXT_RDU_253S:
1501                 func_mode = 0x01;
1502                 break;
1503
1504         default:
1505                 func_mode = 0x01;
1506         }
1507
1508         cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
1509                 value[0] = (u8) 0x6F;
1510                 value[1] = (u8) 0x6F;
1511                 value[2] = (u8) 0x6F;
1512                 value[3] = (u8) 0x6F;
1513                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1514                                                 PWR_CTL_EN, value, 4);
1515     if (1) {
1516
1517         /*Set colibri for low IF*/
1518         status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1519
1520
1521         /* Set C2HH for low IF operation.*/
1522         standard = dev->norm;
1523         status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1524                                                   func_mode, standard);
1525
1526
1527         /* Get colibri offsets.*/
1528         colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1529                                          standard);
1530
1531         cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
1532                                  colibri_carrier_offset, standard);
1533
1534         /* Set the band Pass filter for DIF*/
1535         cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset)
1536                  , spectral_invert, mode);
1537     }
1538 }
1539
1540 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1541 {
1542     u32 colibri_carrier_offset = 0;
1543
1544
1545     if (mode == TUNER_MODE_FM_RADIO) {
1546                 colibri_carrier_offset = 1100000;
1547         } else if (standerd & (V4L2_STD_NTSC | V4L2_STD_NTSC_M_JP)) {
1548                 colibri_carrier_offset = 4832000;  /*4.83MHz    */
1549         } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1550                 colibri_carrier_offset = 2700000;  /*2.70MHz       */
1551         } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1552                         | V4L2_STD_SECAM)) {
1553                 colibri_carrier_offset = 2100000;  /*2.10MHz    */
1554         }
1555
1556
1557     return colibri_carrier_offset;
1558 }
1559
1560 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1561                  u8 spectral_invert, u32 mode)
1562 {
1563
1564     unsigned long pll_freq_word;
1565     int status = 0;
1566     u32 dif_misc_ctrl_value = 0;
1567     u64 pll_freq_u64 = 0;
1568     u32 i = 0;
1569
1570
1571         cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1572                          if_freq, spectral_invert, mode);
1573
1574
1575     if (mode == TUNER_MODE_FM_RADIO) {
1576         pll_freq_word = 0x905A1CAC;
1577         status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD,  pll_freq_word);
1578
1579     } else /*KSPROPERTY_TUNER_MODE_TV*/{
1580        /* Calculate the PLL frequency word based on the adjusted if_freq*/
1581         pll_freq_word = if_freq;
1582         pll_freq_u64 = (u64)pll_freq_word << 28L;
1583         do_div(pll_freq_u64, 50000000);
1584         pll_freq_word = (u32)pll_freq_u64;
1585         /*pll_freq_word = 0x3463497;*/
1586         status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD,  pll_freq_word);
1587
1588     if (spectral_invert) {
1589         if_freq -= 400000;
1590         /* Enable Spectral Invert*/
1591         status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1592                                  &dif_misc_ctrl_value);
1593         dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1594         status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1595                                  dif_misc_ctrl_value);
1596     } else {
1597         if_freq += 400000;
1598         /* Disable Spectral Invert*/
1599         status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1600                                  &dif_misc_ctrl_value);
1601         dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1602         status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1603                                  dif_misc_ctrl_value);
1604     }
1605
1606         if_freq = (if_freq/100000)*100000;
1607
1608     if (if_freq < 3000000)
1609         if_freq = 3000000;
1610
1611     if (if_freq > 16000000)
1612         if_freq = 16000000;
1613     }
1614
1615     cx231xx_info("Enter IF=%d\n",
1616                  sizeof(Dif_set_array)/sizeof(struct dif_settings));
1617     for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
1618         if (Dif_set_array[i].if_freq == if_freq) {
1619                 status = vid_blk_write_word(dev,
1620                  Dif_set_array[i].register_address, Dif_set_array[i].value);
1621         }
1622     }
1623
1624 }
1625
1626 /******************************************************************************
1627  *                 D I F - B L O C K    C O N T R O L   functions             *
1628  ******************************************************************************/
1629 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1630                                           u32 function_mode, u32 standard)
1631 {
1632         int status = 0;
1633
1634
1635         if (mode == V4L2_TUNER_RADIO) {
1636                 /* C2HH */
1637                 /* lo if big signal */
1638                 status = cx231xx_reg_mask_write(dev,
1639                                 VID_BLK_I2C_ADDRESS, 32,
1640                                 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1641                 /* FUNC_MODE = DIF */
1642                 status = cx231xx_reg_mask_write(dev,
1643                                 VID_BLK_I2C_ADDRESS, 32,
1644                                 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1645                 /* IF_MODE */
1646                 status = cx231xx_reg_mask_write(dev,
1647                                 VID_BLK_I2C_ADDRESS, 32,
1648                                 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1649                 /* no inv */
1650                 status = cx231xx_reg_mask_write(dev,
1651                                 VID_BLK_I2C_ADDRESS, 32,
1652                                 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1653         } else if (standard != DIF_USE_BASEBAND) {
1654                 if (standard & V4L2_STD_MN) {
1655                         /* lo if big signal */
1656                         status = cx231xx_reg_mask_write(dev,
1657                                         VID_BLK_I2C_ADDRESS, 32,
1658                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1659                         /* FUNC_MODE = DIF */
1660                         status = cx231xx_reg_mask_write(dev,
1661                                         VID_BLK_I2C_ADDRESS, 32,
1662                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1663                                         function_mode);
1664                         /* IF_MODE */
1665                         status = cx231xx_reg_mask_write(dev,
1666                                         VID_BLK_I2C_ADDRESS, 32,
1667                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1668                         /* no inv */
1669                         status = cx231xx_reg_mask_write(dev,
1670                                         VID_BLK_I2C_ADDRESS, 32,
1671                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1672                         /* 0x124, AUD_CHAN1_SRC = 0x3 */
1673                         status = cx231xx_reg_mask_write(dev,
1674                                         VID_BLK_I2C_ADDRESS, 32,
1675                                         AUD_IO_CTRL, 0, 31, 0x00000003);
1676                 } else if ((standard == V4L2_STD_PAL_I) |
1677                         (standard & V4L2_STD_PAL_D) |
1678                         (standard & V4L2_STD_SECAM)) {
1679                         /* C2HH setup */
1680                         /* lo if big signal */
1681                         status = cx231xx_reg_mask_write(dev,
1682                                         VID_BLK_I2C_ADDRESS, 32,
1683                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1684                         /* FUNC_MODE = DIF */
1685                         status = cx231xx_reg_mask_write(dev,
1686                                         VID_BLK_I2C_ADDRESS, 32,
1687                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1688                                         function_mode);
1689                         /* IF_MODE */
1690                         status = cx231xx_reg_mask_write(dev,
1691                                         VID_BLK_I2C_ADDRESS, 32,
1692                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1693                         /* no inv */
1694                         status = cx231xx_reg_mask_write(dev,
1695                                         VID_BLK_I2C_ADDRESS, 32,
1696                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1697                 } else {
1698                         /* default PAL BG */
1699                         /* C2HH setup */
1700                         /* lo if big signal */
1701                         status = cx231xx_reg_mask_write(dev,
1702                                         VID_BLK_I2C_ADDRESS, 32,
1703                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1704                         /* FUNC_MODE = DIF */
1705                         status = cx231xx_reg_mask_write(dev,
1706                                         VID_BLK_I2C_ADDRESS, 32,
1707                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1708                                         function_mode);
1709                         /* IF_MODE */
1710                         status = cx231xx_reg_mask_write(dev,
1711                                         VID_BLK_I2C_ADDRESS, 32,
1712                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1713                         /* no inv */
1714                         status = cx231xx_reg_mask_write(dev,
1715                                         VID_BLK_I2C_ADDRESS, 32,
1716                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1717                 }
1718         }
1719
1720         return status;
1721 }
1722
1723 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1724 {
1725         int status = 0;
1726         u32 dif_misc_ctrl_value = 0;
1727         u32 func_mode = 0;
1728
1729         cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1730
1731         status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1732         if (standard != DIF_USE_BASEBAND)
1733                 dev->norm = standard;
1734
1735         switch (dev->model) {
1736         case CX231XX_BOARD_CNXT_CARRAERA:
1737         case CX231XX_BOARD_CNXT_RDE_250:
1738         case CX231XX_BOARD_CNXT_SHELBY:
1739         case CX231XX_BOARD_CNXT_RDU_250:
1740         case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1741         case CX231XX_BOARD_HAUPPAUGE_EXETER:
1742                 func_mode = 0x03;
1743                 break;
1744         case CX231XX_BOARD_CNXT_RDE_253S:
1745         case CX231XX_BOARD_CNXT_RDU_253S:
1746                 func_mode = 0x01;
1747                 break;
1748         default:
1749                 func_mode = 0x01;
1750         }
1751
1752         status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1753                                                   func_mode, standard);
1754
1755         if (standard == DIF_USE_BASEBAND) {     /* base band */
1756                 /* There is a different SRC_PHASE_INC value
1757                    for baseband vs. DIF */
1758                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1759                 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1760                                                 &dif_misc_ctrl_value);
1761                 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1762                 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1763                                                 dif_misc_ctrl_value);
1764         } else if (standard & V4L2_STD_PAL_D) {
1765                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1766                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1767                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1768                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1769                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1770                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1771                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1772                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1773                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1774                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1775                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1776                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1777                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1778                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1779                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1780                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1781                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1782                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1783                                            0x26001700);
1784                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1785                                            DIF_AGC_RF_CURRENT, 0, 31,
1786                                            0x00002660);
1787                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1788                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1789                                            0x72500800);
1790                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1791                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1792                                            0x27000100);
1793                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1794                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1795                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1796                                            DIF_COMP_FLT_CTRL, 0, 31,
1797                                            0x00000000);
1798                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1799                                            DIF_SRC_PHASE_INC, 0, 31,
1800                                            0x1befbf06);
1801                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1802                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1803                                            0x000035e8);
1804                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1805                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1806                 /* Save the Spec Inversion value */
1807                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1808                 dif_misc_ctrl_value |= 0x3a023F11;
1809         } else if (standard & V4L2_STD_PAL_I) {
1810                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1811                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1812                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1813                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1814                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1815                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1816                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1817                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1818                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1819                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1820                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1821                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1822                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1823                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1824                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1825                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1826                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1827                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1828                                            0x26001700);
1829                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1830                                            DIF_AGC_RF_CURRENT, 0, 31,
1831                                            0x00002660);
1832                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1833                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1834                                            0x72500800);
1835                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1836                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1837                                            0x27000100);
1838                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1839                                            DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1840                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1841                                            DIF_COMP_FLT_CTRL, 0, 31,
1842                                            0x00000000);
1843                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1844                                            DIF_SRC_PHASE_INC, 0, 31,
1845                                            0x1befbf06);
1846                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1847                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1848                                            0x000035e8);
1849                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1850                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1851                 /* Save the Spec Inversion value */
1852                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1853                 dif_misc_ctrl_value |= 0x3a033F11;
1854         } else if (standard & V4L2_STD_PAL_M) {
1855                 /* improved Low Frequency Phase Noise */
1856                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1857                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1858                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1859                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1860                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1861                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1862                                                 0x26001700);
1863                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1864                                                 0x00002660);
1865                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1866                                                 0x72500800);
1867                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1868                                                 0x27000100);
1869                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1870                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1871                                                 0x009f50c1);
1872                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1873                                                 0x1befbf06);
1874                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1875                                                 0x000035e8);
1876                 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1877                                                 0x00000000);
1878                 /* Save the Spec Inversion value */
1879                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1880                 dif_misc_ctrl_value |= 0x3A0A3F10;
1881         } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1882                 /* improved Low Frequency Phase Noise */
1883                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1884                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1885                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1886                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1887                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1888                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1889                                                 0x26001700);
1890                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1891                                                 0x00002660);
1892                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1893                                                 0x72500800);
1894                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1895                                                 0x27000100);
1896                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1897                                                 0x012c405d);
1898                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1899                                                 0x009f50c1);
1900                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1901                                                 0x1befbf06);
1902                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1903                                                 0x000035e8);
1904                 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1905                                                 0x00000000);
1906                 /* Save the Spec Inversion value */
1907                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1908                 dif_misc_ctrl_value = 0x3A093F10;
1909         } else if (standard &
1910                   (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1911                    V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1912
1913                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1914                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1915                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1916                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1917                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1918                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1919                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1920                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1921                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1922                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1923                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1924                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1925                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1926                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1927                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1928                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1929                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1930                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1931                                            0x26001700);
1932                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1933                                            DIF_AGC_RF_CURRENT, 0, 31,
1934                                            0x00002660);
1935                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1936                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1937                                            0x27000100);
1938                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1939                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1940                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1941                                            DIF_COMP_FLT_CTRL, 0, 31,
1942                                            0x00000000);
1943                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1944                                            DIF_SRC_PHASE_INC, 0, 31,
1945                                            0x1befbf06);
1946                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1947                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1948                                            0x000035e8);
1949                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1950                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1951                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1952                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1953                                            0xf4000000);
1954
1955                 /* Save the Spec Inversion value */
1956                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1957                 dif_misc_ctrl_value |= 0x3a023F11;
1958         } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1959                 /* Is it SECAM_L1? */
1960                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1961                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1962                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1963                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1964                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1965                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1966                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1967                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1968                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1969                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1970                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1971                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1972                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1973                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1974                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1975                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1976                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1977                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1978                                            0x26001700);
1979                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1980                                            DIF_AGC_RF_CURRENT, 0, 31,
1981                                            0x00002660);
1982                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1983                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1984                                            0x27000100);
1985                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1986                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1987                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1988                                            DIF_COMP_FLT_CTRL, 0, 31,
1989                                            0x00000000);
1990                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1991                                            DIF_SRC_PHASE_INC, 0, 31,
1992                                            0x1befbf06);
1993                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1994                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1995                                            0x000035e8);
1996                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1997                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1998                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1999                                            DIF_VIDEO_AGC_CTRL, 0, 31,
2000                                            0xf2560000);
2001
2002                 /* Save the Spec Inversion value */
2003                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2004                 dif_misc_ctrl_value |= 0x3a023F11;
2005
2006         } else if (standard & V4L2_STD_NTSC_M) {
2007                 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
2008                    V4L2_STD_NTSC_M_JP (Japan,  0 IRE Setup) */
2009
2010                 /* For NTSC the centre frequency of video coming out of
2011                    sidewinder is around 7.1MHz or 3.6MHz depending on the
2012                    spectral inversion. so for a non spectrally inverted channel
2013                    the pll freq word is 0x03420c49
2014                  */
2015
2016                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2017                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2018                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2019                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2020                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2021                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2022                                                 0x26001700);
2023                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2024                                                 0x00002660);
2025                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2026                                                 0x04000800);
2027                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2028                                                 0x27000100);
2029                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2030
2031                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2032                                                 0x009f50c1);
2033                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2034                                                 0x1befbf06);
2035                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2036                                                 0x000035e8);
2037
2038                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2039                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2040                                                 0xC2262600);
2041                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2042
2043                 /* Save the Spec Inversion value */
2044                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2045                 dif_misc_ctrl_value |= 0x3a003F10;
2046         } else {
2047                 /* default PAL BG */
2048                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2049                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
2050                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2051                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
2052                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2053                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
2054                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2055                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
2056                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2057                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
2058                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2059                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
2060                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2061                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
2062                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2063                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
2064                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2065                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
2066                                            0x26001700);
2067                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2068                                            DIF_AGC_RF_CURRENT, 0, 31,
2069                                            0x00002660);
2070                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2071                                            DIF_VIDEO_AGC_CTRL, 0, 31,
2072                                            0x72500800);
2073                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2074                                            DIF_VID_AUD_OVERRIDE, 0, 31,
2075                                            0x27000100);
2076                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2077                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
2078                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2079                                            DIF_COMP_FLT_CTRL, 0, 31,
2080                                            0x00A653A8);
2081                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2082                                            DIF_SRC_PHASE_INC, 0, 31,
2083                                            0x1befbf06);
2084                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2085                                            DIF_SRC_GAIN_CONTROL, 0, 31,
2086                                            0x000035e8);
2087                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2088                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2089                 /* Save the Spec Inversion value */
2090                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2091                 dif_misc_ctrl_value |= 0x3a013F11;
2092         }
2093
2094         /* The AGC values should be the same for all standards,
2095            AUD_SRC_SEL[19] should always be disabled    */
2096         dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2097
2098         /* It is still possible to get Set Standard calls even when we
2099            are in FM mode.
2100            This is done to override the value for FM. */
2101         if (dev->active_mode == V4L2_TUNER_RADIO)
2102                 dif_misc_ctrl_value = 0x7a080000;
2103
2104         /* Write the calculated value for misc ontrol register      */
2105         status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2106
2107         return status;
2108 }
2109
2110 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2111 {
2112         int status = 0;
2113         u32 dwval;
2114
2115         /* Set the RF and IF k_agc values to 3 */
2116         status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2117         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2118         dwval |= 0x33000000;
2119
2120         status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2121
2122         return status;
2123 }
2124
2125 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2126 {
2127         int status = 0;
2128         u32 dwval;
2129    cx231xx_info("cx231xx_tuner_post_channel_change  dev->tuner_type =0%d\n",
2130                          dev->tuner_type);
2131         /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2132          * SECAM L/B/D standards */
2133         status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2134         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2135
2136         if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2137                          V4L2_STD_SECAM_D)) {
2138                         if (dev->tuner_type == TUNER_NXP_TDA18271) {
2139                                 dwval &= ~FLD_DIF_IF_REF;
2140                                 dwval |= 0x88000300;
2141                         } else
2142                                 dwval |= 0x88000000;
2143                 } else {
2144                         if (dev->tuner_type == TUNER_NXP_TDA18271) {
2145                                 dwval &= ~FLD_DIF_IF_REF;
2146                                 dwval |= 0xCC000300;
2147                         } else
2148                                 dwval |= 0x44000000;
2149                 }
2150
2151         status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2152
2153         return status;
2154 }
2155
2156 /******************************************************************************
2157  *                  I 2 S - B L O C K    C O N T R O L   functions            *
2158  ******************************************************************************/
2159 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2160 {
2161         int status = 0;
2162         u32 value;
2163
2164         status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2165                                        CH_PWR_CTRL1, 1, &value, 1);
2166         /* enables clock to delta-sigma and decimation filter */
2167         value |= 0x80;
2168         status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2169                                         CH_PWR_CTRL1, 1, value, 1);
2170         /* power up all channel */
2171         status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2172                                         CH_PWR_CTRL2, 1, 0x00, 1);
2173
2174         return status;
2175 }
2176
2177 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2178                                         enum AV_MODE avmode)
2179 {
2180         int status = 0;
2181         u32 value = 0;
2182
2183         if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2184                 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2185                                           CH_PWR_CTRL2, 1, &value, 1);
2186                 value |= 0xfe;
2187                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2188                                                 CH_PWR_CTRL2, 1, value, 1);
2189         } else {
2190                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2191                                                 CH_PWR_CTRL2, 1, 0x00, 1);
2192         }
2193
2194         return status;
2195 }
2196
2197 /* set i2s_blk for audio input types */
2198 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2199 {
2200         int status = 0;
2201
2202         switch (audio_input) {
2203         case CX231XX_AMUX_LINE_IN:
2204                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2205                                                 CH_PWR_CTRL2, 1, 0x00, 1);
2206                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2207                                                 CH_PWR_CTRL1, 1, 0x80, 1);
2208                 break;
2209         case CX231XX_AMUX_VIDEO:
2210         default:
2211                 break;
2212         }
2213
2214         dev->ctl_ainput = audio_input;
2215
2216         return status;
2217 }
2218
2219 /******************************************************************************
2220  *                  P O W E R      C O N T R O L   functions                  *
2221  ******************************************************************************/
2222 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2223 {
2224         u8 value[4] = { 0, 0, 0, 0 };
2225         u32 tmp = 0;
2226         int status = 0;
2227
2228         if (dev->power_mode != mode)
2229                 dev->power_mode = mode;
2230         else {
2231                 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
2232                              mode);
2233                 return 0;
2234         }
2235
2236         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2237                                        4);
2238         if (status < 0)
2239                 return status;
2240
2241         tmp = *((u32 *) value);
2242
2243         switch (mode) {
2244         case POLARIS_AVMODE_ENXTERNAL_AV:
2245
2246                 tmp &= (~PWR_MODE_MASK);
2247
2248                 tmp |= PWR_AV_EN;
2249                 value[0] = (u8) tmp;
2250                 value[1] = (u8) (tmp >> 8);
2251                 value[2] = (u8) (tmp >> 16);
2252                 value[3] = (u8) (tmp >> 24);
2253                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2254                                                 PWR_CTL_EN, value, 4);
2255                 msleep(PWR_SLEEP_INTERVAL);
2256
2257                 tmp |= PWR_ISO_EN;
2258                 value[0] = (u8) tmp;
2259                 value[1] = (u8) (tmp >> 8);
2260                 value[2] = (u8) (tmp >> 16);
2261                 value[3] = (u8) (tmp >> 24);
2262                 status =
2263                     cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2264                                            value, 4);
2265                 msleep(PWR_SLEEP_INTERVAL);
2266
2267                 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2268                 value[0] = (u8) tmp;
2269                 value[1] = (u8) (tmp >> 8);
2270                 value[2] = (u8) (tmp >> 16);
2271                 value[3] = (u8) (tmp >> 24);
2272                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2273                                                 PWR_CTL_EN, value, 4);
2274
2275                 /* reset state of xceive tuner */
2276                 dev->xc_fw_load_done = 0;
2277                 break;
2278
2279         case POLARIS_AVMODE_ANALOGT_TV:
2280
2281                 tmp |= PWR_DEMOD_EN;
2282                 tmp |= (I2C_DEMOD_EN);
2283                 value[0] = (u8) tmp;
2284                 value[1] = (u8) (tmp >> 8);
2285                 value[2] = (u8) (tmp >> 16);
2286                 value[3] = (u8) (tmp >> 24);
2287                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2288                                                 PWR_CTL_EN, value, 4);
2289                 msleep(PWR_SLEEP_INTERVAL);
2290
2291                 if (!(tmp & PWR_TUNER_EN)) {
2292                         tmp |= (PWR_TUNER_EN);
2293                         value[0] = (u8) tmp;
2294                         value[1] = (u8) (tmp >> 8);
2295                         value[2] = (u8) (tmp >> 16);
2296                         value[3] = (u8) (tmp >> 24);
2297                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2298                                                         PWR_CTL_EN, value, 4);
2299                         msleep(PWR_SLEEP_INTERVAL);
2300                 }
2301
2302                 if (!(tmp & PWR_AV_EN)) {
2303                         tmp |= PWR_AV_EN;
2304                         value[0] = (u8) tmp;
2305                         value[1] = (u8) (tmp >> 8);
2306                         value[2] = (u8) (tmp >> 16);
2307                         value[3] = (u8) (tmp >> 24);
2308                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2309                                                         PWR_CTL_EN, value, 4);
2310                         msleep(PWR_SLEEP_INTERVAL);
2311                 }
2312                 if (!(tmp & PWR_ISO_EN)) {
2313                         tmp |= PWR_ISO_EN;
2314                         value[0] = (u8) tmp;
2315                         value[1] = (u8) (tmp >> 8);
2316                         value[2] = (u8) (tmp >> 16);
2317                         value[3] = (u8) (tmp >> 24);
2318                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2319                                                         PWR_CTL_EN, value, 4);
2320                         msleep(PWR_SLEEP_INTERVAL);
2321                 }
2322
2323                 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2324                         tmp |= POLARIS_AVMODE_ANALOGT_TV;
2325                         value[0] = (u8) tmp;
2326                         value[1] = (u8) (tmp >> 8);
2327                         value[2] = (u8) (tmp >> 16);
2328                         value[3] = (u8) (tmp >> 24);
2329                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2330                                                         PWR_CTL_EN, value, 4);
2331                         msleep(PWR_SLEEP_INTERVAL);
2332                 }
2333
2334                 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2335                     (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2336                     (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2337                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2338                         /* tuner path to channel 1 from port 3 */
2339                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2340
2341                         /* reset the Tuner */
2342                         cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2343
2344                         if (dev->cx231xx_reset_analog_tuner)
2345                                 dev->cx231xx_reset_analog_tuner(dev);
2346                 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2347                     (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2348                     (dev->model == CX231XX_BOARD_CNXT_RDU_253S)) {
2349                         /* tuner path to channel 1 from port 3 */
2350                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2351                         if (dev->cx231xx_reset_analog_tuner)
2352                                 dev->cx231xx_reset_analog_tuner(dev);
2353                 } else if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) {
2354                         /* tuner path to channel 1 from port 1 ?? */
2355                         cx231xx_enable_i2c_for_tuner(dev, I2C_1);
2356
2357                         if (dev->cx231xx_reset_analog_tuner)
2358                                 dev->cx231xx_reset_analog_tuner(dev);
2359                 }
2360
2361                 break;
2362
2363         case POLARIS_AVMODE_DIGITAL:
2364                 if (!(tmp & PWR_TUNER_EN)) {
2365                         tmp |= (PWR_TUNER_EN);
2366                         value[0] = (u8) tmp;
2367                         value[1] = (u8) (tmp >> 8);
2368                         value[2] = (u8) (tmp >> 16);
2369                         value[3] = (u8) (tmp >> 24);
2370                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2371                                                         PWR_CTL_EN, value, 4);
2372                         msleep(PWR_SLEEP_INTERVAL);
2373                 }
2374                 if (!(tmp & PWR_AV_EN)) {
2375                         tmp |= PWR_AV_EN;
2376                         value[0] = (u8) tmp;
2377                         value[1] = (u8) (tmp >> 8);
2378                         value[2] = (u8) (tmp >> 16);
2379                         value[3] = (u8) (tmp >> 24);
2380                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2381                                                         PWR_CTL_EN, value, 4);
2382                         msleep(PWR_SLEEP_INTERVAL);
2383                 }
2384                 if (!(tmp & PWR_ISO_EN)) {
2385                         tmp |= PWR_ISO_EN;
2386                         value[0] = (u8) tmp;
2387                         value[1] = (u8) (tmp >> 8);
2388                         value[2] = (u8) (tmp >> 16);
2389                         value[3] = (u8) (tmp >> 24);
2390                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2391                                                         PWR_CTL_EN, value, 4);
2392                         msleep(PWR_SLEEP_INTERVAL);
2393                 }
2394
2395                 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
2396                 value[0] = (u8) tmp;
2397                 value[1] = (u8) (tmp >> 8);
2398                 value[2] = (u8) (tmp >> 16);
2399                 value[3] = (u8) (tmp >> 24);
2400                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2401                                                 PWR_CTL_EN, value, 4);
2402                 msleep(PWR_SLEEP_INTERVAL);
2403
2404                 if (!(tmp & PWR_DEMOD_EN)) {
2405                         tmp |= PWR_DEMOD_EN;
2406                         value[0] = (u8) tmp;
2407                         value[1] = (u8) (tmp >> 8);
2408                         value[2] = (u8) (tmp >> 16);
2409                         value[3] = (u8) (tmp >> 24);
2410                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2411                                                         PWR_CTL_EN, value, 4);
2412                         msleep(PWR_SLEEP_INTERVAL);
2413                 }
2414
2415                 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2416                     (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2417                     (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2418                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2419                         /* tuner path to channel 1 from port 3 */
2420                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2421
2422                         /* reset the Tuner */
2423                         cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2424
2425                         if (dev->cx231xx_reset_analog_tuner)
2426                                 dev->cx231xx_reset_analog_tuner(dev);
2427                 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2428                     (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2429                     (dev->model == CX231XX_BOARD_CNXT_RDU_253S)) {
2430                         /* tuner path to channel 1 from port 3 */
2431                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2432                         if (dev->cx231xx_reset_analog_tuner)
2433                                 dev->cx231xx_reset_analog_tuner(dev);
2434                 } else if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) {
2435                         /* tuner path to channel 1 from port 1 ?? */
2436                         cx231xx_enable_i2c_for_tuner(dev, I2C_1);
2437
2438                         if (dev->cx231xx_reset_analog_tuner)
2439                                 dev->cx231xx_reset_analog_tuner(dev);
2440                 }
2441
2442                 break;
2443
2444         default:
2445                 break;
2446         }
2447
2448         msleep(PWR_SLEEP_INTERVAL);
2449
2450         /* For power saving, only enable Pwr_resetout_n
2451            when digital TV is selected. */
2452         if (mode == POLARIS_AVMODE_DIGITAL) {
2453                 tmp |= PWR_RESETOUT_EN;
2454                 value[0] = (u8) tmp;
2455                 value[1] = (u8) (tmp >> 8);
2456                 value[2] = (u8) (tmp >> 16);
2457                 value[3] = (u8) (tmp >> 24);
2458                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2459                                                 PWR_CTL_EN, value, 4);
2460                 msleep(PWR_SLEEP_INTERVAL);
2461         }
2462
2463         /* update power control for afe */
2464         status = cx231xx_afe_update_power_control(dev, mode);
2465
2466         /* update power control for i2s_blk */
2467         status = cx231xx_i2s_blk_update_power_control(dev, mode);
2468
2469         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2470                                        4);
2471
2472         return status;
2473 }
2474
2475 int cx231xx_power_suspend(struct cx231xx *dev)
2476 {
2477         u8 value[4] = { 0, 0, 0, 0 };
2478         u32 tmp = 0;
2479         int status = 0;
2480
2481         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2482                                        value, 4);
2483         if (status > 0)
2484                 return status;
2485
2486         tmp = *((u32 *) value);
2487         tmp &= (~PWR_MODE_MASK);
2488
2489         value[0] = (u8) tmp;
2490         value[1] = (u8) (tmp >> 8);
2491         value[2] = (u8) (tmp >> 16);
2492         value[3] = (u8) (tmp >> 24);
2493         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2494                                         value, 4);
2495
2496         return status;
2497 }
2498
2499 /******************************************************************************
2500  *                  S T R E A M    C O N T R O L   functions                  *
2501  ******************************************************************************/
2502 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2503 {
2504         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2505         u32 tmp = 0;
2506         int status = 0;
2507
2508         cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2509         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2510                                        value, 4);
2511         if (status < 0)
2512                 return status;
2513
2514         tmp = *((u32 *) value);
2515         tmp |= ep_mask;
2516         value[0] = (u8) tmp;
2517         value[1] = (u8) (tmp >> 8);
2518         value[2] = (u8) (tmp >> 16);
2519         value[3] = (u8) (tmp >> 24);
2520
2521         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2522                                         value, 4);
2523
2524         return status;
2525 }
2526
2527 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2528 {
2529         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2530         u32 tmp = 0;
2531         int status = 0;
2532
2533         cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2534         status =
2535             cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2536         if (status < 0)
2537                 return status;
2538
2539         tmp = *((u32 *) value);
2540         tmp &= (~ep_mask);
2541         value[0] = (u8) tmp;
2542         value[1] = (u8) (tmp >> 8);
2543         value[2] = (u8) (tmp >> 16);
2544         value[3] = (u8) (tmp >> 24);
2545
2546         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2547                                         value, 4);
2548
2549         return status;
2550 }
2551
2552 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2553 {
2554         int status = 0;
2555         u32 value = 0;
2556         u8 val[4] = { 0, 0, 0, 0 };
2557
2558         if (dev->udev->speed == USB_SPEED_HIGH) {
2559                 switch (media_type) {
2560                 case 81: /* audio */
2561                         cx231xx_info("%s: Audio enter HANC\n", __func__);
2562                         status =
2563                             cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2564                         break;
2565
2566                 case 2: /* vbi */
2567                         cx231xx_info("%s: set vanc registers\n", __func__);
2568                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2569                         break;
2570
2571                 case 3: /* sliced cc */
2572                         cx231xx_info("%s: set hanc registers\n", __func__);
2573                         status =
2574                             cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2575                         break;
2576
2577                 case 0: /* video */
2578                         cx231xx_info("%s: set video registers\n", __func__);
2579                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2580                         break;
2581
2582                 case 4: /* ts1 */
2583                         cx231xx_info("%s: set ts1 registers", __func__);
2584
2585                 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
2586                         cx231xx_info(" MPEG\n");
2587                         value &= 0xFFFFFFFC;
2588                         value |= 0x3;
2589
2590                         status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2591
2592                         val[0] = 0x04;
2593                         val[1] = 0xA3;
2594                         val[2] = 0x3B;
2595                         val[3] = 0x00;
2596                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2597                                  TS1_CFG_REG, val, 4);
2598
2599                         val[0] = 0x00;
2600                         val[1] = 0x08;
2601                         val[2] = 0x00;
2602                         val[3] = 0x08;
2603                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2604                                  TS1_LENGTH_REG, val, 4);
2605
2606                 } else {
2607                         cx231xx_info(" BDA\n");
2608                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2609                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2610                 }
2611                         break;
2612
2613                 case 6: /* ts1 parallel mode */
2614                         cx231xx_info("%s: set ts1 parrallel mode registers\n",
2615                                      __func__);
2616                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2617                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2618                         break;
2619                 }
2620         } else {
2621                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2622         }
2623
2624         return status;
2625 }
2626
2627 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2628 {
2629         int rc = -1;
2630         u32 ep_mask = -1;
2631         struct pcb_config *pcb_config;
2632
2633         /* get EP for media type */
2634         pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2635
2636         if (pcb_config->config_num == 1) {
2637                 switch (media_type) {
2638                 case 0: /* Video */
2639                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2640                         break;
2641                 case 1: /* Audio */
2642                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2643                         break;
2644                 case 2: /* Vbi */
2645                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2646                         break;
2647                 case 3: /* Sliced_cc */
2648                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2649                         break;
2650                 case 4: /* ts1 */
2651                 case 6: /* ts1 parallel mode */
2652                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2653                         break;
2654                 case 5: /* ts2 */
2655                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2656                         break;
2657                 }
2658
2659         } else if (pcb_config->config_num > 1) {
2660                 switch (media_type) {
2661                 case 0: /* Video */
2662                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2663                         break;
2664                 case 1: /* Audio */
2665                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2666                         break;
2667                 case 2: /* Vbi */
2668                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2669                         break;
2670                 case 3: /* Sliced_cc */
2671                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2672                         break;
2673                 case 4: /* ts1 */
2674                 case 6: /* ts1 parallel mode */
2675                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2676                         break;
2677                 case 5: /* ts2 */
2678                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2679                         break;
2680                 }
2681
2682         }
2683
2684         if (start) {
2685                 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2686
2687                 if (rc < 0)
2688                         return rc;
2689
2690                 /* enable video capture */
2691                 if (ep_mask > 0)
2692                         rc = cx231xx_start_stream(dev, ep_mask);
2693         } else {
2694                 /* disable video capture */
2695                 if (ep_mask > 0)
2696                         rc = cx231xx_stop_stream(dev, ep_mask);
2697         }
2698
2699         if (dev->mode == CX231XX_ANALOG_MODE)
2700                 ;/* do any in Analog mode */
2701         else
2702                 ;/* do any in digital mode */
2703
2704         return rc;
2705 }
2706 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2707
2708 /*****************************************************************************
2709 *                   G P I O   B I T control functions                        *
2710 ******************************************************************************/
2711 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2712 {
2713         int status = 0;
2714
2715         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2716
2717         return status;
2718 }
2719
2720 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2721 {
2722         int status = 0;
2723
2724         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2725
2726         return status;
2727 }
2728
2729 /*
2730 * cx231xx_set_gpio_direction
2731 *      Sets the direction of the GPIO pin to input or output
2732 *
2733 * Parameters :
2734 *      pin_number : The GPIO Pin number to program the direction for
2735 *                   from 0 to 31
2736 *      pin_value : The Direction of the GPIO Pin under reference.
2737 *                      0 = Input direction
2738 *                      1 = Output direction
2739 */
2740 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2741                                int pin_number, int pin_value)
2742 {
2743         int status = 0;
2744         u32 value = 0;
2745
2746         /* Check for valid pin_number - if 32 , bail out */
2747         if (pin_number >= 32)
2748                 return -EINVAL;
2749
2750         /* input */
2751         if (pin_value == 0)
2752                 value = dev->gpio_dir & (~(1 << pin_number));   /* clear */
2753         else
2754                 value = dev->gpio_dir | (1 << pin_number);
2755
2756         status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2757
2758         /* cache the value for future */
2759         dev->gpio_dir = value;
2760
2761         return status;
2762 }
2763
2764 /*
2765 * cx231xx_set_gpio_value
2766 *      Sets the value of the GPIO pin to Logic high or low. The Pin under
2767 *      reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2768 *
2769 * Parameters :
2770 *      pin_number : The GPIO Pin number to program the direction for
2771 *      pin_value : The value of the GPIO Pin under reference.
2772 *                      0 = set it to 0
2773 *                      1 = set it to 1
2774 */
2775 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2776 {
2777         int status = 0;
2778         u32 value = 0;
2779
2780         /* Check for valid pin_number - if 0xFF , bail out */
2781         if (pin_number >= 32)
2782                 return -EINVAL;
2783
2784         /* first do a sanity check - if the Pin is not output, make it output */
2785         if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2786                 /* It was in input mode */
2787                 value = dev->gpio_dir | (1 << pin_number);
2788                 dev->gpio_dir = value;
2789                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2790                                               (u8 *) &dev->gpio_val);
2791                 value = 0;
2792         }
2793
2794         if (pin_value == 0)
2795                 value = dev->gpio_val & (~(1 << pin_number));
2796         else
2797                 value = dev->gpio_val | (1 << pin_number);
2798
2799         /* store the value */
2800         dev->gpio_val = value;
2801
2802         /* toggle bit0 of GP_IO */
2803         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2804
2805         return status;
2806 }
2807
2808 /*****************************************************************************
2809 *                      G P I O I2C related functions                         *
2810 ******************************************************************************/
2811 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2812 {
2813         int status = 0;
2814
2815         /* set SCL to output 1 ; set SDA to output 1 */
2816         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2817         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2818         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2819         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2820
2821         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2822         if (status < 0)
2823                 return -EINVAL;
2824
2825         /* set SCL to output 1; set SDA to output 0 */
2826         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2827         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2828
2829         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2830         if (status < 0)
2831                 return -EINVAL;
2832
2833         /* set SCL to output 0; set SDA to output 0      */
2834         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2835         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2836
2837         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2838         if (status < 0)
2839                 return -EINVAL;
2840
2841         return status;
2842 }
2843
2844 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2845 {
2846         int status = 0;
2847
2848         /* set SCL to output 0; set SDA to output 0      */
2849         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2850         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2851
2852         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2853         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2854
2855         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2856         if (status < 0)
2857                 return -EINVAL;
2858
2859         /* set SCL to output 1; set SDA to output 0      */
2860         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2861         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2862
2863         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2864         if (status < 0)
2865                 return -EINVAL;
2866
2867         /* set SCL to input ,release SCL cable control
2868            set SDA to input ,release SDA cable control */
2869         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2870         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2871
2872         status =
2873             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2874         if (status < 0)
2875                 return -EINVAL;
2876
2877         return status;
2878 }
2879
2880 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2881 {
2882         int status = 0;
2883         u8 i;
2884
2885         /* set SCL to output ; set SDA to output */
2886         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2887         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2888
2889         for (i = 0; i < 8; i++) {
2890                 if (((data << i) & 0x80) == 0) {
2891                         /* set SCL to output 0; set SDA to output 0     */
2892                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2893                         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2894                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2895                                                       (u8 *)&dev->gpio_val);
2896
2897                         /* set SCL to output 1; set SDA to output 0     */
2898                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2899                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2900                                                       (u8 *)&dev->gpio_val);
2901
2902                         /* set SCL to output 0; set SDA to output 0     */
2903                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2904                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2905                                                       (u8 *)&dev->gpio_val);
2906                 } else {
2907                         /* set SCL to output 0; set SDA to output 1     */
2908                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2909                         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2910                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2911                                                       (u8 *)&dev->gpio_val);
2912
2913                         /* set SCL to output 1; set SDA to output 1     */
2914                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2915                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2916                                                       (u8 *)&dev->gpio_val);
2917
2918                         /* set SCL to output 0; set SDA to output 1     */
2919                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2920                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2921                                                       (u8 *)&dev->gpio_val);
2922                 }
2923         }
2924         return status;
2925 }
2926
2927 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2928 {
2929         u8 value = 0;
2930         int status = 0;
2931         u32 gpio_logic_value = 0;
2932         u8 i;
2933
2934         /* read byte */
2935         for (i = 0; i < 8; i++) {       /* send write I2c addr */
2936
2937                 /* set SCL to output 0; set SDA to input */
2938                 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2939                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2940                                               (u8 *)&dev->gpio_val);
2941
2942                 /* set SCL to output 1; set SDA to input */
2943                 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2944                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2945                                               (u8 *)&dev->gpio_val);
2946
2947                 /* get SDA data bit */
2948                 gpio_logic_value = dev->gpio_val;
2949                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2950                                               (u8 *)&dev->gpio_val);
2951                 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2952                         value |= (1 << (8 - i - 1));
2953
2954                 dev->gpio_val = gpio_logic_value;
2955         }
2956
2957         /* set SCL to output 0,finish the read latest SCL signal.
2958            !!!set SDA to input, never to modify SDA direction at
2959            the same times */
2960         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2961         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2962
2963         /* store the value */
2964         *buf = value & 0xff;
2965
2966         return status;
2967 }
2968
2969 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2970 {
2971         int status = 0;
2972         u32 gpio_logic_value = 0;
2973         int nCnt = 10;
2974         int nInit = nCnt;
2975
2976         /* clock stretch; set SCL to input; set SDA to input;
2977            get SCL value till SCL = 1 */
2978         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2979         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2980
2981         gpio_logic_value = dev->gpio_val;
2982         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2983
2984         do {
2985                 msleep(2);
2986                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2987                                               (u8 *)&dev->gpio_val);
2988                 nCnt--;
2989         } while (((dev->gpio_val &
2990                           (1 << dev->board.tuner_scl_gpio)) == 0) &&
2991                          (nCnt > 0));
2992
2993         if (nCnt == 0)
2994                 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2995                              nInit * 10);
2996
2997         /*
2998          * readAck
2999          * through clock stretch, slave has given a SCL signal,
3000          * so the SDA data can be directly read.
3001          */
3002         status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3003
3004         if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
3005                 dev->gpio_val = gpio_logic_value;
3006                 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3007                 status = 0;
3008         } else {
3009                 dev->gpio_val = gpio_logic_value;
3010                 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
3011         }
3012
3013         /* read SDA end, set the SCL to output 0, after this operation,
3014            SDA direction can be changed. */
3015         dev->gpio_val = gpio_logic_value;
3016         dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
3017         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3018         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3019
3020         return status;
3021 }
3022
3023 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
3024 {
3025         int status = 0;
3026
3027         /* set SDA to ouput */
3028         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
3029         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3030
3031         /* set SCL = 0 (output); set SDA = 0 (output) */
3032         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3033         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3034         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3035
3036         /* set SCL = 1 (output); set SDA = 0 (output) */
3037         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3038         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3039
3040         /* set SCL = 0 (output); set SDA = 0 (output) */
3041         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3042         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3043
3044         /* set SDA to input,and then the slave will read data from SDA. */
3045         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3046         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3047
3048         return status;
3049 }
3050
3051 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
3052 {
3053         int status = 0;
3054
3055         /* set scl to output ; set sda to input */
3056         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
3057         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3058         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3059
3060         /* set scl to output 0; set sda to input */
3061         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3062         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3063
3064         /* set scl to output 1; set sda to input */
3065         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3066         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3067
3068         return status;
3069 }
3070
3071 /*****************************************************************************
3072 *                      G P I O I2C related functions                         *
3073 ******************************************************************************/
3074 /* cx231xx_gpio_i2c_read
3075  * Function to read data from gpio based I2C interface
3076  */
3077 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3078 {
3079         int status = 0;
3080         int i = 0;
3081
3082         /* get the lock */
3083         mutex_lock(&dev->gpio_i2c_lock);
3084
3085         /* start */
3086         status = cx231xx_gpio_i2c_start(dev);
3087
3088         /* write dev_addr */
3089         status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3090
3091         /* readAck */
3092         status = cx231xx_gpio_i2c_read_ack(dev);
3093
3094         /* read data */
3095         for (i = 0; i < len; i++) {
3096                 /* read data */
3097                 buf[i] = 0;
3098                 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3099
3100                 if ((i + 1) != len) {
3101                         /* only do write ack if we more length */
3102                         status = cx231xx_gpio_i2c_write_ack(dev);
3103                 }
3104         }
3105
3106         /* write NAK - inform reads are complete */
3107         status = cx231xx_gpio_i2c_write_nak(dev);
3108
3109         /* write end */
3110         status = cx231xx_gpio_i2c_end(dev);
3111
3112         /* release the lock */
3113         mutex_unlock(&dev->gpio_i2c_lock);
3114
3115         return status;
3116 }
3117
3118 /* cx231xx_gpio_i2c_write
3119  * Function to write data to gpio based I2C interface
3120  */
3121 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3122 {
3123         int status = 0;
3124         int i = 0;
3125
3126         /* get the lock */
3127         mutex_lock(&dev->gpio_i2c_lock);
3128
3129         /* start */
3130         status = cx231xx_gpio_i2c_start(dev);
3131
3132         /* write dev_addr */
3133         status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3134
3135         /* read Ack */
3136         status = cx231xx_gpio_i2c_read_ack(dev);
3137
3138         for (i = 0; i < len; i++) {
3139                 /* Write data */
3140                 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3141
3142                 /* read Ack */
3143                 status = cx231xx_gpio_i2c_read_ack(dev);
3144         }
3145
3146         /* write End */
3147         status = cx231xx_gpio_i2c_end(dev);
3148
3149         /* release the lock */
3150         mutex_unlock(&dev->gpio_i2c_lock);
3151
3152         return 0;
3153 }