2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
7 This program contains the specific code to control the avdecoder chip and
8 other related usb control functions for cx231xx based chipset.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/bitmap.h>
30 #include <linux/usb.h>
31 #include <linux/i2c.h>
33 #include <linux/mutex.h>
34 #include <media/tuner.h>
36 #include <media/v4l2-common.h>
37 #include <media/v4l2-ioctl.h>
38 #include <media/v4l2-chip-ident.h>
41 #include "cx231xx-dif.h"
43 #define TUNER_MODE_FM_RADIO 0
44 /******************************************************************************
45 -: BLOCK ARRANGEMENT :-
46 I2S block ----------------------|
49 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
50 [video & audio] | [Audio]
55 *******************************************************************************/
56 /******************************************************************************
59 ******************************************************************************/
60 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
62 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
66 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
71 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
76 void initGPIO(struct cx231xx *dev)
78 u32 _gpio_direction = 0;
82 _gpio_direction = _gpio_direction & 0xFC0003FF;
83 _gpio_direction = _gpio_direction | 0x03FDFC00;
84 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
86 verve_read_byte(dev, 0x07, &val);
87 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
88 verve_write_byte(dev, 0x07, 0xF4);
89 verve_read_byte(dev, 0x07, &val);
90 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
92 cx231xx_capture_start(dev, 1, 2);
94 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
95 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
98 void uninitGPIO(struct cx231xx *dev)
100 u8 value[4] = { 0, 0, 0, 0 };
102 cx231xx_capture_start(dev, 0, 2);
103 verve_write_byte(dev, 0x07, 0x14);
104 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
108 /******************************************************************************
109 * A F E - B L O C K C O N T R O L functions *
110 * [ANALOG FRONT END] *
111 ******************************************************************************/
112 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
114 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
118 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
123 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
129 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
133 u8 afe_power_status = 0;
136 /* super block initialize */
137 temp = (u8) (ref_count & 0xff);
138 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
142 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
146 temp = (u8) ((ref_count & 0x300) >> 8);
148 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
152 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
157 while (afe_power_status != 0x18) {
158 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
161 ": Init Super Block failed in send cmd\n");
165 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
166 afe_power_status &= 0xff;
169 ": Init Super Block failed in receive cmd\n");
175 ": Init Super Block force break in loop !!!!\n");
184 /* start tuning filter */
185 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
192 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
197 int cx231xx_afe_init_channels(struct cx231xx *dev)
201 /* power up all 3 channels, clear pd_buffer */
202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
204 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
206 /* Enable quantizer calibration */
207 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
209 /* channel initialize, force modulator (fb) reset */
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
214 /* start quantilizer calibration */
215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
217 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
220 /* exit modulator (fb) reset */
221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
223 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
225 /* enable the pre_clamp in each channel for single-ended input */
226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
228 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
230 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
231 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
232 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
233 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
234 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
235 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
236 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
238 /* dynamic element matching off */
239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
241 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
246 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
251 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
252 c_value &= (~(0x50));
253 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
259 The Analog Front End in Cx231xx has 3 channels. These
260 channels are used to share between different inputs
261 like tuner, s-video and composite inputs.
263 channel 1 ----- pin 1 to pin4(in reg is 1-4)
264 channel 2 ----- pin 5 to pin8(in reg is 5-8)
265 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
267 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
269 u8 ch1_setting = (u8) input_mux;
270 u8 ch2_setting = (u8) (input_mux >> 8);
271 u8 ch3_setting = (u8) (input_mux >> 16);
275 if (ch1_setting != 0) {
276 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
277 value &= (!INPUT_SEL_MASK);
278 value |= (ch1_setting - 1) << 4;
280 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
283 if (ch2_setting != 0) {
284 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
285 value &= (!INPUT_SEL_MASK);
286 value |= (ch2_setting - 1) << 4;
288 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
291 /* For ch3_setting, the value to put in the register is
292 7 less than the input number */
293 if (ch3_setting != 0) {
294 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
295 value &= (!INPUT_SEL_MASK);
296 value |= (ch3_setting - 1) << 4;
298 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
304 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
309 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
310 * Currently, only baseband works.
314 case AFE_MODE_LOW_IF:
315 cx231xx_Setup_AFE_for_LowIF(dev);
317 case AFE_MODE_BASEBAND:
318 status = cx231xx_afe_setup_AFE_for_baseband(dev);
320 case AFE_MODE_EU_HI_IF:
321 /* SetupAFEforEuHiIF(); */
323 case AFE_MODE_US_HI_IF:
324 /* SetupAFEforUsHiIF(); */
326 case AFE_MODE_JAPAN_HI_IF:
327 /* SetupAFEforJapanHiIF(); */
331 if ((mode != dev->afe_mode) &&
332 (dev->video_input == CX231XX_VMUX_TELEVISION))
333 status = cx231xx_afe_adjust_ref_count(dev,
334 CX231XX_VMUX_TELEVISION);
336 dev->afe_mode = mode;
341 int cx231xx_afe_update_power_control(struct cx231xx *dev,
344 u8 afe_power_status = 0;
347 switch (dev->model) {
348 case CX231XX_BOARD_CNXT_CARRAERA:
349 case CX231XX_BOARD_CNXT_RDE_250:
350 case CX231XX_BOARD_CNXT_SHELBY:
351 case CX231XX_BOARD_CNXT_RDU_250:
352 case CX231XX_BOARD_CNXT_RDE_253S:
353 case CX231XX_BOARD_CNXT_RDU_253S:
354 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
355 case CX231XX_BOARD_HAUPPAUGE_EXETER:
356 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
357 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
358 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
359 FLD_PWRDN_ENABLE_PLL)) {
360 status = afe_write_byte(dev, SUP_BLK_PWRDN,
361 FLD_PWRDN_TUNING_BIAS |
362 FLD_PWRDN_ENABLE_PLL);
363 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
369 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
371 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
373 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
375 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
376 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
378 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
380 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
383 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
385 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
388 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
390 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
391 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
392 FLD_PWRDN_ENABLE_PLL)) {
393 status = afe_write_byte(dev, SUP_BLK_PWRDN,
394 FLD_PWRDN_TUNING_BIAS |
395 FLD_PWRDN_ENABLE_PLL);
396 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
402 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
404 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
406 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
409 cx231xx_info("Invalid AV mode input\n");
414 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
415 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
416 FLD_PWRDN_ENABLE_PLL)) {
417 status = afe_write_byte(dev, SUP_BLK_PWRDN,
418 FLD_PWRDN_TUNING_BIAS |
419 FLD_PWRDN_ENABLE_PLL);
420 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
426 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
428 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
430 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
432 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
433 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
435 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
437 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
440 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
442 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
445 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
447 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
448 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
449 FLD_PWRDN_ENABLE_PLL)) {
450 status = afe_write_byte(dev, SUP_BLK_PWRDN,
451 FLD_PWRDN_TUNING_BIAS |
452 FLD_PWRDN_ENABLE_PLL);
453 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
459 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
461 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
463 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
466 cx231xx_info("Invalid AV mode input\n");
474 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
480 dev->video_input = video_input;
482 if (video_input == CX231XX_VMUX_TELEVISION) {
483 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
484 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
487 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
488 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
492 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
494 switch (input_mode) {
496 dev->afe_ref_count = 0x23C;
499 dev->afe_ref_count = 0x24C;
502 dev->afe_ref_count = 0x258;
505 dev->afe_ref_count = 0x260;
511 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
516 /******************************************************************************
517 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
518 ******************************************************************************/
519 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
521 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
525 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
530 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
536 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
538 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
542 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
544 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
547 int cx231xx_check_fw(struct cx231xx *dev)
551 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
559 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
563 switch (INPUT(input)->type) {
564 case CX231XX_VMUX_COMPOSITE1:
565 case CX231XX_VMUX_SVIDEO:
566 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
567 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
569 status = cx231xx_set_power_mode(dev,
570 POLARIS_AVMODE_ENXTERNAL_AV);
572 cx231xx_errdev("%s: set_power_mode : Failed to"
573 " set Power - errCode [%d]!\n",
578 status = cx231xx_set_decoder_video_input(dev,
582 case CX231XX_VMUX_TELEVISION:
583 case CX231XX_VMUX_CABLE:
584 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
585 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
587 status = cx231xx_set_power_mode(dev,
588 POLARIS_AVMODE_ANALOGT_TV);
590 cx231xx_errdev("%s: set_power_mode:Failed"
591 " to set Power - errCode [%d]!\n",
596 if (dev->tuner_type == TUNER_NXP_TDA18271)
597 status = cx231xx_set_decoder_video_input(dev,
598 CX231XX_VMUX_TELEVISION,
601 status = cx231xx_set_decoder_video_input(dev,
602 CX231XX_VMUX_COMPOSITE1,
607 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
608 __func__, INPUT(input)->type);
612 /* save the selection */
613 dev->video_input = input;
618 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
619 u8 pin_type, u8 input)
624 if (pin_type != dev->video_input) {
625 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
627 cx231xx_errdev("%s: adjust_ref_count :Failed to set"
628 "AFE input mux - errCode [%d]!\n",
634 /* call afe block to set video inputs */
635 status = cx231xx_afe_set_input_mux(dev, input);
637 cx231xx_errdev("%s: set_input_mux :Failed to set"
638 " AFE input mux - errCode [%d]!\n",
644 case CX231XX_VMUX_COMPOSITE1:
645 status = vid_blk_read_word(dev, AFE_CTRL, &value);
646 value |= (0 << 13) | (1 << 4);
649 /* set [24:23] [22:15] to 0 */
650 value &= (~(0x1ff8000));
651 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
653 status = vid_blk_write_word(dev, AFE_CTRL, value);
655 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
657 status = vid_blk_write_word(dev, OUT_CTRL1, value);
659 /* Set output mode */
660 status = cx231xx_read_modify_write_i2c_dword(dev,
664 dev->board.output_mode);
666 /* Tell DIF object to go to baseband mode */
667 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
669 cx231xx_errdev("%s: cx231xx_dif set to By pass"
670 " mode- errCode [%d]!\n",
675 /* Read the DFE_CTRL1 register */
676 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
678 /* enable the VBI_GATE_EN */
679 value |= FLD_VBI_GATE_EN;
681 /* Enable the auto-VGA enable */
682 value |= FLD_VGA_AUTO_EN;
685 status = vid_blk_write_word(dev, DFE_CTRL1, value);
687 /* Disable auto config of registers */
688 status = cx231xx_read_modify_write_i2c_dword(dev,
690 MODE_CTRL, FLD_ACFG_DIS,
691 cx231xx_set_field(FLD_ACFG_DIS, 1));
693 /* Set CVBS input mode */
694 status = cx231xx_read_modify_write_i2c_dword(dev,
696 MODE_CTRL, FLD_INPUT_MODE,
697 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
699 case CX231XX_VMUX_SVIDEO:
700 /* Disable the use of DIF */
702 status = vid_blk_read_word(dev, AFE_CTRL, &value);
704 /* set [24:23] [22:15] to 0 */
705 value &= (~(0x1ff8000));
706 /* set FUNC_MODE[24:23] = 2
707 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
709 status = vid_blk_write_word(dev, AFE_CTRL, value);
711 /* Tell DIF object to go to baseband mode */
712 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
714 cx231xx_errdev("%s: cx231xx_dif set to By pass"
715 " mode- errCode [%d]!\n",
720 /* Read the DFE_CTRL1 register */
721 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
723 /* enable the VBI_GATE_EN */
724 value |= FLD_VBI_GATE_EN;
726 /* Enable the auto-VGA enable */
727 value |= FLD_VGA_AUTO_EN;
730 status = vid_blk_write_word(dev, DFE_CTRL1, value);
732 /* Disable auto config of registers */
733 status = cx231xx_read_modify_write_i2c_dword(dev,
735 MODE_CTRL, FLD_ACFG_DIS,
736 cx231xx_set_field(FLD_ACFG_DIS, 1));
738 /* Set YC input mode */
739 status = cx231xx_read_modify_write_i2c_dword(dev,
743 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
746 status = vid_blk_read_word(dev, AFE_CTRL, &value);
747 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
749 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
750 This sets them to use video
751 rather than audio. Only one of the two will be in use. */
752 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
754 status = vid_blk_write_word(dev, AFE_CTRL, value);
756 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
758 case CX231XX_VMUX_TELEVISION:
759 case CX231XX_VMUX_CABLE:
761 switch (dev->model) {
762 case CX231XX_BOARD_CNXT_CARRAERA:
763 case CX231XX_BOARD_CNXT_RDE_250:
764 case CX231XX_BOARD_CNXT_SHELBY:
765 case CX231XX_BOARD_CNXT_RDU_250:
766 /* Disable the use of DIF */
768 status = vid_blk_read_word(dev, AFE_CTRL, &value);
769 value |= (0 << 13) | (1 << 4);
772 /* set [24:23] [22:15] to 0 */
773 value &= (~(0x1FF8000));
774 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
776 status = vid_blk_write_word(dev, AFE_CTRL, value);
778 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
780 status = vid_blk_write_word(dev, OUT_CTRL1, value);
782 /* Set output mode */
783 status = cx231xx_read_modify_write_i2c_dword(dev,
785 OUT_CTRL1, FLD_OUT_MODE,
786 dev->board.output_mode);
788 /* Tell DIF object to go to baseband mode */
789 status = cx231xx_dif_set_standard(dev,
792 cx231xx_errdev("%s: cx231xx_dif set to By pass"
793 " mode- errCode [%d]!\n",
798 /* Read the DFE_CTRL1 register */
799 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
801 /* enable the VBI_GATE_EN */
802 value |= FLD_VBI_GATE_EN;
804 /* Enable the auto-VGA enable */
805 value |= FLD_VGA_AUTO_EN;
808 status = vid_blk_write_word(dev, DFE_CTRL1, value);
810 /* Disable auto config of registers */
811 status = cx231xx_read_modify_write_i2c_dword(dev,
813 MODE_CTRL, FLD_ACFG_DIS,
814 cx231xx_set_field(FLD_ACFG_DIS, 1));
816 /* Set CVBS input mode */
817 status = cx231xx_read_modify_write_i2c_dword(dev,
819 MODE_CTRL, FLD_INPUT_MODE,
820 cx231xx_set_field(FLD_INPUT_MODE,
824 /* Enable the DIF for the tuner */
826 /* Reinitialize the DIF */
827 status = cx231xx_dif_set_standard(dev, dev->norm);
829 cx231xx_errdev("%s: cx231xx_dif set to By pass"
830 " mode- errCode [%d]!\n",
835 /* Make sure bypass is cleared */
836 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
838 /* Clear the bypass bit */
839 value &= ~FLD_DIF_DIF_BYPASS;
841 /* Enable the use of the DIF block */
842 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
844 /* Read the DFE_CTRL1 register */
845 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
847 /* Disable the VBI_GATE_EN */
848 value &= ~FLD_VBI_GATE_EN;
850 /* Enable the auto-VGA enable, AGC, and
851 set the skip count to 2 */
852 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
855 status = vid_blk_write_word(dev, DFE_CTRL1, value);
857 /* Wait until AGC locks up */
860 /* Disable the auto-VGA enable AGC */
861 value &= ~(FLD_VGA_AUTO_EN);
864 status = vid_blk_write_word(dev, DFE_CTRL1, value);
866 /* Enable Polaris B0 AGC output */
867 status = vid_blk_read_word(dev, PIN_CTRL, &value);
868 value |= (FLD_OEF_AGC_RF) |
869 (FLD_OEF_AGC_IFVGA) |
871 status = vid_blk_write_word(dev, PIN_CTRL, value);
873 /* Set output mode */
874 status = cx231xx_read_modify_write_i2c_dword(dev,
876 OUT_CTRL1, FLD_OUT_MODE,
877 dev->board.output_mode);
879 /* Disable auto config of registers */
880 status = cx231xx_read_modify_write_i2c_dword(dev,
882 MODE_CTRL, FLD_ACFG_DIS,
883 cx231xx_set_field(FLD_ACFG_DIS, 1));
885 /* Set CVBS input mode */
886 status = cx231xx_read_modify_write_i2c_dword(dev,
888 MODE_CTRL, FLD_INPUT_MODE,
889 cx231xx_set_field(FLD_INPUT_MODE,
892 /* Set some bits in AFE_CTRL so that channel 2 or 3
893 * is ready to receive audio */
894 /* Clear clamp for channels 2 and 3 (bit 16-17) */
895 /* Clear droop comp (bit 19-20) */
896 /* Set VGA_SEL (for audio control) (bit 7-8) */
897 status = vid_blk_read_word(dev, AFE_CTRL, &value);
899 /*Set Func mode:01-DIF 10-baseband 11-YUV*/
900 value &= (~(FLD_FUNC_MODE));
903 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
905 status = vid_blk_write_word(dev, AFE_CTRL, value);
907 if (dev->tuner_type == TUNER_NXP_TDA18271) {
908 status = vid_blk_read_word(dev, PIN_CTRL,
910 status = vid_blk_write_word(dev, PIN_CTRL,
911 (value & 0xFFFFFFEF));
920 /* Set raw VBI mode */
921 status = cx231xx_read_modify_write_i2c_dword(dev,
923 OUT_CTRL1, FLD_VBIHACTRAW_EN,
924 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
926 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
929 status = vid_blk_write_word(dev, OUT_CTRL1, value);
935 void cx231xx_enable656(struct cx231xx *dev)
939 /*enable TS1 data[0:7] as output to export 656*/
941 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
943 /*enable TS1 clock as output to export 656*/
945 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
948 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
951 EXPORT_SYMBOL_GPL(cx231xx_enable656);
953 void cx231xx_disable656(struct cx231xx *dev)
959 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
961 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
964 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
966 EXPORT_SYMBOL_GPL(cx231xx_disable656);
969 * Handle any video-mode specific overrides that are different
970 * on a per video standards basis after touching the MODE_CTRL
971 * register which resets many values for autodetect
973 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
977 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
978 (unsigned int)dev->norm);
980 /* Change the DFE_CTRL3 bp_percent to fix flagging */
981 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
983 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
984 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
986 /* Move the close caption lines out of active video,
987 adjust the active video start point */
988 status = cx231xx_read_modify_write_i2c_dword(dev,
991 FLD_VBLANK_CNT, 0x18);
992 status = cx231xx_read_modify_write_i2c_dword(dev,
997 status = cx231xx_read_modify_write_i2c_dword(dev,
1003 status = cx231xx_read_modify_write_i2c_dword(dev,
1004 VID_BLK_I2C_ADDRESS,
1008 (FLD_HBLANK_CNT, 0x79));
1010 } else if (dev->norm & V4L2_STD_SECAM) {
1011 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1012 status = cx231xx_read_modify_write_i2c_dword(dev,
1013 VID_BLK_I2C_ADDRESS,
1015 FLD_VBLANK_CNT, 0x20);
1016 status = cx231xx_read_modify_write_i2c_dword(dev,
1017 VID_BLK_I2C_ADDRESS,
1023 status = cx231xx_read_modify_write_i2c_dword(dev,
1024 VID_BLK_I2C_ADDRESS,
1030 /* Adjust the active video horizontal start point */
1031 status = cx231xx_read_modify_write_i2c_dword(dev,
1032 VID_BLK_I2C_ADDRESS,
1036 (FLD_HBLANK_CNT, 0x85));
1038 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1039 status = cx231xx_read_modify_write_i2c_dword(dev,
1040 VID_BLK_I2C_ADDRESS,
1042 FLD_VBLANK_CNT, 0x20);
1043 status = cx231xx_read_modify_write_i2c_dword(dev,
1044 VID_BLK_I2C_ADDRESS,
1050 status = cx231xx_read_modify_write_i2c_dword(dev,
1051 VID_BLK_I2C_ADDRESS,
1057 /* Adjust the active video horizontal start point */
1058 status = cx231xx_read_modify_write_i2c_dword(dev,
1059 VID_BLK_I2C_ADDRESS,
1063 (FLD_HBLANK_CNT, 0x85));
1070 int cx231xx_unmute_audio(struct cx231xx *dev)
1072 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1074 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1076 int stopAudioFirmware(struct cx231xx *dev)
1078 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1081 int restartAudioFirmware(struct cx231xx *dev)
1083 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1086 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1089 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1091 switch (INPUT(input)->amux) {
1092 case CX231XX_AMUX_VIDEO:
1093 ainput = AUDIO_INPUT_TUNER_TV;
1095 case CX231XX_AMUX_LINE_IN:
1096 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1097 ainput = AUDIO_INPUT_LINE;
1103 status = cx231xx_set_audio_decoder_input(dev, ainput);
1108 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1109 enum AUDIO_INPUT audio_input)
1116 /* Put it in soft reset */
1117 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1119 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1121 switch (audio_input) {
1122 case AUDIO_INPUT_LINE:
1123 /* setup AUD_IO control from Merlin paralle output */
1124 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1125 AUD_CHAN_SRC_PARALLEL);
1126 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1128 /* setup input to Merlin, SRC2 connect to AC97
1129 bypass upsample-by-2, slave mode, sony mode, left justify
1130 adr 091c, dat 01000000 */
1131 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1133 status = vid_blk_write_word(dev, AC97_CTL,
1134 (dwval | FLD_AC97_UP2X_BYPASS));
1136 /* select the parallel1 and SRC3 */
1137 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1138 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1139 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1140 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1142 /* unmute all, AC97 in, independence mode
1143 adr 08d0, data 0x00063073 */
1144 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1145 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1147 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1148 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1149 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1150 (dwval | FLD_PATH1_AVC_THRESHOLD));
1152 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1153 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1154 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1155 (dwval | FLD_PATH1_SC_THRESHOLD));
1158 case AUDIO_INPUT_TUNER_TV:
1160 status = stopAudioFirmware(dev);
1161 /* Setup SRC sources and clocks */
1162 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1163 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1164 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1165 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
1166 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
1167 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
1168 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
1169 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
1170 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1171 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1172 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1173 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1174 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1175 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1177 /* Setup the AUD_IO control */
1178 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1179 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1180 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1181 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1182 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1183 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1185 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1187 /* setAudioStandard(_audio_standard); */
1188 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1190 status = restartAudioFirmware(dev);
1192 switch (dev->board.tuner_type) {
1194 /* SIF passthrough at 28.6363 MHz sample rate */
1195 status = cx231xx_read_modify_write_i2c_dword(dev,
1196 VID_BLK_I2C_ADDRESS,
1199 cx231xx_set_field(FLD_SIF_EN, 1));
1201 case TUNER_NXP_TDA18271:
1202 /* Normal mode: SIF passthrough at 14.32 MHz */
1203 status = cx231xx_read_modify_write_i2c_dword(dev,
1204 VID_BLK_I2C_ADDRESS,
1207 cx231xx_set_field(FLD_SIF_EN, 0));
1210 /* This is just a casual suggestion to people adding
1211 new boards in case they use a tuner type we don't
1212 currently know about */
1213 printk(KERN_INFO "Unknown tuner type configuring SIF");
1218 case AUDIO_INPUT_TUNER_FM:
1219 /* use SIF for FM radio
1221 setAudioStandard(_audio_standard);
1225 case AUDIO_INPUT_MUTE:
1226 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1230 /* Take it out of soft reset */
1231 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1233 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1238 /******************************************************************************
1239 * C H I P Specific C O N T R O L functions *
1240 ******************************************************************************/
1241 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1246 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1247 value |= (~dev->board.ctl_pin_status_mask);
1248 status = vid_blk_write_word(dev, PIN_CTRL, value);
1253 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1254 u8 analog_or_digital)
1258 /* first set the direction to output */
1259 status = cx231xx_set_gpio_direction(dev,
1261 agc_analog_digital_select_gpio, 1);
1263 /* 0 - demod ; 1 - Analog mode */
1264 status = cx231xx_set_gpio_value(dev,
1265 dev->board.agc_analog_digital_select_gpio,
1271 int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1273 u8 value[4] = { 0, 0, 0, 0 };
1276 cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1278 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1279 PWR_CTL_EN, value, 4);
1283 if (I2CIndex == I2C_1) {
1284 if (value[0] & I2C_DEMOD_EN) {
1285 value[0] &= ~I2C_DEMOD_EN;
1286 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1287 PWR_CTL_EN, value, 4);
1290 if (!(value[0] & I2C_DEMOD_EN)) {
1291 value[0] |= I2C_DEMOD_EN;
1292 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1293 PWR_CTL_EN, value, 4);
1300 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_for_tuner);
1301 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1307 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1308 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1309 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1311 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1312 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1313 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1317 void cx231xx_dump_HH_reg(struct cx231xx *dev)
1324 status = vid_blk_write_word(dev, 0x104, value);
1326 for (i = 0x100; i < 0x140; i++) {
1327 status = vid_blk_read_word(dev, i, &value);
1328 cx231xx_info("reg0x%x=0x%x\n", i, value);
1332 for (i = 0x300; i < 0x400; i++) {
1333 status = vid_blk_read_word(dev, i, &value);
1334 cx231xx_info("reg0x%x=0x%x\n", i, value);
1338 for (i = 0x400; i < 0x440; i++) {
1339 status = vid_blk_read_word(dev, i, &value);
1340 cx231xx_info("reg0x%x=0x%x\n", i, value);
1344 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1345 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1346 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1347 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1348 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1351 void cx231xx_dump_SC_reg(struct cx231xx *dev)
1353 u8 value[4] = { 0, 0, 0, 0 };
1355 cx231xx_info("cx231xx_dump_SC_reg %s!\n", __TIME__);
1357 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1359 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1360 value[1], value[2], value[3]);
1361 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1363 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1364 value[1], value[2], value[3]);
1365 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1367 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1368 value[1], value[2], value[3]);
1369 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1371 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1372 value[1], value[2], value[3]);
1374 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1376 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1377 value[1], value[2], value[3]);
1378 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1380 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1381 value[1], value[2], value[3]);
1382 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1384 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1385 value[1], value[2], value[3]);
1386 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1388 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1389 value[1], value[2], value[3]);
1391 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1393 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1394 value[1], value[2], value[3]);
1395 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1397 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1398 value[1], value[2], value[3]);
1399 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1401 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1402 value[1], value[2], value[3]);
1403 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1405 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1406 value[1], value[2], value[3]);
1408 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1410 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1411 value[1], value[2], value[3]);
1412 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1414 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1415 value[1], value[2], value[3]);
1416 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1418 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1419 value[1], value[2], value[3]);
1420 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1422 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1423 value[1], value[2], value[3]);
1425 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1427 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1428 value[1], value[2], value[3]);
1429 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1431 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1432 value[1], value[2], value[3]);
1437 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1445 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1446 value = (value & 0xFE)|0x01;
1447 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1449 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1450 value = (value & 0xFE)|0x00;
1451 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1455 config colibri to lo-if mode
1457 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1458 the diff IF input by half,
1460 for low-if agc defect
1463 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1464 value = (value & 0xFC)|0x00;
1465 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1467 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
1468 value = (value & 0xF9)|0x02;
1469 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
1471 status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1472 value = (value & 0xFB)|0x04;
1473 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1475 status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1476 value = (value & 0xFC)|0x03;
1477 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1479 status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1480 value = (value & 0xFB)|0x04;
1481 status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1483 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1484 value = (value & 0xF8)|0x06;
1485 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1487 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1488 value = (value & 0x8F)|0x40;
1489 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1491 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1492 value = (value & 0xDF)|0x20;
1493 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1496 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1497 u8 spectral_invert, u32 mode)
1499 u32 colibri_carrier_offset = 0;
1501 u32 func_mode = 0x01; /* Device has a DIF if this function is called */
1503 u8 value[4] = { 0, 0, 0, 0 };
1505 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
1506 value[0] = (u8) 0x6F;
1507 value[1] = (u8) 0x6F;
1508 value[2] = (u8) 0x6F;
1509 value[3] = (u8) 0x6F;
1510 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1511 PWR_CTL_EN, value, 4);
1513 /*Set colibri for low IF*/
1514 status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1516 /* Set C2HH for low IF operation.*/
1517 standard = dev->norm;
1518 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1519 func_mode, standard);
1521 /* Get colibri offsets.*/
1522 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1525 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
1526 colibri_carrier_offset, standard);
1528 /* Set the band Pass filter for DIF*/
1529 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
1530 spectral_invert, mode);
1533 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1535 u32 colibri_carrier_offset = 0;
1538 if (mode == TUNER_MODE_FM_RADIO) {
1539 colibri_carrier_offset = 1100000;
1540 } else if (standerd & (V4L2_STD_NTSC | V4L2_STD_NTSC_M_JP)) {
1541 colibri_carrier_offset = 4832000; /*4.83MHz */
1542 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1543 colibri_carrier_offset = 2700000; /*2.70MHz */
1544 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1545 | V4L2_STD_SECAM)) {
1546 colibri_carrier_offset = 2100000; /*2.10MHz */
1550 return colibri_carrier_offset;
1553 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1554 u8 spectral_invert, u32 mode)
1557 unsigned long pll_freq_word;
1559 u32 dif_misc_ctrl_value = 0;
1560 u64 pll_freq_u64 = 0;
1564 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1565 if_freq, spectral_invert, mode);
1568 if (mode == TUNER_MODE_FM_RADIO) {
1569 pll_freq_word = 0x905A1CAC;
1570 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1572 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1573 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1574 pll_freq_word = if_freq;
1575 pll_freq_u64 = (u64)pll_freq_word << 28L;
1576 do_div(pll_freq_u64, 50000000);
1577 pll_freq_word = (u32)pll_freq_u64;
1578 /*pll_freq_word = 0x3463497;*/
1579 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1581 if (spectral_invert) {
1583 /* Enable Spectral Invert*/
1584 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1585 &dif_misc_ctrl_value);
1586 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1587 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1588 dif_misc_ctrl_value);
1591 /* Disable Spectral Invert*/
1592 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1593 &dif_misc_ctrl_value);
1594 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1595 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1596 dif_misc_ctrl_value);
1599 if_freq = (if_freq/100000)*100000;
1601 if (if_freq < 3000000)
1604 if (if_freq > 16000000)
1608 cx231xx_info("Enter IF=%zd\n",
1609 sizeof(Dif_set_array)/sizeof(struct dif_settings));
1610 for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
1611 if (Dif_set_array[i].if_freq == if_freq) {
1612 status = vid_blk_write_word(dev,
1613 Dif_set_array[i].register_address, Dif_set_array[i].value);
1619 /******************************************************************************
1620 * D I F - B L O C K C O N T R O L functions *
1621 ******************************************************************************/
1622 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1623 u32 function_mode, u32 standard)
1628 if (mode == V4L2_TUNER_RADIO) {
1630 /* lo if big signal */
1631 status = cx231xx_reg_mask_write(dev,
1632 VID_BLK_I2C_ADDRESS, 32,
1633 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1634 /* FUNC_MODE = DIF */
1635 status = cx231xx_reg_mask_write(dev,
1636 VID_BLK_I2C_ADDRESS, 32,
1637 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1639 status = cx231xx_reg_mask_write(dev,
1640 VID_BLK_I2C_ADDRESS, 32,
1641 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1643 status = cx231xx_reg_mask_write(dev,
1644 VID_BLK_I2C_ADDRESS, 32,
1645 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1646 } else if (standard != DIF_USE_BASEBAND) {
1647 if (standard & V4L2_STD_MN) {
1648 /* lo if big signal */
1649 status = cx231xx_reg_mask_write(dev,
1650 VID_BLK_I2C_ADDRESS, 32,
1651 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1652 /* FUNC_MODE = DIF */
1653 status = cx231xx_reg_mask_write(dev,
1654 VID_BLK_I2C_ADDRESS, 32,
1655 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1658 status = cx231xx_reg_mask_write(dev,
1659 VID_BLK_I2C_ADDRESS, 32,
1660 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1662 status = cx231xx_reg_mask_write(dev,
1663 VID_BLK_I2C_ADDRESS, 32,
1664 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1665 /* 0x124, AUD_CHAN1_SRC = 0x3 */
1666 status = cx231xx_reg_mask_write(dev,
1667 VID_BLK_I2C_ADDRESS, 32,
1668 AUD_IO_CTRL, 0, 31, 0x00000003);
1669 } else if ((standard == V4L2_STD_PAL_I) |
1670 (standard & V4L2_STD_PAL_D) |
1671 (standard & V4L2_STD_SECAM)) {
1673 /* lo if big signal */
1674 status = cx231xx_reg_mask_write(dev,
1675 VID_BLK_I2C_ADDRESS, 32,
1676 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1677 /* FUNC_MODE = DIF */
1678 status = cx231xx_reg_mask_write(dev,
1679 VID_BLK_I2C_ADDRESS, 32,
1680 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1683 status = cx231xx_reg_mask_write(dev,
1684 VID_BLK_I2C_ADDRESS, 32,
1685 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1687 status = cx231xx_reg_mask_write(dev,
1688 VID_BLK_I2C_ADDRESS, 32,
1689 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1691 /* default PAL BG */
1693 /* lo if big signal */
1694 status = cx231xx_reg_mask_write(dev,
1695 VID_BLK_I2C_ADDRESS, 32,
1696 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1697 /* FUNC_MODE = DIF */
1698 status = cx231xx_reg_mask_write(dev,
1699 VID_BLK_I2C_ADDRESS, 32,
1700 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1703 status = cx231xx_reg_mask_write(dev,
1704 VID_BLK_I2C_ADDRESS, 32,
1705 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1707 status = cx231xx_reg_mask_write(dev,
1708 VID_BLK_I2C_ADDRESS, 32,
1709 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1716 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1719 u32 dif_misc_ctrl_value = 0;
1722 cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1724 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1725 if (standard != DIF_USE_BASEBAND)
1726 dev->norm = standard;
1728 switch (dev->model) {
1729 case CX231XX_BOARD_CNXT_CARRAERA:
1730 case CX231XX_BOARD_CNXT_RDE_250:
1731 case CX231XX_BOARD_CNXT_SHELBY:
1732 case CX231XX_BOARD_CNXT_RDU_250:
1733 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1734 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1737 case CX231XX_BOARD_CNXT_RDE_253S:
1738 case CX231XX_BOARD_CNXT_RDU_253S:
1745 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1746 func_mode, standard);
1748 if (standard == DIF_USE_BASEBAND) { /* base band */
1749 /* There is a different SRC_PHASE_INC value
1750 for baseband vs. DIF */
1751 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1752 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1753 &dif_misc_ctrl_value);
1754 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1755 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1756 dif_misc_ctrl_value);
1757 } else if (standard & V4L2_STD_PAL_D) {
1758 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1759 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1760 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1761 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1762 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1763 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1764 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1765 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1766 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1767 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1768 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1769 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1770 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1771 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1772 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1773 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1774 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1775 DIF_AGC_IF_INT_CURRENT, 0, 31,
1777 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1778 DIF_AGC_RF_CURRENT, 0, 31,
1780 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1781 DIF_VIDEO_AGC_CTRL, 0, 31,
1783 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1784 DIF_VID_AUD_OVERRIDE, 0, 31,
1786 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1787 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1788 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1789 DIF_COMP_FLT_CTRL, 0, 31,
1791 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1792 DIF_SRC_PHASE_INC, 0, 31,
1794 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1795 DIF_SRC_GAIN_CONTROL, 0, 31,
1797 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1798 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1799 /* Save the Spec Inversion value */
1800 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1801 dif_misc_ctrl_value |= 0x3a023F11;
1802 } else if (standard & V4L2_STD_PAL_I) {
1803 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1804 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1805 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1806 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1807 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1808 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1809 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1810 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1811 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1812 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1813 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1814 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1815 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1816 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1817 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1818 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1819 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1820 DIF_AGC_IF_INT_CURRENT, 0, 31,
1822 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1823 DIF_AGC_RF_CURRENT, 0, 31,
1825 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1826 DIF_VIDEO_AGC_CTRL, 0, 31,
1828 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1829 DIF_VID_AUD_OVERRIDE, 0, 31,
1831 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1832 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1833 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1834 DIF_COMP_FLT_CTRL, 0, 31,
1836 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1837 DIF_SRC_PHASE_INC, 0, 31,
1839 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1840 DIF_SRC_GAIN_CONTROL, 0, 31,
1842 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1843 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1844 /* Save the Spec Inversion value */
1845 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1846 dif_misc_ctrl_value |= 0x3a033F11;
1847 } else if (standard & V4L2_STD_PAL_M) {
1848 /* improved Low Frequency Phase Noise */
1849 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1850 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1851 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1852 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1853 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1854 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1856 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1858 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1860 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1862 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1863 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1865 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1867 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1869 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1871 /* Save the Spec Inversion value */
1872 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1873 dif_misc_ctrl_value |= 0x3A0A3F10;
1874 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1875 /* improved Low Frequency Phase Noise */
1876 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1877 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1878 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1879 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1880 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1881 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1883 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1885 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1887 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1889 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1891 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1893 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1895 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1897 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1899 /* Save the Spec Inversion value */
1900 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1901 dif_misc_ctrl_value = 0x3A093F10;
1902 } else if (standard &
1903 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1904 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1906 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1907 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1908 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1909 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1910 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1911 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1912 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1913 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1914 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1915 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1916 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1917 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1918 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1919 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1920 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1921 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1922 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1923 DIF_AGC_IF_INT_CURRENT, 0, 31,
1925 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1926 DIF_AGC_RF_CURRENT, 0, 31,
1928 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1929 DIF_VID_AUD_OVERRIDE, 0, 31,
1931 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1932 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1933 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1934 DIF_COMP_FLT_CTRL, 0, 31,
1936 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1937 DIF_SRC_PHASE_INC, 0, 31,
1939 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1940 DIF_SRC_GAIN_CONTROL, 0, 31,
1942 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1943 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1944 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1945 DIF_VIDEO_AGC_CTRL, 0, 31,
1948 /* Save the Spec Inversion value */
1949 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1950 dif_misc_ctrl_value |= 0x3a023F11;
1951 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1952 /* Is it SECAM_L1? */
1953 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1954 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1955 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1956 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1957 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1958 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1959 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1960 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1961 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1962 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1963 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1964 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1965 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1966 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1967 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1968 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1969 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1970 DIF_AGC_IF_INT_CURRENT, 0, 31,
1972 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1973 DIF_AGC_RF_CURRENT, 0, 31,
1975 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1976 DIF_VID_AUD_OVERRIDE, 0, 31,
1978 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1979 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1980 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1981 DIF_COMP_FLT_CTRL, 0, 31,
1983 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1984 DIF_SRC_PHASE_INC, 0, 31,
1986 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1987 DIF_SRC_GAIN_CONTROL, 0, 31,
1989 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1990 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1991 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1992 DIF_VIDEO_AGC_CTRL, 0, 31,
1995 /* Save the Spec Inversion value */
1996 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1997 dif_misc_ctrl_value |= 0x3a023F11;
1999 } else if (standard & V4L2_STD_NTSC_M) {
2000 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
2001 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
2003 /* For NTSC the centre frequency of video coming out of
2004 sidewinder is around 7.1MHz or 3.6MHz depending on the
2005 spectral inversion. so for a non spectrally inverted channel
2006 the pll freq word is 0x03420c49
2009 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2010 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2011 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2012 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2013 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2014 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2016 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2018 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2020 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2022 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2024 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2026 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2028 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2031 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2032 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2034 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2036 /* Save the Spec Inversion value */
2037 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2038 dif_misc_ctrl_value |= 0x3a003F10;
2040 /* default PAL BG */
2041 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2042 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
2043 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2044 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
2045 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2046 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
2047 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2048 DIF_PLL_CTRL3, 0, 31, 0x00008800);
2049 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2050 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
2051 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2052 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
2053 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2054 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
2055 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2056 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
2057 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2058 DIF_AGC_IF_INT_CURRENT, 0, 31,
2060 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2061 DIF_AGC_RF_CURRENT, 0, 31,
2063 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2064 DIF_VIDEO_AGC_CTRL, 0, 31,
2066 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2067 DIF_VID_AUD_OVERRIDE, 0, 31,
2069 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2070 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
2071 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2072 DIF_COMP_FLT_CTRL, 0, 31,
2074 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2075 DIF_SRC_PHASE_INC, 0, 31,
2077 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2078 DIF_SRC_GAIN_CONTROL, 0, 31,
2080 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2081 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2082 /* Save the Spec Inversion value */
2083 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2084 dif_misc_ctrl_value |= 0x3a013F11;
2087 /* The AGC values should be the same for all standards,
2088 AUD_SRC_SEL[19] should always be disabled */
2089 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2091 /* It is still possible to get Set Standard calls even when we
2093 This is done to override the value for FM. */
2094 if (dev->active_mode == V4L2_TUNER_RADIO)
2095 dif_misc_ctrl_value = 0x7a080000;
2097 /* Write the calculated value for misc ontrol register */
2098 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2103 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2108 /* Set the RF and IF k_agc values to 3 */
2109 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2110 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2111 dwval |= 0x33000000;
2113 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2118 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2122 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n",
2124 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2125 * SECAM L/B/D standards */
2126 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2127 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2129 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2130 V4L2_STD_SECAM_D)) {
2131 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2132 dwval &= ~FLD_DIF_IF_REF;
2133 dwval |= 0x88000300;
2135 dwval |= 0x88000000;
2137 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2138 dwval &= ~FLD_DIF_IF_REF;
2139 dwval |= 0xCC000300;
2141 dwval |= 0x44000000;
2144 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2149 /******************************************************************************
2150 * I 2 S - B L O C K C O N T R O L functions *
2151 ******************************************************************************/
2152 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2157 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2158 CH_PWR_CTRL1, 1, &value, 1);
2159 /* enables clock to delta-sigma and decimation filter */
2161 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2162 CH_PWR_CTRL1, 1, value, 1);
2163 /* power up all channel */
2164 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2165 CH_PWR_CTRL2, 1, 0x00, 1);
2170 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2171 enum AV_MODE avmode)
2176 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2177 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2178 CH_PWR_CTRL2, 1, &value, 1);
2180 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2181 CH_PWR_CTRL2, 1, value, 1);
2183 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2184 CH_PWR_CTRL2, 1, 0x00, 1);
2190 /* set i2s_blk for audio input types */
2191 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2195 switch (audio_input) {
2196 case CX231XX_AMUX_LINE_IN:
2197 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2198 CH_PWR_CTRL2, 1, 0x00, 1);
2199 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2200 CH_PWR_CTRL1, 1, 0x80, 1);
2202 case CX231XX_AMUX_VIDEO:
2207 dev->ctl_ainput = audio_input;
2212 /******************************************************************************
2213 * P O W E R C O N T R O L functions *
2214 ******************************************************************************/
2215 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2217 u8 value[4] = { 0, 0, 0, 0 };
2221 if (dev->power_mode != mode)
2222 dev->power_mode = mode;
2224 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
2229 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2234 tmp = *((u32 *) value);
2237 case POLARIS_AVMODE_ENXTERNAL_AV:
2239 tmp &= (~PWR_MODE_MASK);
2242 value[0] = (u8) tmp;
2243 value[1] = (u8) (tmp >> 8);
2244 value[2] = (u8) (tmp >> 16);
2245 value[3] = (u8) (tmp >> 24);
2246 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2247 PWR_CTL_EN, value, 4);
2248 msleep(PWR_SLEEP_INTERVAL);
2251 value[0] = (u8) tmp;
2252 value[1] = (u8) (tmp >> 8);
2253 value[2] = (u8) (tmp >> 16);
2254 value[3] = (u8) (tmp >> 24);
2256 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2258 msleep(PWR_SLEEP_INTERVAL);
2260 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2261 value[0] = (u8) tmp;
2262 value[1] = (u8) (tmp >> 8);
2263 value[2] = (u8) (tmp >> 16);
2264 value[3] = (u8) (tmp >> 24);
2265 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2266 PWR_CTL_EN, value, 4);
2268 /* reset state of xceive tuner */
2269 dev->xc_fw_load_done = 0;
2272 case POLARIS_AVMODE_ANALOGT_TV:
2274 tmp |= PWR_DEMOD_EN;
2275 tmp |= (I2C_DEMOD_EN);
2276 value[0] = (u8) tmp;
2277 value[1] = (u8) (tmp >> 8);
2278 value[2] = (u8) (tmp >> 16);
2279 value[3] = (u8) (tmp >> 24);
2280 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2281 PWR_CTL_EN, value, 4);
2282 msleep(PWR_SLEEP_INTERVAL);
2284 if (!(tmp & PWR_TUNER_EN)) {
2285 tmp |= (PWR_TUNER_EN);
2286 value[0] = (u8) tmp;
2287 value[1] = (u8) (tmp >> 8);
2288 value[2] = (u8) (tmp >> 16);
2289 value[3] = (u8) (tmp >> 24);
2290 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2291 PWR_CTL_EN, value, 4);
2292 msleep(PWR_SLEEP_INTERVAL);
2295 if (!(tmp & PWR_AV_EN)) {
2297 value[0] = (u8) tmp;
2298 value[1] = (u8) (tmp >> 8);
2299 value[2] = (u8) (tmp >> 16);
2300 value[3] = (u8) (tmp >> 24);
2301 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2302 PWR_CTL_EN, value, 4);
2303 msleep(PWR_SLEEP_INTERVAL);
2305 if (!(tmp & PWR_ISO_EN)) {
2307 value[0] = (u8) tmp;
2308 value[1] = (u8) (tmp >> 8);
2309 value[2] = (u8) (tmp >> 16);
2310 value[3] = (u8) (tmp >> 24);
2311 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2312 PWR_CTL_EN, value, 4);
2313 msleep(PWR_SLEEP_INTERVAL);
2316 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2317 tmp |= POLARIS_AVMODE_ANALOGT_TV;
2318 value[0] = (u8) tmp;
2319 value[1] = (u8) (tmp >> 8);
2320 value[2] = (u8) (tmp >> 16);
2321 value[3] = (u8) (tmp >> 24);
2322 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2323 PWR_CTL_EN, value, 4);
2324 msleep(PWR_SLEEP_INTERVAL);
2327 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2328 (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2329 (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2330 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2331 /* tuner path to channel 1 from port 3 */
2332 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2334 /* reset the Tuner */
2335 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2337 if (dev->cx231xx_reset_analog_tuner)
2338 dev->cx231xx_reset_analog_tuner(dev);
2339 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2340 (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2341 (dev->model == CX231XX_BOARD_CNXT_RDU_253S) ||
2342 (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER)) {
2343 /* tuner path to channel 1 from port 3 */
2344 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2345 if (dev->cx231xx_reset_analog_tuner)
2346 dev->cx231xx_reset_analog_tuner(dev);
2351 case POLARIS_AVMODE_DIGITAL:
2352 if (!(tmp & PWR_TUNER_EN)) {
2353 tmp |= (PWR_TUNER_EN);
2354 value[0] = (u8) tmp;
2355 value[1] = (u8) (tmp >> 8);
2356 value[2] = (u8) (tmp >> 16);
2357 value[3] = (u8) (tmp >> 24);
2358 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2359 PWR_CTL_EN, value, 4);
2360 msleep(PWR_SLEEP_INTERVAL);
2362 if (!(tmp & PWR_AV_EN)) {
2364 value[0] = (u8) tmp;
2365 value[1] = (u8) (tmp >> 8);
2366 value[2] = (u8) (tmp >> 16);
2367 value[3] = (u8) (tmp >> 24);
2368 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2369 PWR_CTL_EN, value, 4);
2370 msleep(PWR_SLEEP_INTERVAL);
2372 if (!(tmp & PWR_ISO_EN)) {
2374 value[0] = (u8) tmp;
2375 value[1] = (u8) (tmp >> 8);
2376 value[2] = (u8) (tmp >> 16);
2377 value[3] = (u8) (tmp >> 24);
2378 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2379 PWR_CTL_EN, value, 4);
2380 msleep(PWR_SLEEP_INTERVAL);
2383 tmp &= (~PWR_AV_MODE);
2384 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
2385 value[0] = (u8) tmp;
2386 value[1] = (u8) (tmp >> 8);
2387 value[2] = (u8) (tmp >> 16);
2388 value[3] = (u8) (tmp >> 24);
2389 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2390 PWR_CTL_EN, value, 4);
2391 msleep(PWR_SLEEP_INTERVAL);
2393 if (!(tmp & PWR_DEMOD_EN)) {
2394 tmp |= PWR_DEMOD_EN;
2395 value[0] = (u8) tmp;
2396 value[1] = (u8) (tmp >> 8);
2397 value[2] = (u8) (tmp >> 16);
2398 value[3] = (u8) (tmp >> 24);
2399 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2400 PWR_CTL_EN, value, 4);
2401 msleep(PWR_SLEEP_INTERVAL);
2404 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2405 (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2406 (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2407 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2408 /* tuner path to channel 1 from port 3 */
2409 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2411 /* reset the Tuner */
2412 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2414 if (dev->cx231xx_reset_analog_tuner)
2415 dev->cx231xx_reset_analog_tuner(dev);
2416 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2417 (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2418 (dev->model == CX231XX_BOARD_CNXT_RDU_253S)) {
2419 /* tuner path to channel 1 from port 3 */
2420 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2421 if (dev->cx231xx_reset_analog_tuner)
2422 dev->cx231xx_reset_analog_tuner(dev);
2423 } else if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) {
2424 /* tuner path to channel 1 from port 1 ?? */
2425 cx231xx_enable_i2c_for_tuner(dev, I2C_1);
2427 if (dev->cx231xx_reset_analog_tuner)
2428 dev->cx231xx_reset_analog_tuner(dev);
2437 msleep(PWR_SLEEP_INTERVAL);
2439 /* For power saving, only enable Pwr_resetout_n
2440 when digital TV is selected. */
2441 if (mode == POLARIS_AVMODE_DIGITAL) {
2442 tmp |= PWR_RESETOUT_EN;
2443 value[0] = (u8) tmp;
2444 value[1] = (u8) (tmp >> 8);
2445 value[2] = (u8) (tmp >> 16);
2446 value[3] = (u8) (tmp >> 24);
2447 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2448 PWR_CTL_EN, value, 4);
2449 msleep(PWR_SLEEP_INTERVAL);
2452 /* update power control for afe */
2453 status = cx231xx_afe_update_power_control(dev, mode);
2455 /* update power control for i2s_blk */
2456 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2458 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2464 int cx231xx_power_suspend(struct cx231xx *dev)
2466 u8 value[4] = { 0, 0, 0, 0 };
2470 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2475 tmp = *((u32 *) value);
2476 tmp &= (~PWR_MODE_MASK);
2478 value[0] = (u8) tmp;
2479 value[1] = (u8) (tmp >> 8);
2480 value[2] = (u8) (tmp >> 16);
2481 value[3] = (u8) (tmp >> 24);
2482 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2488 /******************************************************************************
2489 * S T R E A M C O N T R O L functions *
2490 ******************************************************************************/
2491 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2493 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2497 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2498 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2503 tmp = *((u32 *) value);
2505 value[0] = (u8) tmp;
2506 value[1] = (u8) (tmp >> 8);
2507 value[2] = (u8) (tmp >> 16);
2508 value[3] = (u8) (tmp >> 24);
2510 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2516 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2518 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2522 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2524 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2528 tmp = *((u32 *) value);
2530 value[0] = (u8) tmp;
2531 value[1] = (u8) (tmp >> 8);
2532 value[2] = (u8) (tmp >> 16);
2533 value[3] = (u8) (tmp >> 24);
2535 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2541 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2545 u8 val[4] = { 0, 0, 0, 0 };
2547 if (dev->udev->speed == USB_SPEED_HIGH) {
2548 switch (media_type) {
2549 case 81: /* audio */
2550 cx231xx_info("%s: Audio enter HANC\n", __func__);
2552 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2556 cx231xx_info("%s: set vanc registers\n", __func__);
2557 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2560 case 3: /* sliced cc */
2561 cx231xx_info("%s: set hanc registers\n", __func__);
2563 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2567 cx231xx_info("%s: set video registers\n", __func__);
2568 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2572 cx231xx_info("%s: set ts1 registers", __func__);
2574 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
2575 cx231xx_info(" MPEG\n");
2576 value &= 0xFFFFFFFC;
2579 status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2585 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2586 TS1_CFG_REG, val, 4);
2592 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2593 TS1_LENGTH_REG, val, 4);
2596 cx231xx_info(" BDA\n");
2597 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2598 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2602 case 6: /* ts1 parallel mode */
2603 cx231xx_info("%s: set ts1 parrallel mode registers\n",
2605 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2606 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2610 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2616 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2620 struct pcb_config *pcb_config;
2622 /* get EP for media type */
2623 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2625 if (pcb_config->config_num == 1) {
2626 switch (media_type) {
2628 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2631 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2634 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2636 case 3: /* Sliced_cc */
2637 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2640 case 6: /* ts1 parallel mode */
2641 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2644 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2648 } else if (pcb_config->config_num > 1) {
2649 switch (media_type) {
2651 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2654 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2657 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2659 case 3: /* Sliced_cc */
2660 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2663 case 6: /* ts1 parallel mode */
2664 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2667 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2674 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2679 /* enable video capture */
2681 rc = cx231xx_start_stream(dev, ep_mask);
2683 /* disable video capture */
2685 rc = cx231xx_stop_stream(dev, ep_mask);
2688 if (dev->mode == CX231XX_ANALOG_MODE)
2689 ;/* do any in Analog mode */
2691 ;/* do any in digital mode */
2695 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2697 /*****************************************************************************
2698 * G P I O B I T control functions *
2699 ******************************************************************************/
2700 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2704 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2709 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2713 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2719 * cx231xx_set_gpio_direction
2720 * Sets the direction of the GPIO pin to input or output
2723 * pin_number : The GPIO Pin number to program the direction for
2725 * pin_value : The Direction of the GPIO Pin under reference.
2726 * 0 = Input direction
2727 * 1 = Output direction
2729 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2730 int pin_number, int pin_value)
2735 /* Check for valid pin_number - if 32 , bail out */
2736 if (pin_number >= 32)
2741 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
2743 value = dev->gpio_dir | (1 << pin_number);
2745 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2747 /* cache the value for future */
2748 dev->gpio_dir = value;
2754 * cx231xx_set_gpio_value
2755 * Sets the value of the GPIO pin to Logic high or low. The Pin under
2756 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2759 * pin_number : The GPIO Pin number to program the direction for
2760 * pin_value : The value of the GPIO Pin under reference.
2764 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2769 /* Check for valid pin_number - if 0xFF , bail out */
2770 if (pin_number >= 32)
2773 /* first do a sanity check - if the Pin is not output, make it output */
2774 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2775 /* It was in input mode */
2776 value = dev->gpio_dir | (1 << pin_number);
2777 dev->gpio_dir = value;
2778 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2779 (u8 *) &dev->gpio_val);
2784 value = dev->gpio_val & (~(1 << pin_number));
2786 value = dev->gpio_val | (1 << pin_number);
2788 /* store the value */
2789 dev->gpio_val = value;
2791 /* toggle bit0 of GP_IO */
2792 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2797 /*****************************************************************************
2798 * G P I O I2C related functions *
2799 ******************************************************************************/
2800 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2804 /* set SCL to output 1 ; set SDA to output 1 */
2805 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2806 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2807 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2808 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2810 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2814 /* set SCL to output 1; set SDA to output 0 */
2815 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2816 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2818 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2822 /* set SCL to output 0; set SDA to output 0 */
2823 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2824 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2826 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2833 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2837 /* set SCL to output 0; set SDA to output 0 */
2838 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2839 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2841 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2842 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2844 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2848 /* set SCL to output 1; set SDA to output 0 */
2849 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2850 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2852 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2856 /* set SCL to input ,release SCL cable control
2857 set SDA to input ,release SDA cable control */
2858 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2859 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2862 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2869 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2874 /* set SCL to output ; set SDA to output */
2875 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2876 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2878 for (i = 0; i < 8; i++) {
2879 if (((data << i) & 0x80) == 0) {
2880 /* set SCL to output 0; set SDA to output 0 */
2881 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2882 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2883 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2884 (u8 *)&dev->gpio_val);
2886 /* set SCL to output 1; set SDA to output 0 */
2887 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2888 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2889 (u8 *)&dev->gpio_val);
2891 /* set SCL to output 0; set SDA to output 0 */
2892 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2893 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2894 (u8 *)&dev->gpio_val);
2896 /* set SCL to output 0; set SDA to output 1 */
2897 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2898 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2899 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2900 (u8 *)&dev->gpio_val);
2902 /* set SCL to output 1; set SDA to output 1 */
2903 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2904 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2905 (u8 *)&dev->gpio_val);
2907 /* set SCL to output 0; set SDA to output 1 */
2908 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2909 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2910 (u8 *)&dev->gpio_val);
2916 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2920 u32 gpio_logic_value = 0;
2924 for (i = 0; i < 8; i++) { /* send write I2c addr */
2926 /* set SCL to output 0; set SDA to input */
2927 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2928 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2929 (u8 *)&dev->gpio_val);
2931 /* set SCL to output 1; set SDA to input */
2932 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2933 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2934 (u8 *)&dev->gpio_val);
2936 /* get SDA data bit */
2937 gpio_logic_value = dev->gpio_val;
2938 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2939 (u8 *)&dev->gpio_val);
2940 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2941 value |= (1 << (8 - i - 1));
2943 dev->gpio_val = gpio_logic_value;
2946 /* set SCL to output 0,finish the read latest SCL signal.
2947 !!!set SDA to input, never to modify SDA direction at
2949 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2950 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2952 /* store the value */
2953 *buf = value & 0xff;
2958 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2961 u32 gpio_logic_value = 0;
2965 /* clock stretch; set SCL to input; set SDA to input;
2966 get SCL value till SCL = 1 */
2967 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2968 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2970 gpio_logic_value = dev->gpio_val;
2971 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2975 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2976 (u8 *)&dev->gpio_val);
2978 } while (((dev->gpio_val &
2979 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2983 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2988 * through clock stretch, slave has given a SCL signal,
2989 * so the SDA data can be directly read.
2991 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2993 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2994 dev->gpio_val = gpio_logic_value;
2995 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2998 dev->gpio_val = gpio_logic_value;
2999 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
3002 /* read SDA end, set the SCL to output 0, after this operation,
3003 SDA direction can be changed. */
3004 dev->gpio_val = gpio_logic_value;
3005 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
3006 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3007 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3012 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
3016 /* set SDA to ouput */
3017 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
3018 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3020 /* set SCL = 0 (output); set SDA = 0 (output) */
3021 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3022 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3023 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3025 /* set SCL = 1 (output); set SDA = 0 (output) */
3026 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3027 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3029 /* set SCL = 0 (output); set SDA = 0 (output) */
3030 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3031 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3033 /* set SDA to input,and then the slave will read data from SDA. */
3034 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3035 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3040 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
3044 /* set scl to output ; set sda to input */
3045 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
3046 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3047 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3049 /* set scl to output 0; set sda to input */
3050 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3051 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3053 /* set scl to output 1; set sda to input */
3054 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3055 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3060 /*****************************************************************************
3061 * G P I O I2C related functions *
3062 ******************************************************************************/
3063 /* cx231xx_gpio_i2c_read
3064 * Function to read data from gpio based I2C interface
3066 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3072 mutex_lock(&dev->gpio_i2c_lock);
3075 status = cx231xx_gpio_i2c_start(dev);
3077 /* write dev_addr */
3078 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3081 status = cx231xx_gpio_i2c_read_ack(dev);
3084 for (i = 0; i < len; i++) {
3087 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3089 if ((i + 1) != len) {
3090 /* only do write ack if we more length */
3091 status = cx231xx_gpio_i2c_write_ack(dev);
3095 /* write NAK - inform reads are complete */
3096 status = cx231xx_gpio_i2c_write_nak(dev);
3099 status = cx231xx_gpio_i2c_end(dev);
3101 /* release the lock */
3102 mutex_unlock(&dev->gpio_i2c_lock);
3107 /* cx231xx_gpio_i2c_write
3108 * Function to write data to gpio based I2C interface
3110 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3116 mutex_lock(&dev->gpio_i2c_lock);
3119 status = cx231xx_gpio_i2c_start(dev);
3121 /* write dev_addr */
3122 status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3125 status = cx231xx_gpio_i2c_read_ack(dev);
3127 for (i = 0; i < len; i++) {
3129 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3132 status = cx231xx_gpio_i2c_read_ack(dev);
3136 status = cx231xx_gpio_i2c_end(dev);
3138 /* release the lock */
3139 mutex_unlock(&dev->gpio_i2c_lock);