drivers/media/video/cx23885/cx23885-417.c

   1 /*
   2  *
   3  *  Support for a cx23417 mpeg encoder via cx23885 host port.
   4  *
   5  *    (c) 2004 Jelle Foks <jelle@foks.us>
   6  *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
   7  *    (c) 2008 Steven Toth <stoth@linuxtv.org>
   8  *      - CX23885/7/8 support
   9  *
  10  *  Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
  11  *
  12  *  This program is free software; you can redistribute it and/or modify
  13  *  it under the terms of the GNU General Public License as published by
  14  *  the Free Software Foundation; either version 2 of the License, or
  15  *  (at your option) any later version.
  16  *
  17  *  This program is distributed in the hope that it will be useful,
  18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *  GNU General Public License for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License
  23  *  along with this program; if not, write to the Free Software
  24  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/fs.h>
  31 #include <linux/delay.h>
  32 #include <linux/device.h>
  33 #include <linux/firmware.h>
  34 #include <linux/smp_lock.h>
  35 #include <media/v4l2-common.h>
  36 #include <media/v4l2-ioctl.h>
  37 #include <media/cx2341x.h>
  38
  39 #include "cx23885.h"
  40
  41 #define CX23885_FIRM_IMAGE_SIZE 376836
  42 #define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
  43
  44 static unsigned int mpegbufs = 32;
  45 module_param(mpegbufs, int, 0644);
  46 MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
  47 static unsigned int mpeglines = 32;
  48 module_param(mpeglines, int, 0644);
  49 MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
  50 static unsigned int mpeglinesize = 512;
  51 module_param(mpeglinesize, int, 0644);
  52 MODULE_PARM_DESC(mpeglinesize,
  53         "number of bytes in each line of an MPEG buffer, range 512-1024");
  54
  55 static unsigned int v4l_debug;
  56 module_param(v4l_debug, int, 0644);
  57 MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
  58
  59 #define dprintk(level, fmt, arg...)\
  60         do { if (v4l_debug >= level) \
  61                 printk(KERN_DEBUG "%s: " fmt, \
  62                 (dev) ? dev->name : "cx23885[?]", ## arg); \
  63         } while (0)
  64
  65 static struct cx23885_tvnorm cx23885_tvnorms[] = {
  66         {
  67                 .name      = "NTSC-M",
  68                 .id        = V4L2_STD_NTSC_M,
  69         }, {
  70                 .name      = "NTSC-JP",
  71                 .id        = V4L2_STD_NTSC_M_JP,
  72         }, {
  73                 .name      = "PAL-BG",
  74                 .id        = V4L2_STD_PAL_BG,
  75         }, {
  76                 .name      = "PAL-DK",
  77                 .id        = V4L2_STD_PAL_DK,
  78         }, {
  79                 .name      = "PAL-I",
  80                 .id        = V4L2_STD_PAL_I,
  81         }, {
  82                 .name      = "PAL-M",
  83                 .id        = V4L2_STD_PAL_M,
  84         }, {
  85                 .name      = "PAL-N",
  86                 .id        = V4L2_STD_PAL_N,
  87         }, {
  88                 .name      = "PAL-Nc",
  89                 .id        = V4L2_STD_PAL_Nc,
  90         }, {
  91                 .name      = "PAL-60",
  92                 .id        = V4L2_STD_PAL_60,
  93         }, {
  94                 .name      = "SECAM-L",
  95                 .id        = V4L2_STD_SECAM_L,
  96         }, {
  97                 .name      = "SECAM-DK",
  98                 .id        = V4L2_STD_SECAM_DK,
  99         }
 100 };
 101
 102 /* ------------------------------------------------------------------ */
 103 enum cx23885_capture_type {
 104         CX23885_MPEG_CAPTURE,
 105         CX23885_RAW_CAPTURE,
 106         CX23885_RAW_PASSTHRU_CAPTURE
 107 };
 108 enum cx23885_capture_bits {
 109         CX23885_RAW_BITS_NONE             = 0x00,
 110         CX23885_RAW_BITS_YUV_CAPTURE      = 0x01,
 111         CX23885_RAW_BITS_PCM_CAPTURE      = 0x02,
 112         CX23885_RAW_BITS_VBI_CAPTURE      = 0x04,
 113         CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
 114         CX23885_RAW_BITS_TO_HOST_CAPTURE  = 0x10
 115 };
 116 enum cx23885_capture_end {
 117         CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */
 118         CX23885_END_NOW, /* stop immediately, no irq */
 119 };
 120 enum cx23885_framerate {
 121         CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */
 122         CX23885_FRAMERATE_PAL_25   /* PAL: 25fps */
 123 };
 124 enum cx23885_stream_port {
 125         CX23885_OUTPUT_PORT_MEMORY,
 126         CX23885_OUTPUT_PORT_STREAMING,
 127         CX23885_OUTPUT_PORT_SERIAL
 128 };
 129 enum cx23885_data_xfer_status {
 130         CX23885_MORE_BUFFERS_FOLLOW,
 131         CX23885_LAST_BUFFER,
 132 };
 133 enum cx23885_picture_mask {
 134         CX23885_PICTURE_MASK_NONE,
 135         CX23885_PICTURE_MASK_I_FRAMES,
 136         CX23885_PICTURE_MASK_I_P_FRAMES = 0x3,
 137         CX23885_PICTURE_MASK_ALL_FRAMES = 0x7,
 138 };
 139 enum cx23885_vbi_mode_bits {
 140         CX23885_VBI_BITS_SLICED,
 141         CX23885_VBI_BITS_RAW,
 142 };
 143 enum cx23885_vbi_insertion_bits {
 144         CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
 145         CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
 146         CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
 147         CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
 148         CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
 149 };
 150 enum cx23885_dma_unit {
 151         CX23885_DMA_BYTES,
 152         CX23885_DMA_FRAMES,
 153 };
 154 enum cx23885_dma_transfer_status_bits {
 155         CX23885_DMA_TRANSFER_BITS_DONE = 0x01,
 156         CX23885_DMA_TRANSFER_BITS_ERROR = 0x04,
 157         CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
 158 };
 159 enum cx23885_pause {
 160         CX23885_PAUSE_ENCODING,
 161         CX23885_RESUME_ENCODING,
 162 };
 163 enum cx23885_copyright {
 164         CX23885_COPYRIGHT_OFF,
 165         CX23885_COPYRIGHT_ON,
 166 };
 167 enum cx23885_notification_type {
 168         CX23885_NOTIFICATION_REFRESH,
 169 };
 170 enum cx23885_notification_status {
 171         CX23885_NOTIFICATION_OFF,
 172         CX23885_NOTIFICATION_ON,
 173 };
 174 enum cx23885_notification_mailbox {
 175         CX23885_NOTIFICATION_NO_MAILBOX = -1,
 176 };
 177 enum cx23885_field1_lines {
 178         CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */
 179         CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */
 180         CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */
 181 };
 182 enum cx23885_field2_lines {
 183         CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */
 184         CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */
 185         CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */
 186 };
 187 enum cx23885_custom_data_type {
 188         CX23885_CUSTOM_EXTENSION_USR_DATA,
 189         CX23885_CUSTOM_PRIVATE_PACKET,
 190 };
 191 enum cx23885_mute {
 192         CX23885_UNMUTE,
 193         CX23885_MUTE,
 194 };
 195 enum cx23885_mute_video_mask {
 196         CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00,
 197         CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000,
 198         CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000,
 199 };
 200 enum cx23885_mute_video_shift {
 201         CX23885_MUTE_VIDEO_V_SHIFT = 8,
 202         CX23885_MUTE_VIDEO_U_SHIFT = 16,
 203         CX23885_MUTE_VIDEO_Y_SHIFT = 24,
 204 };
 205
 206 /* defines below are from ivtv-driver.h */
 207 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
 208
 209 /* Firmware API commands */
 210 #define IVTV_API_STD_TIMEOUT 500
 211
 212 /* Registers */
 213 /* IVTV_REG_OFFSET */
 214 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
 215 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
 216 #define IVTV_REG_SPU (0x9050)
 217 #define IVTV_REG_HW_BLOCKS (0x9054)
 218 #define IVTV_REG_VPU (0x9058)
 219 #define IVTV_REG_APU (0xA064)
 220
 221 /**** Bit definitions for MC417_RWD and MC417_OEN registers  ***
 222   bits 31-16
 223 +-----------+
 224 | Reserved  |
 225 +-----------+
 226   bit 15  bit 14  bit 13 bit 12  bit 11  bit 10  bit 9   bit 8
 227 +-------+-------+-------+-------+-------+-------+-------+-------+
 228 | MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
 229 +-------+-------+-------+-------+-------+-------+-------+-------+
 230  bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
 231 +-------+-------+-------+-------+-------+-------+-------+-------+
 232 |MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
 233 +-------+-------+-------+-------+-------+-------+-------+-------+
 234 ***/
 235 #define MC417_MIWR      0x8000
 236 #define MC417_MIRD      0x4000
 237 #define MC417_MICS      0x2000
 238 #define MC417_MIRDY     0x1000
 239 #define MC417_MIADDR    0x0F00
 240 #define MC417_MIDATA    0x00FF
 241
 242 /* MIADDR* nibble definitions */
 243 #define  MCI_MEMORY_DATA_BYTE0          0x000
 244 #define  MCI_MEMORY_DATA_BYTE1          0x100
 245 #define  MCI_MEMORY_DATA_BYTE2          0x200
 246 #define  MCI_MEMORY_DATA_BYTE3          0x300
 247 #define  MCI_MEMORY_ADDRESS_BYTE2       0x400
 248 #define  MCI_MEMORY_ADDRESS_BYTE1       0x500
 249 #define  MCI_MEMORY_ADDRESS_BYTE0       0x600
 250 #define  MCI_REGISTER_DATA_BYTE0        0x800
 251 #define  MCI_REGISTER_DATA_BYTE1        0x900
 252 #define  MCI_REGISTER_DATA_BYTE2        0xA00
 253 #define  MCI_REGISTER_DATA_BYTE3        0xB00
 254 #define  MCI_REGISTER_ADDRESS_BYTE0     0xC00
 255 #define  MCI_REGISTER_ADDRESS_BYTE1     0xD00
 256 #define  MCI_REGISTER_MODE              0xE00
 257
 258 /* Read and write modes */
 259 #define  MCI_MODE_REGISTER_READ         0
 260 #define  MCI_MODE_REGISTER_WRITE        1
 261 #define  MCI_MODE_MEMORY_READ           0
 262 #define  MCI_MODE_MEMORY_WRITE          0x40
 263
 264 /*** Bit definitions for MC417_CTL register ****
 265  bits 31-6   bits 5-4   bit 3    bits 2-1       Bit 0
 266 +--------+-------------+--------+--------------+------------+
 267 |Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
 268 +--------+-------------+--------+--------------+------------+
 269 ***/
 270 #define MC417_SPD_CTL(x)        (((x) << 4) & 0x00000030)
 271 #define MC417_GPIO_SEL(x)       (((x) << 1) & 0x00000006)
 272 #define MC417_UART_GPIO_EN      0x00000001
 273
 274 /* Values for speed control */
 275 #define MC417_SPD_CTL_SLOW      0x1
 276 #define MC417_SPD_CTL_MEDIUM    0x0
 277 #define MC417_SPD_CTL_FAST      0x3     /* b'1x, but we use b'11 */
 278
 279 /* Values for GPIO select */
 280 #define MC417_GPIO_SEL_GPIO3    0x3
 281 #define MC417_GPIO_SEL_GPIO2    0x2
 282 #define MC417_GPIO_SEL_GPIO1    0x1
 283 #define MC417_GPIO_SEL_GPIO0    0x0
 284
 285 void cx23885_mc417_init(struct cx23885_dev *dev)
 286 {
 287         u32 regval;
 288
 289         dprintk(2, "%s()\n", __func__);
 290
 291         /* Configure MC417_CTL register to defaults. */
 292         regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST)      |
 293                  MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3)   |
 294                  MC417_UART_GPIO_EN;
 295         cx_write(MC417_CTL, regval);
 296
 297         /* Configure MC417_OEN to defaults. */
 298         regval = MC417_MIRDY;
 299         cx_write(MC417_OEN, regval);
 300
 301         /* Configure MC417_RWD to defaults. */
 302         regval = MC417_MIWR | MC417_MIRD | MC417_MICS;
 303         cx_write(MC417_RWD, regval);
 304 }
 305
 306 static int mc417_wait_ready(struct cx23885_dev *dev)
 307 {
 308         u32 mi_ready;
 309         unsigned long timeout = jiffies + msecs_to_jiffies(1);
 310
 311         for (;;) {
 312                 mi_ready = cx_read(MC417_RWD) & MC417_MIRDY;
 313                 if (mi_ready != 0)
 314                         return 0;
 315                 if (time_after(jiffies, timeout))
 316                         return -1;
 317                 udelay(1);
 318         }
 319 }
 320
 321 static int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value)
 322 {
 323         u32 regval;
 324
 325         /* Enable MC417 GPIO outputs except for MC417_MIRDY,
 326          * which is an input.
 327          */
 328         cx_write(MC417_OEN, MC417_MIRDY);
 329
 330         /* Write data byte 0 */
 331         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 |
 332                 (value & 0x000000FF);
 333         cx_write(MC417_RWD, regval);
 334
 335         /* Transition CS/WR to effect write transaction across bus. */
 336         regval |= MC417_MICS | MC417_MIWR;
 337         cx_write(MC417_RWD, regval);
 338
 339         /* Write data byte 1 */
 340         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 |
 341                 ((value >> 8) & 0x000000FF);
 342         cx_write(MC417_RWD, regval);
 343         regval |= MC417_MICS | MC417_MIWR;
 344         cx_write(MC417_RWD, regval);
 345
 346         /* Write data byte 2 */
 347         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 |
 348                 ((value >> 16) & 0x000000FF);
 349         cx_write(MC417_RWD, regval);
 350         regval |= MC417_MICS | MC417_MIWR;
 351         cx_write(MC417_RWD, regval);
 352
 353         /* Write data byte 3 */
 354         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 |
 355                 ((value >> 24) & 0x000000FF);
 356         cx_write(MC417_RWD, regval);
 357         regval |= MC417_MICS | MC417_MIWR;
 358         cx_write(MC417_RWD, regval);
 359
 360         /* Write address byte 0 */
 361         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
 362                 (address & 0xFF);
 363         cx_write(MC417_RWD, regval);
 364         regval |= MC417_MICS | MC417_MIWR;
 365         cx_write(MC417_RWD, regval);
 366
 367         /* Write address byte 1 */
 368         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
 369                 ((address >> 8) & 0xFF);
 370         cx_write(MC417_RWD, regval);
 371         regval |= MC417_MICS | MC417_MIWR;
 372         cx_write(MC417_RWD, regval);
 373
 374         /* Indicate that this is a write. */
 375         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
 376                 MCI_MODE_REGISTER_WRITE;
 377         cx_write(MC417_RWD, regval);
 378         regval |= MC417_MICS | MC417_MIWR;
 379         cx_write(MC417_RWD, regval);
 380
 381         /* Wait for the trans to complete (MC417_MIRDY asserted). */
 382         return mc417_wait_ready(dev);
 383 }
 384
 385 static int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value)
 386 {
 387         int retval;
 388         u32 regval;
 389         u32 tempval;
 390         u32 dataval;
 391
 392         /* Enable MC417 GPIO outputs except for MC417_MIRDY,
 393          * which is an input.
 394          */
 395         cx_write(MC417_OEN, MC417_MIRDY);
 396
 397         /* Write address byte 0 */
 398         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
 399                 ((address & 0x00FF));
 400         cx_write(MC417_RWD, regval);
 401         regval |= MC417_MICS | MC417_MIWR;
 402         cx_write(MC417_RWD, regval);
 403
 404         /* Write address byte 1 */
 405         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
 406                 ((address >> 8) & 0xFF);
 407         cx_write(MC417_RWD, regval);
 408         regval |= MC417_MICS | MC417_MIWR;
 409         cx_write(MC417_RWD, regval);
 410
 411         /* Indicate that this is a register read. */
 412         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
 413                 MCI_MODE_REGISTER_READ;
 414         cx_write(MC417_RWD, regval);
 415         regval |= MC417_MICS | MC417_MIWR;
 416         cx_write(MC417_RWD, regval);
 417
 418         /* Wait for the trans to complete (MC417_MIRDY asserted). */
 419         retval = mc417_wait_ready(dev);
 420
 421         /* switch the DAT0-7 GPIO[10:3] to input mode */
 422         cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
 423
 424         /* Read data byte 0 */
 425         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
 426         cx_write(MC417_RWD, regval);
 427
 428         /* Transition RD to effect read transaction across bus.
 429          * Transtion 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)?
 430          * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its
 431          * input only...)
 432          */
 433         regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
 434         cx_write(MC417_RWD, regval);
 435
 436         /* Collect byte */
 437         tempval = cx_read(MC417_RWD);
 438         dataval = tempval & 0x000000FF;
 439
 440         /* Bring CS and RD high. */
 441         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 442         cx_write(MC417_RWD, regval);
 443
 444         /* Read data byte 1 */
 445         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
 446         cx_write(MC417_RWD, regval);
 447         regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
 448         cx_write(MC417_RWD, regval);
 449         tempval = cx_read(MC417_RWD);
 450         dataval |= ((tempval & 0x000000FF) << 8);
 451         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 452         cx_write(MC417_RWD, regval);
 453
 454         /* Read data byte 2 */
 455         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
 456         cx_write(MC417_RWD, regval);
 457         regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
 458         cx_write(MC417_RWD, regval);
 459         tempval = cx_read(MC417_RWD);
 460         dataval |= ((tempval & 0x000000FF) << 16);
 461         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 462         cx_write(MC417_RWD, regval);
 463
 464         /* Read data byte 3 */
 465         regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
 466         cx_write(MC417_RWD, regval);
 467         regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
 468         cx_write(MC417_RWD, regval);
 469         tempval = cx_read(MC417_RWD);
 470         dataval |= ((tempval & 0x000000FF) << 24);
 471         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 472         cx_write(MC417_RWD, regval);
 473
 474         *value  = dataval;
 475
 476         return retval;
 477 }
 478
 479 int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value)
 480 {
 481         u32 regval;
 482
 483         /* Enable MC417 GPIO outputs except for MC417_MIRDY,
 484          * which is an input.
 485          */
 486         cx_write(MC417_OEN, MC417_MIRDY);
 487
 488         /* Write data byte 0 */
 489         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 |
 490                 (value & 0x000000FF);
 491         cx_write(MC417_RWD, regval);
 492
 493         /* Transition CS/WR to effect write transaction across bus. */
 494         regval |= MC417_MICS | MC417_MIWR;
 495         cx_write(MC417_RWD, regval);
 496
 497         /* Write data byte 1 */
 498         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 |
 499                 ((value >> 8) & 0x000000FF);
 500         cx_write(MC417_RWD, regval);
 501         regval |= MC417_MICS | MC417_MIWR;
 502         cx_write(MC417_RWD, regval);
 503
 504         /* Write data byte 2 */
 505         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 |
 506                 ((value >> 16) & 0x000000FF);
 507         cx_write(MC417_RWD, regval);
 508         regval |= MC417_MICS | MC417_MIWR;
 509         cx_write(MC417_RWD, regval);
 510
 511         /* Write data byte 3 */
 512         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 |
 513                 ((value >> 24) & 0x000000FF);
 514         cx_write(MC417_RWD, regval);
 515         regval |= MC417_MICS | MC417_MIWR;
 516         cx_write(MC417_RWD, regval);
 517
 518         /* Write address byte 2 */
 519         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
 520                 MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F);
 521         cx_write(MC417_RWD, regval);
 522         regval |= MC417_MICS | MC417_MIWR;
 523         cx_write(MC417_RWD, regval);
 524
 525         /* Write address byte 1 */
 526         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
 527                 ((address >> 8) & 0xFF);
 528         cx_write(MC417_RWD, regval);
 529         regval |= MC417_MICS | MC417_MIWR;
 530         cx_write(MC417_RWD, regval);
 531
 532         /* Write address byte 0 */
 533         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
 534                 (address & 0xFF);
 535         cx_write(MC417_RWD, regval);
 536         regval |= MC417_MICS | MC417_MIWR;
 537         cx_write(MC417_RWD, regval);
 538
 539         /* Wait for the trans to complete (MC417_MIRDY asserted). */
 540         return mc417_wait_ready(dev);
 541 }
 542
 543 int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value)
 544 {
 545         int retval;
 546         u32 regval;
 547         u32 tempval;
 548         u32 dataval;
 549
 550         /* Enable MC417 GPIO outputs except for MC417_MIRDY,
 551          * which is an input.
 552          */
 553         cx_write(MC417_OEN, MC417_MIRDY);
 554
 555         /* Write address byte 2 */
 556         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
 557                 MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F);
 558         cx_write(MC417_RWD, regval);
 559         regval |= MC417_MICS | MC417_MIWR;
 560         cx_write(MC417_RWD, regval);
 561
 562         /* Write address byte 1 */
 563         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
 564                 ((address >> 8) & 0xFF);
 565         cx_write(MC417_RWD, regval);
 566         regval |= MC417_MICS | MC417_MIWR;
 567         cx_write(MC417_RWD, regval);
 568
 569         /* Write address byte 0 */
 570         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
 571                 (address & 0xFF);
 572         cx_write(MC417_RWD, regval);
 573         regval |= MC417_MICS | MC417_MIWR;
 574         cx_write(MC417_RWD, regval);
 575
 576         /* Wait for the trans to complete (MC417_MIRDY asserted). */
 577         retval = mc417_wait_ready(dev);
 578
 579         /* switch the DAT0-7 GPIO[10:3] to input mode */
 580         cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
 581
 582         /* Read data byte 3 */
 583         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
 584         cx_write(MC417_RWD, regval);
 585
 586         /* Transition RD to effect read transaction across bus. */
 587         regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
 588         cx_write(MC417_RWD, regval);
 589
 590         /* Collect byte */
 591         tempval = cx_read(MC417_RWD);
 592         dataval = ((tempval & 0x000000FF) << 24);
 593
 594         /* Bring CS and RD high. */
 595         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 596         cx_write(MC417_RWD, regval);
 597
 598         /* Read data byte 2 */
 599         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
 600         cx_write(MC417_RWD, regval);
 601         regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
 602         cx_write(MC417_RWD, regval);
 603         tempval = cx_read(MC417_RWD);
 604         dataval |= ((tempval & 0x000000FF) << 16);
 605         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 606         cx_write(MC417_RWD, regval);
 607
 608         /* Read data byte 1 */
 609         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
 610         cx_write(MC417_RWD, regval);
 611         regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
 612         cx_write(MC417_RWD, regval);
 613         tempval = cx_read(MC417_RWD);
 614         dataval |= ((tempval & 0x000000FF) << 8);
 615         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 616         cx_write(MC417_RWD, regval);
 617
 618         /* Read data byte 0 */
 619         regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
 620         cx_write(MC417_RWD, regval);
 621         regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
 622         cx_write(MC417_RWD, regval);
 623         tempval = cx_read(MC417_RWD);
 624         dataval |= (tempval & 0x000000FF);
 625         regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
 626         cx_write(MC417_RWD, regval);
 627
 628         *value  = dataval;
 629
 630         return retval;
 631 }
 632
 633 void mc417_gpio_set(struct cx23885_dev *dev, u32 mask)
 634 {
 635         u32 val;
 636
 637         /* Set the gpio value */
 638         mc417_register_read(dev, 0x900C, &val);
 639         val |= (mask & 0x000ffff);
 640         mc417_register_write(dev, 0x900C, val);
 641 }
 642
 643 void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask)
 644 {
 645         u32 val;
 646
 647         /* Clear the gpio value */
 648         mc417_register_read(dev, 0x900C, &val);
 649         val &= ~(mask & 0x0000ffff);
 650         mc417_register_write(dev, 0x900C, val);
 651 }
 652
 653 void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
 654 {
 655         u32 val;
 656
 657         /* Enable GPIO direction bits */
 658         mc417_register_read(dev, 0x9020, &val);
 659         if (asoutput)
 660                 val |= (mask & 0x0000ffff);
 661         else
 662                 val &= ~(mask & 0x0000ffff);
 663
 664         mc417_register_write(dev, 0x9020, val);
 665 }
 666 /* ------------------------------------------------------------------ */
 667
 668 /* MPEG encoder API */
 669 static char *cmd_to_str(int cmd)
 670 {
 671         switch (cmd) {
 672         case CX2341X_ENC_PING_FW:
 673                 return  "PING_FW";
 674         case CX2341X_ENC_START_CAPTURE:
 675                 return  "START_CAPTURE";
 676         case CX2341X_ENC_STOP_CAPTURE:
 677                 return  "STOP_CAPTURE";
 678         case CX2341X_ENC_SET_AUDIO_ID:
 679                 return  "SET_AUDIO_ID";
 680         case CX2341X_ENC_SET_VIDEO_ID:
 681                 return  "SET_VIDEO_ID";
 682         case CX2341X_ENC_SET_PCR_ID:
 683                 return  "SET_PCR_PID";
 684         case CX2341X_ENC_SET_FRAME_RATE:
 685                 return  "SET_FRAME_RATE";
 686         case CX2341X_ENC_SET_FRAME_SIZE:
 687                 return  "SET_FRAME_SIZE";
 688         case CX2341X_ENC_SET_BIT_RATE:
 689                 return  "SET_BIT_RATE";
 690         case CX2341X_ENC_SET_GOP_PROPERTIES:
 691                 return  "SET_GOP_PROPERTIES";
 692         case CX2341X_ENC_SET_ASPECT_RATIO:
 693                 return  "SET_ASPECT_RATIO";
 694         case CX2341X_ENC_SET_DNR_FILTER_MODE:
 695                 return  "SET_DNR_FILTER_PROPS";
 696         case CX2341X_ENC_SET_DNR_FILTER_PROPS:
 697                 return  "SET_DNR_FILTER_PROPS";
 698         case CX2341X_ENC_SET_CORING_LEVELS:
 699                 return  "SET_CORING_LEVELS";
 700         case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
 701                 return  "SET_SPATIAL_FILTER_TYPE";
 702         case CX2341X_ENC_SET_VBI_LINE:
 703                 return  "SET_VBI_LINE";
 704         case CX2341X_ENC_SET_STREAM_TYPE:
 705                 return  "SET_STREAM_TYPE";
 706         case CX2341X_ENC_SET_OUTPUT_PORT:
 707                 return  "SET_OUTPUT_PORT";
 708         case CX2341X_ENC_SET_AUDIO_PROPERTIES:
 709                 return  "SET_AUDIO_PROPERTIES";
 710         case CX2341X_ENC_HALT_FW:
 711                 return  "HALT_FW";
 712         case CX2341X_ENC_GET_VERSION:
 713                 return  "GET_VERSION";
 714         case CX2341X_ENC_SET_GOP_CLOSURE:
 715                 return  "SET_GOP_CLOSURE";
 716         case CX2341X_ENC_GET_SEQ_END:
 717                 return  "GET_SEQ_END";
 718         case CX2341X_ENC_SET_PGM_INDEX_INFO:
 719                 return  "SET_PGM_INDEX_INFO";
 720         case CX2341X_ENC_SET_VBI_CONFIG:
 721                 return  "SET_VBI_CONFIG";
 722         case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
 723                 return  "SET_DMA_BLOCK_SIZE";
 724         case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
 725                 return  "GET_PREV_DMA_INFO_MB_10";
 726         case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
 727                 return  "GET_PREV_DMA_INFO_MB_9";
 728         case CX2341X_ENC_SCHED_DMA_TO_HOST:
 729                 return  "SCHED_DMA_TO_HOST";
 730         case CX2341X_ENC_INITIALIZE_INPUT:
 731                 return  "INITIALIZE_INPUT";
 732         case CX2341X_ENC_SET_FRAME_DROP_RATE:
 733                 return  "SET_FRAME_DROP_RATE";
 734         case CX2341X_ENC_PAUSE_ENCODER:
 735                 return  "PAUSE_ENCODER";
 736         case CX2341X_ENC_REFRESH_INPUT:
 737                 return  "REFRESH_INPUT";
 738         case CX2341X_ENC_SET_COPYRIGHT:
 739                 return  "SET_COPYRIGHT";
 740         case CX2341X_ENC_SET_EVENT_NOTIFICATION:
 741                 return  "SET_EVENT_NOTIFICATION";
 742         case CX2341X_ENC_SET_NUM_VSYNC_LINES:
 743                 return  "SET_NUM_VSYNC_LINES";
 744         case CX2341X_ENC_SET_PLACEHOLDER:
 745                 return  "SET_PLACEHOLDER";
 746         case CX2341X_ENC_MUTE_VIDEO:
 747                 return  "MUTE_VIDEO";
 748         case CX2341X_ENC_MUTE_AUDIO:
 749                 return  "MUTE_AUDIO";
 750         case CX2341X_ENC_MISC:
 751                 return  "MISC";
 752         default:
 753                 return "UNKNOWN";
 754         }
 755 }
 756
 757 static int cx23885_mbox_func(void *priv,
 758                              u32 command,
 759                              int in,
 760                              int out,
 761                              u32 data[CX2341X_MBOX_MAX_DATA])
 762 {
 763         struct cx23885_dev *dev = priv;
 764         unsigned long timeout;
 765         u32 value, flag, retval = 0;
 766         int i;
 767
 768         dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
 769                 cmd_to_str(command));
 770
 771         /* this may not be 100% safe if we can't read any memory location
 772            without side effects */
 773         mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
 774         if (value != 0x12345678) {
 775                 printk(KERN_ERR
 776                         "Firmware and/or mailbox pointer not initialized "
 777                         "or corrupted, signature = 0x%x, cmd = %s\n", value,
 778                         cmd_to_str(command));
 779                 return -1;
 780         }
 781
 782         /* This read looks at 32 bits, but flag is only 8 bits.
 783          * Seems we also bail if CMD or TIMEOUT bytes are set???
 784          */
 785         mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
 786         if (flag) {
 787                 printk(KERN_ERR "ERROR: Mailbox appears to be in use "
 788                         "(%x), cmd = %s\n", flag, cmd_to_str(command));
 789                 return -1;
 790         }
 791
 792         flag |= 1; /* tell 'em we're working on it */
 793         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 794
 795         /* write command + args + fill remaining with zeros */
 796         /* command code */
 797         mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
 798         mc417_memory_write(dev, dev->cx23417_mailbox + 3,
 799                 IVTV_API_STD_TIMEOUT); /* timeout */
 800         for (i = 0; i < in; i++) {
 801                 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
 802                 dprintk(3, "API Input %d = %d\n", i, data[i]);
 803         }
 804         for (; i < CX2341X_MBOX_MAX_DATA; i++)
 805                 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
 806
 807         flag |= 3; /* tell 'em we're done writing */
 808         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 809
 810         /* wait for firmware to handle the API command */
 811         timeout = jiffies + msecs_to_jiffies(10);
 812         for (;;) {
 813                 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
 814                 if (0 != (flag & 4))
 815                         break;
 816                 if (time_after(jiffies, timeout)) {
 817                         printk(KERN_ERR "ERROR: API Mailbox timeout\n");
 818                         return -1;
 819                 }
 820                 udelay(10);
 821         }
 822
 823         /* read output values */
 824         for (i = 0; i < out; i++) {
 825                 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
 826                 dprintk(3, "API Output %d = %d\n", i, data[i]);
 827         }
 828
 829         mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
 830         dprintk(3, "API result = %d\n", retval);
 831
 832         flag = 0;
 833         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 834
 835         return retval;
 836 }
 837
 838 /* We don't need to call the API often, so using just one
 839  * mailbox will probably suffice
 840  */
 841 static int cx23885_api_cmd(struct cx23885_dev *dev,
 842                            u32 command,
 843                            u32 inputcnt,
 844                            u32 outputcnt,
 845                            ...)
 846 {
 847         u32 data[CX2341X_MBOX_MAX_DATA];
 848         va_list vargs;
 849         int i, err;
 850
 851         dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
 852
 853         va_start(vargs, outputcnt);
 854         for (i = 0; i < inputcnt; i++)
 855                 data[i] = va_arg(vargs, int);
 856
 857         err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data);
 858         for (i = 0; i < outputcnt; i++) {
 859                 int *vptr = va_arg(vargs, int *);
 860                 *vptr = data[i];
 861         }
 862         va_end(vargs);
 863
 864         return err;
 865 }
 866
 867 static int cx23885_find_mailbox(struct cx23885_dev *dev)
 868 {
 869         u32 signature[4] = {
 870                 0x12345678, 0x34567812, 0x56781234, 0x78123456
 871         };
 872         int signaturecnt = 0;
 873         u32 value;
 874         int i;
 875
 876         dprintk(2, "%s()\n", __func__);
 877
 878         for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) {
 879                 mc417_memory_read(dev, i, &value);
 880                 if (value == signature[signaturecnt])
 881                         signaturecnt++;
 882                 else
 883                         signaturecnt = 0;
 884                 if (4 == signaturecnt) {
 885                         dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
 886                         return i+1;
 887                 }
 888         }
 889         printk(KERN_ERR "Mailbox signature values not found!\n");
 890         return -1;
 891 }
 892
 893 static int cx23885_load_firmware(struct cx23885_dev *dev)
 894 {
 895         static const unsigned char magic[8] = {
 896                 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
 897         };
 898         const struct firmware *firmware;
 899         int i, retval = 0;
 900         u32 value = 0;
 901         u32 gpio_output = 0;
 902         u32 checksum = 0;
 903         u32 *dataptr;
 904
 905         dprintk(2, "%s()\n", __func__);
 906
 907         /* Save GPIO settings before reset of APU */
 908         retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
 909         retval |= mc417_memory_read(dev, 0x900C, &value);
 910
 911         retval  = mc417_register_write(dev,
 912                 IVTV_REG_VPU, 0xFFFFFFED);
 913         retval |= mc417_register_write(dev,
 914                 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
 915         retval |= mc417_register_write(dev,
 916                 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
 917         retval |= mc417_register_write(dev,
 918                 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
 919         retval |= mc417_register_write(dev,
 920                 IVTV_REG_APU, 0);
 921
 922         if (retval != 0) {
 923                 printk(KERN_ERR "%s: Error with mc417_register_write\n",
 924                         __func__);
 925                 return -1;
 926         }
 927
 928         retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME,
 929                                   &dev->pci->dev);
 930
 931         if (retval != 0) {
 932                 printk(KERN_ERR
 933                         "ERROR: Hotplug firmware request failed (%s).\n",
 934                         CX23885_FIRM_IMAGE_NAME);
 935                 printk(KERN_ERR "Please fix your hotplug setup, the board will "
 936                         "not work without firmware loaded!\n");
 937                 return -1;
 938         }
 939
 940         if (firmware->size != CX23885_FIRM_IMAGE_SIZE) {
 941                 printk(KERN_ERR "ERROR: Firmware size mismatch "
 942                         "(have %zd, expected %d)\n",
 943                         firmware->size, CX23885_FIRM_IMAGE_SIZE);
 944                 release_firmware(firmware);
 945                 return -1;
 946         }
 947
 948         if (0 != memcmp(firmware->data, magic, 8)) {
 949                 printk(KERN_ERR
 950                         "ERROR: Firmware magic mismatch, wrong file?\n");
 951                 release_firmware(firmware);
 952                 return -1;
 953         }
 954
 955         /* transfer to the chip */
 956         dprintk(2, "Loading firmware ...\n");
 957         dataptr = (u32 *)firmware->data;
 958         for (i = 0; i < (firmware->size >> 2); i++) {
 959                 value = *dataptr;
 960                 checksum += ~value;
 961                 if (mc417_memory_write(dev, i, value) != 0) {
 962                         printk(KERN_ERR "ERROR: Loading firmware failed!\n");
 963                         release_firmware(firmware);
 964                         return -1;
 965                 }
 966                 dataptr++;
 967         }
 968
 969         /* read back to verify with the checksum */
 970         dprintk(1, "Verifying firmware ...\n");
 971         for (i--; i >= 0; i--) {
 972                 if (mc417_memory_read(dev, i, &value) != 0) {
 973                         printk(KERN_ERR "ERROR: Reading firmware failed!\n");
 974                         release_firmware(firmware);
 975                         return -1;
 976                 }
 977                 checksum -= ~value;
 978         }
 979         if (checksum) {
 980                 printk(KERN_ERR
 981                         "ERROR: Firmware load failed (checksum mismatch).\n");
 982                 release_firmware(firmware);
 983                 return -1;
 984         }
 985         release_firmware(firmware);
 986         dprintk(1, "Firmware upload successful.\n");
 987
 988         retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
 989                 IVTV_CMD_HW_BLOCKS_RST);
 990
 991         /* F/W power up disturbs the GPIOs, restore state */
 992         retval |= mc417_register_write(dev, 0x9020, gpio_output);
 993         retval |= mc417_register_write(dev, 0x900C, value);
 994
 995         retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
 996         retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
 997
 998         if (retval < 0)
 999                 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1000                         __func__);
1001         return 0;
1002 }
1003
1004 void cx23885_417_check_encoder(struct cx23885_dev *dev)
1005 {
1006         u32 status, seq;
1007
1008         status = seq = 0;
1009         cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1010         dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1011 }
1012
1013 static void cx23885_codec_settings(struct cx23885_dev *dev)
1014 {
1015         dprintk(1, "%s()\n", __func__);
1016
1017         /* assign frame size */
1018         cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1019                                 dev->ts1.height, dev->ts1.width);
1020
1021         dev->mpeg_params.width = dev->ts1.width;
1022         dev->mpeg_params.height = dev->ts1.height;
1023         dev->mpeg_params.is_50hz =
1024                 (dev->encodernorm.id & V4L2_STD_625_50) != 0;
1025
1026         cx2341x_update(dev, cx23885_mbox_func, NULL, &dev->mpeg_params);
1027
1028         cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1029         cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1030 }
1031
1032 static int cx23885_initialize_codec(struct cx23885_dev *dev)
1033 {
1034         int version;
1035         int retval;
1036         u32 i, data[7];
1037
1038         dprintk(1, "%s()\n", __func__);
1039
1040         retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1041         if (retval < 0) {
1042                 dprintk(2, "%s() PING OK\n", __func__);
1043                 retval = cx23885_load_firmware(dev);
1044                 if (retval < 0) {
1045                         printk(KERN_ERR "%s() f/w load failed\n", __func__);
1046                         return retval;
1047                 }
1048                 retval = cx23885_find_mailbox(dev);
1049                 if (retval < 0) {
1050                         printk(KERN_ERR "%s() mailbox < 0, error\n",
1051                                 __func__);
1052                         return -1;
1053                 }
1054                 dev->cx23417_mailbox = retval;
1055                 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1056                 if (retval < 0) {
1057                         printk(KERN_ERR
1058                                 "ERROR: cx23417 firmware ping failed!\n");
1059                         return -1;
1060                 }
1061                 retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1062                         &version);
1063                 if (retval < 0) {
1064                         printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
1065                                 "version failed!\n");
1066                         return -1;
1067                 }
1068                 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1069                 msleep(200);
1070         }
1071
1072         cx23885_codec_settings(dev);
1073         msleep(60);
1074
1075         cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1076                 CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115);
1077         cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1078                 CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1079                 0, 0);
1080
1081         /* Setup to capture VBI */
1082         data[0] = 0x0001BD00;
1083         data[1] = 1;          /* frames per interrupt */
1084         data[2] = 4;          /* total bufs */
1085         data[3] = 0x91559155; /* start codes */
1086         data[4] = 0x206080C0; /* stop codes */
1087         data[5] = 6;          /* lines */
1088         data[6] = 64;         /* BPL */
1089
1090         cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1091                 data[2], data[3], data[4], data[5], data[6]);
1092
1093         for (i = 2; i <= 24; i++) {
1094                 int valid;
1095
1096                 valid = ((i >= 19) && (i <= 21));
1097                 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1098                                 valid, 0 , 0, 0);
1099                 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1100                                 i | 0x80000000, valid, 0, 0, 0);
1101         }
1102
1103         cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE);
1104         msleep(60);
1105
1106         /* initialize the video input */
1107         cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1108         msleep(60);
1109
1110         /* Enable VIP style pixel invalidation so we work with scaled mode */
1111         mc417_memory_write(dev, 2120, 0x00000080);
1112
1113         /* start capturing to the host interface */
1114         cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1115                 CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE);
1116         msleep(10);
1117
1118         return 0;
1119 }
1120
1121 /* ------------------------------------------------------------------ */
1122
1123 static int bb_buf_setup(struct videobuf_queue *q,
1124         unsigned int *count, unsigned int *size)
1125 {
1126         struct cx23885_fh *fh = q->priv_data;
1127
1128         fh->dev->ts1.ts_packet_size  = mpeglinesize;
1129         fh->dev->ts1.ts_packet_count = mpeglines;
1130
1131         *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1132         *count = mpegbufs;
1133
1134         return 0;
1135 }
1136
1137 static int bb_buf_prepare(struct videobuf_queue *q,
1138         struct videobuf_buffer *vb, enum v4l2_field field)
1139 {
1140         struct cx23885_fh *fh = q->priv_data;
1141         return cx23885_buf_prepare(q, &fh->dev->ts1,
1142                 (struct cx23885_buffer *)vb,
1143                 field);
1144 }
1145
1146 static void bb_buf_queue(struct videobuf_queue *q,
1147         struct videobuf_buffer *vb)
1148 {
1149         struct cx23885_fh *fh = q->priv_data;
1150         cx23885_buf_queue(&fh->dev->ts1, (struct cx23885_buffer *)vb);
1151 }
1152
1153 static void bb_buf_release(struct videobuf_queue *q,
1154         struct videobuf_buffer *vb)
1155 {
1156         cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
1157 }
1158
1159 static struct videobuf_queue_ops cx23885_qops = {
1160         .buf_setup    = bb_buf_setup,
1161         .buf_prepare  = bb_buf_prepare,
1162         .buf_queue    = bb_buf_queue,
1163         .buf_release  = bb_buf_release,
1164 };
1165
1166 /* ------------------------------------------------------------------ */
1167
1168 static const u32 *ctrl_classes[] = {
1169         cx2341x_mpeg_ctrls,
1170         NULL
1171 };
1172
1173 static int cx23885_queryctrl(struct cx23885_dev *dev,
1174         struct v4l2_queryctrl *qctrl)
1175 {
1176         qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
1177         if (qctrl->id == 0)
1178                 return -EINVAL;
1179
1180         /* MPEG V4L2 controls */
1181         if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
1182                 qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
1183
1184         return 0;
1185 }
1186
1187 static int cx23885_querymenu(struct cx23885_dev *dev,
1188         struct v4l2_querymenu *qmenu)
1189 {
1190         struct v4l2_queryctrl qctrl;
1191
1192         qctrl.id = qmenu->id;
1193         cx23885_queryctrl(dev, &qctrl);
1194         return v4l2_ctrl_query_menu(qmenu, &qctrl,
1195                 cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
1196 }
1197
1198 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
1199 {
1200         struct cx23885_fh  *fh  = file->private_data;
1201         struct cx23885_dev *dev = fh->dev;
1202         unsigned int i;
1203
1204         for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++)
1205                 if (*id & cx23885_tvnorms[i].id)
1206                         break;
1207         if (i == ARRAY_SIZE(cx23885_tvnorms))
1208                 return -EINVAL;
1209         dev->encodernorm = cx23885_tvnorms[i];
1210         return 0;
1211 }
1212
1213 static int vidioc_enum_input(struct file *file, void *priv,
1214                                 struct v4l2_input *i)
1215 {
1216         struct cx23885_fh  *fh  = file->private_data;
1217         struct cx23885_dev *dev = fh->dev;
1218         struct cx23885_input *input;
1219         int n;
1220
1221         if (i->index >= 4)
1222                 return -EINVAL;
1223
1224         input = &cx23885_boards[dev->board].input[i->index];
1225
1226         if (input->type == 0)
1227                 return -EINVAL;
1228
1229         /* FIXME
1230          * strcpy(i->name, input->name); */
1231         strcpy(i->name, "unset");
1232
1233         if (input->type == CX23885_VMUX_TELEVISION ||
1234             input->type == CX23885_VMUX_CABLE)
1235                 i->type = V4L2_INPUT_TYPE_TUNER;
1236         else
1237                 i->type  = V4L2_INPUT_TYPE_CAMERA;
1238
1239         for (n = 0; n < ARRAY_SIZE(cx23885_tvnorms); n++)
1240                 i->std |= cx23885_tvnorms[n].id;
1241         return 0;
1242 }
1243
1244 static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1245 {
1246         struct cx23885_fh  *fh  = file->private_data;
1247         struct cx23885_dev *dev = fh->dev;
1248
1249         *i = dev->input;
1250         return 0;
1251 }
1252
1253 static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1254 {
1255         if (i >= 4)
1256                 return -EINVAL;
1257
1258         return 0;
1259 }
1260
1261 static int vidioc_g_tuner(struct file *file, void *priv,
1262                                 struct v4l2_tuner *t)
1263 {
1264         struct cx23885_fh  *fh  = file->private_data;
1265         struct cx23885_dev *dev = fh->dev;
1266
1267         if (UNSET == dev->tuner_type)
1268                 return -EINVAL;
1269         if (0 != t->index)
1270                 return -EINVAL;
1271         strcpy(t->name, "Television");
1272         call_all(dev, tuner, g_tuner, t);
1273
1274         dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type);
1275
1276         return 0;
1277 }
1278
1279 static int vidioc_s_tuner(struct file *file, void *priv,
1280                                 struct v4l2_tuner *t)
1281 {
1282         struct cx23885_fh  *fh  = file->private_data;
1283         struct cx23885_dev *dev = fh->dev;
1284
1285         if (UNSET == dev->tuner_type)
1286                 return -EINVAL;
1287
1288         /* Update the A/V core */
1289         call_all(dev, tuner, s_tuner, t);
1290
1291         return 0;
1292 }
1293
1294 static int vidioc_g_frequency(struct file *file, void *priv,
1295                                 struct v4l2_frequency *f)
1296 {
1297         struct cx23885_fh  *fh  = file->private_data;
1298         struct cx23885_dev *dev = fh->dev;
1299
1300         if (UNSET == dev->tuner_type)
1301                 return -EINVAL;
1302         f->type = V4L2_TUNER_ANALOG_TV;
1303         f->frequency = dev->freq;
1304
1305         call_all(dev, tuner, g_frequency, f);
1306
1307         return 0;
1308 }
1309
1310 static int vidioc_s_frequency(struct file *file, void *priv,
1311                                 struct v4l2_frequency *f)
1312 {
1313         struct cx23885_fh  *fh  = file->private_data;
1314         struct cx23885_dev *dev = fh->dev;
1315
1316         cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1317                 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1318                 CX23885_RAW_BITS_NONE);
1319
1320         dprintk(1, "VIDIOC_S_FREQUENCY: dev type %d, f\n",
1321                 dev->tuner_type);
1322         dprintk(1, "VIDIOC_S_FREQUENCY: f tuner %d, f type %d\n",
1323                 f->tuner, f->type);
1324         if (UNSET == dev->tuner_type)
1325                 return -EINVAL;
1326         if (f->tuner != 0)
1327                 return -EINVAL;
1328         if (f->type != V4L2_TUNER_ANALOG_TV)
1329                 return -EINVAL;
1330         dev->freq = f->frequency;
1331
1332         call_all(dev, tuner, s_frequency, f);
1333
1334         cx23885_initialize_codec(dev);
1335
1336         return 0;
1337 }
1338
1339 static int vidioc_s_ctrl(struct file *file, void *priv,
1340                                 struct v4l2_control *ctl)
1341 {
1342         struct cx23885_fh  *fh  = file->private_data;
1343         struct cx23885_dev *dev = fh->dev;
1344
1345         /* Update the A/V core */
1346         call_all(dev, core, s_ctrl, ctl);
1347         return 0;
1348 }
1349
1350 static int vidioc_querycap(struct file *file, void  *priv,
1351                                 struct v4l2_capability *cap)
1352 {
1353         struct cx23885_fh  *fh  = file->private_data;
1354         struct cx23885_dev *dev = fh->dev;
1355         struct cx23885_tsport  *tsport = &dev->ts1;
1356
1357         strcpy(cap->driver, dev->name);
1358         strlcpy(cap->card, cx23885_boards[tsport->dev->board].name,
1359                 sizeof(cap->card));
1360         sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
1361         cap->version = CX23885_VERSION_CODE;
1362         cap->capabilities =
1363                 V4L2_CAP_VIDEO_CAPTURE |
1364                 V4L2_CAP_READWRITE     |
1365                 V4L2_CAP_STREAMING     |
1366                 0;
1367         if (UNSET != dev->tuner_type)
1368                 cap->capabilities |= V4L2_CAP_TUNER;
1369
1370         return 0;
1371 }
1372
1373 static int vidioc_enum_fmt_vid_cap(struct file *file, void  *priv,
1374                                         struct v4l2_fmtdesc *f)
1375 {
1376         if (f->index != 0)
1377                 return -EINVAL;
1378
1379         strlcpy(f->description, "MPEG", sizeof(f->description));
1380         f->pixelformat = V4L2_PIX_FMT_MPEG;
1381
1382         return 0;
1383 }
1384
1385 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1386                                 struct v4l2_format *f)
1387 {
1388         struct cx23885_fh  *fh  = file->private_data;
1389         struct cx23885_dev *dev = fh->dev;
1390
1391         f->fmt.pix.pixelformat  = V4L2_PIX_FMT_MPEG;
1392         f->fmt.pix.bytesperline = 0;
1393         f->fmt.pix.sizeimage    =
1394                 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1395         f->fmt.pix.colorspace   = 0;
1396         f->fmt.pix.width        = dev->ts1.width;
1397         f->fmt.pix.height       = dev->ts1.height;
1398         f->fmt.pix.field        = fh->mpegq.field;
1399         dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1400                 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1401         return 0;
1402 }
1403
1404 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1405                                 struct v4l2_format *f)
1406 {
1407         struct cx23885_fh  *fh  = file->private_data;
1408         struct cx23885_dev *dev = fh->dev;
1409
1410         f->fmt.pix.pixelformat  = V4L2_PIX_FMT_MPEG;
1411         f->fmt.pix.bytesperline = 0;
1412         f->fmt.pix.sizeimage    =
1413                 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1414         f->fmt.pix.colorspace   = 0;
1415         dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1416                 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1417         return 0;
1418 }
1419
1420 static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
1421                                 struct v4l2_format *f)
1422 {
1423         struct cx23885_fh  *fh  = file->private_data;
1424         struct cx23885_dev *dev = fh->dev;
1425
1426         f->fmt.pix.pixelformat  = V4L2_PIX_FMT_MPEG;
1427         f->fmt.pix.bytesperline = 0;
1428         f->fmt.pix.sizeimage    =
1429                 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1430         f->fmt.pix.colorspace   = 0;
1431         dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n",
1432                 f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field);
1433         return 0;
1434 }
1435
1436 static int vidioc_reqbufs(struct file *file, void *priv,
1437                                 struct v4l2_requestbuffers *p)
1438 {
1439         struct cx23885_fh  *fh  = file->private_data;
1440
1441         return videobuf_reqbufs(&fh->mpegq, p);
1442 }
1443
1444 static int vidioc_querybuf(struct file *file, void *priv,
1445                                 struct v4l2_buffer *p)
1446 {
1447         struct cx23885_fh  *fh  = file->private_data;
1448
1449         return videobuf_querybuf(&fh->mpegq, p);
1450 }
1451
1452 static int vidioc_qbuf(struct file *file, void *priv,
1453                                 struct v4l2_buffer *p)
1454 {
1455         struct cx23885_fh  *fh  = file->private_data;
1456
1457         return videobuf_qbuf(&fh->mpegq, p);
1458 }
1459
1460 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1461 {
1462         struct cx23885_fh  *fh  = priv;
1463
1464         return videobuf_dqbuf(&fh->mpegq, b, file->f_flags & O_NONBLOCK);
1465 }
1466
1467
1468 static int vidioc_streamon(struct file *file, void *priv,
1469                                 enum v4l2_buf_type i)
1470 {
1471         struct cx23885_fh  *fh  = file->private_data;
1472
1473         return videobuf_streamon(&fh->mpegq);
1474 }
1475
1476 static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1477 {
1478         struct cx23885_fh  *fh  = file->private_data;
1479
1480         return videobuf_streamoff(&fh->mpegq);
1481 }
1482
1483 static int vidioc_g_ext_ctrls(struct file *file, void *priv,
1484                                 struct v4l2_ext_controls *f)
1485 {
1486         struct cx23885_fh  *fh  = priv;
1487         struct cx23885_dev *dev = fh->dev;
1488
1489         if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1490                 return -EINVAL;
1491         return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
1492 }
1493
1494 static int vidioc_s_ext_ctrls(struct file *file, void *priv,
1495                                 struct v4l2_ext_controls *f)
1496 {
1497         struct cx23885_fh  *fh  = priv;
1498         struct cx23885_dev *dev = fh->dev;
1499         struct cx2341x_mpeg_params p;
1500         int err;
1501
1502         if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1503                 return -EINVAL;
1504
1505         p = dev->mpeg_params;
1506         err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_S_EXT_CTRLS);
1507
1508         if (err == 0) {
1509                 err = cx2341x_update(dev, cx23885_mbox_func,
1510                         &dev->mpeg_params, &p);
1511                 dev->mpeg_params = p;
1512         }
1513         return err;
1514 }
1515
1516 static int vidioc_try_ext_ctrls(struct file *file, void *priv,
1517                                 struct v4l2_ext_controls *f)
1518 {
1519         struct cx23885_fh  *fh  = priv;
1520         struct cx23885_dev *dev = fh->dev;
1521         struct cx2341x_mpeg_params p;
1522         int err;
1523
1524         if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1525                 return -EINVAL;
1526
1527         p = dev->mpeg_params;
1528         err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1529         return err;
1530 }
1531
1532 static int vidioc_log_status(struct file *file, void *priv)
1533 {
1534         struct cx23885_fh  *fh  = priv;
1535         struct cx23885_dev *dev = fh->dev;
1536         char name[32 + 2];
1537
1538         snprintf(name, sizeof(name), "%s/2", dev->name);
1539         printk(KERN_INFO
1540                 "%s/2: ============  START LOG STATUS  ============\n",
1541                dev->name);
1542         call_all(dev, core, log_status);
1543         cx2341x_log_status(&dev->mpeg_params, name);
1544         printk(KERN_INFO
1545                 "%s/2: =============  END LOG STATUS  =============\n",
1546                dev->name);
1547         return 0;
1548 }
1549
1550 static int vidioc_querymenu(struct file *file, void *priv,
1551                                 struct v4l2_querymenu *a)
1552 {
1553         struct cx23885_fh  *fh  = priv;
1554         struct cx23885_dev *dev = fh->dev;
1555
1556         return cx23885_querymenu(dev, a);
1557 }
1558
1559 static int vidioc_queryctrl(struct file *file, void *priv,
1560                                 struct v4l2_queryctrl *c)
1561 {
1562         struct cx23885_fh  *fh  = priv;
1563         struct cx23885_dev *dev = fh->dev;
1564
1565         return cx23885_queryctrl(dev, c);
1566 }
1567
1568 static int mpeg_open(struct file *file)
1569 {
1570         int minor = video_devdata(file)->minor;
1571         struct cx23885_dev *h, *dev = NULL;
1572         struct list_head *list;
1573         struct cx23885_fh *fh;
1574
1575         dprintk(2, "%s()\n", __func__);
1576
1577         lock_kernel();
1578         list_for_each(list, &cx23885_devlist) {
1579                 h = list_entry(list, struct cx23885_dev, devlist);
1580                 if (h->v4l_device &&
1581                     h->v4l_device->minor == minor) {
1582                         dev = h;
1583                         break;
1584                 }
1585         }
1586
1587         if (dev == NULL) {
1588                 unlock_kernel();
1589                 return -ENODEV;
1590         }
1591
1592         /* allocate + initialize per filehandle data */
1593         fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1594         if (NULL == fh) {
1595                 unlock_kernel();
1596                 return -ENOMEM;
1597         }
1598
1599         file->private_data = fh;
1600         fh->dev      = dev;
1601
1602         videobuf_queue_sg_init(&fh->mpegq, &cx23885_qops,
1603                             &dev->pci->dev, &dev->ts1.slock,
1604                             V4L2_BUF_TYPE_VIDEO_CAPTURE,
1605                             V4L2_FIELD_INTERLACED,
1606                             sizeof(struct cx23885_buffer),
1607                             fh);
1608         unlock_kernel();
1609
1610         return 0;
1611 }
1612
1613 static int mpeg_release(struct file *file)
1614 {
1615         struct cx23885_fh  *fh  = file->private_data;
1616         struct cx23885_dev *dev = fh->dev;
1617
1618         dprintk(2, "%s()\n", __func__);
1619
1620         /* FIXME: Review this crap */
1621         /* Shut device down on last close */
1622         if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
1623                 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
1624                         /* stop mpeg capture */
1625                         cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1626                                 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1627                                 CX23885_RAW_BITS_NONE);
1628
1629                         msleep(500);
1630                         cx23885_417_check_encoder(dev);
1631
1632                         cx23885_cancel_buffers(&fh->dev->ts1);
1633                 }
1634         }
1635
1636         if (fh->mpegq.streaming)
1637                 videobuf_streamoff(&fh->mpegq);
1638         if (fh->mpegq.reading)
1639                 videobuf_read_stop(&fh->mpegq);
1640
1641         videobuf_mmap_free(&fh->mpegq);
1642         file->private_data = NULL;
1643         kfree(fh);
1644
1645         return 0;
1646 }
1647
1648 static ssize_t mpeg_read(struct file *file, char __user *data,
1649         size_t count, loff_t *ppos)
1650 {
1651         struct cx23885_fh *fh = file->private_data;
1652         struct cx23885_dev *dev = fh->dev;
1653
1654         dprintk(2, "%s()\n", __func__);
1655
1656         /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
1657         /* Start mpeg encoder on first read. */
1658         if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
1659                 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
1660                         if (cx23885_initialize_codec(dev) < 0)
1661                                 return -EINVAL;
1662                 }
1663         }
1664
1665         return videobuf_read_stream(&fh->mpegq, data, count, ppos, 0,
1666                                     file->f_flags & O_NONBLOCK);
1667 }
1668
1669 static unsigned int mpeg_poll(struct file *file,
1670         struct poll_table_struct *wait)
1671 {
1672         struct cx23885_fh *fh = file->private_data;
1673         struct cx23885_dev *dev = fh->dev;
1674
1675         dprintk(2, "%s\n", __func__);
1676
1677         return videobuf_poll_stream(file, &fh->mpegq, wait);
1678 }
1679
1680 static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
1681 {
1682         struct cx23885_fh *fh = file->private_data;
1683         struct cx23885_dev *dev = fh->dev;
1684
1685         dprintk(2, "%s()\n", __func__);
1686
1687         return videobuf_mmap_mapper(&fh->mpegq, vma);
1688 }
1689
1690 static struct v4l2_file_operations mpeg_fops = {
1691         .owner         = THIS_MODULE,
1692         .open          = mpeg_open,
1693         .release       = mpeg_release,
1694         .read          = mpeg_read,
1695         .poll          = mpeg_poll,
1696         .mmap          = mpeg_mmap,
1697         .ioctl         = video_ioctl2,
1698 };
1699
1700 static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
1701         .vidioc_s_std            = vidioc_s_std,
1702         .vidioc_enum_input       = vidioc_enum_input,
1703         .vidioc_g_input          = vidioc_g_input,
1704         .vidioc_s_input          = vidioc_s_input,
1705         .vidioc_g_tuner          = vidioc_g_tuner,
1706         .vidioc_s_tuner          = vidioc_s_tuner,
1707         .vidioc_g_frequency      = vidioc_g_frequency,
1708         .vidioc_s_frequency      = vidioc_s_frequency,
1709         .vidioc_s_ctrl           = vidioc_s_ctrl,
1710         .vidioc_querycap         = vidioc_querycap,
1711         .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1712         .vidioc_g_fmt_vid_cap    = vidioc_g_fmt_vid_cap,
1713         .vidioc_try_fmt_vid_cap  = vidioc_try_fmt_vid_cap,
1714         .vidioc_s_fmt_vid_cap    = vidioc_s_fmt_vid_cap,
1715         .vidioc_reqbufs          = vidioc_reqbufs,
1716         .vidioc_querybuf         = vidioc_querybuf,
1717         .vidioc_qbuf             = vidioc_qbuf,
1718         .vidioc_dqbuf            = vidioc_dqbuf,
1719         .vidioc_streamon         = vidioc_streamon,
1720         .vidioc_streamoff        = vidioc_streamoff,
1721         .vidioc_g_ext_ctrls      = vidioc_g_ext_ctrls,
1722         .vidioc_s_ext_ctrls      = vidioc_s_ext_ctrls,
1723         .vidioc_try_ext_ctrls    = vidioc_try_ext_ctrls,
1724         .vidioc_log_status       = vidioc_log_status,
1725         .vidioc_querymenu        = vidioc_querymenu,
1726         .vidioc_queryctrl        = vidioc_queryctrl,
1727 };
1728
1729 static struct video_device cx23885_mpeg_template = {
1730         .name          = "cx23885",
1731         .fops          = &mpeg_fops,
1732         .ioctl_ops     = &mpeg_ioctl_ops,
1733         .minor         = -1,
1734         .tvnorms       = CX23885_NORMS,
1735         .current_norm  = V4L2_STD_NTSC_M,
1736 };
1737
1738 void cx23885_417_unregister(struct cx23885_dev *dev)
1739 {
1740         dprintk(1, "%s()\n", __func__);
1741
1742         if (dev->v4l_device) {
1743                 if (-1 != dev->v4l_device->minor)
1744                         video_unregister_device(dev->v4l_device);
1745                 else
1746                         video_device_release(dev->v4l_device);
1747                 dev->v4l_device = NULL;
1748         }
1749 }
1750
1751 static struct video_device *cx23885_video_dev_alloc(
1752         struct cx23885_tsport *tsport,
1753         struct pci_dev *pci,
1754         struct video_device *template,
1755         char *type)
1756 {
1757         struct video_device *vfd;
1758         struct cx23885_dev *dev = tsport->dev;
1759
1760         dprintk(1, "%s()\n", __func__);
1761
1762         vfd = video_device_alloc();
1763         if (NULL == vfd)
1764                 return NULL;
1765         *vfd = *template;
1766         snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
1767                 type, cx23885_boards[tsport->dev->board].name);
1768         vfd->parent  = &pci->dev;
1769         vfd->release = video_device_release;
1770         return vfd;
1771 }
1772
1773 int cx23885_417_register(struct cx23885_dev *dev)
1774 {
1775         /* FIXME: Port1 hardcoded here */
1776         int err = -ENODEV;
1777         struct cx23885_tsport *tsport = &dev->ts1;
1778
1779         dprintk(1, "%s()\n", __func__);
1780
1781         if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER)
1782                 return err;
1783
1784         /* Set default TV standard */
1785         dev->encodernorm = cx23885_tvnorms[0];
1786
1787         if (dev->encodernorm.id & V4L2_STD_525_60)
1788                 tsport->height = 480;
1789         else
1790                 tsport->height = 576;
1791
1792         tsport->width = 720;
1793         cx2341x_fill_defaults(&dev->mpeg_params);
1794
1795         dev->mpeg_params.port = CX2341X_PORT_SERIAL;
1796
1797         /* Allocate and initialize V4L video device */
1798         dev->v4l_device = cx23885_video_dev_alloc(tsport,
1799                 dev->pci, &cx23885_mpeg_template, "mpeg");
1800         err = video_register_device(dev->v4l_device,
1801                 VFL_TYPE_GRABBER, -1);
1802         if (err < 0) {
1803                 printk(KERN_INFO "%s: can't register mpeg device\n", dev->name);
1804                 return err;
1805         }
1806
1807         printk(KERN_INFO "%s: registered device video%d [mpeg]\n",
1808                dev->name, dev->v4l_device->num);
1809
1810         return 0;
1811 }