drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34
  35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
  37 MODULE_LICENSE("GPL");
  38
  39 static unsigned int debug = 0;
  40 module_param(debug,int,0644);
  41 MODULE_PARM_DESC(debug,"enable debug messages");
  42
  43 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  44 module_param_array(card,  int, NULL, 0444);
  45 MODULE_PARM_DESC(card,"card type");
  46
  47 #define dprintk(level,fmt, arg...)      if (debug >= level) \
  48         printk(KERN_DEBUG "%s/0: " fmt, dev->name , ## arg)
  49
  50 static unsigned int cx23885_devcount;
  51
  52 static DEFINE_MUTEX(devlist);
  53 static LIST_HEAD(cx23885_devlist);
  54
  55 #define NO_SYNC_LINE (-1U)
  56
  57 /*
  58  * CX23885 Assumptions
  59  * 1 line = 16 bytes of CDT
  60  * cmds size = 80
  61  * cdt size = 16 * linesize
  62  * iqsize = 64
  63  * maxlines = 6
  64  *
  65  * Address Space:
  66  * 0x00000000 0x00008fff FIFO clusters
  67  * 0x00010000 0x000104af Channel Management Data Structures
  68  * 0x000104b0 0x000104ff Free
  69  * 0x00010500 0x000108bf 15 channels * iqsize
  70  * 0x000108c0 0x000108ff Free
  71  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  72  *                       15 channels * (iqsize + (maxlines * linesize))
  73  * 0x00010ea0 0x00010xxx Free
  74  */
  75
  76 struct sram_channel cx23885_sram_channels[] = {
  77         [SRAM_CH01] = {
  78                 .name           = "test ch1",
  79                 .cmds_start     = 0x10000,
  80                 .ctrl_start     = 0x10500,
  81                 .cdt            = 0x10900,
  82                 .fifo_start     = 0x3000,
  83                 .fifo_size      = 0x1000,
  84                 .ptr1_reg       = DMA1_PTR1,
  85                 .ptr2_reg       = DMA1_PTR2,
  86                 .cnt1_reg       = DMA1_CNT1,
  87                 .cnt2_reg       = DMA1_CNT2,
  88                 .jumponly       = 1,
  89         },
  90         [SRAM_CH02] = {
  91                 .name           = "ch2",
  92                 .cmds_start     = 0x0,
  93                 .ctrl_start     = 0x0,
  94                 .cdt            = 0x0,
  95                 .fifo_start     = 0x0,
  96                 .fifo_size      = 0x0,
  97                 .ptr1_reg       = DMA2_PTR1,
  98                 .ptr2_reg       = DMA2_PTR2,
  99                 .cnt1_reg       = DMA2_CNT1,
 100                 .cnt2_reg       = DMA2_CNT2,
 101         },
 102         [SRAM_CH03] = {
 103                 .name           = "ch3",
 104                 .cmds_start     = 0x0,
 105                 .ctrl_start     = 0x0,
 106                 .cdt            = 0x0,
 107                 .fifo_start     = 0x0,
 108                 .fifo_size      = 0x0,
 109                 .ptr1_reg       = DMA3_PTR1,
 110                 .ptr2_reg       = DMA3_PTR2,
 111                 .cnt1_reg       = DMA3_CNT1,
 112                 .cnt2_reg       = DMA3_CNT2,
 113         },
 114         [SRAM_CH04] = {
 115                 .name           = "ch4",
 116                 .cmds_start     = 0x0,
 117                 .ctrl_start     = 0x0,
 118                 .cdt            = 0x0,
 119                 .fifo_start     = 0x0,
 120                 .fifo_size      = 0x0,
 121                 .ptr1_reg       = DMA4_PTR1,
 122                 .ptr2_reg       = DMA4_PTR2,
 123                 .cnt1_reg       = DMA4_CNT1,
 124                 .cnt2_reg       = DMA4_CNT2,
 125         },
 126         [SRAM_CH05] = {
 127                 .name           = "ch5",
 128                 .cmds_start     = 0x0,
 129                 .ctrl_start     = 0x0,
 130                 .cdt            = 0x0,
 131                 .fifo_start     = 0x0,
 132                 .fifo_size      = 0x0,
 133                 .ptr1_reg       = DMA5_PTR1,
 134                 .ptr2_reg       = DMA5_PTR2,
 135                 .cnt1_reg       = DMA5_CNT1,
 136                 .cnt2_reg       = DMA5_CNT2,
 137         },
 138         [SRAM_CH06] = {
 139                 .name           = "TS2 C",
 140                 .cmds_start     = 0x10140,
 141                 .ctrl_start     = 0x10680,
 142                 .cdt            = 0x10480,
 143                 .fifo_start     = 0x6000,
 144                 .fifo_size      = 0x1000,
 145                 .ptr1_reg       = DMA5_PTR1,
 146                 .ptr2_reg       = DMA5_PTR2,
 147                 .cnt1_reg       = DMA5_CNT1,
 148                 .cnt2_reg       = DMA5_CNT2,
 149         },
 150         [SRAM_CH07] = {
 151                 .name           = "ch7",
 152                 .cmds_start     = 0x0,
 153                 .ctrl_start     = 0x0,
 154                 .cdt            = 0x0,
 155                 .fifo_start     = 0x0,
 156                 .fifo_size      = 0x0,
 157                 .ptr1_reg       = DMA6_PTR1,
 158                 .ptr2_reg       = DMA6_PTR2,
 159                 .cnt1_reg       = DMA6_CNT1,
 160                 .cnt2_reg       = DMA6_CNT2,
 161         },
 162         [SRAM_CH08] = {
 163                 .name           = "ch8",
 164                 .cmds_start     = 0x0,
 165                 .ctrl_start     = 0x0,
 166                 .cdt            = 0x0,
 167                 .fifo_start     = 0x0,
 168                 .fifo_size      = 0x0,
 169                 .ptr1_reg       = DMA7_PTR1,
 170                 .ptr2_reg       = DMA7_PTR2,
 171                 .cnt1_reg       = DMA7_CNT1,
 172                 .cnt2_reg       = DMA7_CNT2,
 173         },
 174         [SRAM_CH09] = {
 175                 .name           = "ch9",
 176                 .cmds_start     = 0x0,
 177                 .ctrl_start     = 0x0,
 178                 .cdt            = 0x0,
 179                 .fifo_start     = 0x0,
 180                 .fifo_size      = 0x0,
 181                 .ptr1_reg       = DMA8_PTR1,
 182                 .ptr2_reg       = DMA8_PTR2,
 183                 .cnt1_reg       = DMA8_CNT1,
 184                 .cnt2_reg       = DMA8_CNT2,
 185         },
 186 };
 187
 188 /* FIXME, these allocations will change when
 189  * analog arrives. The be reviewed.
 190  * CX23887 Assumptions
 191  * 1 line = 16 bytes of CDT
 192  * cmds size = 80
 193  * cdt size = 16 * linesize
 194  * iqsize = 64
 195  * maxlines = 6
 196  *
 197  * Address Space:
 198  * 0x00000000 0x00008fff FIFO clusters
 199  * 0x00010000 0x000104af Channel Management Data Structures
 200  * 0x000104b0 0x000104ff Free
 201  * 0x00010500 0x000108bf 15 channels * iqsize
 202  * 0x000108c0 0x000108ff Free
 203  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
 204  *                       15 channels * (iqsize + (maxlines * linesize))
 205  * 0x00010ea0 0x00010xxx Free
 206  */
 207
 208 struct sram_channel cx23887_sram_channels[] = {
 209         [SRAM_CH01] = {
 210                 .name           = "test ch1",
 211                 .cmds_start     = 0x0,
 212                 .ctrl_start     = 0x0,
 213                 .cdt            = 0x0,
 214                 .fifo_start     = 0x0,
 215                 .fifo_size      = 0x0,
 216                 .ptr1_reg       = DMA1_PTR1,
 217                 .ptr2_reg       = DMA1_PTR2,
 218                 .cnt1_reg       = DMA1_CNT1,
 219                 .cnt2_reg       = DMA1_CNT2,
 220         },
 221         [SRAM_CH02] = {
 222                 .name           = "ch2",
 223                 .cmds_start     = 0x0,
 224                 .ctrl_start     = 0x0,
 225                 .cdt            = 0x0,
 226                 .fifo_start     = 0x0,
 227                 .fifo_size      = 0x0,
 228                 .ptr1_reg       = DMA2_PTR1,
 229                 .ptr2_reg       = DMA2_PTR2,
 230                 .cnt1_reg       = DMA2_CNT1,
 231                 .cnt2_reg       = DMA2_CNT2,
 232         },
 233         [SRAM_CH03] = {
 234                 .name           = "ch3",
 235                 .cmds_start     = 0x0,
 236                 .ctrl_start     = 0x0,
 237                 .cdt            = 0x0,
 238                 .fifo_start     = 0x0,
 239                 .fifo_size      = 0x0,
 240                 .ptr1_reg       = DMA3_PTR1,
 241                 .ptr2_reg       = DMA3_PTR2,
 242                 .cnt1_reg       = DMA3_CNT1,
 243                 .cnt2_reg       = DMA3_CNT2,
 244         },
 245         [SRAM_CH04] = {
 246                 .name           = "ch4",
 247                 .cmds_start     = 0x0,
 248                 .ctrl_start     = 0x0,
 249                 .cdt            = 0x0,
 250                 .fifo_start     = 0x0,
 251                 .fifo_size      = 0x0,
 252                 .ptr1_reg       = DMA4_PTR1,
 253                 .ptr2_reg       = DMA4_PTR2,
 254                 .cnt1_reg       = DMA4_CNT1,
 255                 .cnt2_reg       = DMA4_CNT2,
 256         },
 257         [SRAM_CH05] = {
 258                 .name           = "ch5",
 259                 .cmds_start     = 0x0,
 260                 .ctrl_start     = 0x0,
 261                 .cdt            = 0x0,
 262                 .fifo_start     = 0x0,
 263                 .fifo_size      = 0x0,
 264                 .ptr1_reg       = DMA5_PTR1,
 265                 .ptr2_reg       = DMA5_PTR2,
 266                 .cnt1_reg       = DMA5_CNT1,
 267                 .cnt2_reg       = DMA5_CNT2,
 268         },
 269         [SRAM_CH06] = {
 270                 .name           = "TS2 C",
 271                 .cmds_start     = 0x10140,
 272                 .ctrl_start     = 0x10680,
 273                 .cdt            = 0x108d0,
 274                 .fifo_start     = 0x6000,
 275                 .fifo_size      = 0x1000,
 276                 .ptr1_reg       = DMA5_PTR1,
 277                 .ptr2_reg       = DMA5_PTR2,
 278                 .cnt1_reg       = DMA5_CNT1,
 279                 .cnt2_reg       = DMA5_CNT2,
 280         },
 281         [SRAM_CH07] = {
 282                 .name           = "ch7",
 283                 .cmds_start     = 0x0,
 284                 .ctrl_start     = 0x0,
 285                 .cdt            = 0x0,
 286                 .fifo_start     = 0x0,
 287                 .fifo_size      = 0x0,
 288                 .ptr1_reg       = DMA6_PTR1,
 289                 .ptr2_reg       = DMA6_PTR2,
 290                 .cnt1_reg       = DMA6_CNT1,
 291                 .cnt2_reg       = DMA6_CNT2,
 292         },
 293         [SRAM_CH08] = {
 294                 .name           = "ch8",
 295                 .cmds_start     = 0x0,
 296                 .ctrl_start     = 0x0,
 297                 .cdt            = 0x0,
 298                 .fifo_start     = 0x0,
 299                 .fifo_size      = 0x0,
 300                 .ptr1_reg       = DMA7_PTR1,
 301                 .ptr2_reg       = DMA7_PTR2,
 302                 .cnt1_reg       = DMA7_CNT1,
 303                 .cnt2_reg       = DMA7_CNT2,
 304         },
 305         [SRAM_CH09] = {
 306                 .name           = "ch9",
 307                 .cmds_start     = 0x0,
 308                 .ctrl_start     = 0x0,
 309                 .cdt            = 0x0,
 310                 .fifo_start     = 0x0,
 311                 .fifo_size      = 0x0,
 312                 .ptr1_reg       = DMA8_PTR1,
 313                 .ptr2_reg       = DMA8_PTR2,
 314                 .cnt1_reg       = DMA8_CNT1,
 315                 .cnt2_reg       = DMA8_CNT2,
 316         },
 317 };
 318
 319 static int cx23885_risc_decode(u32 risc)
 320 {
 321         static char *instr[16] = {
 322                 [ RISC_SYNC    >> 28 ] = "sync",
 323                 [ RISC_WRITE   >> 28 ] = "write",
 324                 [ RISC_WRITEC  >> 28 ] = "writec",
 325                 [ RISC_READ    >> 28 ] = "read",
 326                 [ RISC_READC   >> 28 ] = "readc",
 327                 [ RISC_JUMP    >> 28 ] = "jump",
 328                 [ RISC_SKIP    >> 28 ] = "skip",
 329                 [ RISC_WRITERM >> 28 ] = "writerm",
 330                 [ RISC_WRITECM >> 28 ] = "writecm",
 331                 [ RISC_WRITECR >> 28 ] = "writecr",
 332         };
 333         static int incr[16] = {
 334                 [ RISC_WRITE   >> 28 ] = 3, // 2
 335                 [ RISC_JUMP    >> 28 ] = 3, // 2
 336                 [ RISC_SKIP    >> 28 ] = 1,
 337                 [ RISC_SYNC    >> 28 ] = 1,
 338                 [ RISC_WRITERM >> 28 ] = 3,
 339                 [ RISC_WRITECM >> 28 ] = 3,
 340                 [ RISC_WRITECR >> 28 ] = 4,
 341         };
 342         static char *bits[] = {
 343                 "12",   "13",   "14",   "resync",
 344                 "cnt0", "cnt1", "18",   "19",
 345                 "20",   "21",   "22",   "23",
 346                 "irq1", "irq2", "eol",  "sol",
 347         };
 348         int i;
 349
 350         printk("0x%08x [ %s", risc,
 351                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 352         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 353                 if (risc & (1 << (i + 12)))
 354                         printk(" %s", bits[i]);
 355         printk(" count=%d ]\n", risc & 0xfff);
 356         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 357 }
 358
 359 void cx23885_wakeup(struct cx23885_tsport *port,
 360                     struct cx23885_dmaqueue *q, u32 count)
 361 {
 362         struct cx23885_dev *dev = port->dev;
 363         struct cx23885_buffer *buf;
 364         int bc;
 365
 366         for (bc = 0;; bc++) {
 367                 if (list_empty(&q->active))
 368                         break;
 369                 buf = list_entry(q->active.next,
 370                                  struct cx23885_buffer, vb.queue);
 371                 /* count comes from the hw and is is 16bit wide --
 372                  * this trick handles wrap-arounds correctly for
 373                  * up to 32767 buffers in flight... */
 374                 if ((s16) (count - buf->count) < 0)
 375                         break;
 376                 do_gettimeofday(&buf->vb.ts);
 377                 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
 378                         count, buf->count);
 379                 buf->vb.state = STATE_DONE;
 380                 list_del(&buf->vb.queue);
 381                 wake_up(&buf->vb.done);
 382         }
 383         if (list_empty(&q->active)) {
 384                 del_timer(&q->timeout);
 385         } else {
 386                 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
 387         }
 388         if (bc != 1)
 389                 printk("%s: %d buffers handled (should be 1)\n",
 390                        __FUNCTION__, bc);
 391 }
 392 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 393                                struct sram_channel *ch);
 394
 395 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 396                                struct sram_channel *ch,
 397                                unsigned int bpl, u32 risc)
 398 {
 399         unsigned int i, lines;
 400         u32 cdt;
 401
 402         if (ch->cmds_start == 0)
 403         {
 404                 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__,
 405                         ch->name);
 406                 cx_write(ch->ptr1_reg, 0);
 407                 cx_write(ch->ptr2_reg, 0);
 408                 cx_write(ch->cnt2_reg, 0);
 409                 cx_write(ch->cnt1_reg, 0);
 410                 return 0;
 411         } else {
 412                 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__,
 413                         ch->name);
 414         }
 415
 416         bpl   = (bpl + 7) & ~7; /* alignment */
 417         cdt   = ch->cdt;
 418         lines = ch->fifo_size / bpl;
 419         if (lines > 6)
 420                 lines = 6;
 421         BUG_ON(lines < 2);
 422
 423         cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
 424         cx_write(8 + 4, cpu_to_le32(8) );
 425         cx_write(8 + 8, cpu_to_le32(0) );
 426
 427         /* write CDT */
 428         for (i = 0; i < lines; i++) {
 429                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i,
 430                         ch->fifo_start + bpl*i);
 431                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 432                 cx_write(cdt + 16*i +  4, 0);
 433                 cx_write(cdt + 16*i +  8, 0);
 434                 cx_write(cdt + 16*i + 12, 0);
 435         }
 436
 437         /* write CMDS */
 438         if (ch->jumponly)
 439                 cx_write(ch->cmds_start +  0, 8);
 440         else
 441                 cx_write(ch->cmds_start +  0, risc);
 442         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 443         cx_write(ch->cmds_start +  8, cdt);
 444         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 445         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 446         if (ch->jumponly)
 447                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
 448         else
 449                 cx_write(ch->cmds_start + 20, 64 >> 2);
 450         for (i = 24; i < 80; i += 4)
 451                 cx_write(ch->cmds_start + i, 0);
 452
 453         /* fill registers */
 454         cx_write(ch->ptr1_reg, ch->fifo_start);
 455         cx_write(ch->ptr2_reg, cdt);
 456         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 457         cx_write(ch->cnt1_reg, (bpl >> 3) -1);
 458
 459         dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 460                 dev->bridge,
 461                 ch->name,
 462                 bpl,
 463                 lines);
 464
 465         return 0;
 466 }
 467
 468 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 469                                struct sram_channel *ch)
 470 {
 471         static char *name[] = {
 472                 "init risc lo",
 473                 "init risc hi",
 474                 "cdt base",
 475                 "cdt size",
 476                 "iq base",
 477                 "iq size",
 478                 "risc pc lo",
 479                 "risc pc hi",
 480                 "iq wr ptr",
 481                 "iq rd ptr",
 482                 "cdt current",
 483                 "pci target lo",
 484                 "pci target hi",
 485                 "line / byte",
 486         };
 487         u32 risc;
 488         unsigned int i, j, n;
 489
 490         printk("%s: %s - dma channel status dump\n",
 491                dev->name, ch->name);
 492         for (i = 0; i < ARRAY_SIZE(name); i++)
 493                 printk("%s:   cmds: %-15s: 0x%08x\n",
 494                        dev->name, name[i],
 495                        cx_read(ch->cmds_start + 4*i));
 496
 497         for (i = 0; i < 4; i++) {
 498                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 499                 printk("%s:   risc%d: ", dev->name, i);
 500                 cx23885_risc_decode(risc);
 501         }
 502         for (i = 0; i < (64 >> 2); i += n) {
 503                 risc = cx_read(ch->ctrl_start + 4 * i);
 504                 /* No consideration for bits 63-32 */
 505
 506                 printk("%s:   (0x%08x) iq %x: ", dev->name,
 507                        ch->ctrl_start + 4 * i, i);
 508                 n = cx23885_risc_decode(risc);
 509                 for (j = 1; j < n; j++) {
 510                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 511                         printk("%s:   iq %x: 0x%08x [ arg #%d ]\n",
 512                                dev->name, i+j, risc, j);
 513                 }
 514         }
 515
 516         printk("%s: fifo: 0x%08x -> 0x%x\n",
 517                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 518         printk("%s: ctrl: 0x%08x -> 0x%x\n",
 519                dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 520         printk("%s:   ptr1_reg: 0x%08x\n",
 521                dev->name, cx_read(ch->ptr1_reg));
 522         printk("%s:   ptr2_reg: 0x%08x\n",
 523                dev->name, cx_read(ch->ptr2_reg));
 524         printk("%s:   cnt1_reg: 0x%08x\n",
 525                dev->name, cx_read(ch->cnt1_reg));
 526         printk("%s:   cnt2_reg: 0x%08x\n",
 527                dev->name, cx_read(ch->cnt2_reg));
 528 }
 529
 530 void cx23885_risc_disasm(struct cx23885_tsport *port,
 531                          struct btcx_riscmem *risc)
 532 {
 533         struct cx23885_dev *dev = port->dev;
 534         unsigned int i, j, n;
 535
 536         printk("%s: risc disasm: %p [dma=0x%08lx]\n",
 537                dev->name, risc->cpu, (unsigned long)risc->dma);
 538         for (i = 0; i < (risc->size >> 2); i += n) {
 539                 printk("%s:   %04d: ", dev->name, i);
 540                 n = cx23885_risc_decode(risc->cpu[i]);
 541                 for (j = 1; j < n; j++)
 542                         printk("%s:   %04d: 0x%08x [ arg #%d ]\n",
 543                                dev->name, i + j, risc->cpu[i + j], j);
 544                 if (risc->cpu[i] == RISC_JUMP)
 545                         break;
 546         }
 547 }
 548
 549 void cx23885_shutdown(struct cx23885_dev *dev)
 550 {
 551         /* disable RISC controller */
 552         cx_write(DEV_CNTRL2, 0);
 553
 554         /* Disable all IR activity */
 555         cx_write(IR_CNTRL_REG, 0);
 556
 557         /* Disable Video A/B activity */
 558         cx_write(VID_A_DMA_CTL, 0);
 559         cx_write(VID_B_DMA_CTL, 0);
 560         cx_write(VID_C_DMA_CTL, 0);
 561
 562         /* Disable Audio activity */
 563         cx_write(AUD_INT_DMA_CTL, 0);
 564         cx_write(AUD_EXT_DMA_CTL, 0);
 565
 566         /* Disable Serial port */
 567         cx_write(UART_CTL, 0);
 568
 569         /* Disable Interrupts */
 570         cx_write(PCI_INT_MSK, 0);
 571         cx_write(VID_A_INT_MSK, 0);
 572         cx_write(VID_B_INT_MSK, 0);
 573         cx_write(VID_C_INT_MSK, 0);
 574         cx_write(AUDIO_INT_INT_MSK, 0);
 575         cx_write(AUDIO_EXT_INT_MSK, 0);
 576
 577 }
 578
 579 void cx23885_reset(struct cx23885_dev *dev)
 580 {
 581         dprintk(1, "%s()\n", __FUNCTION__);
 582
 583         cx23885_shutdown(dev);
 584
 585         cx_write(PCI_INT_STAT, 0xffffffff);
 586         cx_write(VID_A_INT_STAT, 0xffffffff);
 587         cx_write(VID_B_INT_STAT, 0xffffffff);
 588         cx_write(VID_C_INT_STAT, 0xffffffff);
 589         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 590         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 591         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 592
 593         mdelay(100);
 594
 595         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH01 ], 188*4, 0);
 596         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH02 ], 128, 0);
 597         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 128, 0);
 598         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH04 ], 128, 0);
 599         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH05 ], 128, 0);
 600         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH06 ], 188*4, 0);
 601         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH07 ], 128, 0);
 602         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH08 ], 128, 0);
 603         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH09 ], 128, 0);
 604
 605         switch(dev->board) {
 606         case CX23885_BOARD_HAUPPAUGE_HVR1800:
 607                 /* GPIO-0 656_CLK */
 608                 /* GPIO-1 656_D0 */
 609                 /* GPIO-2 8295A Reset */
 610                 /* GPIO-3-10 cx23417 data0-7 */
 611                 /* GPIO-11-14 cx23417 addr0-3 */
 612                 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
 613                 /* GPIO-19 IR_RX */
 614                 dprintk( 1, "%s() Configuring HVR1800 GPIO's\n", __FUNCTION__);
 615                 // FIXME: Analog requires the tuner is brought out of reset
 616                 break;
 617         }
 618 }
 619
 620
 621 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 622 {
 623         dprintk(1, "%s()\n", __FUNCTION__);
 624
 625         switch(dev->board) {
 626         case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
 627                 cx_clear(RDR_TLCTL0, 1 << 4);
 628                 break;
 629         }
 630         return 0;
 631 }
 632
 633 static int get_resources(struct cx23885_dev *dev)
 634 {
 635         if (request_mem_region(pci_resource_start(dev->pci,0),
 636                                pci_resource_len(dev->pci,0),
 637                                dev->name))
 638                 return 0;
 639
 640         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 641                 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
 642
 643         return -EBUSY;
 644 }
 645
 646 static void cx23885_timeout(unsigned long data);
 647 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 648                          u32 reg, u32 mask, u32 value);
 649
 650 static int cx23885_ir_init(struct cx23885_dev *dev)
 651 {
 652         dprintk(1, "%s()\n", __FUNCTION__);
 653
 654         switch (dev->board) {
 655         case CX23885_BOARD_HAUPPAUGE_HVR1800:
 656                 dprintk(1, "%s() FIXME - Implement IR support\n", __FUNCTION__);
 657                 break;
 658         }
 659
 660         return 0;
 661 }
 662
 663 static int cx23885_dev_setup(struct cx23885_dev *dev)
 664 {
 665         int i;
 666
 667         mutex_init(&dev->lock);
 668
 669         atomic_inc(&dev->refcount);
 670
 671         dev->nr = cx23885_devcount++;
 672         dev->pci_bus  = dev->pci->bus->number;
 673         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 674         dev->pci_irqmask = 0x001f00;
 675
 676         /* External Master 1 Bus */
 677         dev->i2c_bus[0].nr = 0;
 678         dev->i2c_bus[0].dev = dev;
 679         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 680         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 681         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 682         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 683         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 684         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 685
 686         /* External Master 2 Bus */
 687         dev->i2c_bus[1].nr = 1;
 688         dev->i2c_bus[1].dev = dev;
 689         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 690         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 691         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 692         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 693         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 694         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 695
 696         /* Internal Master 3 Bus */
 697         dev->i2c_bus[2].nr = 2;
 698         dev->i2c_bus[2].dev = dev;
 699         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 700         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 701         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 702         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 703         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 704         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 705
 706         /* Transport bus init dma queue */
 707         spin_lock_init(&dev->ts2.slock);
 708         dev->ts2.dev = dev;
 709         dev->ts2.nr = 2;
 710         dev->ts2.sram_chno = SRAM_CH06;
 711         INIT_LIST_HEAD(&dev->ts2.mpegq.active);
 712         INIT_LIST_HEAD(&dev->ts2.mpegq.queued);
 713         dev->ts2.mpegq.timeout.function = cx23885_timeout;
 714         dev->ts2.mpegq.timeout.data     = (unsigned long)&dev->ts2;
 715         init_timer(&dev->ts2.mpegq.timeout);
 716
 717         dev->ts2.reg_gpcnt = VID_C_GPCNT;
 718         dev->ts2.reg_gpcnt_ctl = VID_C_GPCNT_CTL;
 719         dev->ts2.reg_dma_ctl = VID_C_DMA_CTL;
 720         dev->ts2.reg_lngth = VID_C_LNGTH;
 721         dev->ts2.reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
 722         dev->ts2.reg_gen_ctrl = VID_C_GEN_CTL;
 723         dev->ts2.reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
 724         dev->ts2.reg_sop_status = VID_C_SOP_STATUS;
 725         dev->ts2.reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 726         dev->ts2.reg_vld_misc = VID_C_VLD_MISC;
 727         dev->ts2.reg_ts_clk_en = VID_C_TS_CLK_EN;
 728         dev->ts2.reg_ts_int_msk = VID_C_INT_MSK;
 729
 730         // FIXME: Make this board specific
 731         dev->ts2.pci_irqmask = 0x04; /* TS Port 2 bit */
 732         dev->ts2.dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
 733         dev->ts2.ts_int_msk_val = 0x1111; /* TS port bits for RISC */
 734         dev->ts2.gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
 735         dev->ts2.ts_clk_en_val = 0x1; /* Enable TS_CLK */
 736
 737         cx23885_risc_stopper(dev->pci, &dev->ts2.mpegq.stopper,
 738                              dev->ts2.reg_dma_ctl, dev->ts2.dma_ctl_val, 0x00);
 739
 740         sprintf(dev->name, "cx23885[%d]", dev->nr);
 741
 742         if (get_resources(dev) < 0) {
 743                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 744                        "subsystem: %04x:%04x\n",
 745                        dev->name, dev->pci->subsystem_vendor,
 746                        dev->pci->subsystem_device);
 747
 748                 cx23885_devcount--;
 749                 goto fail_free;
 750         }
 751
 752         mutex_lock(&devlist);
 753         list_add_tail(&dev->devlist, &cx23885_devlist);
 754         mutex_unlock(&devlist);
 755
 756         /* PCIe stuff */
 757         dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
 758                              pci_resource_len(dev->pci,0));
 759
 760         dev->bmmio = (u8 __iomem *)dev->lmmio;
 761
 762         cx23885_pci_quirks(dev);
 763
 764         /* board config */
 765         dev->board = UNSET;
 766         if (card[dev->nr] < cx23885_bcount)
 767                 dev->board = card[dev->nr];
 768         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 769                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 770                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 771                         dev->board = cx23885_subids[i].card;
 772         if (UNSET == dev->board) {
 773                 dev->board = CX23885_BOARD_UNKNOWN;
 774                 cx23885_card_list(dev);
 775         }
 776         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 777                dev->name, dev->pci->subsystem_vendor,
 778                dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 779                dev->board, card[dev->nr] == dev->board ?
 780                "insmod option" : "autodetected");
 781
 782         /* Configure the internal memory */
 783         if(dev->pci->device == 0x8880) {
 784                 dev->bridge = CX23885_BRIDGE_887;
 785                 dev->sram_channels = cx23887_sram_channels;
 786         } else
 787         if(dev->pci->device == 0x8852) {
 788                 dev->bridge = CX23885_BRIDGE_885;
 789                 dev->sram_channels = cx23885_sram_channels;
 790         }
 791         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 792                 __FUNCTION__, dev->bridge);
 793
 794         /* init hardware */
 795         cx23885_reset(dev);
 796
 797         cx23885_i2c_register(&dev->i2c_bus[0]);
 798         cx23885_i2c_register(&dev->i2c_bus[1]);
 799         cx23885_i2c_register(&dev->i2c_bus[2]);
 800         cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
 801
 802         cx23885_card_setup(dev);
 803         cx23885_ir_init(dev);
 804
 805         if (cx23885_dvb_register(&dev->ts2) < 0) {
 806                 printk(KERN_ERR "%s() Failed to register dvb adapters\n",
 807                        __FUNCTION__);
 808         }
 809
 810         return 0;
 811
 812 fail_free:
 813         kfree(dev);
 814         return -ENODEV;
 815 }
 816
 817 void cx23885_dev_unregister(struct cx23885_dev *dev)
 818 {
 819         release_mem_region(pci_resource_start(dev->pci,0),
 820                            pci_resource_len(dev->pci,0));
 821
 822         if (!atomic_dec_and_test(&dev->refcount))
 823                 return;
 824
 825         cx23885_dvb_unregister(&dev->ts2);
 826         cx23885_i2c_unregister(&dev->i2c_bus[2]);
 827         cx23885_i2c_unregister(&dev->i2c_bus[1]);
 828         cx23885_i2c_unregister(&dev->i2c_bus[0]);
 829
 830         iounmap(dev->lmmio);
 831 }
 832
 833 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
 834                                unsigned int offset, u32 sync_line,
 835                                unsigned int bpl, unsigned int padding,
 836                                unsigned int lines)
 837 {
 838         struct scatterlist *sg;
 839         unsigned int line, todo;
 840
 841         /* sync instruction */
 842         if (sync_line != NO_SYNC_LINE)
 843                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 844
 845         /* scan lines */
 846         sg = sglist;
 847         for (line = 0; line < lines; line++) {
 848                 while (offset && offset >= sg_dma_len(sg)) {
 849                         offset -= sg_dma_len(sg);
 850                         sg++;
 851                 }
 852                 if (bpl <= sg_dma_len(sg)-offset) {
 853                         /* fits into current chunk */
 854                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
 855                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 856                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 857                         offset+=bpl;
 858                 } else {
 859                         /* scanline needs to be split */
 860                         todo = bpl;
 861                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
 862                                             (sg_dma_len(sg)-offset));
 863                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 864                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 865                         todo -= (sg_dma_len(sg)-offset);
 866                         offset = 0;
 867                         sg++;
 868                         while (todo > sg_dma_len(sg)) {
 869                                 *(rp++)=cpu_to_le32(RISC_WRITE|
 870                                                     sg_dma_len(sg));
 871                                 *(rp++)=cpu_to_le32(sg_dma_address(sg));
 872                                 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 873                                 todo -= sg_dma_len(sg);
 874                                 sg++;
 875                         }
 876                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
 877                         *(rp++)=cpu_to_le32(sg_dma_address(sg));
 878                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 879                         offset += todo;
 880                 }
 881                 offset += padding;
 882         }
 883
 884         return rp;
 885 }
 886
 887 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 888                         struct scatterlist *sglist, unsigned int top_offset,
 889                         unsigned int bottom_offset, unsigned int bpl,
 890                         unsigned int padding, unsigned int lines)
 891 {
 892         u32 instructions, fields;
 893         u32 *rp;
 894         int rc;
 895
 896         fields = 0;
 897         if (UNSET != top_offset)
 898                 fields++;
 899         if (UNSET != bottom_offset)
 900                 fields++;
 901
 902         /* estimate risc mem: worst case is one write per page border +
 903            one write per scan line + syncs + jump (all 2 dwords).  Padding
 904            can cause next bpl to start close to a page border.  First DMA
 905            region may be smaller than PAGE_SIZE */
 906         /* write and jump need and extra dword */
 907         instructions  = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
 908         instructions += 2;
 909         //if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
 910         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 911                 return rc;
 912
 913         /* write risc instructions */
 914         rp = risc->cpu;
 915         if (UNSET != top_offset)
 916                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
 917                                         bpl, padding, lines);
 918         if (UNSET != bottom_offset)
 919                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
 920                                         bpl, padding, lines);
 921
 922         /* save pointer to jmp instruction address */
 923         risc->jmp = rp;
 924         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 925         return 0;
 926 }
 927
 928 int cx23885_risc_databuffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 929                             struct scatterlist *sglist, unsigned int bpl,
 930                             unsigned int lines)
 931 {
 932         u32 instructions;
 933         u32 *rp;
 934         int rc;
 935
 936         /* estimate risc mem: worst case is one write per page border +
 937            one write per scan line + syncs + jump (all 2 dwords).  Here
 938            there is no padding and no sync.  First DMA region may be smaller
 939            than PAGE_SIZE */
 940         /* Jump and write need an extra dword */
 941         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
 942         instructions += 1;
 943
 944         //if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
 945         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 946                 return rc;
 947
 948         /* write risc instructions */
 949         rp = risc->cpu;
 950         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
 951
 952         /* save pointer to jmp instruction address */
 953         risc->jmp = rp;
 954         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 955         return 0;
 956 }
 957
 958 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 959                          u32 reg, u32 mask, u32 value)
 960 {
 961         u32 *rp;
 962         int rc;
 963
 964         if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
 965                 return rc;
 966
 967         /* write risc instructions */
 968         rp = risc->cpu;
 969         //*(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2 | RISC_IMM);
 970         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
 971         *(rp++) = cpu_to_le32(reg);
 972         *(rp++) = cpu_to_le32(value);
 973         *(rp++) = cpu_to_le32(mask);
 974         *(rp++) = cpu_to_le32(RISC_JUMP);
 975         *(rp++) = cpu_to_le32(risc->dma);
 976         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
 977         return 0;
 978 }
 979
 980 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
 981 {
 982         BUG_ON(in_interrupt());
 983         videobuf_waiton(&buf->vb, 0, 0);
 984         videobuf_dma_unmap(q, &buf->vb.dma);
 985         videobuf_dma_free(&buf->vb.dma);
 986         btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
 987         buf->vb.state = STATE_NEEDS_INIT;
 988 }
 989
 990 static int cx23885_start_dma(struct cx23885_tsport *port,
 991                              struct cx23885_dmaqueue *q,
 992                              struct cx23885_buffer   *buf)
 993 {
 994         struct cx23885_dev *dev = port->dev;
 995
 996         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
 997                 buf->vb.width, buf->vb.height, buf->vb.field);
 998
 999         /* setup fifo + format */
1000         cx23885_sram_channel_setup(dev,
1001                                    &dev->sram_channels[ port->sram_chno ],
1002                                    port->ts_packet_size, buf->risc.dma);
1003         if(debug > 5) {
1004                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1005                 cx23885_risc_disasm(port, &buf->risc);
1006         }
1007
1008         /* write TS length to chip */
1009         cx_write(port->reg_lngth, buf->vb.width);
1010
1011         if (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) {
1012                 printk( "%s() Failed. Unsupported value in .portc (0x%08x)\n",
1013                         __FUNCTION__, cx23885_boards[dev->board].portc );
1014                 return -EINVAL;
1015         }
1016
1017         // FIXME: review the need for these two lines
1018         dprintk( 1, "%s() doing .dvb\n", __FUNCTION__);
1019         udelay(100);
1020
1021         cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1022         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1023
1024         // FIXME: review the need for this
1025         cx_write(GPIO2, 0x00);
1026
1027         switch (dev->board) {
1028         case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1029         case CX23885_BOARD_HAUPPAUGE_HVR1800:
1030                 cx_write(port->reg_vld_misc, 0x00);
1031                 dprintk(1, "%s() Configuring HVR1800/lp/1500 board\n",
1032                         __FUNCTION__);
1033                 break;
1034         default:
1035                 // FIXME
1036                 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1037         }
1038
1039         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1040         udelay(100);
1041
1042         /* reset counter to zero */
1043         cx_write(port->reg_gpcnt_ctl, 3);
1044         q->count = 1;
1045
1046         /* A bug in the current 887 implementation, causes an NMI assert during
1047          * starting or stopping interrupts or dma. Avoid the bug for the time being,
1048          * enabling the developer to work on the demod/tuner locking work.
1049          */
1050         switch(dev->bridge) {
1051         case CX23885_BRIDGE_885:
1052         case CX23885_BRIDGE_887:
1053                 /* enable irqs */
1054                 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1055                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1056                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1057                 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1058                 break;
1059         default:
1060                 // FIXME: generate a sensible switch-default message
1061                 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1062         }
1063
1064         dprintk(1, "%s() Register Dump\n", __FUNCTION__);
1065         dprintk(1, "%s() set port ts_int_msk, now %x\n", __FUNCTION__, cx_read(port->reg_ts_int_msk) );
1066         dprintk(1, "%s() DEV_CNTRL2      0x%08x\n", __FUNCTION__, cx_read(DEV_CNTRL2) );
1067         dprintk(1, "%s() PCI_INT_MSK     0x%08x\n", __FUNCTION__, cx_read(PCI_INT_MSK) );
1068         dprintk(1, "%s() VID_A_INT_MSK   0x%08x\n", __FUNCTION__, cx_read(VID_A_INT_MSK) );
1069         dprintk(1, "%s() VID_B_INT_MSK   0x%08x\n", __FUNCTION__, cx_read(VID_B_INT_MSK) );
1070         dprintk(1, "%s() VID_C_INT_MSK   0x%08x\n", __FUNCTION__, cx_read(VID_C_INT_MSK) );
1071         dprintk(1, "%s() VID_A_DMA_CTL   0x%08x\n", __FUNCTION__, cx_read(VID_A_DMA_CTL) );
1072         dprintk(1, "%s() VID_B_DMA_CTL   0x%08x\n", __FUNCTION__, cx_read(VID_B_DMA_CTL) );
1073         dprintk(1, "%s() VID_C_DMA_CTL   0x%08x\n", __FUNCTION__, cx_read(VID_C_DMA_CTL) );
1074         dprintk(1, "%s() AUD_INT_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(AUDIO_INT_INT_MSK) );
1075         dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(AUD_INT_DMA_CTL) );
1076         dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(AUDIO_EXT_INT_MSK) );
1077         dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(AUD_EXT_DMA_CTL) );
1078
1079         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1080
1081         dprintk(1, "%s() set dev_cntrl2, now %x\n", __FUNCTION__, cx_read(DEV_CNTRL2) );
1082         dprintk(1, "%s() VID_C_DMA_CTL   , now %x\n", __FUNCTION__, cx_read(port->reg_dma_ctl) );
1083         dprintk(1, "%s() VID_C_DMA_CTL   , now %x\n", __FUNCTION__, cx_read(VID_C_DMA_CTL) );
1084         dprintk(1, "%s() PAD_CTRL %x\n", __FUNCTION__, cx_read(PAD_CTRL) );
1085         dprintk(1, "%s() GPIO2 %x\n", __FUNCTION__, cx_read(GPIO2) );
1086         dprintk(1, "%s() VID_C_LN_LNGTH  , now %x\n", __FUNCTION__, cx_read(port->reg_lngth) );
1087         dprintk(1, "%s() VID_C_HW_SOP_CTL, now %x\n", __FUNCTION__, cx_read(port->reg_hw_sop_ctrl) );
1088         dprintk(1, "%s() VID_C_GEN_CTL   , now %x\n", __FUNCTION__, cx_read(port->reg_gen_ctrl) );
1089         dprintk(1, "%s() VID_C_SOP_STATUS, now %x\n", __FUNCTION__, cx_read(VID_C_SOP_STATUS) );
1090         dprintk(1, "%s() VID_C_TS_CLK_EN , now %x\n", __FUNCTION__, cx_read(VID_C_TS_CLK_EN) );
1091         dprintk(1, "%s() VID_C_FIFO_OVLST, now %x\n", __FUNCTION__, cx_read(VID_C_FIFO_OVFL_STAT) );
1092         dprintk(1, "%s() VID_C_INT_MSTAT , now 0x%08x\n", __FUNCTION__, cx_read(VID_C_INT_MSTAT) );
1093         return 0;
1094 }
1095
1096 static int cx23885_stop_dma(struct cx23885_tsport *port)
1097 {
1098         struct cx23885_dev *dev = port->dev;
1099         dprintk(1, "%s()\n", __FUNCTION__);
1100
1101         /* Stop interrupts and DMA */
1102         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1103         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1104
1105         return 0;
1106 }
1107
1108 static int cx23885_restart_queue(struct cx23885_tsport *port,
1109                                 struct cx23885_dmaqueue *q)
1110 {
1111         struct cx23885_dev *dev = port->dev;
1112         struct cx23885_buffer *buf;
1113         struct list_head *item;
1114
1115         dprintk(5, "%s()\n", __FUNCTION__);
1116         if (list_empty(&q->active))
1117         {
1118                 struct cx23885_buffer *prev;
1119                 prev = NULL;
1120
1121                 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1122
1123                 for (;;) {
1124                         if (list_empty(&q->queued))
1125                                 return 0;
1126                         buf = list_entry(q->queued.next, struct cx23885_buffer,
1127                                          vb.queue);
1128                         if (NULL == prev) {
1129                                 list_del(&buf->vb.queue);
1130                                 list_add_tail(&buf->vb.queue, &q->active);
1131                                 cx23885_start_dma(port, q, buf);
1132                                 buf->vb.state = STATE_ACTIVE;
1133                                 buf->count    = q->count++;
1134                                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1135                                 dprintk(5, "[%p/%d] restart_queue - first active\n",
1136                                         buf, buf->vb.i);
1137
1138                         } else if (prev->vb.width  == buf->vb.width  &&
1139                                    prev->vb.height == buf->vb.height &&
1140                                    prev->fmt       == buf->fmt) {
1141                                 list_del(&buf->vb.queue);
1142                                 list_add_tail(&buf->vb.queue, &q->active);
1143                                 buf->vb.state = STATE_ACTIVE;
1144                                 buf->count    = q->count++;
1145                                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1146                                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1147                                 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1148                                         buf, buf->vb.i);
1149                         } else {
1150                                 return 0;
1151                         }
1152                         prev = buf;
1153                 }
1154                 return 0;
1155         }
1156
1157         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1158         dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1159                 buf, buf->vb.i);
1160         cx23885_start_dma(port, q, buf);
1161         list_for_each(item, &q->active) {
1162                 buf = list_entry(item, struct cx23885_buffer, vb.queue);
1163                 buf->count = q->count++;
1164         }
1165         mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1166         return 0;
1167 }
1168
1169 /* ------------------------------------------------------------------ */
1170
1171 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1172                         struct cx23885_buffer *buf, enum v4l2_field field)
1173 {
1174         struct cx23885_dev *dev = port->dev;
1175         int size = port->ts_packet_size * port->ts_packet_count;
1176         int rc;
1177
1178         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1179         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1180                 return -EINVAL;
1181
1182         if (STATE_NEEDS_INIT == buf->vb.state) {
1183                 buf->vb.width  = port->ts_packet_size;
1184                 buf->vb.height = port->ts_packet_count;
1185                 buf->vb.size   = size;
1186                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1187
1188                 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1189                         goto fail;
1190                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1191                                      buf->vb.dma.sglist,
1192                                      buf->vb.width, buf->vb.height);
1193         }
1194         buf->vb.state = STATE_PREPARED;
1195         return 0;
1196
1197  fail:
1198         cx23885_free_buffer(q, buf);
1199         return rc;
1200 }
1201
1202 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1203 {
1204         struct cx23885_buffer    *prev;
1205         struct cx23885_dev *dev = port->dev;
1206         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1207
1208         /* add jump to stopper */
1209         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1210         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1211         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1212
1213         if (list_empty(&cx88q->active)) {
1214                 dprintk( 1, "queue is empty - first active\n" );
1215                 list_add_tail(&buf->vb.queue, &cx88q->active);
1216                 cx23885_start_dma(port, cx88q, buf);
1217                 buf->vb.state = STATE_ACTIVE;
1218                 buf->count    = cx88q->count++;
1219                 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1220                 dprintk(1, "[%p/%d] %s - first active\n",
1221                         buf, buf->vb.i, __FUNCTION__);
1222
1223         } else {
1224                 dprintk( 1, "queue is not empty - append to active\n" );
1225                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1226                                   vb.queue);
1227                 list_add_tail(&buf->vb.queue, &cx88q->active);
1228                 buf->vb.state = STATE_ACTIVE;
1229                 buf->count    = cx88q->count++;
1230                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1231                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1232                 dprintk( 1, "[%p/%d] %s - append to active\n",
1233                          buf, buf->vb.i, __FUNCTION__);
1234         }
1235 }
1236
1237 /* ----------------------------------------------------------- */
1238
1239 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1240                               int restart)
1241 {
1242         struct cx23885_dev *dev = port->dev;
1243         struct cx23885_dmaqueue *q = &port->mpegq;
1244         struct cx23885_buffer *buf;
1245         unsigned long flags;
1246
1247         spin_lock_irqsave(&port->slock, flags);
1248         while (!list_empty(&q->active)) {
1249                 buf = list_entry(q->active.next, struct cx23885_buffer,
1250                                  vb.queue);
1251                 list_del(&buf->vb.queue);
1252                 buf->vb.state = STATE_ERROR;
1253                 wake_up(&buf->vb.done);
1254                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1255                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1256         }
1257         if (restart) {
1258                 dprintk(1, "restarting queue\n" );
1259                 cx23885_restart_queue(port, q);
1260         }
1261         spin_unlock_irqrestore(&port->slock, flags);
1262 }
1263
1264 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1265 {
1266         struct cx23885_dev *dev = port->dev;
1267         struct cx23885_dmaqueue *q = &port->mpegq;
1268
1269         dprintk(1, "%s()\n", __FUNCTION__);
1270         del_timer_sync(&q->timeout);
1271         cx23885_stop_dma(port);
1272         do_cancel_buffers(port, "cancel", 0);
1273 }
1274
1275 static void cx23885_timeout(unsigned long data)
1276 {
1277         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1278         struct cx23885_dev *dev = port->dev;
1279
1280         dprintk(1, "%s()\n",__FUNCTION__);
1281
1282         if (debug > 5)
1283                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1284
1285         cx23885_stop_dma(port);
1286         do_cancel_buffers(port, "timeout", 1);
1287 }
1288
1289 #define PCI_MSK_APB_DMA   (1 << 12)
1290 #define PCI_MSK_AL_WR     (1 << 11)
1291 #define PCI_MSK_AL_RD     (1 << 10)
1292 #define PCI_MSK_RISC_WR   (1 <<  9)
1293 #define PCI_MSK_RISC_RD   (1 <<  8)
1294
1295 #define PCI_MSK_AUD_EXT   (1 <<  4)
1296 #define PCI_MSK_AUD_INT   (1 <<  3)
1297 #define PCI_MSK_VID_C     (1 <<  2)
1298 #define PCI_MSK_VID_B     (1 <<  1)
1299 #define PCI_MSK_VID_A      1
1300
1301 #define VID_C_MSK_BAD_PKT (1 << 20)
1302 #define VID_C_MSK_OPC_ERR (1 << 16)
1303 #define VID_C_MSK_SYNC    (1 << 12)
1304 #define VID_C_MSK_OF      (1 <<  8)
1305 #define VID_C_MSK_RISCI2  (1 <<  4)
1306 #define VID_C_MSK_RISCI1   1
1307
1308 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1309 {
1310         struct cx23885_dev *dev = dev_id;
1311         struct cx23885_tsport *port = &dev->ts2;
1312         u32 pci_status, pci_mask;
1313         u32 ts2_status, ts2_mask;
1314         int count = 0, handled = 0;
1315
1316         pci_status = cx_read(PCI_INT_STAT);
1317         pci_mask = cx_read(PCI_INT_MSK);
1318
1319         ts2_status = cx_read(VID_C_INT_STAT);
1320         ts2_mask = cx_read(VID_C_INT_MSK);
1321
1322         if ( (pci_status == 0) && (ts2_status == 0) )
1323                 goto out;
1324
1325         count = cx_read(port->reg_gpcnt);
1326         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n", pci_status, pci_mask );
1327         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, count );
1328
1329         if ( (pci_status & PCI_MSK_RISC_RD) ||
1330              (pci_status & PCI_MSK_RISC_WR) ||
1331              (pci_status & PCI_MSK_AL_RD) ||
1332              (pci_status & PCI_MSK_AL_WR) ||
1333              (pci_status & PCI_MSK_APB_DMA) ||
1334              (pci_status & PCI_MSK_VID_C) ||
1335              (pci_status & PCI_MSK_VID_B) ||
1336              (pci_status & PCI_MSK_VID_A) ||
1337              (pci_status & PCI_MSK_AUD_INT) ||
1338              (pci_status & PCI_MSK_AUD_EXT) )
1339         {
1340
1341                 if (pci_status & PCI_MSK_RISC_RD)
1342                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n", PCI_MSK_RISC_RD);
1343                 if (pci_status & PCI_MSK_RISC_WR)
1344                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n", PCI_MSK_RISC_WR);
1345                 if (pci_status & PCI_MSK_AL_RD)
1346                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n", PCI_MSK_AL_RD);
1347                 if (pci_status & PCI_MSK_AL_WR)
1348                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n", PCI_MSK_AL_WR);
1349                 if (pci_status & PCI_MSK_APB_DMA)
1350                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n", PCI_MSK_APB_DMA);
1351                 if (pci_status & PCI_MSK_VID_C)
1352                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n", PCI_MSK_VID_C);
1353                 if (pci_status & PCI_MSK_VID_B)
1354                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n", PCI_MSK_VID_B);
1355                 if (pci_status & PCI_MSK_VID_A)
1356                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n", PCI_MSK_VID_A);
1357                 if (pci_status & PCI_MSK_AUD_INT)
1358                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n", PCI_MSK_AUD_INT);
1359                 if (pci_status & PCI_MSK_AUD_EXT)
1360                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n", PCI_MSK_AUD_EXT);
1361
1362         }
1363
1364         if ( (ts2_status & VID_C_MSK_OPC_ERR) ||
1365              (ts2_status & VID_C_MSK_BAD_PKT) ||
1366              (ts2_status & VID_C_MSK_SYNC) ||
1367              (ts2_status & VID_C_MSK_OF))
1368         {
1369                 if (ts2_status & VID_C_MSK_OPC_ERR)
1370                         dprintk(7, " (VID_C_MSK_OPC_ERR 0x%08x)\n", VID_C_MSK_OPC_ERR);
1371                 if (ts2_status & VID_C_MSK_BAD_PKT)
1372                         dprintk(7, " (VID_C_MSK_BAD_PKT 0x%08x)\n", VID_C_MSK_BAD_PKT);
1373                 if (ts2_status & VID_C_MSK_SYNC)
1374                         dprintk(7, " (VID_C_MSK_SYNC    0x%08x)\n", VID_C_MSK_SYNC);
1375                 if (ts2_status & VID_C_MSK_OF)
1376                         dprintk(7, " (VID_C_MSK_OF      0x%08x)\n", VID_C_MSK_OF);
1377
1378                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1379
1380                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1381                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1382
1383         } else if (ts2_status & VID_C_MSK_RISCI1) {
1384
1385                 dprintk(7, " (RISCI1            0x%08x)\n", VID_C_MSK_RISCI1);
1386
1387                 spin_lock(&port->slock);
1388                 count = cx_read(port->reg_gpcnt);
1389                 cx23885_wakeup(port, &port->mpegq, count);
1390                 spin_unlock(&port->slock);
1391
1392         } else if (ts2_status & VID_C_MSK_RISCI2) {
1393
1394                 dprintk(7, " (RISCI2            0x%08x)\n", VID_C_MSK_RISCI2);
1395
1396                 spin_lock(&port->slock);
1397                 cx23885_restart_queue(port, &port->mpegq);
1398                 spin_unlock(&port->slock);
1399
1400         }
1401
1402         cx_write(VID_C_INT_STAT, ts2_status);
1403         cx_write(PCI_INT_STAT, pci_status);
1404         handled = 1;
1405 out:
1406         return IRQ_RETVAL(handled);
1407 }
1408
1409 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1410                                      const struct pci_device_id *pci_id)
1411 {
1412         struct cx23885_dev *dev;
1413         int err;
1414
1415         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1416         if (NULL == dev)
1417                 return -ENOMEM;
1418
1419         /* pci init */
1420         dev->pci = pci_dev;
1421         if (pci_enable_device(pci_dev)) {
1422                 err = -EIO;
1423                 goto fail_free;
1424         }
1425
1426         if (cx23885_dev_setup(dev) < 0) {
1427                 err = -EINVAL;
1428                 goto fail_free;
1429         }
1430
1431         /* print pci info */
1432         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1433         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1434         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1435                "latency: %d, mmio: 0x%llx\n", dev->name,
1436                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1437                dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1438
1439         pci_set_master(pci_dev);
1440         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1441                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1442                 err = -EIO;
1443                 goto fail_irq;
1444         }
1445
1446         err = request_irq(pci_dev->irq, cx23885_irq,
1447                           IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1448         if (err < 0) {
1449                 printk(KERN_ERR "%s: can't get IRQ %d\n",
1450                        dev->name, pci_dev->irq);
1451                 goto fail_irq;
1452         }
1453
1454         pci_set_drvdata(pci_dev, dev);
1455         return 0;
1456
1457 fail_irq:
1458         cx23885_dev_unregister(dev);
1459 fail_free:
1460         kfree(dev);
1461         return err;
1462 }
1463
1464 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1465 {
1466         struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1467
1468         cx23885_shutdown(dev);
1469
1470         pci_disable_device(pci_dev);
1471
1472         /* unregister stuff */
1473         free_irq(pci_dev->irq, dev);
1474         pci_set_drvdata(pci_dev, NULL);
1475
1476         mutex_lock(&devlist);
1477         list_del(&dev->devlist);
1478         mutex_unlock(&devlist);
1479
1480         cx23885_dev_unregister(dev);
1481         kfree(dev);
1482 }
1483
1484 static struct pci_device_id cx23885_pci_tbl[] = {
1485         {
1486                 /* CX23885 */
1487                 .vendor       = 0x14f1,
1488                 .device       = 0x8852,
1489                 .subvendor    = PCI_ANY_ID,
1490                 .subdevice    = PCI_ANY_ID,
1491         },{
1492                 /* CX23887 Rev 2 */
1493                 .vendor       = 0x14f1,
1494                 .device       = 0x8880,
1495                 .subvendor    = PCI_ANY_ID,
1496                 .subdevice    = PCI_ANY_ID,
1497         },{
1498                 /* --- end of list --- */
1499         }
1500 };
1501 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1502
1503 static struct pci_driver cx23885_pci_driver = {
1504         .name     = "cx23885",
1505         .id_table = cx23885_pci_tbl,
1506         .probe    = cx23885_initdev,
1507         .remove   = __devexit_p(cx23885_finidev),
1508         /* TODO */
1509         .suspend  = NULL,
1510         .resume   = NULL,
1511 };
1512
1513 static int cx23885_init(void)
1514 {
1515         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1516                (CX23885_VERSION_CODE >> 16) & 0xff,
1517                (CX23885_VERSION_CODE >>  8) & 0xff,
1518                CX23885_VERSION_CODE & 0xff);
1519 #ifdef SNAPSHOT
1520         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1521                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1522 #endif
1523         return pci_register_driver(&cx23885_pci_driver);
1524 }
1525
1526 static void cx23885_fini(void)
1527 {
1528         pci_unregister_driver(&cx23885_pci_driver);
1529 }
1530
1531 module_init(cx23885_init);
1532 module_exit(cx23885_fini);
1533
1534 /* ----------------------------------------------------------- */
1535 /*
1536  * Local variables:
1537  * c-basic-offset: 8
1538  * End:
1539  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1540  */