2 * Driver for the Conexant CX23885/7/8 PCIe bridge
4 * CX23888 Integrated Consumer Infrared Controller
6 * Copyright (C) 2009 Andy Walls <awalls@radix.net>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 #include <linux/kfifo.h>
26 #include <media/v4l2-device.h>
27 #include <media/v4l2-chip-ident.h>
31 static unsigned int ir_888_debug;
32 module_param(ir_888_debug, int, 0644);
33 MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
35 #define CX23888_IR_REG_BASE 0x170000
37 * These CX23888 register offsets have a straightforward one to one mapping
38 * to the CX23885 register offsets of 0x200 through 0x218
40 #define CX23888_IR_CNTRL_REG 0x170000
41 #define CNTRL_WIN_3_3 0x00000000
42 #define CNTRL_WIN_4_3 0x00000001
43 #define CNTRL_WIN_3_4 0x00000002
44 #define CNTRL_WIN_4_4 0x00000003
45 #define CNTRL_WIN 0x00000003
46 #define CNTRL_EDG_NONE 0x00000000
47 #define CNTRL_EDG_FALL 0x00000004
48 #define CNTRL_EDG_RISE 0x00000008
49 #define CNTRL_EDG_BOTH 0x0000000C
50 #define CNTRL_EDG 0x0000000C
51 #define CNTRL_DMD 0x00000010
52 #define CNTRL_MOD 0x00000020
53 #define CNTRL_RFE 0x00000040
54 #define CNTRL_TFE 0x00000080
55 #define CNTRL_RXE 0x00000100
56 #define CNTRL_TXE 0x00000200
57 #define CNTRL_RIC 0x00000400
58 #define CNTRL_TIC 0x00000800
59 #define CNTRL_CPL 0x00001000
60 #define CNTRL_LBM 0x00002000
61 #define CNTRL_R 0x00004000
63 #define CX23888_IR_TXCLK_REG 0x170004
64 #define TXCLK_TCD 0x0000FFFF
66 #define CX23888_IR_RXCLK_REG 0x170008
67 #define RXCLK_RCD 0x0000FFFF
69 #define CX23888_IR_CDUTY_REG 0x17000C
70 #define CDUTY_CDC 0x0000000F
72 #define CX23888_IR_STATS_REG 0x170010
73 #define STATS_RTO 0x00000001
74 #define STATS_ROR 0x00000002
75 #define STATS_RBY 0x00000004
76 #define STATS_TBY 0x00000008
77 #define STATS_RSR 0x00000010
78 #define STATS_TSR 0x00000020
80 #define CX23888_IR_IRQEN_REG 0x170014
81 #define IRQEN_RTE 0x00000001
82 #define IRQEN_ROE 0x00000002
83 #define IRQEN_RSE 0x00000010
84 #define IRQEN_TSE 0x00000020
86 #define CX23888_IR_FILTR_REG 0x170018
87 #define FILTR_LPF 0x0000FFFF
89 /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */
90 #define CX23888_IR_FIFO_REG 0x170040
91 #define FIFO_RXTX 0x0000FFFF
92 #define FIFO_RXTX_LVL 0x00010000
93 #define FIFO_RXTX_RTO 0x0001FFFF
94 #define FIFO_RX_NDV 0x00020000
95 #define FIFO_RX_DEPTH 8
96 #define FIFO_TX_DEPTH 8
98 /* CX23888 unique registers */
99 #define CX23888_IR_SEEDP_REG 0x17001C
100 #define CX23888_IR_TIMOL_REG 0x170020
101 #define CX23888_IR_WAKE0_REG 0x170024
102 #define CX23888_IR_WAKE1_REG 0x170028
103 #define CX23888_IR_WAKE2_REG 0x17002C
104 #define CX23888_IR_MASK0_REG 0x170030
105 #define CX23888_IR_MASK1_REG 0x170034
106 #define CX23888_IR_MAKS2_REG 0x170038
107 #define CX23888_IR_DPIPG_REG 0x17003C
108 #define CX23888_IR_LEARN_REG 0x170044
110 #define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
111 #define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2)
113 #define CX23888_IR_RX_KFIFO_SIZE (512 * sizeof(u32))
114 #define CX23888_IR_TX_KFIFO_SIZE (512 * sizeof(u32))
116 struct cx23888_ir_state {
117 struct v4l2_subdev sd;
118 struct cx23885_dev *dev;
122 struct v4l2_subdev_ir_parameters rx_params;
123 struct mutex rx_params_lock;
124 atomic_t rxclk_divider;
127 struct kfifo *rx_kfifo;
128 spinlock_t rx_kfifo_lock;
130 struct v4l2_subdev_ir_parameters tx_params;
131 struct mutex tx_params_lock;
132 atomic_t txclk_divider;
134 struct kfifo *tx_kfifo;
135 spinlock_t tx_kfifo_lock;
138 static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd)
140 return v4l2_get_subdevdata(sd);
144 * IR register block read and write functions
147 inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value)
149 cx_write(addr, value);
153 static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr)
155 return cx_read(addr);
158 static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
159 u32 and_mask, u32 or_value)
161 cx_andor(addr, ~and_mask, or_value);
166 * Rx and Tx Clock Divider register computations
168 * Note the largest clock divider value of 0xffff corresponds to:
169 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
170 * which fits in 21 bits, so we'll use unsigned int for time arguments.
172 static inline u16 count_to_clock_divider(unsigned int d)
174 if (d > RXCLK_RCD + 1)
183 static inline u16 ns_to_clock_divider(unsigned int ns)
185 return count_to_clock_divider(
186 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
189 static inline unsigned int clock_divider_to_ns(unsigned int divider)
191 /* Period of the Rx or Tx clock in ns */
192 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
193 CX23888_IR_REFCLK_FREQ / 1000000);
196 static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
198 return count_to_clock_divider(
199 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16));
202 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
204 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
207 static inline u16 freq_to_clock_divider(unsigned int freq,
208 unsigned int rollovers)
210 return count_to_clock_divider(
211 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers));
214 static inline unsigned int clock_divider_to_freq(unsigned int divider,
215 unsigned int rollovers)
217 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ,
218 (divider + 1) * rollovers);
222 * Low Pass Filter register calculations
224 * Note the largest count value of 0xffff corresponds to:
225 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
226 * which fits in 21 bits, so we'll use unsigned int for time arguments.
228 static inline u16 count_to_lpf_count(unsigned int d)
237 static inline u16 ns_to_lpf_count(unsigned int ns)
239 return count_to_lpf_count(
240 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
243 static inline unsigned int lpf_count_to_ns(unsigned int count)
245 /* Duration of the Low Pass Filter rejection window in ns */
246 return DIV_ROUND_CLOSEST(count * 1000,
247 CX23888_IR_REFCLK_FREQ / 1000000);
250 static inline unsigned int lpf_count_to_us(unsigned int count)
252 /* Duration of the Low Pass Filter rejection window in us */
253 return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000);
257 * FIFO register pulse width count compuations
259 static u32 clock_divider_to_resolution(u16 divider)
262 * Resolution is the duration of 1 tick of the readable portion of
263 * of the pulse width counter as read from the FIFO. The two lsb's are
264 * not readable, hence the << 2. This function returns ns.
266 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
267 CX23888_IR_REFCLK_FREQ / 1000000);
270 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
276 * The 2 lsb's of the pulse width timer count are not readable, hence
277 * the (count << 2) | 0x3
279 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
280 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
281 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
286 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
292 * The 2 lsb's of the pulse width timer count are not readable, hence
293 * the (count << 2) | 0x3
295 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
296 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
297 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
299 return (unsigned int) n;
303 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
305 * The total pulse clock count is an 18 bit pulse width timer count as the most
306 * significant part and (up to) 16 bit clock divider count as a modulus.
307 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
308 * width timer count's least significant bit.
310 static u64 ns_to_pulse_clocks(u32 ns)
314 clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
315 rem = do_div(clocks, 1000); /* /1000 = cycles */
321 static u16 pulse_clocks_to_clock_divider(u64 count)
325 rem = do_div(count, (FIFO_RXTX << 2) | 0x3);
327 /* net result needs to be rounded down and decremented by 1 */
328 if (count > RXCLK_RCD + 1)
338 * IR Control Register helpers
340 enum tx_fifo_watermark {
341 TX_FIFO_HALF_EMPTY = 0,
342 TX_FIFO_EMPTY = CNTRL_TIC,
345 enum rx_fifo_watermark {
346 RX_FIFO_HALF_FULL = 0,
347 RX_FIFO_NOT_EMPTY = CNTRL_RIC,
350 static inline void control_tx_irq_watermark(struct cx23885_dev *dev,
351 enum tx_fifo_watermark level)
353 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level);
356 static inline void control_rx_irq_watermark(struct cx23885_dev *dev,
357 enum rx_fifo_watermark level)
359 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level);
362 static inline void control_tx_enable(struct cx23885_dev *dev, bool enable)
364 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
365 enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
368 static inline void control_rx_enable(struct cx23885_dev *dev, bool enable)
370 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
371 enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
374 static inline void control_tx_modulation_enable(struct cx23885_dev *dev,
377 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD,
378 enable ? CNTRL_MOD : 0);
381 static inline void control_rx_demodulation_enable(struct cx23885_dev *dev,
384 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD,
385 enable ? CNTRL_DMD : 0);
388 static inline void control_rx_s_edge_detection(struct cx23885_dev *dev,
391 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
392 edge_types & CNTRL_EDG_BOTH);
395 static void control_rx_s_carrier_window(struct cx23885_dev *dev,
396 unsigned int carrier,
397 unsigned int *carrier_range_low,
398 unsigned int *carrier_range_high)
401 unsigned int c16 = carrier * 16;
403 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
405 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
408 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
411 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
413 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
416 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
418 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v);
421 static inline void control_tx_polarity_invert(struct cx23885_dev *dev,
424 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL,
425 invert ? CNTRL_CPL : 0);
429 * IR Rx & Tx Clock Register helpers
431 static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev,
435 *divider = carrier_freq_to_clock_divider(freq);
436 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
437 return clock_divider_to_carrier_freq(*divider);
440 static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev,
444 *divider = carrier_freq_to_clock_divider(freq);
445 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
446 return clock_divider_to_carrier_freq(*divider);
449 static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
454 if (ns > V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
455 ns = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS;
456 pulse_clocks = ns_to_pulse_clocks(ns);
457 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
458 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
459 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
462 static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
467 if (ns > V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
468 ns = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS;
469 pulse_clocks = ns_to_pulse_clocks(ns);
470 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
471 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
472 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
476 * IR Tx Carrier Duty Cycle register helpers
478 static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev,
479 unsigned int duty_cycle)
482 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
487 cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n);
488 return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
492 * IR Filter Register helpers
494 static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns)
496 u32 count = ns_to_lpf_count(min_width_ns);
497 cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count);
498 return lpf_count_to_ns(count);
502 * IR IRQ Enable Register helpers
504 static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask)
506 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
507 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG,
508 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
511 static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask)
514 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask);
518 * V4L2 Subdevice IR Ops
520 static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status,
523 struct cx23888_ir_state *state = to_state(sd);
524 struct cx23885_dev *dev = state->dev;
526 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
527 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
528 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
530 u32 rx_data[FIFO_RX_DEPTH];
533 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
535 tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
536 rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
537 rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
538 ror = stats & STATS_ROR; /* Rx FIFO Over Run */
540 tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
541 rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
542 rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
543 roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
546 v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n",
547 tsr ? "tsr" : " ", rsr ? "rsr" : " ",
548 rto ? "rto" : " ", ror ? "ror" : " ",
549 stats & STATS_TBY ? "tby" : " ",
550 stats & STATS_RBY ? "rby" : " ");
552 v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n",
553 tse ? "tse" : " ", rse ? "rse" : " ",
554 rte ? "rte" : " ", roe ? "roe" : " ");
557 * Transmitter interrupt service
562 * Check the watermark threshold setting
563 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
564 * Push the data to the hardware FIFO.
565 * If there was nothing more to send in the tx_kfifo, disable
566 * the TSR IRQ and notify the v4l2_device.
567 * If there was something in the tx_kfifo, check the tx_kfifo
568 * level and notify the v4l2_device, if it is low.
570 /* For now, inhibit TSR interrupt until Tx is implemented */
571 irqenable_tx(dev, 0);
572 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
573 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
578 * Receiver interrupt service
581 if ((rse && rsr) || (rte && rto)) {
583 * Receive data on RSR to clear the STATS_RSR.
584 * Receive data on RTO, since we may not have yet hit the RSR
585 * watermark when we receive the RTO.
587 for (i = 0, v = FIFO_RX_NDV;
588 (v & FIFO_RX_NDV) && !kror; i = 0) {
590 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
591 v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG);
592 rx_data[i++] = v & ~FIFO_RX_NDV;
597 k = kfifo_put(state->rx_kfifo,
598 (unsigned char *) rx_data, j);
600 kror++; /* rx_kfifo over run */
608 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
609 v4l2_err(sd, "IR receiver software FIFO overrun\n");
613 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
614 * the Rx FIFO Over Run status (STATS_ROR)
617 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
618 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
622 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
623 * the Rx Pulse Width Timer Time Out (STATS_RTO)
626 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
629 /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
630 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
631 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
634 if (kfifo_len(state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2)
635 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
638 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
643 static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
646 struct cx23888_ir_state *state = to_state(sd);
647 bool invert = (bool) atomic_read(&state->rx_invert);
648 u16 divider = (u16) atomic_read(&state->rxclk_divider);
654 n = count / sizeof(u32) * sizeof(u32);
660 n = kfifo_get(state->rx_kfifo, buf, n);
663 *num = n * sizeof(u32);
665 for (p = (u32 *) buf, i = 0; i < n; p++, i++) {
666 if ((*p & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
667 *p = V4L2_SUBDEV_IR_PULSE_RX_SEQ_END;
668 v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n");
672 u = (*p & FIFO_RXTX_LVL) ? V4L2_SUBDEV_IR_PULSE_LEVEL_MASK : 0;
674 u = u ? 0 : V4L2_SUBDEV_IR_PULSE_LEVEL_MASK;
676 v = (u32) pulse_width_count_to_ns((u16) (*p & FIFO_RXTX),
678 if (v >= V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
679 v = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS - 1;
683 v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s\n",
684 v, u ? "mark" : "space");
689 static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd,
690 struct v4l2_subdev_ir_parameters *p)
692 struct cx23888_ir_state *state = to_state(sd);
693 mutex_lock(&state->rx_params_lock);
694 memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters));
695 mutex_unlock(&state->rx_params_lock);
699 static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd)
701 struct cx23888_ir_state *state = to_state(sd);
702 struct cx23885_dev *dev = state->dev;
704 mutex_lock(&state->rx_params_lock);
706 /* Disable or slow down all IR Rx circuits and counters */
707 irqenable_rx(dev, 0);
708 control_rx_enable(dev, false);
709 control_rx_demodulation_enable(dev, false);
710 control_rx_s_edge_detection(dev, CNTRL_EDG_NONE);
711 filter_rx_s_min_width(dev, 0);
712 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD);
714 state->rx_params.shutdown = true;
716 mutex_unlock(&state->rx_params_lock);
720 static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd,
721 struct v4l2_subdev_ir_parameters *p)
723 struct cx23888_ir_state *state = to_state(sd);
724 struct cx23885_dev *dev = state->dev;
725 struct v4l2_subdev_ir_parameters *o = &state->rx_params;
729 return cx23888_ir_rx_shutdown(sd);
731 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
734 mutex_lock(&state->rx_params_lock);
736 o->shutdown = p->shutdown;
738 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
740 o->bytes_per_data_element = p->bytes_per_data_element = sizeof(u32);
742 /* Before we tweak the hardware, we have to disable the receiver */
743 irqenable_rx(dev, 0);
744 control_rx_enable(dev, false);
746 control_rx_demodulation_enable(dev, p->modulation);
747 o->modulation = p->modulation;
750 p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq,
753 o->carrier_freq = p->carrier_freq;
755 o->duty_cycle = p->duty_cycle = 50;
757 control_rx_s_carrier_window(dev, p->carrier_freq,
758 &p->carrier_range_lower,
759 &p->carrier_range_upper);
760 o->carrier_range_lower = p->carrier_range_lower;
761 o->carrier_range_upper = p->carrier_range_upper;
764 rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width,
766 o->max_pulse_width = p->max_pulse_width;
768 atomic_set(&state->rxclk_divider, rxclk_divider);
770 p->noise_filter_min_width =
771 filter_rx_s_min_width(dev, p->noise_filter_min_width);
772 o->noise_filter_min_width = p->noise_filter_min_width;
774 p->resolution = clock_divider_to_resolution(rxclk_divider);
775 o->resolution = p->resolution;
777 /* FIXME - make this dependent on resolution for better performance */
778 control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL);
780 control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH);
782 o->invert = p->invert;
783 atomic_set(&state->rx_invert, p->invert);
785 o->interrupt_enable = p->interrupt_enable;
786 o->enable = p->enable;
788 kfifo_reset(state->rx_kfifo);
789 if (p->interrupt_enable)
790 irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
791 control_rx_enable(dev, p->enable);
794 mutex_unlock(&state->rx_params_lock);
799 static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
802 struct cx23888_ir_state *state = to_state(sd);
803 struct cx23885_dev *dev = state->dev;
804 /* For now enable the Tx FIFO Service interrupt & pretend we did work */
805 irqenable_tx(dev, IRQEN_TSE);
810 static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd,
811 struct v4l2_subdev_ir_parameters *p)
813 struct cx23888_ir_state *state = to_state(sd);
814 mutex_lock(&state->tx_params_lock);
815 memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters));
816 mutex_unlock(&state->tx_params_lock);
820 static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd)
822 struct cx23888_ir_state *state = to_state(sd);
823 struct cx23885_dev *dev = state->dev;
825 mutex_lock(&state->tx_params_lock);
827 /* Disable or slow down all IR Tx circuits and counters */
828 irqenable_tx(dev, 0);
829 control_tx_enable(dev, false);
830 control_tx_modulation_enable(dev, false);
831 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD);
833 state->tx_params.shutdown = true;
835 mutex_unlock(&state->tx_params_lock);
839 static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd,
840 struct v4l2_subdev_ir_parameters *p)
842 struct cx23888_ir_state *state = to_state(sd);
843 struct cx23885_dev *dev = state->dev;
844 struct v4l2_subdev_ir_parameters *o = &state->tx_params;
848 return cx23888_ir_tx_shutdown(sd);
850 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
853 mutex_lock(&state->tx_params_lock);
855 o->shutdown = p->shutdown;
857 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
859 o->bytes_per_data_element = p->bytes_per_data_element = sizeof(u32);
861 /* Before we tweak the hardware, we have to disable the transmitter */
862 irqenable_tx(dev, 0);
863 control_tx_enable(dev, false);
865 control_tx_modulation_enable(dev, p->modulation);
866 o->modulation = p->modulation;
869 p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq,
871 o->carrier_freq = p->carrier_freq;
873 p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle);
874 o->duty_cycle = p->duty_cycle;
877 txclk_tx_s_max_pulse_width(dev, p->max_pulse_width,
879 o->max_pulse_width = p->max_pulse_width;
881 atomic_set(&state->txclk_divider, txclk_divider);
883 p->resolution = clock_divider_to_resolution(txclk_divider);
884 o->resolution = p->resolution;
886 /* FIXME - make this dependent on resolution for better performance */
887 control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY);
889 control_tx_polarity_invert(dev, p->invert);
890 o->invert = p->invert;
892 o->interrupt_enable = p->interrupt_enable;
893 o->enable = p->enable;
895 kfifo_reset(state->tx_kfifo);
896 if (p->interrupt_enable)
897 irqenable_tx(dev, IRQEN_TSE);
898 control_tx_enable(dev, p->enable);
901 mutex_unlock(&state->tx_params_lock);
907 * V4L2 Subdevice Core Ops
909 static int cx23888_ir_log_status(struct v4l2_subdev *sd)
911 struct cx23888_ir_state *state = to_state(sd);
912 struct cx23885_dev *dev = state->dev;
916 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
917 u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD;
918 u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD;
919 u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC;
920 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
921 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
922 u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF;
924 v4l2_info(sd, "IR Receiver:\n");
925 v4l2_info(sd, "\tEnabled: %s\n",
926 cntrl & CNTRL_RXE ? "yes" : "no");
927 v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
928 cntrl & CNTRL_DMD ? "enabled" : "disabled");
929 v4l2_info(sd, "\tFIFO: %s\n",
930 cntrl & CNTRL_RFE ? "enabled" : "disabled");
931 switch (cntrl & CNTRL_EDG) {
942 s = "rising & falling edges";
948 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
949 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
950 cntrl & CNTRL_R ? "not loaded" : "overflow marker");
951 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
952 cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
953 v4l2_info(sd, "\tLoopback mode: %s\n",
954 cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
955 if (cntrl & CNTRL_DMD) {
956 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
957 clock_divider_to_carrier_freq(rxclk));
958 switch (cntrl & CNTRL_WIN) {
980 v4l2_info(sd, "\tNext carrier edge window: 16 clocks "
981 "-%1d/+%1d, %u to %u Hz\n", i, j,
982 clock_divider_to_freq(rxclk, 16 + j),
983 clock_divider_to_freq(rxclk, 16 - i));
985 v4l2_info(sd, "\tMax measurable pulse width: %u us, "
987 pulse_width_count_to_us(FIFO_RXTX, rxclk),
988 pulse_width_count_to_ns(FIFO_RXTX, rxclk));
990 v4l2_info(sd, "\tLow pass filter: %s\n",
991 filtr ? "enabled" : "disabled");
993 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, "
995 lpf_count_to_us(filtr),
996 lpf_count_to_ns(filtr));
997 v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
998 stats & STATS_RTO ? "yes" : "no");
999 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
1000 irqen & IRQEN_RTE ? "enabled" : "disabled");
1001 v4l2_info(sd, "\tFIFO overrun: %s\n",
1002 stats & STATS_ROR ? "yes" : "no");
1003 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
1004 irqen & IRQEN_ROE ? "enabled" : "disabled");
1005 v4l2_info(sd, "\tBusy: %s\n",
1006 stats & STATS_RBY ? "yes" : "no");
1007 v4l2_info(sd, "\tFIFO service requested: %s\n",
1008 stats & STATS_RSR ? "yes" : "no");
1009 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1010 irqen & IRQEN_RSE ? "enabled" : "disabled");
1012 v4l2_info(sd, "IR Transmitter:\n");
1013 v4l2_info(sd, "\tEnabled: %s\n",
1014 cntrl & CNTRL_TXE ? "yes" : "no");
1015 v4l2_info(sd, "\tModulation onto a carrier: %s\n",
1016 cntrl & CNTRL_MOD ? "enabled" : "disabled");
1017 v4l2_info(sd, "\tFIFO: %s\n",
1018 cntrl & CNTRL_TFE ? "enabled" : "disabled");
1019 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1020 cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1021 v4l2_info(sd, "\tSignal polarity: %s\n",
1022 cntrl & CNTRL_CPL ? "0:mark 1:space" : "0:space 1:mark");
1023 if (cntrl & CNTRL_MOD) {
1024 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
1025 clock_divider_to_carrier_freq(txclk));
1026 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
1029 v4l2_info(sd, "\tMax pulse width: %u us, "
1031 pulse_width_count_to_us(FIFO_RXTX, txclk),
1032 pulse_width_count_to_ns(FIFO_RXTX, txclk));
1034 v4l2_info(sd, "\tBusy: %s\n",
1035 stats & STATS_TBY ? "yes" : "no");
1036 v4l2_info(sd, "\tFIFO service requested: %s\n",
1037 stats & STATS_TSR ? "yes" : "no");
1038 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1039 irqen & IRQEN_TSE ? "enabled" : "disabled");
1044 static inline int cx23888_ir_dbg_match(const struct v4l2_dbg_match *match)
1046 return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 2;
1049 static int cx23888_ir_g_chip_ident(struct v4l2_subdev *sd,
1050 struct v4l2_dbg_chip_ident *chip)
1052 struct cx23888_ir_state *state = to_state(sd);
1054 if (cx23888_ir_dbg_match(&chip->match)) {
1055 chip->ident = state->id;
1056 chip->revision = state->rev;
1061 #ifdef CONFIG_VIDEO_ADV_DEBUG
1062 static int cx23888_ir_g_register(struct v4l2_subdev *sd,
1063 struct v4l2_dbg_register *reg)
1065 struct cx23888_ir_state *state = to_state(sd);
1066 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1068 if (!cx23888_ir_dbg_match(®->match))
1070 if ((addr & 0x3) != 0)
1072 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1074 if (!capable(CAP_SYS_ADMIN))
1077 reg->val = cx23888_ir_read4(state->dev, addr);
1081 static int cx23888_ir_s_register(struct v4l2_subdev *sd,
1082 struct v4l2_dbg_register *reg)
1084 struct cx23888_ir_state *state = to_state(sd);
1085 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
1087 if (!cx23888_ir_dbg_match(®->match))
1089 if ((addr & 0x3) != 0)
1091 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
1093 if (!capable(CAP_SYS_ADMIN))
1095 cx23888_ir_write4(state->dev, addr, reg->val);
1100 static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = {
1101 .g_chip_ident = cx23888_ir_g_chip_ident,
1102 .log_status = cx23888_ir_log_status,
1103 #ifdef CONFIG_VIDEO_ADV_DEBUG
1104 .g_register = cx23888_ir_g_register,
1105 .s_register = cx23888_ir_s_register,
1109 static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = {
1110 .interrupt_service_routine = cx23888_ir_irq_handler,
1112 .rx_read = cx23888_ir_rx_read,
1113 .rx_g_parameters = cx23888_ir_rx_g_parameters,
1114 .rx_s_parameters = cx23888_ir_rx_s_parameters,
1116 .tx_write = cx23888_ir_tx_write,
1117 .tx_g_parameters = cx23888_ir_tx_g_parameters,
1118 .tx_s_parameters = cx23888_ir_tx_s_parameters,
1121 static const struct v4l2_subdev_ops cx23888_ir_controller_ops = {
1122 .core = &cx23888_ir_core_ops,
1123 .ir = &cx23888_ir_ir_ops,
1126 static const struct v4l2_subdev_ir_parameters default_rx_params = {
1127 .bytes_per_data_element = sizeof(u32),
1128 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1131 .interrupt_enable = false,
1135 .carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */
1137 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1138 /* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1139 .noise_filter_min_width = 333333, /* ns */
1140 .carrier_range_lower = 35000,
1141 .carrier_range_upper = 37000,
1145 static const struct v4l2_subdev_ir_parameters default_tx_params = {
1146 .bytes_per_data_element = sizeof(u32),
1147 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1150 .interrupt_enable = false,
1154 .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1155 .duty_cycle = 25, /* 25 % - RC-5 carrier */
1159 int cx23888_ir_probe(struct cx23885_dev *dev)
1161 struct cx23888_ir_state *state;
1162 struct v4l2_subdev *sd;
1163 struct v4l2_subdev_ir_parameters default_params;
1166 state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL);
1170 spin_lock_init(&state->rx_kfifo_lock);
1171 state->rx_kfifo = kfifo_alloc(CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL,
1172 &state->rx_kfifo_lock);
1173 if (state->rx_kfifo == NULL)
1176 spin_lock_init(&state->tx_kfifo_lock);
1177 state->tx_kfifo = kfifo_alloc(CX23888_IR_TX_KFIFO_SIZE, GFP_KERNEL,
1178 &state->tx_kfifo_lock);
1179 if (state->tx_kfifo == NULL) {
1180 kfifo_free(state->rx_kfifo);
1185 state->id = V4L2_IDENT_CX23888_IR;
1189 v4l2_subdev_init(sd, &cx23888_ir_controller_ops);
1190 v4l2_set_subdevdata(sd, state);
1191 /* FIXME - fix the formatting of dev->v4l2_dev.name and use it */
1192 snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name);
1193 sd->grp_id = CX23885_HW_888_IR;
1195 ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd);
1198 * Ensure no interrupts arrive from '888 specific conditions,
1199 * since we ignore them in this driver to have commonality with
1200 * similar IR controller cores.
1202 cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0);
1204 mutex_init(&state->rx_params_lock);
1205 memcpy(&default_params, &default_rx_params,
1206 sizeof(struct v4l2_subdev_ir_parameters));
1207 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1209 mutex_init(&state->tx_params_lock);
1210 memcpy(&default_params, &default_tx_params,
1211 sizeof(struct v4l2_subdev_ir_parameters));
1212 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1214 kfifo_free(state->rx_kfifo);
1215 kfifo_free(state->tx_kfifo);
1220 int cx23888_ir_remove(struct cx23885_dev *dev)
1222 struct v4l2_subdev *sd;
1223 struct cx23888_ir_state *state;
1225 sd = cx23885_find_hw(dev, CX23885_HW_888_IR);
1229 cx23888_ir_rx_shutdown(sd);
1230 cx23888_ir_tx_shutdown(sd);
1232 state = to_state(sd);
1233 v4l2_device_unregister_subdev(sd);
1234 kfifo_free(state->rx_kfifo);
1235 kfifo_free(state->tx_kfifo);
1237 /* Nothing more to free() as state held the actual v4l2_subdev object */