drivers/media/video/cx25840/cx25840-core.c

   1 /* cx25840 - Conexant CX25840 audio/video decoder driver
   2  *
   3  * Copyright (C) 2004 Ulf Eklund
   4  *
   5  * Based on the saa7115 driver and on the first verison of Chris Kennedy's
   6  * cx25840 driver.
   7  *
   8  * Changes by Tyler Trafford <tatrafford@comcast.net>
   9  *    - cleanup/rewrite for V4L2 API (2005)
  10  *
  11  * VBI support by Hans Verkuil <hverkuil@xs4all.nl>.
  12  *
  13  * NTSC sliced VBI support by Christopher Neufeld <television@cneufeld.ca>
  14  * with additional fixes by Hans Verkuil <hverkuil@xs4all.nl>.
  15  *
  16  * CX23885 support by Steven Toth <stoth@linuxtv.org>.
  17  *
  18  * CX2388[578] IRQ handling, IO Pin mux configuration and other small fixes are
  19  * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net>
  20  *
  21  * This program is free software; you can redistribute it and/or
  22  * modify it under the terms of the GNU General Public License
  23  * as published by the Free Software Foundation; either version 2
  24  * of the License, or (at your option) any later version.
  25  *
  26  * This program is distributed in the hope that it will be useful,
  27  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  28  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  29  * GNU General Public License for more details.
  30  *
  31  * You should have received a copy of the GNU General Public License
  32  * along with this program; if not, write to the Free Software
  33  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  34  */
  35
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/slab.h>
  40 #include <linux/videodev2.h>
  41 #include <linux/i2c.h>
  42 #include <linux/delay.h>
  43 #include <media/v4l2-common.h>
  44 #include <media/v4l2-chip-ident.h>
  45 #include <media/cx25840.h>
  46
  47 #include "cx25840-core.h"
  48
  49 MODULE_DESCRIPTION("Conexant CX25840 audio/video decoder driver");
  50 MODULE_AUTHOR("Ulf Eklund, Chris Kennedy, Hans Verkuil, Tyler Trafford");
  51 MODULE_LICENSE("GPL");
  52
  53 #define CX25840_VID_INT_STAT_REG 0x410
  54 #define CX25840_VID_INT_STAT_BITS 0x0000ffff
  55 #define CX25840_VID_INT_MASK_BITS 0xffff0000
  56 #define CX25840_VID_INT_MASK_SHFT 16
  57 #define CX25840_VID_INT_MASK_REG 0x412
  58
  59 #define CX23885_AUD_MC_INT_MASK_REG 0x80c
  60 #define CX23885_AUD_MC_INT_STAT_BITS 0xffff0000
  61 #define CX23885_AUD_MC_INT_CTRL_BITS 0x0000ffff
  62 #define CX23885_AUD_MC_INT_STAT_SHFT 16
  63
  64 #define CX25840_AUD_INT_CTRL_REG 0x812
  65 #define CX25840_AUD_INT_STAT_REG 0x813
  66
  67 #define CX23885_PIN_CTRL_IRQ_REG 0x123
  68 #define CX23885_PIN_CTRL_IRQ_IR_STAT  0x40
  69 #define CX23885_PIN_CTRL_IRQ_AUD_STAT 0x20
  70 #define CX23885_PIN_CTRL_IRQ_VID_STAT 0x10
  71
  72 #define CX25840_IR_STATS_REG    0x210
  73 #define CX25840_IR_IRQEN_REG    0x214
  74
  75 static int cx25840_debug;
  76
  77 module_param_named(debug,cx25840_debug, int, 0644);
  78
  79 MODULE_PARM_DESC(debug, "Debugging messages [0=Off (default) 1=On]");
  80
  81
  82 /* ----------------------------------------------------------------------- */
  83
  84 int cx25840_write(struct i2c_client *client, u16 addr, u8 value)
  85 {
  86         u8 buffer[3];
  87         buffer[0] = addr >> 8;
  88         buffer[1] = addr & 0xff;
  89         buffer[2] = value;
  90         return i2c_master_send(client, buffer, 3);
  91 }
  92
  93 int cx25840_write4(struct i2c_client *client, u16 addr, u32 value)
  94 {
  95         u8 buffer[6];
  96         buffer[0] = addr >> 8;
  97         buffer[1] = addr & 0xff;
  98         buffer[2] = value & 0xff;
  99         buffer[3] = (value >> 8) & 0xff;
 100         buffer[4] = (value >> 16) & 0xff;
 101         buffer[5] = value >> 24;
 102         return i2c_master_send(client, buffer, 6);
 103 }
 104
 105 u8 cx25840_read(struct i2c_client * client, u16 addr)
 106 {
 107         struct i2c_msg msgs[2];
 108         u8 tx_buf[2], rx_buf[1];
 109
 110         /* Write register address */
 111         tx_buf[0] = addr >> 8;
 112         tx_buf[1] = addr & 0xff;
 113         msgs[0].addr = client->addr;
 114         msgs[0].flags = 0;
 115         msgs[0].len = 2;
 116         msgs[0].buf = (char *) tx_buf;
 117
 118         /* Read data from register */
 119         msgs[1].addr = client->addr;
 120         msgs[1].flags = I2C_M_RD;
 121         msgs[1].len = 1;
 122         msgs[1].buf = (char *) rx_buf;
 123
 124         if (i2c_transfer(client->adapter, msgs, 2) < 2)
 125                 return 0;
 126
 127         return rx_buf[0];
 128 }
 129
 130 u32 cx25840_read4(struct i2c_client * client, u16 addr)
 131 {
 132         struct i2c_msg msgs[2];
 133         u8 tx_buf[2], rx_buf[4];
 134
 135         /* Write register address */
 136         tx_buf[0] = addr >> 8;
 137         tx_buf[1] = addr & 0xff;
 138         msgs[0].addr = client->addr;
 139         msgs[0].flags = 0;
 140         msgs[0].len = 2;
 141         msgs[0].buf = (char *) tx_buf;
 142
 143         /* Read data from registers */
 144         msgs[1].addr = client->addr;
 145         msgs[1].flags = I2C_M_RD;
 146         msgs[1].len = 4;
 147         msgs[1].buf = (char *) rx_buf;
 148
 149         if (i2c_transfer(client->adapter, msgs, 2) < 2)
 150                 return 0;
 151
 152         return (rx_buf[3] << 24) | (rx_buf[2] << 16) | (rx_buf[1] << 8) |
 153                 rx_buf[0];
 154 }
 155
 156 int cx25840_and_or(struct i2c_client *client, u16 addr, unsigned and_mask,
 157                    u8 or_value)
 158 {
 159         return cx25840_write(client, addr,
 160                              (cx25840_read(client, addr) & and_mask) |
 161                              or_value);
 162 }
 163
 164 int cx25840_and_or4(struct i2c_client *client, u16 addr, u32 and_mask,
 165                     u32 or_value)
 166 {
 167         return cx25840_write4(client, addr,
 168                               (cx25840_read4(client, addr) & and_mask) |
 169                               or_value);
 170 }
 171
 172 /* ----------------------------------------------------------------------- */
 173
 174 static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
 175                                                 enum cx25840_audio_input aud_input);
 176
 177 /* ----------------------------------------------------------------------- */
 178
 179 static int cx23885_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
 180                                       struct v4l2_subdev_io_pin_config *p)
 181 {
 182         struct i2c_client *client = v4l2_get_subdevdata(sd);
 183         int i;
 184         u32 pin_ctrl;
 185         u8 gpio_oe, gpio_data, strength;
 186
 187         pin_ctrl = cx25840_read4(client, 0x120);
 188         gpio_oe = cx25840_read(client, 0x160);
 189         gpio_data = cx25840_read(client, 0x164);
 190
 191         for (i = 0; i < n; i++) {
 192                 strength = p[i].strength;
 193                 if (strength > CX25840_PIN_DRIVE_FAST)
 194                         strength = CX25840_PIN_DRIVE_FAST;
 195
 196                 switch (p[i].pin) {
 197                 case CX23885_PIN_IRQ_N_GPIO16:
 198                         if (p[i].function != CX23885_PAD_IRQ_N) {
 199                                 /* GPIO16 */
 200                                 pin_ctrl &= ~(0x1 << 25);
 201                         } else {
 202                                 /* IRQ_N */
 203                                 if (p[i].flags &
 204                                         (V4L2_SUBDEV_IO_PIN_DISABLE |
 205                                          V4L2_SUBDEV_IO_PIN_INPUT)) {
 206                                         pin_ctrl &= ~(0x1 << 25);
 207                                 } else {
 208                                         pin_ctrl |= (0x1 << 25);
 209                                 }
 210                                 if (p[i].flags &
 211                                         V4L2_SUBDEV_IO_PIN_ACTIVE_LOW) {
 212                                         pin_ctrl &= ~(0x1 << 24);
 213                                 } else {
 214                                         pin_ctrl |= (0x1 << 24);
 215                                 }
 216                         }
 217                         break;
 218                 case CX23885_PIN_IR_RX_GPIO19:
 219                         if (p[i].function != CX23885_PAD_GPIO19) {
 220                                 /* IR_RX */
 221                                 gpio_oe |= (0x1 << 0);
 222                                 pin_ctrl &= ~(0x3 << 18);
 223                                 pin_ctrl |= (strength << 18);
 224                         } else {
 225                                 /* GPIO19 */
 226                                 gpio_oe &= ~(0x1 << 0);
 227                                 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
 228                                         gpio_data &= ~(0x1 << 0);
 229                                         gpio_data |= ((p[i].value & 0x1) << 0);
 230                                 }
 231                                 pin_ctrl &= ~(0x3 << 12);
 232                                 pin_ctrl |= (strength << 12);
 233                         }
 234                         break;
 235                 case CX23885_PIN_IR_TX_GPIO20:
 236                         if (p[i].function != CX23885_PAD_GPIO20) {
 237                                 /* IR_TX */
 238                                 gpio_oe |= (0x1 << 1);
 239                                 if (p[i].flags & V4L2_SUBDEV_IO_PIN_DISABLE)
 240                                         pin_ctrl &= ~(0x1 << 10);
 241                                 else
 242                                         pin_ctrl |= (0x1 << 10);
 243                                 pin_ctrl &= ~(0x3 << 18);
 244                                 pin_ctrl |= (strength << 18);
 245                         } else {
 246                                 /* GPIO20 */
 247                                 gpio_oe &= ~(0x1 << 1);
 248                                 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
 249                                         gpio_data &= ~(0x1 << 1);
 250                                         gpio_data |= ((p[i].value & 0x1) << 1);
 251                                 }
 252                                 pin_ctrl &= ~(0x3 << 12);
 253                                 pin_ctrl |= (strength << 12);
 254                         }
 255                         break;
 256                 case CX23885_PIN_I2S_SDAT_GPIO21:
 257                         if (p[i].function != CX23885_PAD_GPIO21) {
 258                                 /* I2S_SDAT */
 259                                 /* TODO: Input or Output config */
 260                                 gpio_oe |= (0x1 << 2);
 261                                 pin_ctrl &= ~(0x3 << 22);
 262                                 pin_ctrl |= (strength << 22);
 263                         } else {
 264                                 /* GPIO21 */
 265                                 gpio_oe &= ~(0x1 << 2);
 266                                 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
 267                                         gpio_data &= ~(0x1 << 2);
 268                                         gpio_data |= ((p[i].value & 0x1) << 2);
 269                                 }
 270                                 pin_ctrl &= ~(0x3 << 12);
 271                                 pin_ctrl |= (strength << 12);
 272                         }
 273                         break;
 274                 case CX23885_PIN_I2S_WCLK_GPIO22:
 275                         if (p[i].function != CX23885_PAD_GPIO22) {
 276                                 /* I2S_WCLK */
 277                                 /* TODO: Input or Output config */
 278                                 gpio_oe |= (0x1 << 3);
 279                                 pin_ctrl &= ~(0x3 << 22);
 280                                 pin_ctrl |= (strength << 22);
 281                         } else {
 282                                 /* GPIO22 */
 283                                 gpio_oe &= ~(0x1 << 3);
 284                                 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
 285                                         gpio_data &= ~(0x1 << 3);
 286                                         gpio_data |= ((p[i].value & 0x1) << 3);
 287                                 }
 288                                 pin_ctrl &= ~(0x3 << 12);
 289                                 pin_ctrl |= (strength << 12);
 290                         }
 291                         break;
 292                 case CX23885_PIN_I2S_BCLK_GPIO23:
 293                         if (p[i].function != CX23885_PAD_GPIO23) {
 294                                 /* I2S_BCLK */
 295                                 /* TODO: Input or Output config */
 296                                 gpio_oe |= (0x1 << 4);
 297                                 pin_ctrl &= ~(0x3 << 22);
 298                                 pin_ctrl |= (strength << 22);
 299                         } else {
 300                                 /* GPIO23 */
 301                                 gpio_oe &= ~(0x1 << 4);
 302                                 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
 303                                         gpio_data &= ~(0x1 << 4);
 304                                         gpio_data |= ((p[i].value & 0x1) << 4);
 305                                 }
 306                                 pin_ctrl &= ~(0x3 << 12);
 307                                 pin_ctrl |= (strength << 12);
 308                         }
 309                         break;
 310                 }
 311         }
 312
 313         cx25840_write(client, 0x164, gpio_data);
 314         cx25840_write(client, 0x160, gpio_oe);
 315         cx25840_write4(client, 0x120, pin_ctrl);
 316         return 0;
 317 }
 318
 319 static int common_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
 320                                       struct v4l2_subdev_io_pin_config *pincfg)
 321 {
 322         struct cx25840_state *state = to_state(sd);
 323
 324         if (is_cx2388x(state))
 325                 return cx23885_s_io_pin_config(sd, n, pincfg);
 326         return 0;
 327 }
 328
 329 /* ----------------------------------------------------------------------- */
 330
 331 static void init_dll1(struct i2c_client *client)
 332 {
 333         /* This is the Hauppauge sequence used to
 334          * initialize the Delay Lock Loop 1 (ADC DLL). */
 335         cx25840_write(client, 0x159, 0x23);
 336         cx25840_write(client, 0x15a, 0x87);
 337         cx25840_write(client, 0x15b, 0x06);
 338         udelay(10);
 339         cx25840_write(client, 0x159, 0xe1);
 340         udelay(10);
 341         cx25840_write(client, 0x15a, 0x86);
 342         cx25840_write(client, 0x159, 0xe0);
 343         cx25840_write(client, 0x159, 0xe1);
 344         cx25840_write(client, 0x15b, 0x10);
 345 }
 346
 347 static void init_dll2(struct i2c_client *client)
 348 {
 349         /* This is the Hauppauge sequence used to
 350          * initialize the Delay Lock Loop 2 (ADC DLL). */
 351         cx25840_write(client, 0x15d, 0xe3);
 352         cx25840_write(client, 0x15e, 0x86);
 353         cx25840_write(client, 0x15f, 0x06);
 354         udelay(10);
 355         cx25840_write(client, 0x15d, 0xe1);
 356         cx25840_write(client, 0x15d, 0xe0);
 357         cx25840_write(client, 0x15d, 0xe1);
 358 }
 359
 360 static void cx25836_initialize(struct i2c_client *client)
 361 {
 362         /* reset configuration is described on page 3-77 of the CX25836 datasheet */
 363         /* 2. */
 364         cx25840_and_or(client, 0x000, ~0x01, 0x01);
 365         cx25840_and_or(client, 0x000, ~0x01, 0x00);
 366         /* 3a. */
 367         cx25840_and_or(client, 0x15a, ~0x70, 0x00);
 368         /* 3b. */
 369         cx25840_and_or(client, 0x15b, ~0x1e, 0x06);
 370         /* 3c. */
 371         cx25840_and_or(client, 0x159, ~0x02, 0x02);
 372         /* 3d. */
 373         udelay(10);
 374         /* 3e. */
 375         cx25840_and_or(client, 0x159, ~0x02, 0x00);
 376         /* 3f. */
 377         cx25840_and_or(client, 0x159, ~0xc0, 0xc0);
 378         /* 3g. */
 379         cx25840_and_or(client, 0x159, ~0x01, 0x00);
 380         cx25840_and_or(client, 0x159, ~0x01, 0x01);
 381         /* 3h. */
 382         cx25840_and_or(client, 0x15b, ~0x1e, 0x10);
 383 }
 384
 385 static void cx25840_work_handler(struct work_struct *work)
 386 {
 387         struct cx25840_state *state = container_of(work, struct cx25840_state, fw_work);
 388         cx25840_loadfw(state->c);
 389         wake_up(&state->fw_wait);
 390 }
 391
 392 static void cx25840_initialize(struct i2c_client *client)
 393 {
 394         DEFINE_WAIT(wait);
 395         struct cx25840_state *state = to_state(i2c_get_clientdata(client));
 396         struct workqueue_struct *q;
 397
 398         /* datasheet startup in numbered steps, refer to page 3-77 */
 399         /* 2. */
 400         cx25840_and_or(client, 0x803, ~0x10, 0x00);
 401         /* The default of this register should be 4, but I get 0 instead.
 402          * Set this register to 4 manually. */
 403         cx25840_write(client, 0x000, 0x04);
 404         /* 3. */
 405         init_dll1(client);
 406         init_dll2(client);
 407         cx25840_write(client, 0x136, 0x0a);
 408         /* 4. */
 409         cx25840_write(client, 0x13c, 0x01);
 410         cx25840_write(client, 0x13c, 0x00);
 411         /* 5. */
 412         /* Do the firmware load in a work handler to prevent.
 413            Otherwise the kernel is blocked waiting for the
 414            bit-banging i2c interface to finish uploading the
 415            firmware. */
 416         INIT_WORK(&state->fw_work, cx25840_work_handler);
 417         init_waitqueue_head(&state->fw_wait);
 418         q = create_singlethread_workqueue("cx25840_fw");
 419         prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
 420         queue_work(q, &state->fw_work);
 421         schedule();
 422         finish_wait(&state->fw_wait, &wait);
 423         destroy_workqueue(q);
 424
 425         /* 6. */
 426         cx25840_write(client, 0x115, 0x8c);
 427         cx25840_write(client, 0x116, 0x07);
 428         cx25840_write(client, 0x118, 0x02);
 429         /* 7. */
 430         cx25840_write(client, 0x4a5, 0x80);
 431         cx25840_write(client, 0x4a5, 0x00);
 432         cx25840_write(client, 0x402, 0x00);
 433         /* 8. */
 434         cx25840_and_or(client, 0x401, ~0x18, 0);
 435         cx25840_and_or(client, 0x4a2, ~0x10, 0x10);
 436         /* steps 8c and 8d are done in change_input() */
 437         /* 10. */
 438         cx25840_write(client, 0x8d3, 0x1f);
 439         cx25840_write(client, 0x8e3, 0x03);
 440
 441         cx25840_std_setup(client);
 442
 443         /* trial and error says these are needed to get audio */
 444         cx25840_write(client, 0x914, 0xa0);
 445         cx25840_write(client, 0x918, 0xa0);
 446         cx25840_write(client, 0x919, 0x01);
 447
 448         /* stereo prefered */
 449         cx25840_write(client, 0x809, 0x04);
 450         /* AC97 shift */
 451         cx25840_write(client, 0x8cf, 0x0f);
 452
 453         /* (re)set input */
 454         set_input(client, state->vid_input, state->aud_input);
 455
 456         /* start microcontroller */
 457         cx25840_and_or(client, 0x803, ~0x10, 0x10);
 458 }
 459
 460 static void cx23885_initialize(struct i2c_client *client)
 461 {
 462         DEFINE_WAIT(wait);
 463         struct cx25840_state *state = to_state(i2c_get_clientdata(client));
 464         struct workqueue_struct *q;
 465
 466         /*
 467          * Come out of digital power down
 468          * The CX23888, at least, needs this, otherwise registers aside from
 469          * 0x0-0x2 can't be read or written.
 470          */
 471         cx25840_write(client, 0x000, 0);
 472
 473         /* Internal Reset */
 474         cx25840_and_or(client, 0x102, ~0x01, 0x01);
 475         cx25840_and_or(client, 0x102, ~0x01, 0x00);
 476
 477         /* Stop microcontroller */
 478         cx25840_and_or(client, 0x803, ~0x10, 0x00);
 479
 480         /* DIF in reset? */
 481         cx25840_write(client, 0x398, 0);
 482
 483         /*
 484          * Trust the default xtal, no division
 485          * '885: 28.636363... MHz
 486          * '887: 25.000000 MHz
 487          * '888: 50.000000 MHz
 488          */
 489         cx25840_write(client, 0x2, 0x76);
 490
 491         /* Power up all the PLL's and DLL */
 492         cx25840_write(client, 0x1, 0x40);
 493
 494         /* Sys PLL */
 495         switch (state->id) {
 496         case V4L2_IDENT_CX23888_AV:
 497                 /*
 498                  * 50.0 MHz * (0xb + 0xe8ba26/0x2000000)/4 = 5 * 28.636363 MHz
 499                  * 572.73 MHz before post divide
 500                  */
 501                 cx25840_write4(client, 0x11c, 0x00e8ba26);
 502                 cx25840_write4(client, 0x118, 0x0000040b);
 503                 break;
 504         case V4L2_IDENT_CX23887_AV:
 505                 /*
 506                  * 25.0 MHz * (0x16 + 0x1d1744c/0x2000000)/4 = 5 * 28.636363 MHz
 507                  * 572.73 MHz before post divide
 508                  */
 509                 cx25840_write4(client, 0x11c, 0x01d1744c);
 510                 cx25840_write4(client, 0x118, 0x00000416);
 511                 break;
 512         case V4L2_IDENT_CX23885_AV:
 513         default:
 514                 /*
 515                  * 28.636363 MHz * (0x14 + 0x0/0x2000000)/4 = 5 * 28.636363 MHz
 516                  * 572.73 MHz before post divide
 517                  */
 518                 cx25840_write4(client, 0x11c, 0x00000000);
 519                 cx25840_write4(client, 0x118, 0x00000414);
 520                 break;
 521         }
 522
 523         /* Disable DIF bypass */
 524         cx25840_write4(client, 0x33c, 0x00000001);
 525
 526         /* DIF Src phase inc */
 527         cx25840_write4(client, 0x340, 0x0df7df83);
 528
 529         /*
 530          * Vid PLL
 531          * Setup for a BT.656 pixel clock of 13.5 Mpixels/second
 532          *
 533          * 28.636363 MHz * (0xf + 0x02be2c9/0x2000000)/4 = 8 * 13.5 MHz
 534          * 432.0 MHz before post divide
 535          */
 536         cx25840_write4(client, 0x10c, 0x002be2c9);
 537         cx25840_write4(client, 0x108, 0x0000040f);
 538
 539         /* Luma */
 540         cx25840_write4(client, 0x414, 0x00107d12);
 541
 542         /* Chroma */
 543         cx25840_write4(client, 0x420, 0x3d008282);
 544
 545         /*
 546          * Aux PLL
 547          * Initial setup for audio sample clock:
 548          * 48 ksps, 16 bits/sample, x160 multiplier = 122.88 MHz
 549          * Intial I2S output/master clock(?):
 550          * 48 ksps, 16 bits/sample, x16 multiplier = 12.288 MHz
 551          */
 552         switch (state->id) {
 553         case V4L2_IDENT_CX23888_AV:
 554                 /*
 555                  * 50.0 MHz * (0x7 + 0x0bedfa4/0x2000000)/3 = 122.88 MHz
 556                  * 368.64 MHz before post divide
 557                  * 122.88 MHz / 0xa = 12.288 MHz
 558                  */
 559                 cx25840_write4(client, 0x114, 0x00bedfa4);
 560                 cx25840_write4(client, 0x110, 0x000a0307);
 561                 break;
 562         case V4L2_IDENT_CX23887_AV:
 563                 /*
 564                  * 25.0 MHz * (0xe + 0x17dbf48/0x2000000)/3 = 122.88 MHz
 565                  * 368.64 MHz before post divide
 566                  * 122.88 MHz / 0xa = 12.288 MHz
 567                  */
 568                 cx25840_write4(client, 0x114, 0x017dbf48);
 569                 cx25840_write4(client, 0x110, 0x000a030e);
 570                 break;
 571         case V4L2_IDENT_CX23885_AV:
 572         default:
 573                 /*
 574                  * 28.636363 MHz * (0xc + 0x1bf0c9e/0x2000000)/3 = 122.88 MHz
 575                  * 368.64 MHz before post divide
 576                  * 122.88 MHz / 0xa = 12.288 MHz
 577                  */
 578                 cx25840_write4(client, 0x114, 0x01bf0c9e);
 579                 cx25840_write4(client, 0x110, 0x000a030c);
 580                 break;
 581         };
 582
 583         /* ADC2 input select */
 584         cx25840_write(client, 0x102, 0x10);
 585
 586         /* VIN1 & VIN5 */
 587         cx25840_write(client, 0x103, 0x11);
 588
 589         /* Enable format auto detect */
 590         cx25840_write(client, 0x400, 0);
 591         /* Fast subchroma lock */
 592         /* White crush, Chroma AGC & Chroma Killer enabled */
 593         cx25840_write(client, 0x401, 0xe8);
 594
 595         /* Select AFE clock pad output source */
 596         cx25840_write(client, 0x144, 0x05);
 597
 598         /* Drive GPIO2 direction and values for HVR1700
 599          * where an onboard mux selects the output of demodulator
 600          * vs the 417. Failure to set this results in no DTV.
 601          * It's safe to set this across all Hauppauge boards
 602          * currently, regardless of the board type.
 603          */
 604         cx25840_write(client, 0x160, 0x1d);
 605         cx25840_write(client, 0x164, 0x00);
 606
 607         /* Do the firmware load in a work handler to prevent.
 608            Otherwise the kernel is blocked waiting for the
 609            bit-banging i2c interface to finish uploading the
 610            firmware. */
 611         INIT_WORK(&state->fw_work, cx25840_work_handler);
 612         init_waitqueue_head(&state->fw_wait);
 613         q = create_singlethread_workqueue("cx25840_fw");
 614         prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
 615         queue_work(q, &state->fw_work);
 616         schedule();
 617         finish_wait(&state->fw_wait, &wait);
 618         destroy_workqueue(q);
 619
 620         cx25840_std_setup(client);
 621
 622         /* (re)set input */
 623         set_input(client, state->vid_input, state->aud_input);
 624
 625         /* start microcontroller */
 626         cx25840_and_or(client, 0x803, ~0x10, 0x10);
 627
 628         /* Disable and clear video interrupts - we don't use them */
 629         cx25840_write4(client, CX25840_VID_INT_STAT_REG, 0xffffffff);
 630
 631         /* Disable and clear audio interrupts - we don't use them */
 632         cx25840_write(client, CX25840_AUD_INT_CTRL_REG, 0xff);
 633         cx25840_write(client, CX25840_AUD_INT_STAT_REG, 0xff);
 634 }
 635
 636 /* ----------------------------------------------------------------------- */
 637
 638 static void cx231xx_initialize(struct i2c_client *client)
 639 {
 640         DEFINE_WAIT(wait);
 641         struct cx25840_state *state = to_state(i2c_get_clientdata(client));
 642         struct workqueue_struct *q;
 643
 644         /* Internal Reset */
 645         cx25840_and_or(client, 0x102, ~0x01, 0x01);
 646         cx25840_and_or(client, 0x102, ~0x01, 0x00);
 647
 648         /* Stop microcontroller */
 649         cx25840_and_or(client, 0x803, ~0x10, 0x00);
 650
 651         /* DIF in reset? */
 652         cx25840_write(client, 0x398, 0);
 653
 654         /* Trust the default xtal, no division */
 655         /* This changes for the cx23888 products */
 656         cx25840_write(client, 0x2, 0x76);
 657
 658         /* Bring down the regulator for AUX clk */
 659         cx25840_write(client, 0x1, 0x40);
 660
 661         /* Disable DIF bypass */
 662         cx25840_write4(client, 0x33c, 0x00000001);
 663
 664         /* DIF Src phase inc */
 665         cx25840_write4(client, 0x340, 0x0df7df83);
 666
 667         /* Luma */
 668         cx25840_write4(client, 0x414, 0x00107d12);
 669
 670         /* Chroma */
 671         cx25840_write4(client, 0x420, 0x3d008282);
 672
 673         /* ADC2 input select */
 674         cx25840_write(client, 0x102, 0x10);
 675
 676         /* VIN1 & VIN5 */
 677         cx25840_write(client, 0x103, 0x11);
 678
 679         /* Enable format auto detect */
 680         cx25840_write(client, 0x400, 0);
 681         /* Fast subchroma lock */
 682         /* White crush, Chroma AGC & Chroma Killer enabled */
 683         cx25840_write(client, 0x401, 0xe8);
 684
 685         /* Do the firmware load in a work handler to prevent.
 686            Otherwise the kernel is blocked waiting for the
 687            bit-banging i2c interface to finish uploading the
 688            firmware. */
 689         INIT_WORK(&state->fw_work, cx25840_work_handler);
 690         init_waitqueue_head(&state->fw_wait);
 691         q = create_singlethread_workqueue("cx25840_fw");
 692         prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
 693         queue_work(q, &state->fw_work);
 694         schedule();
 695         finish_wait(&state->fw_wait, &wait);
 696         destroy_workqueue(q);
 697
 698         cx25840_std_setup(client);
 699
 700         /* (re)set input */
 701         set_input(client, state->vid_input, state->aud_input);
 702
 703         /* start microcontroller */
 704         cx25840_and_or(client, 0x803, ~0x10, 0x10);
 705 }
 706
 707 /* ----------------------------------------------------------------------- */
 708
 709 void cx25840_std_setup(struct i2c_client *client)
 710 {
 711         struct cx25840_state *state = to_state(i2c_get_clientdata(client));
 712         v4l2_std_id std = state->std;
 713         int hblank, hactive, burst, vblank, vactive, sc;
 714         int vblank656, src_decimation;
 715         int luma_lpf, uv_lpf, comb;
 716         u32 pll_int, pll_frac, pll_post;
 717
 718         /* datasheet startup, step 8d */
 719         if (std & ~V4L2_STD_NTSC)
 720                 cx25840_write(client, 0x49f, 0x11);
 721         else
 722                 cx25840_write(client, 0x49f, 0x14);
 723
 724         if (std & V4L2_STD_625_50) {
 725                 hblank = 132;
 726                 hactive = 720;
 727                 burst = 93;
 728                 vblank = 36;
 729                 vactive = 580;
 730                 vblank656 = 40;
 731                 src_decimation = 0x21f;
 732                 luma_lpf = 2;
 733
 734                 if (std & V4L2_STD_SECAM) {
 735                         uv_lpf = 0;
 736                         comb = 0;
 737                         sc = 0x0a425f;
 738                 } else if (std == V4L2_STD_PAL_Nc) {
 739                         uv_lpf = 1;
 740                         comb = 0x20;
 741                         sc = 556453;
 742                 } else {
 743                         uv_lpf = 1;
 744                         comb = 0x20;
 745                         sc = 688739;
 746                 }
 747         } else {
 748                 hactive = 720;
 749                 hblank = 122;
 750                 vactive = 487;
 751                 luma_lpf = 1;
 752                 uv_lpf = 1;
 753
 754                 src_decimation = 0x21f;
 755                 if (std == V4L2_STD_PAL_60) {
 756                         vblank = 26;
 757                         vblank656 = 26;
 758                         burst = 0x5b;
 759                         luma_lpf = 2;
 760                         comb = 0x20;
 761                         sc = 688739;
 762                 } else if (std == V4L2_STD_PAL_M) {
 763                         vblank = 20;
 764                         vblank656 = 24;
 765                         burst = 0x61;
 766                         comb = 0x20;
 767                         sc = 555452;
 768                 } else {
 769                         vblank = 26;
 770                         vblank656 = 26;
 771                         burst = 0x5b;
 772                         comb = 0x66;
 773                         sc = 556063;
 774                 }
 775         }
 776
 777         /* DEBUG: Displays configured PLL frequency */
 778         if (!is_cx231xx(state)) {
 779                 pll_int = cx25840_read(client, 0x108);
 780                 pll_frac = cx25840_read4(client, 0x10c) & 0x1ffffff;
 781                 pll_post = cx25840_read(client, 0x109);
 782                 v4l_dbg(1, cx25840_debug, client,
 783                         "PLL regs = int: %u, frac: %u, post: %u\n",
 784                         pll_int, pll_frac, pll_post);
 785
 786                 if (pll_post) {
 787                         int fin, fsc;
 788                         int pll = (28636363L * ((((u64)pll_int) << 25L) + pll_frac)) >> 25L;
 789
 790                         pll /= pll_post;
 791                         v4l_dbg(1, cx25840_debug, client, "PLL = %d.%06d MHz\n",
 792                                         pll / 1000000, pll % 1000000);
 793                         v4l_dbg(1, cx25840_debug, client, "PLL/8 = %d.%06d MHz\n",
 794                                         pll / 8000000, (pll / 8) % 1000000);
 795
 796                         fin = ((u64)src_decimation * pll) >> 12;
 797                         v4l_dbg(1, cx25840_debug, client,
 798                                         "ADC Sampling freq = %d.%06d MHz\n",
 799                                         fin / 1000000, fin % 1000000);
 800
 801                         fsc = (((u64)sc) * pll) >> 24L;
 802                         v4l_dbg(1, cx25840_debug, client,
 803                                         "Chroma sub-carrier freq = %d.%06d MHz\n",
 804                                         fsc / 1000000, fsc % 1000000);
 805
 806                         v4l_dbg(1, cx25840_debug, client, "hblank %i, hactive %i, "
 807                                 "vblank %i, vactive %i, vblank656 %i, src_dec %i, "
 808                                 "burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, "
 809                                 "sc 0x%06x\n",
 810                                 hblank, hactive, vblank, vactive, vblank656,
 811                                 src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
 812                 }
 813         }
 814
 815         /* Sets horizontal blanking delay and active lines */
 816         cx25840_write(client, 0x470, hblank);
 817         cx25840_write(client, 0x471,
 818                         0xff & (((hblank >> 8) & 0x3) | (hactive << 4)));
 819         cx25840_write(client, 0x472, hactive >> 4);
 820
 821         /* Sets burst gate delay */
 822         cx25840_write(client, 0x473, burst);
 823
 824         /* Sets vertical blanking delay and active duration */
 825         cx25840_write(client, 0x474, vblank);
 826         cx25840_write(client, 0x475,
 827                         0xff & (((vblank >> 8) & 0x3) | (vactive << 4)));
 828         cx25840_write(client, 0x476, vactive >> 4);
 829         cx25840_write(client, 0x477, vblank656);
 830
 831         /* Sets src decimation rate */
 832         cx25840_write(client, 0x478, 0xff & src_decimation);
 833         cx25840_write(client, 0x479, 0xff & (src_decimation >> 8));
 834
 835         /* Sets Luma and UV Low pass filters */
 836         cx25840_write(client, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
 837
 838         /* Enables comb filters */
 839         cx25840_write(client, 0x47b, comb);
 840
 841         /* Sets SC Step*/
 842         cx25840_write(client, 0x47c, sc);
 843         cx25840_write(client, 0x47d, 0xff & sc >> 8);
 844         cx25840_write(client, 0x47e, 0xff & sc >> 16);
 845
 846         /* Sets VBI parameters */
 847         if (std & V4L2_STD_625_50) {
 848                 cx25840_write(client, 0x47f, 0x01);
 849                 state->vbi_line_offset = 5;
 850         } else {
 851                 cx25840_write(client, 0x47f, 0x00);
 852                 state->vbi_line_offset = 8;
 853         }
 854 }
 855
 856 /* ----------------------------------------------------------------------- */
 857
 858 static void input_change(struct i2c_client *client)
 859 {
 860         struct cx25840_state *state = to_state(i2c_get_clientdata(client));
 861         v4l2_std_id std = state->std;
 862
 863         /* Follow step 8c and 8d of section 3.16 in the cx25840 datasheet */
 864         if (std & V4L2_STD_SECAM) {
 865                 cx25840_write(client, 0x402, 0);
 866         }
 867         else {
 868                 cx25840_write(client, 0x402, 0x04);
 869                 cx25840_write(client, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
 870         }
 871         cx25840_and_or(client, 0x401, ~0x60, 0);
 872         cx25840_and_or(client, 0x401, ~0x60, 0x60);
 873
 874         /* Don't write into audio registers on cx2583x chips */
 875         if (is_cx2583x(state))
 876                 return;
 877
 878         cx25840_and_or(client, 0x810, ~0x01, 1);
 879
 880         if (state->radio) {
 881                 cx25840_write(client, 0x808, 0xf9);
 882                 cx25840_write(client, 0x80b, 0x00);
 883         }
 884         else if (std & V4L2_STD_525_60) {
 885                 /* Certain Hauppauge PVR150 models have a hardware bug
 886                    that causes audio to drop out. For these models the
 887                    audio standard must be set explicitly.
 888                    To be precise: it affects cards with tuner models
 889                    85, 99 and 112 (model numbers from tveeprom). */
 890                 int hw_fix = state->pvr150_workaround;
 891
 892                 if (std == V4L2_STD_NTSC_M_JP) {
 893                         /* Japan uses EIAJ audio standard */
 894                         cx25840_write(client, 0x808, hw_fix ? 0x2f : 0xf7);
 895                 } else if (std == V4L2_STD_NTSC_M_KR) {
 896                         /* South Korea uses A2 audio standard */
 897                         cx25840_write(client, 0x808, hw_fix ? 0x3f : 0xf8);
 898                 } else {
 899                         /* Others use the BTSC audio standard */
 900                         cx25840_write(client, 0x808, hw_fix ? 0x1f : 0xf6);
 901                 }
 902                 cx25840_write(client, 0x80b, 0x00);
 903         } else if (std & V4L2_STD_PAL) {
 904                 /* Autodetect audio standard and audio system */
 905                 cx25840_write(client, 0x808, 0xff);
 906                 /* Since system PAL-L is pretty much non-existant and
 907                    not used by any public broadcast network, force
 908                    6.5 MHz carrier to be interpreted as System DK,
 909                    this avoids DK audio detection instability */
 910                cx25840_write(client, 0x80b, 0x00);
 911         } else if (std & V4L2_STD_SECAM) {
 912                 /* Autodetect audio standard and audio system */
 913                 cx25840_write(client, 0x808, 0xff);
 914                 /* If only one of SECAM-DK / SECAM-L is required, then force
 915                   6.5MHz carrier, else autodetect it */
 916                 if ((std & V4L2_STD_SECAM_DK) &&
 917                     !(std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
 918                         /* 6.5 MHz carrier to be interpreted as System DK */
 919                         cx25840_write(client, 0x80b, 0x00);
 920                } else if (!(std & V4L2_STD_SECAM_DK) &&
 921                           (std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
 922                         /* 6.5 MHz carrier to be interpreted as System L */
 923                         cx25840_write(client, 0x80b, 0x08);
 924                } else {
 925                         /* 6.5 MHz carrier to be autodetected */
 926                         cx25840_write(client, 0x80b, 0x10);
 927                }
 928         }
 929
 930         cx25840_and_or(client, 0x810, ~0x01, 0);
 931 }
 932
 933 static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
 934                                                 enum cx25840_audio_input aud_input)
 935 {
 936         struct cx25840_state *state = to_state(i2c_get_clientdata(client));
 937         u8 is_composite = (vid_input >= CX25840_COMPOSITE1 &&
 938                            vid_input <= CX25840_COMPOSITE8);
 939         u8 is_component = (vid_input & CX25840_COMPONENT_ON) ==
 940                         CX25840_COMPONENT_ON;
 941         int luma = vid_input & 0xf0;
 942         int chroma = vid_input & 0xf00;
 943         u8 reg;
 944
 945         v4l_dbg(1, cx25840_debug, client,
 946                 "decoder set video input %d, audio input %d\n",
 947                 vid_input, aud_input);
 948
 949         if (vid_input >= CX25840_VIN1_CH1) {
 950                 v4l_dbg(1, cx25840_debug, client, "vid_input 0x%x\n",
 951                         vid_input);
 952                 reg = vid_input & 0xff;
 953                 is_composite = !is_component &&
 954                         ((vid_input & CX25840_SVIDEO_ON) != CX25840_SVIDEO_ON);
 955
 956                 v4l_dbg(1, cx25840_debug, client, "mux cfg 0x%x comp=%d\n",
 957                         reg, is_composite);
 958         } else if (is_composite) {
 959                 reg = 0xf0 + (vid_input - CX25840_COMPOSITE1);
 960         } else {
 961                 if ((vid_input & ~0xff0) ||
 962                     luma < CX25840_SVIDEO_LUMA1 || luma > CX25840_SVIDEO_LUMA8 ||
 963                     chroma < CX25840_SVIDEO_CHROMA4 || chroma > CX25840_SVIDEO_CHROMA8) {
 964                         v4l_err(client, "0x%04x is not a valid video input!\n",
 965                                 vid_input);
 966                         return -EINVAL;
 967                 }
 968                 reg = 0xf0 + ((luma - CX25840_SVIDEO_LUMA1) >> 4);
 969                 if (chroma >= CX25840_SVIDEO_CHROMA7) {
 970                         reg &= 0x3f;
 971                         reg |= (chroma - CX25840_SVIDEO_CHROMA7) >> 2;
 972                 } else {
 973                         reg &= 0xcf;
 974                         reg |= (chroma - CX25840_SVIDEO_CHROMA4) >> 4;
 975                 }
 976         }
 977
 978         /* The caller has previously prepared the correct routing
 979          * configuration in reg (for the cx23885) so we have no
 980          * need to attempt to flip bits for earlier av decoders.
 981          */
 982         if (!is_cx2388x(state) && !is_cx231xx(state)) {
 983                 switch (aud_input) {
 984                 case CX25840_AUDIO_SERIAL:
 985                         /* do nothing, use serial audio input */
 986                         break;
 987                 case CX25840_AUDIO4: reg &= ~0x30; break;
 988                 case CX25840_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
 989                 case CX25840_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
 990                 case CX25840_AUDIO7: reg &= ~0xc0; break;
 991                 case CX25840_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
 992
 993                 default:
 994                         v4l_err(client, "0x%04x is not a valid audio input!\n",
 995                                 aud_input);
 996                         return -EINVAL;
 997                 }
 998         }
 999
1000         cx25840_write(client, 0x103, reg);
1001
1002         /* Set INPUT_MODE to Composite, S-Video or Component */
1003         if (is_component)
1004                 cx25840_and_or(client, 0x401, ~0x6, 0x6);
1005         else
1006                 cx25840_and_or(client, 0x401, ~0x6, is_composite ? 0 : 0x02);
1007
1008         if (!is_cx2388x(state) && !is_cx231xx(state)) {
1009                 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
1010                 cx25840_and_or(client, 0x102, ~0x2, (reg & 0x80) == 0 ? 2 : 0);
1011                 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2&CH3 */
1012                 if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
1013                         cx25840_and_or(client, 0x102, ~0x4, 4);
1014                 else
1015                         cx25840_and_or(client, 0x102, ~0x4, 0);
1016         } else {
1017                 /* Set DUAL_MODE_ADC2 to 1 if component*/
1018                 cx25840_and_or(client, 0x102, ~0x4, is_component ? 0x4 : 0x0);
1019                 if (is_composite) {
1020                         /* ADC2 input select channel 2 */
1021                         cx25840_and_or(client, 0x102, ~0x2, 0);
1022                 } else if (!is_component) {
1023                         /* S-Video */
1024                         if (chroma >= CX25840_SVIDEO_CHROMA7) {
1025                                 /* ADC2 input select channel 3 */
1026                                 cx25840_and_or(client, 0x102, ~0x2, 2);
1027                         } else {
1028                                 /* ADC2 input select channel 2 */
1029                                 cx25840_and_or(client, 0x102, ~0x2, 0);
1030                         }
1031                 }
1032         }
1033
1034         state->vid_input = vid_input;
1035         state->aud_input = aud_input;
1036         cx25840_audio_set_path(client);
1037         input_change(client);
1038
1039         if (is_cx2388x(state)) {
1040                 /* Audio channel 1 src : Parallel 1 */
1041                 cx25840_write(client, 0x124, 0x03);
1042
1043                 /* Select AFE clock pad output source */
1044                 cx25840_write(client, 0x144, 0x05);
1045
1046                 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
1047                 cx25840_write(client, 0x914, 0xa0);
1048
1049                 /* I2S_OUT_CTL:
1050                  * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
1051                  * I2S_OUT_MASTER_MODE = Master
1052                  */
1053                 cx25840_write(client, 0x918, 0xa0);
1054                 cx25840_write(client, 0x919, 0x01);
1055         } else if (is_cx231xx(state)) {
1056                 /* Audio channel 1 src : Parallel 1 */
1057                 cx25840_write(client, 0x124, 0x03);
1058
1059                 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
1060                 cx25840_write(client, 0x914, 0xa0);
1061
1062                 /* I2S_OUT_CTL:
1063                  * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
1064                  * I2S_OUT_MASTER_MODE = Master
1065                  */
1066                 cx25840_write(client, 0x918, 0xa0);
1067                 cx25840_write(client, 0x919, 0x01);
1068         }
1069
1070         return 0;
1071 }
1072
1073 /* ----------------------------------------------------------------------- */
1074
1075 static int set_v4lstd(struct i2c_client *client)
1076 {
1077         struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1078         u8 fmt = 0;     /* zero is autodetect */
1079         u8 pal_m = 0;
1080
1081         /* First tests should be against specific std */
1082         if (state->std == V4L2_STD_NTSC_M_JP) {
1083                 fmt = 0x2;
1084         } else if (state->std == V4L2_STD_NTSC_443) {
1085                 fmt = 0x3;
1086         } else if (state->std == V4L2_STD_PAL_M) {
1087                 pal_m = 1;
1088                 fmt = 0x5;
1089         } else if (state->std == V4L2_STD_PAL_N) {
1090                 fmt = 0x6;
1091         } else if (state->std == V4L2_STD_PAL_Nc) {
1092                 fmt = 0x7;
1093         } else if (state->std == V4L2_STD_PAL_60) {
1094                 fmt = 0x8;
1095         } else {
1096                 /* Then, test against generic ones */
1097                 if (state->std & V4L2_STD_NTSC)
1098                         fmt = 0x1;
1099                 else if (state->std & V4L2_STD_PAL)
1100                         fmt = 0x4;
1101                 else if (state->std & V4L2_STD_SECAM)
1102                         fmt = 0xc;
1103         }
1104
1105         v4l_dbg(1, cx25840_debug, client, "changing video std to fmt %i\n",fmt);
1106
1107         /* Follow step 9 of section 3.16 in the cx25840 datasheet.
1108            Without this PAL may display a vertical ghosting effect.
1109            This happens for example with the Yuan MPC622. */
1110         if (fmt >= 4 && fmt < 8) {
1111                 /* Set format to NTSC-M */
1112                 cx25840_and_or(client, 0x400, ~0xf, 1);
1113                 /* Turn off LCOMB */
1114                 cx25840_and_or(client, 0x47b, ~6, 0);
1115         }
1116         cx25840_and_or(client, 0x400, ~0xf, fmt);
1117         cx25840_and_or(client, 0x403, ~0x3, pal_m);
1118         cx25840_std_setup(client);
1119         if (!is_cx2583x(state))
1120                 input_change(client);
1121         return 0;
1122 }
1123
1124 /* ----------------------------------------------------------------------- */
1125
1126 static int cx25840_s_ctrl(struct v4l2_ctrl *ctrl)
1127 {
1128         struct v4l2_subdev *sd = to_sd(ctrl);
1129         struct i2c_client *client = v4l2_get_subdevdata(sd);
1130
1131         switch (ctrl->id) {
1132         case V4L2_CID_BRIGHTNESS:
1133                 cx25840_write(client, 0x414, ctrl->val - 128);
1134                 break;
1135
1136         case V4L2_CID_CONTRAST:
1137                 cx25840_write(client, 0x415, ctrl->val << 1);
1138                 break;
1139
1140         case V4L2_CID_SATURATION:
1141                 cx25840_write(client, 0x420, ctrl->val << 1);
1142                 cx25840_write(client, 0x421, ctrl->val << 1);
1143                 break;
1144
1145         case V4L2_CID_HUE:
1146                 cx25840_write(client, 0x422, ctrl->val);
1147                 break;
1148
1149         default:
1150                 return -EINVAL;
1151         }
1152
1153         return 0;
1154 }
1155
1156 /* ----------------------------------------------------------------------- */
1157
1158 static int cx25840_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
1159 {
1160         struct cx25840_state *state = to_state(sd);
1161         struct i2c_client *client = v4l2_get_subdevdata(sd);
1162         int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
1163         int is_50Hz = !(state->std & V4L2_STD_525_60);
1164
1165         if (fmt->code != V4L2_MBUS_FMT_FIXED)
1166                 return -EINVAL;
1167
1168         fmt->field = V4L2_FIELD_INTERLACED;
1169         fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1170
1171         Vsrc = (cx25840_read(client, 0x476) & 0x3f) << 4;
1172         Vsrc |= (cx25840_read(client, 0x475) & 0xf0) >> 4;
1173
1174         Hsrc = (cx25840_read(client, 0x472) & 0x3f) << 4;
1175         Hsrc |= (cx25840_read(client, 0x471) & 0xf0) >> 4;
1176
1177         Vlines = fmt->height + (is_50Hz ? 4 : 7);
1178
1179         if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) ||
1180                         (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
1181                 v4l_err(client, "%dx%d is not a valid size!\n",
1182                                 fmt->width, fmt->height);
1183                 return -ERANGE;
1184         }
1185
1186         HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20);
1187         VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
1188         VSC &= 0x1fff;
1189
1190         if (fmt->width >= 385)
1191                 filter = 0;
1192         else if (fmt->width > 192)
1193                 filter = 1;
1194         else if (fmt->width > 96)
1195                 filter = 2;
1196         else
1197                 filter = 3;
1198
1199         v4l_dbg(1, cx25840_debug, client, "decoder set size %dx%d -> scale  %ux%u\n",
1200                         fmt->width, fmt->height, HSC, VSC);
1201
1202         /* HSCALE=HSC */
1203         cx25840_write(client, 0x418, HSC & 0xff);
1204         cx25840_write(client, 0x419, (HSC >> 8) & 0xff);
1205         cx25840_write(client, 0x41a, HSC >> 16);
1206         /* VSCALE=VSC */
1207         cx25840_write(client, 0x41c, VSC & 0xff);
1208         cx25840_write(client, 0x41d, VSC >> 8);
1209         /* VS_INTRLACE=1 VFILT=filter */
1210         cx25840_write(client, 0x41e, 0x8 | filter);
1211         return 0;
1212 }
1213
1214 /* ----------------------------------------------------------------------- */
1215
1216 static void log_video_status(struct i2c_client *client)
1217 {
1218         static const char *const fmt_strs[] = {
1219                 "0x0",
1220                 "NTSC-M", "NTSC-J", "NTSC-4.43",
1221                 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
1222                 "0x9", "0xA", "0xB",
1223                 "SECAM",
1224                 "0xD", "0xE", "0xF"
1225         };
1226
1227         struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1228         u8 vidfmt_sel = cx25840_read(client, 0x400) & 0xf;
1229         u8 gen_stat1 = cx25840_read(client, 0x40d);
1230         u8 gen_stat2 = cx25840_read(client, 0x40e);
1231         int vid_input = state->vid_input;
1232
1233         v4l_info(client, "Video signal:              %spresent\n",
1234                     (gen_stat2 & 0x20) ? "" : "not ");
1235         v4l_info(client, "Detected format:           %s\n",
1236                     fmt_strs[gen_stat1 & 0xf]);
1237
1238         v4l_info(client, "Specified standard:        %s\n",
1239                     vidfmt_sel ? fmt_strs[vidfmt_sel] : "automatic detection");
1240
1241         if (vid_input >= CX25840_COMPOSITE1 &&
1242             vid_input <= CX25840_COMPOSITE8) {
1243                 v4l_info(client, "Specified video input:     Composite %d\n",
1244                         vid_input - CX25840_COMPOSITE1 + 1);
1245         } else {
1246                 v4l_info(client, "Specified video input:     S-Video (Luma In%d, Chroma In%d)\n",
1247                         (vid_input & 0xf0) >> 4, (vid_input & 0xf00) >> 8);
1248         }
1249
1250         v4l_info(client, "Specified audioclock freq: %d Hz\n", state->audclk_freq);
1251 }
1252
1253 /* ----------------------------------------------------------------------- */
1254
1255 static void log_audio_status(struct i2c_client *client)
1256 {
1257         struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1258         u8 download_ctl = cx25840_read(client, 0x803);
1259         u8 mod_det_stat0 = cx25840_read(client, 0x804);
1260         u8 mod_det_stat1 = cx25840_read(client, 0x805);
1261         u8 audio_config = cx25840_read(client, 0x808);
1262         u8 pref_mode = cx25840_read(client, 0x809);
1263         u8 afc0 = cx25840_read(client, 0x80b);
1264         u8 mute_ctl = cx25840_read(client, 0x8d3);
1265         int aud_input = state->aud_input;
1266         char *p;
1267
1268         switch (mod_det_stat0) {
1269         case 0x00: p = "mono"; break;
1270         case 0x01: p = "stereo"; break;
1271         case 0x02: p = "dual"; break;
1272         case 0x04: p = "tri"; break;
1273         case 0x10: p = "mono with SAP"; break;
1274         case 0x11: p = "stereo with SAP"; break;
1275         case 0x12: p = "dual with SAP"; break;
1276         case 0x14: p = "tri with SAP"; break;
1277         case 0xfe: p = "forced mode"; break;
1278         default: p = "not defined";
1279         }
1280         v4l_info(client, "Detected audio mode:       %s\n", p);
1281
1282         switch (mod_det_stat1) {
1283         case 0x00: p = "not defined"; break;
1284         case 0x01: p = "EIAJ"; break;
1285         case 0x02: p = "A2-M"; break;
1286         case 0x03: p = "A2-BG"; break;
1287         case 0x04: p = "A2-DK1"; break;
1288         case 0x05: p = "A2-DK2"; break;
1289         case 0x06: p = "A2-DK3"; break;
1290         case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1291         case 0x08: p = "AM-L"; break;
1292         case 0x09: p = "NICAM-BG"; break;
1293         case 0x0a: p = "NICAM-DK"; break;
1294         case 0x0b: p = "NICAM-I"; break;
1295         case 0x0c: p = "NICAM-L"; break;
1296         case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1297         case 0x0e: p = "IF FM Radio"; break;
1298         case 0x0f: p = "BTSC"; break;
1299         case 0x10: p = "high-deviation FM"; break;
1300         case 0x11: p = "very high-deviation FM"; break;
1301         case 0xfd: p = "unknown audio standard"; break;
1302         case 0xfe: p = "forced audio standard"; break;
1303         case 0xff: p = "no detected audio standard"; break;
1304         default: p = "not defined";
1305         }
1306         v4l_info(client, "Detected audio standard:   %s\n", p);
1307         v4l_info(client, "Audio microcontroller:     %s\n",
1308                     (download_ctl & 0x10) ?
1309                                 ((mute_ctl & 0x2) ? "detecting" : "running") : "stopped");
1310
1311         switch (audio_config >> 4) {
1312         case 0x00: p = "undefined"; break;
1313         case 0x01: p = "BTSC"; break;
1314         case 0x02: p = "EIAJ"; break;
1315         case 0x03: p = "A2-M"; break;
1316         case 0x04: p = "A2-BG"; break;
1317         case 0x05: p = "A2-DK1"; break;
1318         case 0x06: p = "A2-DK2"; break;
1319         case 0x07: p = "A2-DK3"; break;
1320         case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1321         case 0x09: p = "AM-L"; break;
1322         case 0x0a: p = "NICAM-BG"; break;
1323         case 0x0b: p = "NICAM-DK"; break;
1324         case 0x0c: p = "NICAM-I"; break;
1325         case 0x0d: p = "NICAM-L"; break;
1326         case 0x0e: p = "FM radio"; break;
1327         case 0x0f: p = "automatic detection"; break;
1328         default: p = "undefined";
1329         }
1330         v4l_info(client, "Configured audio standard: %s\n", p);
1331
1332         if ((audio_config >> 4) < 0xF) {
1333                 switch (audio_config & 0xF) {
1334                 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1335                 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1336                 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1337                 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1338                 case 0x04: p = "STEREO"; break;
1339                 case 0x05: p = "DUAL1 (AB)"; break;
1340                 case 0x06: p = "DUAL2 (AC) (FM)"; break;
1341                 case 0x07: p = "DUAL3 (BC) (FM)"; break;
1342                 case 0x08: p = "DUAL4 (AC) (AM)"; break;
1343                 case 0x09: p = "DUAL5 (BC) (AM)"; break;
1344                 case 0x0a: p = "SAP"; break;
1345                 default: p = "undefined";
1346                 }
1347                 v4l_info(client, "Configured audio mode:     %s\n", p);
1348         } else {
1349                 switch (audio_config & 0xF) {
1350                 case 0x00: p = "BG"; break;
1351                 case 0x01: p = "DK1"; break;
1352                 case 0x02: p = "DK2"; break;
1353                 case 0x03: p = "DK3"; break;
1354                 case 0x04: p = "I"; break;
1355                 case 0x05: p = "L"; break;
1356                 case 0x06: p = "BTSC"; break;
1357                 case 0x07: p = "EIAJ"; break;
1358                 case 0x08: p = "A2-M"; break;
1359                 case 0x09: p = "FM Radio"; break;
1360                 case 0x0f: p = "automatic standard and mode detection"; break;
1361                 default: p = "undefined";
1362                 }
1363                 v4l_info(client, "Configured audio system:   %s\n", p);
1364         }
1365
1366         if (aud_input) {
1367                 v4l_info(client, "Specified audio input:     Tuner (In%d)\n", aud_input);
1368         } else {
1369                 v4l_info(client, "Specified audio input:     External\n");
1370         }
1371
1372         switch (pref_mode & 0xf) {
1373         case 0: p = "mono/language A"; break;
1374         case 1: p = "language B"; break;
1375         case 2: p = "language C"; break;
1376         case 3: p = "analog fallback"; break;
1377         case 4: p = "stereo"; break;
1378         case 5: p = "language AC"; break;
1379         case 6: p = "language BC"; break;
1380         case 7: p = "language AB"; break;
1381         default: p = "undefined";
1382         }
1383         v4l_info(client, "Preferred audio mode:      %s\n", p);
1384
1385         if ((audio_config & 0xf) == 0xf) {
1386                 switch ((afc0 >> 3) & 0x3) {
1387                 case 0: p = "system DK"; break;
1388                 case 1: p = "system L"; break;
1389                 case 2: p = "autodetect"; break;
1390                 default: p = "undefined";
1391                 }
1392                 v4l_info(client, "Selected 65 MHz format:    %s\n", p);
1393
1394                 switch (afc0 & 0x7) {
1395                 case 0: p = "chroma"; break;
1396                 case 1: p = "BTSC"; break;
1397                 case 2: p = "EIAJ"; break;
1398                 case 3: p = "A2-M"; break;
1399                 case 4: p = "autodetect"; break;
1400                 default: p = "undefined";
1401                 }
1402                 v4l_info(client, "Selected 45 MHz format:    %s\n", p);
1403         }
1404 }
1405
1406 /* ----------------------------------------------------------------------- */
1407
1408 /* This load_fw operation must be called to load the driver's firmware.
1409    Without this the audio standard detection will fail and you will
1410    only get mono.
1411
1412    Since loading the firmware is often problematic when the driver is
1413    compiled into the kernel I recommend postponing calling this function
1414    until the first open of the video device. Another reason for
1415    postponing it is that loading this firmware takes a long time (seconds)
1416    due to the slow i2c bus speed. So it will speed up the boot process if
1417    you can avoid loading the fw as long as the video device isn't used.  */
1418 static int cx25840_load_fw(struct v4l2_subdev *sd)
1419 {
1420         struct cx25840_state *state = to_state(sd);
1421         struct i2c_client *client = v4l2_get_subdevdata(sd);
1422
1423         if (!state->is_initialized) {
1424                 /* initialize and load firmware */
1425                 state->is_initialized = 1;
1426                 if (is_cx2583x(state))
1427                         cx25836_initialize(client);
1428                 else if (is_cx2388x(state))
1429                         cx23885_initialize(client);
1430                 else if (is_cx231xx(state))
1431                         cx231xx_initialize(client);
1432                 else
1433                         cx25840_initialize(client);
1434         }
1435         return 0;
1436 }
1437
1438 #ifdef CONFIG_VIDEO_ADV_DEBUG
1439 static int cx25840_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1440 {
1441         struct i2c_client *client = v4l2_get_subdevdata(sd);
1442
1443         if (!v4l2_chip_match_i2c_client(client, &reg->match))
1444                 return -EINVAL;
1445         if (!capable(CAP_SYS_ADMIN))
1446                 return -EPERM;
1447         reg->size = 1;
1448         reg->val = cx25840_read(client, reg->reg & 0x0fff);
1449         return 0;
1450 }
1451
1452 static int cx25840_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1453 {
1454         struct i2c_client *client = v4l2_get_subdevdata(sd);
1455
1456         if (!v4l2_chip_match_i2c_client(client, &reg->match))
1457                 return -EINVAL;
1458         if (!capable(CAP_SYS_ADMIN))
1459                 return -EPERM;
1460         cx25840_write(client, reg->reg & 0x0fff, reg->val & 0xff);
1461         return 0;
1462 }
1463 #endif
1464
1465 static int cx25840_s_audio_stream(struct v4l2_subdev *sd, int enable)
1466 {
1467         struct cx25840_state *state = to_state(sd);
1468         struct i2c_client *client = v4l2_get_subdevdata(sd);
1469         u8 v;
1470
1471         if (is_cx2583x(state) || is_cx2388x(state) || is_cx231xx(state))
1472                 return 0;
1473
1474         v4l_dbg(1, cx25840_debug, client, "%s audio output\n",
1475                         enable ? "enable" : "disable");
1476
1477         if (enable) {
1478                 v = cx25840_read(client, 0x115) | 0x80;
1479                 cx25840_write(client, 0x115, v);
1480                 v = cx25840_read(client, 0x116) | 0x03;
1481                 cx25840_write(client, 0x116, v);
1482         } else {
1483                 v = cx25840_read(client, 0x115) & ~(0x80);
1484                 cx25840_write(client, 0x115, v);
1485                 v = cx25840_read(client, 0x116) & ~(0x03);
1486                 cx25840_write(client, 0x116, v);
1487         }
1488         return 0;
1489 }
1490
1491 static int cx25840_s_stream(struct v4l2_subdev *sd, int enable)
1492 {
1493         struct cx25840_state *state = to_state(sd);
1494         struct i2c_client *client = v4l2_get_subdevdata(sd);
1495         u8 v;
1496
1497         v4l_dbg(1, cx25840_debug, client, "%s video output\n",
1498                         enable ? "enable" : "disable");
1499         if (enable) {
1500                 if (is_cx2388x(state) || is_cx231xx(state)) {
1501                         v = cx25840_read(client, 0x421) | 0x0b;
1502                         cx25840_write(client, 0x421, v);
1503                 } else {
1504                         v = cx25840_read(client, 0x115) | 0x0c;
1505                         cx25840_write(client, 0x115, v);
1506                         v = cx25840_read(client, 0x116) | 0x04;
1507                         cx25840_write(client, 0x116, v);
1508                 }
1509         } else {
1510                 if (is_cx2388x(state) || is_cx231xx(state)) {
1511                         v = cx25840_read(client, 0x421) & ~(0x0b);
1512                         cx25840_write(client, 0x421, v);
1513                 } else {
1514                         v = cx25840_read(client, 0x115) & ~(0x0c);
1515                         cx25840_write(client, 0x115, v);
1516                         v = cx25840_read(client, 0x116) & ~(0x04);
1517                         cx25840_write(client, 0x116, v);
1518                 }
1519         }
1520         return 0;
1521 }
1522
1523 static int cx25840_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1524 {
1525         struct cx25840_state *state = to_state(sd);
1526         struct i2c_client *client = v4l2_get_subdevdata(sd);
1527
1528         if (state->radio == 0 && state->std == std)
1529                 return 0;
1530         state->radio = 0;
1531         state->std = std;
1532         return set_v4lstd(client);
1533 }
1534
1535 static int cx25840_s_radio(struct v4l2_subdev *sd)
1536 {
1537         struct cx25840_state *state = to_state(sd);
1538
1539         state->radio = 1;
1540         return 0;
1541 }
1542
1543 static int cx25840_s_video_routing(struct v4l2_subdev *sd,
1544                                    u32 input, u32 output, u32 config)
1545 {
1546         struct cx25840_state *state = to_state(sd);
1547         struct i2c_client *client = v4l2_get_subdevdata(sd);
1548
1549         return set_input(client, input, state->aud_input);
1550 }
1551
1552 static int cx25840_s_audio_routing(struct v4l2_subdev *sd,
1553                                    u32 input, u32 output, u32 config)
1554 {
1555         struct cx25840_state *state = to_state(sd);
1556         struct i2c_client *client = v4l2_get_subdevdata(sd);
1557
1558         return set_input(client, state->vid_input, input);
1559 }
1560
1561 static int cx25840_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1562 {
1563         struct i2c_client *client = v4l2_get_subdevdata(sd);
1564
1565         input_change(client);
1566         return 0;
1567 }
1568
1569 static int cx25840_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1570 {
1571         struct cx25840_state *state = to_state(sd);
1572         struct i2c_client *client = v4l2_get_subdevdata(sd);
1573         u8 vpres = cx25840_read(client, 0x40e) & 0x20;
1574         u8 mode;
1575         int val = 0;
1576
1577         if (state->radio)
1578                 return 0;
1579
1580         vt->signal = vpres ? 0xffff : 0x0;
1581         if (is_cx2583x(state))
1582                 return 0;
1583
1584         vt->capability |=
1585                 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
1586                 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
1587
1588         mode = cx25840_read(client, 0x804);
1589
1590         /* get rxsubchans and audmode */
1591         if ((mode & 0xf) == 1)
1592                 val |= V4L2_TUNER_SUB_STEREO;
1593         else
1594                 val |= V4L2_TUNER_SUB_MONO;
1595
1596         if (mode == 2 || mode == 4)
1597                 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1598
1599         if (mode & 0x10)
1600                 val |= V4L2_TUNER_SUB_SAP;
1601
1602         vt->rxsubchans = val;
1603         vt->audmode = state->audmode;
1604         return 0;
1605 }
1606
1607 static int cx25840_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1608 {
1609         struct cx25840_state *state = to_state(sd);
1610         struct i2c_client *client = v4l2_get_subdevdata(sd);
1611
1612         if (state->radio || is_cx2583x(state))
1613                 return 0;
1614
1615         switch (vt->audmode) {
1616                 case V4L2_TUNER_MODE_MONO:
1617                         /* mono      -> mono
1618                            stereo    -> mono
1619                            bilingual -> lang1 */
1620                         cx25840_and_or(client, 0x809, ~0xf, 0x00);
1621                         break;
1622                 case V4L2_TUNER_MODE_STEREO:
1623                 case V4L2_TUNER_MODE_LANG1:
1624                         /* mono      -> mono
1625                            stereo    -> stereo
1626                            bilingual -> lang1 */
1627                         cx25840_and_or(client, 0x809, ~0xf, 0x04);
1628                         break;
1629                 case V4L2_TUNER_MODE_LANG1_LANG2:
1630                         /* mono      -> mono
1631                            stereo    -> stereo
1632                            bilingual -> lang1/lang2 */
1633                         cx25840_and_or(client, 0x809, ~0xf, 0x07);
1634                         break;
1635                 case V4L2_TUNER_MODE_LANG2:
1636                         /* mono      -> mono
1637                            stereo    -> stereo
1638                            bilingual -> lang2 */
1639                         cx25840_and_or(client, 0x809, ~0xf, 0x01);
1640                         break;
1641                 default:
1642                         return -EINVAL;
1643         }
1644         state->audmode = vt->audmode;
1645         return 0;
1646 }
1647
1648 static int cx25840_reset(struct v4l2_subdev *sd, u32 val)
1649 {
1650         struct cx25840_state *state = to_state(sd);
1651         struct i2c_client *client = v4l2_get_subdevdata(sd);
1652
1653         if (is_cx2583x(state))
1654                 cx25836_initialize(client);
1655         else if (is_cx2388x(state))
1656                 cx23885_initialize(client);
1657         else if (is_cx231xx(state))
1658                 cx231xx_initialize(client);
1659         else
1660                 cx25840_initialize(client);
1661         return 0;
1662 }
1663
1664 static int cx25840_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
1665 {
1666         struct cx25840_state *state = to_state(sd);
1667         struct i2c_client *client = v4l2_get_subdevdata(sd);
1668
1669         return v4l2_chip_ident_i2c_client(client, chip, state->id, state->rev);
1670 }
1671
1672 static int cx25840_log_status(struct v4l2_subdev *sd)
1673 {
1674         struct cx25840_state *state = to_state(sd);
1675         struct i2c_client *client = v4l2_get_subdevdata(sd);
1676
1677         log_video_status(client);
1678         if (!is_cx2583x(state))
1679                 log_audio_status(client);
1680         cx25840_ir_log_status(sd);
1681         v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
1682         return 0;
1683 }
1684
1685 static int cx25840_s_config(struct v4l2_subdev *sd, int irq, void *platform_data)
1686 {
1687         struct cx25840_state *state = to_state(sd);
1688         struct i2c_client *client = v4l2_get_subdevdata(sd);
1689
1690         if (platform_data) {
1691                 struct cx25840_platform_data *pdata = platform_data;
1692
1693                 state->pvr150_workaround = pdata->pvr150_workaround;
1694                 set_input(client, state->vid_input, state->aud_input);
1695         }
1696         return 0;
1697 }
1698
1699 static int cx23885_irq_handler(struct v4l2_subdev *sd, u32 status,
1700                                bool *handled)
1701 {
1702         struct cx25840_state *state = to_state(sd);
1703         struct i2c_client *c = v4l2_get_subdevdata(sd);
1704         u8 irq_stat, aud_stat, aud_en, ir_stat, ir_en;
1705         u32 vid_stat, aud_mc_stat;
1706         bool block_handled;
1707         int ret = 0;
1708
1709         irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
1710         v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (entry): %s %s %s\n",
1711                 irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : "  ",
1712                 irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : "   ",
1713                 irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : "   ");
1714
1715         if ((is_cx23885(state) || is_cx23887(state))) {
1716                 ir_stat = cx25840_read(c, CX25840_IR_STATS_REG);
1717                 ir_en = cx25840_read(c, CX25840_IR_IRQEN_REG);
1718                 v4l_dbg(2, cx25840_debug, c,
1719                         "AV Core ir IRQ status: %#04x disables: %#04x\n",
1720                         ir_stat, ir_en);
1721                 if (irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT) {
1722                         block_handled = false;
1723                         ret = cx25840_ir_irq_handler(sd,
1724                                                      status, &block_handled);
1725                         if (block_handled)
1726                                 *handled = true;
1727                 }
1728         }
1729
1730         aud_stat = cx25840_read(c, CX25840_AUD_INT_STAT_REG);
1731         aud_en = cx25840_read(c, CX25840_AUD_INT_CTRL_REG);
1732         v4l_dbg(2, cx25840_debug, c,
1733                 "AV Core audio IRQ status: %#04x disables: %#04x\n",
1734                 aud_stat, aud_en);
1735         aud_mc_stat = cx25840_read4(c, CX23885_AUD_MC_INT_MASK_REG);
1736         v4l_dbg(2, cx25840_debug, c,
1737                 "AV Core audio MC IRQ status: %#06x enables: %#06x\n",
1738                 aud_mc_stat >> CX23885_AUD_MC_INT_STAT_SHFT,
1739                 aud_mc_stat & CX23885_AUD_MC_INT_CTRL_BITS);
1740         if (irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT) {
1741                 if (aud_stat) {
1742                         cx25840_write(c, CX25840_AUD_INT_STAT_REG, aud_stat);
1743                         *handled = true;
1744                 }
1745         }
1746
1747         vid_stat = cx25840_read4(c, CX25840_VID_INT_STAT_REG);
1748         v4l_dbg(2, cx25840_debug, c,
1749                 "AV Core video IRQ status: %#06x disables: %#06x\n",
1750                 vid_stat & CX25840_VID_INT_STAT_BITS,
1751                 vid_stat >> CX25840_VID_INT_MASK_SHFT);
1752         if (irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT) {
1753                 if (vid_stat & CX25840_VID_INT_STAT_BITS) {
1754                         cx25840_write4(c, CX25840_VID_INT_STAT_REG, vid_stat);
1755                         *handled = true;
1756                 }
1757         }
1758
1759         irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
1760         v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (exit): %s %s %s\n",
1761                 irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : "  ",
1762                 irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : "   ",
1763                 irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : "   ");
1764
1765         return ret;
1766 }
1767
1768 static int cx25840_irq_handler(struct v4l2_subdev *sd, u32 status,
1769                                bool *handled)
1770 {
1771         struct cx25840_state *state = to_state(sd);
1772
1773         *handled = false;
1774
1775         /* Only support the CX2388[578] AV Core for now */
1776         if (is_cx2388x(state))
1777                 return cx23885_irq_handler(sd, status, handled);
1778
1779         return -ENODEV;
1780 }
1781
1782 /* ----------------------------------------------------------------------- */
1783
1784 static const struct v4l2_ctrl_ops cx25840_ctrl_ops = {
1785         .s_ctrl = cx25840_s_ctrl,
1786 };
1787
1788 static const struct v4l2_subdev_core_ops cx25840_core_ops = {
1789         .log_status = cx25840_log_status,
1790         .s_config = cx25840_s_config,
1791         .g_chip_ident = cx25840_g_chip_ident,
1792         .g_ctrl = v4l2_subdev_g_ctrl,
1793         .s_ctrl = v4l2_subdev_s_ctrl,
1794         .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1795         .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1796         .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1797         .queryctrl = v4l2_subdev_queryctrl,
1798         .querymenu = v4l2_subdev_querymenu,
1799         .s_std = cx25840_s_std,
1800         .reset = cx25840_reset,
1801         .load_fw = cx25840_load_fw,
1802         .s_io_pin_config = common_s_io_pin_config,
1803 #ifdef CONFIG_VIDEO_ADV_DEBUG
1804         .g_register = cx25840_g_register,
1805         .s_register = cx25840_s_register,
1806 #endif
1807         .interrupt_service_routine = cx25840_irq_handler,
1808 };
1809
1810 static const struct v4l2_subdev_tuner_ops cx25840_tuner_ops = {
1811         .s_frequency = cx25840_s_frequency,
1812         .s_radio = cx25840_s_radio,
1813         .g_tuner = cx25840_g_tuner,
1814         .s_tuner = cx25840_s_tuner,
1815 };
1816
1817 static const struct v4l2_subdev_audio_ops cx25840_audio_ops = {
1818         .s_clock_freq = cx25840_s_clock_freq,
1819         .s_routing = cx25840_s_audio_routing,
1820         .s_stream = cx25840_s_audio_stream,
1821 };
1822
1823 static const struct v4l2_subdev_video_ops cx25840_video_ops = {
1824         .s_routing = cx25840_s_video_routing,
1825         .s_mbus_fmt = cx25840_s_mbus_fmt,
1826         .s_stream = cx25840_s_stream,
1827 };
1828
1829 static const struct v4l2_subdev_vbi_ops cx25840_vbi_ops = {
1830         .decode_vbi_line = cx25840_decode_vbi_line,
1831         .s_raw_fmt = cx25840_s_raw_fmt,
1832         .s_sliced_fmt = cx25840_s_sliced_fmt,
1833         .g_sliced_fmt = cx25840_g_sliced_fmt,
1834 };
1835
1836 static const struct v4l2_subdev_ops cx25840_ops = {
1837         .core = &cx25840_core_ops,
1838         .tuner = &cx25840_tuner_ops,
1839         .audio = &cx25840_audio_ops,
1840         .video = &cx25840_video_ops,
1841         .vbi = &cx25840_vbi_ops,
1842         .ir = &cx25840_ir_ops,
1843 };
1844
1845 /* ----------------------------------------------------------------------- */
1846
1847 static u32 get_cx2388x_ident(struct i2c_client *client)
1848 {
1849         u32 ret;
1850
1851         /* Come out of digital power down */
1852         cx25840_write(client, 0x000, 0);
1853
1854         /* Detecting whether the part is cx23885/7/8 is more
1855          * difficult than it needs to be. No ID register. Instead we
1856          * probe certain registers indicated in the datasheets to look
1857          * for specific defaults that differ between the silicon designs. */
1858
1859         /* It's either 885/7 if the IR Tx Clk Divider register exists */
1860         if (cx25840_read4(client, 0x204) & 0xffff) {
1861                 /* CX23885 returns bogus repetitive byte values for the DIF,
1862                  * which doesn't exist for it. (Ex. 8a8a8a8a or 31313131) */
1863                 ret = cx25840_read4(client, 0x300);
1864                 if (((ret & 0xffff0000) >> 16) == (ret & 0xffff)) {
1865                         /* No DIF */
1866                         ret = V4L2_IDENT_CX23885_AV;
1867                 } else {
1868                         /* CX23887 has a broken DIF, but the registers
1869                          * appear valid (but unsed), good enough to detect. */
1870                         ret = V4L2_IDENT_CX23887_AV;
1871                 }
1872         } else if (cx25840_read4(client, 0x300) & 0x0fffffff) {
1873                 /* DIF PLL Freq Word reg exists; chip must be a CX23888 */
1874                 ret = V4L2_IDENT_CX23888_AV;
1875         } else {
1876                 v4l_err(client, "Unable to detect h/w, assuming cx23887\n");
1877                 ret = V4L2_IDENT_CX23887_AV;
1878         }
1879
1880         /* Back into digital power down */
1881         cx25840_write(client, 0x000, 2);
1882         return ret;
1883 }
1884
1885 static int cx25840_probe(struct i2c_client *client,
1886                          const struct i2c_device_id *did)
1887 {
1888         struct cx25840_state *state;
1889         struct v4l2_subdev *sd;
1890         int default_volume;
1891         u32 id = V4L2_IDENT_NONE;
1892         u16 device_id;
1893
1894         /* Check if the adapter supports the needed features */
1895         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1896                 return -EIO;
1897
1898         v4l_dbg(1, cx25840_debug, client, "detecting cx25840 client on address 0x%x\n", client->addr << 1);
1899
1900         device_id = cx25840_read(client, 0x101) << 8;
1901         device_id |= cx25840_read(client, 0x100);
1902         v4l_dbg(1, cx25840_debug, client, "device_id = 0x%04x\n", device_id);
1903
1904         /* The high byte of the device ID should be
1905          * 0x83 for the cx2583x and 0x84 for the cx2584x */
1906         if ((device_id & 0xff00) == 0x8300) {
1907                 id = V4L2_IDENT_CX25836 + ((device_id >> 4) & 0xf) - 6;
1908         } else if ((device_id & 0xff00) == 0x8400) {
1909                 id = V4L2_IDENT_CX25840 + ((device_id >> 4) & 0xf);
1910         } else if (device_id == 0x0000) {
1911                 id = get_cx2388x_ident(client);
1912         } else if ((device_id & 0xfff0) == 0x5A30) {
1913                 /* The CX23100 (0x5A3C = 23100) doesn't have an A/V decoder */
1914                 id = V4L2_IDENT_CX2310X_AV;
1915         } else if ((device_id & 0xff) == (device_id >> 8)) {
1916                 v4l_err(client,
1917                         "likely a confused/unresponsive cx2388[578] A/V decoder"
1918                         " found @ 0x%x (%s)\n",
1919                         client->addr << 1, client->adapter->name);
1920                 v4l_err(client, "A method to reset it from the cx25840 driver"
1921                         " software is not known at this time\n");
1922                 return -ENODEV;
1923         } else {
1924                 v4l_dbg(1, cx25840_debug, client, "cx25840 not found\n");
1925                 return -ENODEV;
1926         }
1927
1928         state = kzalloc(sizeof(struct cx25840_state), GFP_KERNEL);
1929         if (state == NULL)
1930                 return -ENOMEM;
1931
1932         sd = &state->sd;
1933         v4l2_i2c_subdev_init(sd, client, &cx25840_ops);
1934
1935         switch (id) {
1936         case V4L2_IDENT_CX23885_AV:
1937                 v4l_info(client, "cx23885 A/V decoder found @ 0x%x (%s)\n",
1938                          client->addr << 1, client->adapter->name);
1939                 break;
1940         case V4L2_IDENT_CX23887_AV:
1941                 v4l_info(client, "cx23887 A/V decoder found @ 0x%x (%s)\n",
1942                          client->addr << 1, client->adapter->name);
1943                 break;
1944         case V4L2_IDENT_CX23888_AV:
1945                 v4l_info(client, "cx23888 A/V decoder found @ 0x%x (%s)\n",
1946                          client->addr << 1, client->adapter->name);
1947                 break;
1948         case V4L2_IDENT_CX2310X_AV:
1949                 v4l_info(client, "cx%d A/V decoder found @ 0x%x (%s)\n",
1950                          device_id, client->addr << 1, client->adapter->name);
1951                 break;
1952         case V4L2_IDENT_CX25840:
1953         case V4L2_IDENT_CX25841:
1954         case V4L2_IDENT_CX25842:
1955         case V4L2_IDENT_CX25843:
1956                 /* Note: revision '(device_id & 0x0f) == 2' was never built. The
1957                    marking skips from 0x1 == 22 to 0x3 == 23. */
1958                 v4l_info(client, "cx25%3x-2%x found @ 0x%x (%s)\n",
1959                          (device_id & 0xfff0) >> 4,
1960                          (device_id & 0x0f) < 3 ? (device_id & 0x0f) + 1
1961                                                 : (device_id & 0x0f),
1962                          client->addr << 1, client->adapter->name);
1963                 break;
1964         case V4L2_IDENT_CX25836:
1965         case V4L2_IDENT_CX25837:
1966         default:
1967                 v4l_info(client, "cx25%3x-%x found @ 0x%x (%s)\n",
1968                          (device_id & 0xfff0) >> 4, device_id & 0x0f,
1969                          client->addr << 1, client->adapter->name);
1970                 break;
1971         }
1972
1973         state->c = client;
1974         state->vid_input = CX25840_COMPOSITE7;
1975         state->aud_input = CX25840_AUDIO8;
1976         state->audclk_freq = 48000;
1977         state->pvr150_workaround = 0;
1978         state->audmode = V4L2_TUNER_MODE_LANG1;
1979         state->vbi_line_offset = 8;
1980         state->id = id;
1981         state->rev = device_id;
1982         v4l2_ctrl_handler_init(&state->hdl, 9);
1983         v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1984                         V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1985         v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1986                         V4L2_CID_CONTRAST, 0, 127, 1, 64);
1987         v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1988                         V4L2_CID_SATURATION, 0, 127, 1, 64);
1989         v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1990                         V4L2_CID_HUE, -128, 127, 1, 0);
1991         if (!is_cx2583x(state)) {
1992                 default_volume = cx25840_read(client, 0x8d4);
1993                 /*
1994                  * Enforce the legacy PVR-350/MSP3400 to PVR-150/CX25843 volume
1995                  * scale mapping limits to avoid -ERANGE errors when
1996                  * initializing the volume control
1997                  */
1998                 if (default_volume > 228) {
1999                         /* Bottom out at -96 dB, v4l2 vol range 0x2e00-0x2fff */
2000                         default_volume = 228;
2001                         cx25840_write(client, 0x8d4, 228);
2002                 }
2003                 else if (default_volume < 20) {
2004                         /* Top out at + 8 dB, v4l2 vol range 0xfe00-0xffff */
2005                         default_volume = 20;
2006                         cx25840_write(client, 0x8d4, 20);
2007                 }
2008                 default_volume = (((228 - default_volume) >> 1) + 23) << 9;
2009
2010                 state->volume = v4l2_ctrl_new_std(&state->hdl,
2011                         &cx25840_audio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
2012                         0, 65535, 65535 / 100, default_volume);
2013                 state->mute = v4l2_ctrl_new_std(&state->hdl,
2014                         &cx25840_audio_ctrl_ops, V4L2_CID_AUDIO_MUTE,
2015                         0, 1, 1, 0);
2016                 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2017                         V4L2_CID_AUDIO_BALANCE,
2018                         0, 65535, 65535 / 100, 32768);
2019                 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2020                         V4L2_CID_AUDIO_BASS,
2021                         0, 65535, 65535 / 100, 32768);
2022                 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2023                         V4L2_CID_AUDIO_TREBLE,
2024                         0, 65535, 65535 / 100, 32768);
2025         }
2026         sd->ctrl_handler = &state->hdl;
2027         if (state->hdl.error) {
2028                 int err = state->hdl.error;
2029
2030                 v4l2_ctrl_handler_free(&state->hdl);
2031                 kfree(state);
2032                 return err;
2033         }
2034         v4l2_ctrl_cluster(2, &state->volume);
2035         v4l2_ctrl_handler_setup(&state->hdl);
2036
2037         cx25840_ir_probe(sd);
2038         return 0;
2039 }
2040
2041 static int cx25840_remove(struct i2c_client *client)
2042 {
2043         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2044         struct cx25840_state *state = to_state(sd);
2045
2046         cx25840_ir_remove(sd);
2047         v4l2_device_unregister_subdev(sd);
2048         v4l2_ctrl_handler_free(&state->hdl);
2049         kfree(state);
2050         return 0;
2051 }
2052
2053 static const struct i2c_device_id cx25840_id[] = {
2054         { "cx25840", 0 },
2055         { }
2056 };
2057 MODULE_DEVICE_TABLE(i2c, cx25840_id);
2058
2059 static struct i2c_driver cx25840_driver = {
2060         .driver = {
2061                 .owner  = THIS_MODULE,
2062                 .name   = "cx25840",
2063         },
2064         .probe          = cx25840_probe,
2065         .remove         = cx25840_remove,
2066         .id_table       = cx25840_id,
2067 };
2068
2069 static __init int init_cx25840(void)
2070 {
2071         return i2c_add_driver(&cx25840_driver);
2072 }
2073
2074 static __exit void exit_cx25840(void)
2075 {
2076         i2c_del_driver(&cx25840_driver);
2077 }
2078
2079 module_init(init_cx25840);
2080 module_exit(exit_cx25840);