2 * Driver for the Conexant CX2584x Audio/Video decoder chip and related cores
4 * Integrated Consumer Infrared Controller
6 * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 #include <linux/slab.h>
25 #include <linux/kfifo.h>
26 #include <media/cx25840.h>
28 #include "cx25840-core.h"
30 static unsigned int ir_debug;
31 module_param(ir_debug, int, 0644);
32 MODULE_PARM_DESC(ir_debug, "enable integrated IR debug messages");
34 #define CX25840_IR_REG_BASE 0x200
36 #define CX25840_IR_CNTRL_REG 0x200
37 #define CNTRL_WIN_3_3 0x00000000
38 #define CNTRL_WIN_4_3 0x00000001
39 #define CNTRL_WIN_3_4 0x00000002
40 #define CNTRL_WIN_4_4 0x00000003
41 #define CNTRL_WIN 0x00000003
42 #define CNTRL_EDG_NONE 0x00000000
43 #define CNTRL_EDG_FALL 0x00000004
44 #define CNTRL_EDG_RISE 0x00000008
45 #define CNTRL_EDG_BOTH 0x0000000C
46 #define CNTRL_EDG 0x0000000C
47 #define CNTRL_DMD 0x00000010
48 #define CNTRL_MOD 0x00000020
49 #define CNTRL_RFE 0x00000040
50 #define CNTRL_TFE 0x00000080
51 #define CNTRL_RXE 0x00000100
52 #define CNTRL_TXE 0x00000200
53 #define CNTRL_RIC 0x00000400
54 #define CNTRL_TIC 0x00000800
55 #define CNTRL_CPL 0x00001000
56 #define CNTRL_LBM 0x00002000
57 #define CNTRL_R 0x00004000
59 #define CX25840_IR_TXCLK_REG 0x204
60 #define TXCLK_TCD 0x0000FFFF
62 #define CX25840_IR_RXCLK_REG 0x208
63 #define RXCLK_RCD 0x0000FFFF
65 #define CX25840_IR_CDUTY_REG 0x20C
66 #define CDUTY_CDC 0x0000000F
68 #define CX25840_IR_STATS_REG 0x210
69 #define STATS_RTO 0x00000001
70 #define STATS_ROR 0x00000002
71 #define STATS_RBY 0x00000004
72 #define STATS_TBY 0x00000008
73 #define STATS_RSR 0x00000010
74 #define STATS_TSR 0x00000020
76 #define CX25840_IR_IRQEN_REG 0x214
77 #define IRQEN_RTE 0x00000001
78 #define IRQEN_ROE 0x00000002
79 #define IRQEN_RSE 0x00000010
80 #define IRQEN_TSE 0x00000020
81 #define IRQEN_MSK 0x00000033
83 #define CX25840_IR_FILTR_REG 0x218
84 #define FILTR_LPF 0x0000FFFF
86 #define CX25840_IR_FIFO_REG 0x23C
87 #define FIFO_RXTX 0x0000FFFF
88 #define FIFO_RXTX_LVL 0x00010000
89 #define FIFO_RXTX_RTO 0x0001FFFF
90 #define FIFO_RX_NDV 0x00020000
91 #define FIFO_RX_DEPTH 8
92 #define FIFO_TX_DEPTH 8
94 #define CX25840_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
95 #define CX25840_IR_REFCLK_FREQ (CX25840_VIDCLK_FREQ / 2)
97 #define CX25840_IR_RX_KFIFO_SIZE (512 * sizeof(u32))
98 #define CX25840_IR_TX_KFIFO_SIZE (512 * sizeof(u32))
100 struct cx25840_ir_state {
101 struct i2c_client *c;
103 struct v4l2_subdev_ir_parameters rx_params;
104 struct mutex rx_params_lock; /* protects Rx parameter settings cache */
105 atomic_t rxclk_divider;
108 struct kfifo rx_kfifo;
109 spinlock_t rx_kfifo_lock; /* protect Rx data kfifo */
111 struct v4l2_subdev_ir_parameters tx_params;
112 struct mutex tx_params_lock; /* protects Tx parameter settings cache */
113 atomic_t txclk_divider;
116 static inline struct cx25840_ir_state *to_ir_state(struct v4l2_subdev *sd)
118 struct cx25840_state *state = to_state(sd);
119 return state ? state->ir_state : NULL;
124 * Rx and Tx Clock Divider register computations
126 * Note the largest clock divider value of 0xffff corresponds to:
127 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
128 * which fits in 21 bits, so we'll use unsigned int for time arguments.
130 static inline u16 count_to_clock_divider(unsigned int d)
132 if (d > RXCLK_RCD + 1)
141 static inline u16 ns_to_clock_divider(unsigned int ns)
143 return count_to_clock_divider(
144 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
147 static inline unsigned int clock_divider_to_ns(unsigned int divider)
149 /* Period of the Rx or Tx clock in ns */
150 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
151 CX25840_IR_REFCLK_FREQ / 1000000);
154 static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
156 return count_to_clock_divider(
157 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * 16));
160 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
162 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
165 static inline u16 freq_to_clock_divider(unsigned int freq,
166 unsigned int rollovers)
168 return count_to_clock_divider(
169 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * rollovers));
172 static inline unsigned int clock_divider_to_freq(unsigned int divider,
173 unsigned int rollovers)
175 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ,
176 (divider + 1) * rollovers);
180 * Low Pass Filter register calculations
182 * Note the largest count value of 0xffff corresponds to:
183 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
184 * which fits in 21 bits, so we'll use unsigned int for time arguments.
186 static inline u16 count_to_lpf_count(unsigned int d)
195 static inline u16 ns_to_lpf_count(unsigned int ns)
197 return count_to_lpf_count(
198 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
201 static inline unsigned int lpf_count_to_ns(unsigned int count)
203 /* Duration of the Low Pass Filter rejection window in ns */
204 return DIV_ROUND_CLOSEST(count * 1000,
205 CX25840_IR_REFCLK_FREQ / 1000000);
208 static inline unsigned int lpf_count_to_us(unsigned int count)
210 /* Duration of the Low Pass Filter rejection window in us */
211 return DIV_ROUND_CLOSEST(count, CX25840_IR_REFCLK_FREQ / 1000000);
215 * FIFO register pulse width count compuations
217 static u32 clock_divider_to_resolution(u16 divider)
220 * Resolution is the duration of 1 tick of the readable portion of
221 * of the pulse width counter as read from the FIFO. The two lsb's are
222 * not readable, hence the << 2. This function returns ns.
224 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
225 CX25840_IR_REFCLK_FREQ / 1000000);
228 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
234 * The 2 lsb's of the pulse width timer count are not readable, hence
235 * the (count << 2) | 0x3
237 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
238 rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
239 if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
245 /* Keep as we will need this for Transmit functionality */
246 static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
253 * The 2 lsb's of the pulse width timer count are not accessable, hence
256 n = ((u64) ns) * CX25840_IR_REFCLK_FREQ / 1000000; /* millicycles */
257 d = (1 << 2) * ((u32) divider + 1) * 1000; /* millicycles/count */
270 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
276 * The 2 lsb's of the pulse width timer count are not readable, hence
277 * the (count << 2) | 0x3
279 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
280 rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
281 if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
283 return (unsigned int) n;
287 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
289 * The total pulse clock count is an 18 bit pulse width timer count as the most
290 * significant part and (up to) 16 bit clock divider count as a modulus.
291 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
292 * width timer count's least significant bit.
294 static u64 ns_to_pulse_clocks(u32 ns)
298 clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
299 rem = do_div(clocks, 1000); /* /1000 = cycles */
305 static u16 pulse_clocks_to_clock_divider(u64 count)
309 rem = do_div(count, (FIFO_RXTX << 2) | 0x3);
311 /* net result needs to be rounded down and decremented by 1 */
312 if (count > RXCLK_RCD + 1)
322 * IR Control Register helpers
324 enum tx_fifo_watermark {
325 TX_FIFO_HALF_EMPTY = 0,
326 TX_FIFO_EMPTY = CNTRL_TIC,
329 enum rx_fifo_watermark {
330 RX_FIFO_HALF_FULL = 0,
331 RX_FIFO_NOT_EMPTY = CNTRL_RIC,
334 static inline void control_tx_irq_watermark(struct i2c_client *c,
335 enum tx_fifo_watermark level)
337 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_TIC, level);
340 static inline void control_rx_irq_watermark(struct i2c_client *c,
341 enum rx_fifo_watermark level)
343 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_RIC, level);
346 static inline void control_tx_enable(struct i2c_client *c, bool enable)
348 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
349 enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
352 static inline void control_rx_enable(struct i2c_client *c, bool enable)
354 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
355 enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
358 static inline void control_tx_modulation_enable(struct i2c_client *c,
361 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_MOD,
362 enable ? CNTRL_MOD : 0);
365 static inline void control_rx_demodulation_enable(struct i2c_client *c,
368 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_DMD,
369 enable ? CNTRL_DMD : 0);
372 static inline void control_rx_s_edge_detection(struct i2c_client *c,
375 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
376 edge_types & CNTRL_EDG_BOTH);
379 static void control_rx_s_carrier_window(struct i2c_client *c,
380 unsigned int carrier,
381 unsigned int *carrier_range_low,
382 unsigned int *carrier_range_high)
385 unsigned int c16 = carrier * 16;
387 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
389 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
392 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
395 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
397 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
400 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
402 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_WIN, v);
405 static inline void control_tx_polarity_invert(struct i2c_client *c,
408 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_CPL,
409 invert ? CNTRL_CPL : 0);
413 * IR Rx & Tx Clock Register helpers
415 static unsigned int txclk_tx_s_carrier(struct i2c_client *c,
419 *divider = carrier_freq_to_clock_divider(freq);
420 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
421 return clock_divider_to_carrier_freq(*divider);
424 static unsigned int rxclk_rx_s_carrier(struct i2c_client *c,
428 *divider = carrier_freq_to_clock_divider(freq);
429 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
430 return clock_divider_to_carrier_freq(*divider);
433 static u32 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns,
438 if (ns > V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
439 ns = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS;
440 pulse_clocks = ns_to_pulse_clocks(ns);
441 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
442 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
443 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
446 static u32 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns,
451 if (ns > V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
452 ns = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS;
453 pulse_clocks = ns_to_pulse_clocks(ns);
454 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
455 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
456 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
460 * IR Tx Carrier Duty Cycle register helpers
462 static unsigned int cduty_tx_s_duty_cycle(struct i2c_client *c,
463 unsigned int duty_cycle)
466 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
471 cx25840_write4(c, CX25840_IR_CDUTY_REG, n);
472 return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
476 * IR Filter Register helpers
478 static u32 filter_rx_s_min_width(struct i2c_client *c, u32 min_width_ns)
480 u32 count = ns_to_lpf_count(min_width_ns);
481 cx25840_write4(c, CX25840_IR_FILTR_REG, count);
482 return lpf_count_to_ns(count);
486 * IR IRQ Enable Register helpers
488 static inline void irqenable_rx(struct v4l2_subdev *sd, u32 mask)
490 struct cx25840_state *state = to_state(sd);
492 if (is_cx23885(state) || is_cx23887(state))
494 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
495 cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG,
496 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
499 static inline void irqenable_tx(struct v4l2_subdev *sd, u32 mask)
501 struct cx25840_state *state = to_state(sd);
503 if (is_cx23885(state) || is_cx23887(state))
506 cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, ~IRQEN_TSE, mask);
510 * V4L2 Subdevice IR Ops
512 int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled)
514 struct cx25840_state *state = to_state(sd);
515 struct cx25840_ir_state *ir_state = to_ir_state(sd);
516 struct i2c_client *c = NULL;
519 u32 rx_data[FIFO_RX_DEPTH];
522 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
523 u32 cntrl, irqen, stats;
526 if (ir_state == NULL)
531 /* Only support the IR controller for the CX2388[57] AV Core for now */
532 if (!(is_cx23885(state) || is_cx23887(state)))
535 cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
536 irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
537 if (is_cx23885(state) || is_cx23887(state))
539 stats = cx25840_read4(c, CX25840_IR_STATS_REG);
541 tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
542 rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
543 rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
544 ror = stats & STATS_ROR; /* Rx FIFO Over Run */
546 tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
547 rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
548 rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
549 roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
551 v4l2_dbg(2, ir_debug, sd, "IR IRQ Status: %s %s %s %s %s %s\n",
552 tsr ? "tsr" : " ", rsr ? "rsr" : " ",
553 rto ? "rto" : " ", ror ? "ror" : " ",
554 stats & STATS_TBY ? "tby" : " ",
555 stats & STATS_RBY ? "rby" : " ");
557 v4l2_dbg(2, ir_debug, sd, "IR IRQ Enables: %s %s %s %s\n",
558 tse ? "tse" : " ", rse ? "rse" : " ",
559 rte ? "rte" : " ", roe ? "roe" : " ");
562 * Transmitter interrupt service
567 * Check the watermark threshold setting
568 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
569 * Push the data to the hardware FIFO.
570 * If there was nothing more to send in the tx_kfifo, disable
571 * the TSR IRQ and notify the v4l2_device.
572 * If there was something in the tx_kfifo, check the tx_kfifo
573 * level and notify the v4l2_device, if it is low.
575 /* For now, inhibit TSR interrupt until Tx is implemented */
577 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
578 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
583 * Receiver interrupt service
586 if ((rse && rsr) || (rte && rto)) {
588 * Receive data on RSR to clear the STATS_RSR.
589 * Receive data on RTO, since we may not have yet hit the RSR
590 * watermark when we receive the RTO.
592 for (i = 0, v = FIFO_RX_NDV;
593 (v & FIFO_RX_NDV) && !kror; i = 0) {
595 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
596 v = cx25840_read4(c, CX25840_IR_FIFO_REG);
597 rx_data[i++] = v & ~FIFO_RX_NDV;
602 k = kfifo_in_locked(&ir_state->rx_kfifo,
603 (unsigned char *) rx_data, j,
604 &ir_state->rx_kfifo_lock);
606 kror++; /* rx_kfifo over run */
614 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
615 v4l2_err(sd, "IR receiver software FIFO overrun\n");
619 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
620 * the Rx FIFO Over Run status (STATS_ROR)
623 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
624 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
628 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
629 * the Rx Pulse Width Timer Time Out (STATS_RTO)
632 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
635 /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
636 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v);
637 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl);
640 spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
641 if (kfifo_len(&ir_state->rx_kfifo) >= CX25840_IR_RX_KFIFO_SIZE / 2)
642 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
643 spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
646 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
651 static int cx25840_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
654 struct cx25840_ir_state *ir_state = to_ir_state(sd);
661 if (ir_state == NULL)
664 invert = (bool) atomic_read(&ir_state->rx_invert);
665 divider = (u16) atomic_read(&ir_state->rxclk_divider);
667 n = count / sizeof(u32) * sizeof(u32);
673 n = kfifo_out_locked(&ir_state->rx_kfifo, buf, n,
674 &ir_state->rx_kfifo_lock);
677 *num = n * sizeof(u32);
679 for (p = (u32 *) buf, i = 0; i < n; p++, i++) {
681 if ((*p & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
682 /* Assume RTO was because of no IR light input */
684 v4l2_dbg(2, ir_debug, sd, "rx read: end of rx\n");
686 u = (*p & FIFO_RXTX_LVL)
687 ? V4L2_SUBDEV_IR_PULSE_LEVEL_MASK : 0;
689 u = u ? 0 : V4L2_SUBDEV_IR_PULSE_LEVEL_MASK;
692 v = (u32) pulse_width_count_to_ns((u16) (*p & FIFO_RXTX),
694 if (v >= V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS)
695 v = V4L2_SUBDEV_IR_PULSE_MAX_WIDTH_NS - 1;
699 v4l2_dbg(2, ir_debug, sd, "rx read: %10u ns %s\n",
700 v, u ? "mark" : "space");
705 static int cx25840_ir_rx_g_parameters(struct v4l2_subdev *sd,
706 struct v4l2_subdev_ir_parameters *p)
708 struct cx25840_ir_state *ir_state = to_ir_state(sd);
710 if (ir_state == NULL)
713 mutex_lock(&ir_state->rx_params_lock);
714 memcpy(p, &ir_state->rx_params,
715 sizeof(struct v4l2_subdev_ir_parameters));
716 mutex_unlock(&ir_state->rx_params_lock);
720 static int cx25840_ir_rx_shutdown(struct v4l2_subdev *sd)
722 struct cx25840_ir_state *ir_state = to_ir_state(sd);
723 struct i2c_client *c;
725 if (ir_state == NULL)
729 mutex_lock(&ir_state->rx_params_lock);
731 /* Disable or slow down all IR Rx circuits and counters */
733 control_rx_enable(c, false);
734 control_rx_demodulation_enable(c, false);
735 control_rx_s_edge_detection(c, CNTRL_EDG_NONE);
736 filter_rx_s_min_width(c, 0);
737 cx25840_write4(c, CX25840_IR_RXCLK_REG, RXCLK_RCD);
739 ir_state->rx_params.shutdown = true;
741 mutex_unlock(&ir_state->rx_params_lock);
745 static int cx25840_ir_rx_s_parameters(struct v4l2_subdev *sd,
746 struct v4l2_subdev_ir_parameters *p)
748 struct cx25840_ir_state *ir_state = to_ir_state(sd);
749 struct i2c_client *c;
750 struct v4l2_subdev_ir_parameters *o;
753 if (ir_state == NULL)
757 return cx25840_ir_rx_shutdown(sd);
759 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
763 o = &ir_state->rx_params;
765 mutex_lock(&ir_state->rx_params_lock);
767 o->shutdown = p->shutdown;
769 p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
772 p->bytes_per_data_element = sizeof(u32);
773 o->bytes_per_data_element = p->bytes_per_data_element;
775 /* Before we tweak the hardware, we have to disable the receiver */
777 control_rx_enable(c, false);
779 control_rx_demodulation_enable(c, p->modulation);
780 o->modulation = p->modulation;
783 p->carrier_freq = rxclk_rx_s_carrier(c, p->carrier_freq,
786 o->carrier_freq = p->carrier_freq;
789 o->duty_cycle = p->duty_cycle;
791 control_rx_s_carrier_window(c, p->carrier_freq,
792 &p->carrier_range_lower,
793 &p->carrier_range_upper);
794 o->carrier_range_lower = p->carrier_range_lower;
795 o->carrier_range_upper = p->carrier_range_upper;
798 (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
801 rxclk_rx_s_max_pulse_width(c, p->max_pulse_width,
804 o->max_pulse_width = p->max_pulse_width;
805 atomic_set(&ir_state->rxclk_divider, rxclk_divider);
807 p->noise_filter_min_width =
808 filter_rx_s_min_width(c, p->noise_filter_min_width);
809 o->noise_filter_min_width = p->noise_filter_min_width;
811 p->resolution = clock_divider_to_resolution(rxclk_divider);
812 o->resolution = p->resolution;
814 /* FIXME - make this dependent on resolution for better performance */
815 control_rx_irq_watermark(c, RX_FIFO_HALF_FULL);
817 control_rx_s_edge_detection(c, CNTRL_EDG_BOTH);
819 o->invert_level = p->invert_level;
820 atomic_set(&ir_state->rx_invert, p->invert_level);
822 o->interrupt_enable = p->interrupt_enable;
823 o->enable = p->enable;
827 spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
828 kfifo_reset(&ir_state->rx_kfifo);
829 spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
830 if (p->interrupt_enable)
831 irqenable_rx(sd, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
832 control_rx_enable(c, p->enable);
835 mutex_unlock(&ir_state->rx_params_lock);
840 static int cx25840_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
843 struct cx25840_ir_state *ir_state = to_ir_state(sd);
844 struct i2c_client *c;
846 if (ir_state == NULL)
852 * FIXME - the code below is an incomplete and untested sketch of what
853 * may need to be done. The critical part is to get 4 (or 8) pulses
854 * from the tx_kfifo, or converted from ns to the proper units from the
855 * input, and push them off to the hardware Tx FIFO right away, if the
856 * HW TX fifo needs service. The rest can be pushed to the tx_kfifo in
857 * a less critical timeframe. Also watch out for overruning the
858 * tx_kfifo - don't let it happen and let the caller know not all his
859 * pulses were written.
861 u32 *ns_pulse = (u32 *) buf;
863 u32 fifo_pulse[FIFO_TX_DEPTH];
866 /* Compute how much we can fit in the tx kfifo */
867 n = CX25840_IR_TX_KFIFO_SIZE - kfifo_len(ir_state->tx_kfifo);
868 n = min(n, (unsigned int) count);
871 /* FIXME - turn on Tx Fifo service interrupt
872 * check hardware fifo level, and other stuff
874 for (i = 0; i < n; ) {
875 for (j = 0; j < FIFO_TX_DEPTH / 2 && i < n; j++) {
876 mark = ns_pulse[i] & V4L2_SUBDEV_IR_PULSE_LEVEL_MASK;
877 fifo_pulse[j] = ns_to_pulse_width_count(
879 ~V4L2_SUBDEV_IR_PULSE_LEVEL_MASK,
880 ir_state->txclk_divider);
882 fifo_pulse[j] &= FIFO_RXTX_LVL;
885 kfifo_put(ir_state->tx_kfifo, (u8 *) fifo_pulse,
888 *num = n * sizeof(u32);
890 /* For now enable the Tx FIFO Service interrupt & pretend we did work */
891 irqenable_tx(sd, IRQEN_TSE);
897 static int cx25840_ir_tx_g_parameters(struct v4l2_subdev *sd,
898 struct v4l2_subdev_ir_parameters *p)
900 struct cx25840_ir_state *ir_state = to_ir_state(sd);
902 if (ir_state == NULL)
905 mutex_lock(&ir_state->tx_params_lock);
906 memcpy(p, &ir_state->tx_params,
907 sizeof(struct v4l2_subdev_ir_parameters));
908 mutex_unlock(&ir_state->tx_params_lock);
912 static int cx25840_ir_tx_shutdown(struct v4l2_subdev *sd)
914 struct cx25840_ir_state *ir_state = to_ir_state(sd);
915 struct i2c_client *c;
917 if (ir_state == NULL)
921 mutex_lock(&ir_state->tx_params_lock);
923 /* Disable or slow down all IR Tx circuits and counters */
925 control_tx_enable(c, false);
926 control_tx_modulation_enable(c, false);
927 cx25840_write4(c, CX25840_IR_TXCLK_REG, TXCLK_TCD);
929 ir_state->tx_params.shutdown = true;
931 mutex_unlock(&ir_state->tx_params_lock);
935 static int cx25840_ir_tx_s_parameters(struct v4l2_subdev *sd,
936 struct v4l2_subdev_ir_parameters *p)
938 struct cx25840_ir_state *ir_state = to_ir_state(sd);
939 struct i2c_client *c;
940 struct v4l2_subdev_ir_parameters *o;
943 if (ir_state == NULL)
947 return cx25840_ir_tx_shutdown(sd);
949 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
953 o = &ir_state->tx_params;
954 mutex_lock(&ir_state->tx_params_lock);
956 o->shutdown = p->shutdown;
958 p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
961 p->bytes_per_data_element = sizeof(u32);
962 o->bytes_per_data_element = p->bytes_per_data_element;
964 /* Before we tweak the hardware, we have to disable the transmitter */
966 control_tx_enable(c, false);
968 control_tx_modulation_enable(c, p->modulation);
969 o->modulation = p->modulation;
972 p->carrier_freq = txclk_tx_s_carrier(c, p->carrier_freq,
974 o->carrier_freq = p->carrier_freq;
976 p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle);
977 o->duty_cycle = p->duty_cycle;
980 (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
983 txclk_tx_s_max_pulse_width(c, p->max_pulse_width,
986 o->max_pulse_width = p->max_pulse_width;
987 atomic_set(&ir_state->txclk_divider, txclk_divider);
989 p->resolution = clock_divider_to_resolution(txclk_divider);
990 o->resolution = p->resolution;
992 /* FIXME - make this dependent on resolution for better performance */
993 control_tx_irq_watermark(c, TX_FIFO_HALF_EMPTY);
995 control_tx_polarity_invert(c, p->invert_carrier_sense);
996 o->invert_carrier_sense = p->invert_carrier_sense;
999 * FIXME: we don't have hardware help for IO pin level inversion
1000 * here like we have on the CX23888.
1001 * Act on this with some mix of logical inversion of data levels,
1002 * carrier polarity, and carrier duty cycle.
1004 o->invert_level = p->invert_level;
1006 o->interrupt_enable = p->interrupt_enable;
1007 o->enable = p->enable;
1009 /* reset tx_fifo here */
1010 if (p->interrupt_enable)
1011 irqenable_tx(sd, IRQEN_TSE);
1012 control_tx_enable(c, p->enable);
1015 mutex_unlock(&ir_state->tx_params_lock);
1021 * V4L2 Subdevice Core Ops support
1023 int cx25840_ir_log_status(struct v4l2_subdev *sd)
1025 struct cx25840_state *state = to_state(sd);
1026 struct i2c_client *c = state->c;
1029 u32 cntrl, txclk, rxclk, cduty, stats, irqen, filtr;
1031 /* The CX23888 chip doesn't have an IR controller on the A/V core */
1032 if (is_cx23888(state))
1035 cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
1036 txclk = cx25840_read4(c, CX25840_IR_TXCLK_REG) & TXCLK_TCD;
1037 rxclk = cx25840_read4(c, CX25840_IR_RXCLK_REG) & RXCLK_RCD;
1038 cduty = cx25840_read4(c, CX25840_IR_CDUTY_REG) & CDUTY_CDC;
1039 stats = cx25840_read4(c, CX25840_IR_STATS_REG);
1040 irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
1041 if (is_cx23885(state) || is_cx23887(state))
1043 filtr = cx25840_read4(c, CX25840_IR_FILTR_REG) & FILTR_LPF;
1045 v4l2_info(sd, "IR Receiver:\n");
1046 v4l2_info(sd, "\tEnabled: %s\n",
1047 cntrl & CNTRL_RXE ? "yes" : "no");
1048 v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
1049 cntrl & CNTRL_DMD ? "enabled" : "disabled");
1050 v4l2_info(sd, "\tFIFO: %s\n",
1051 cntrl & CNTRL_RFE ? "enabled" : "disabled");
1052 switch (cntrl & CNTRL_EDG) {
1053 case CNTRL_EDG_NONE:
1056 case CNTRL_EDG_FALL:
1059 case CNTRL_EDG_RISE:
1062 case CNTRL_EDG_BOTH:
1063 s = "rising & falling edges";
1069 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
1070 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
1071 cntrl & CNTRL_R ? "not loaded" : "overflow marker");
1072 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1073 cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
1074 v4l2_info(sd, "\tLoopback mode: %s\n",
1075 cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
1076 if (cntrl & CNTRL_DMD) {
1077 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
1078 clock_divider_to_carrier_freq(rxclk));
1079 switch (cntrl & CNTRL_WIN) {
1101 v4l2_info(sd, "\tNext carrier edge window: 16 clocks "
1102 "-%1d/+%1d, %u to %u Hz\n", i, j,
1103 clock_divider_to_freq(rxclk, 16 + j),
1104 clock_divider_to_freq(rxclk, 16 - i));
1106 v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n",
1107 pulse_width_count_to_us(FIFO_RXTX, rxclk),
1108 pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1109 v4l2_info(sd, "\tLow pass filter: %s\n",
1110 filtr ? "enabled" : "disabled");
1112 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, "
1114 lpf_count_to_us(filtr),
1115 lpf_count_to_ns(filtr));
1116 v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
1117 stats & STATS_RTO ? "yes" : "no");
1118 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
1119 irqen & IRQEN_RTE ? "enabled" : "disabled");
1120 v4l2_info(sd, "\tFIFO overrun: %s\n",
1121 stats & STATS_ROR ? "yes" : "no");
1122 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
1123 irqen & IRQEN_ROE ? "enabled" : "disabled");
1124 v4l2_info(sd, "\tBusy: %s\n",
1125 stats & STATS_RBY ? "yes" : "no");
1126 v4l2_info(sd, "\tFIFO service requested: %s\n",
1127 stats & STATS_RSR ? "yes" : "no");
1128 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1129 irqen & IRQEN_RSE ? "enabled" : "disabled");
1131 v4l2_info(sd, "IR Transmitter:\n");
1132 v4l2_info(sd, "\tEnabled: %s\n",
1133 cntrl & CNTRL_TXE ? "yes" : "no");
1134 v4l2_info(sd, "\tModulation onto a carrier: %s\n",
1135 cntrl & CNTRL_MOD ? "enabled" : "disabled");
1136 v4l2_info(sd, "\tFIFO: %s\n",
1137 cntrl & CNTRL_TFE ? "enabled" : "disabled");
1138 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1139 cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1140 v4l2_info(sd, "\tCarrier polarity: %s\n",
1141 cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1142 : "space:noburst mark:burst");
1143 if (cntrl & CNTRL_MOD) {
1144 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
1145 clock_divider_to_carrier_freq(txclk));
1146 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
1149 v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n",
1150 pulse_width_count_to_us(FIFO_RXTX, txclk),
1151 pulse_width_count_to_ns(FIFO_RXTX, txclk));
1152 v4l2_info(sd, "\tBusy: %s\n",
1153 stats & STATS_TBY ? "yes" : "no");
1154 v4l2_info(sd, "\tFIFO service requested: %s\n",
1155 stats & STATS_TSR ? "yes" : "no");
1156 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1157 irqen & IRQEN_TSE ? "enabled" : "disabled");
1163 const struct v4l2_subdev_ir_ops cx25840_ir_ops = {
1164 .rx_read = cx25840_ir_rx_read,
1165 .rx_g_parameters = cx25840_ir_rx_g_parameters,
1166 .rx_s_parameters = cx25840_ir_rx_s_parameters,
1168 .tx_write = cx25840_ir_tx_write,
1169 .tx_g_parameters = cx25840_ir_tx_g_parameters,
1170 .tx_s_parameters = cx25840_ir_tx_s_parameters,
1174 static const struct v4l2_subdev_ir_parameters default_rx_params = {
1175 .bytes_per_data_element = sizeof(u32),
1176 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1179 .interrupt_enable = false,
1183 .carrier_freq = 36000, /* 36 kHz - RC-5, and RC-6 carrier */
1185 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1186 /* RC-6: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1187 .noise_filter_min_width = 333333, /* ns */
1188 .carrier_range_lower = 35000,
1189 .carrier_range_upper = 37000,
1190 .invert_level = false,
1193 static const struct v4l2_subdev_ir_parameters default_tx_params = {
1194 .bytes_per_data_element = sizeof(u32),
1195 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1198 .interrupt_enable = false,
1202 .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1203 .duty_cycle = 25, /* 25 % - RC-5 carrier */
1204 .invert_level = false,
1205 .invert_carrier_sense = false,
1208 int cx25840_ir_probe(struct v4l2_subdev *sd)
1210 struct cx25840_state *state = to_state(sd);
1211 struct cx25840_ir_state *ir_state;
1212 struct v4l2_subdev_ir_parameters default_params;
1214 /* Only init the IR controller for the CX2388[57] AV Core for now */
1215 if (!(is_cx23885(state) || is_cx23887(state)))
1218 ir_state = kzalloc(sizeof(struct cx25840_ir_state), GFP_KERNEL);
1219 if (ir_state == NULL)
1222 spin_lock_init(&ir_state->rx_kfifo_lock);
1223 if (kfifo_alloc(&ir_state->rx_kfifo,
1224 CX25840_IR_RX_KFIFO_SIZE, GFP_KERNEL)) {
1229 ir_state->c = state->c;
1230 state->ir_state = ir_state;
1232 /* Ensure no interrupts arrive yet */
1233 if (is_cx23885(state) || is_cx23887(state))
1234 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, IRQEN_MSK);
1236 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, 0);
1238 mutex_init(&ir_state->rx_params_lock);
1239 memcpy(&default_params, &default_rx_params,
1240 sizeof(struct v4l2_subdev_ir_parameters));
1241 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1243 mutex_init(&ir_state->tx_params_lock);
1244 memcpy(&default_params, &default_tx_params,
1245 sizeof(struct v4l2_subdev_ir_parameters));
1246 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1251 int cx25840_ir_remove(struct v4l2_subdev *sd)
1253 struct cx25840_state *state = to_state(sd);
1254 struct cx25840_ir_state *ir_state = to_ir_state(sd);
1256 if (ir_state == NULL)
1259 cx25840_ir_rx_shutdown(sd);
1260 cx25840_ir_tx_shutdown(sd);
1262 kfifo_free(&ir_state->rx_kfifo);
1264 state->ir_state = NULL;