1 #define EM_GPIO_0 (1 << 0)
2 #define EM_GPIO_1 (1 << 1)
3 #define EM_GPIO_2 (1 << 2)
4 #define EM_GPIO_3 (1 << 3)
5 #define EM_GPIO_4 (1 << 4)
6 #define EM_GPIO_5 (1 << 5)
7 #define EM_GPIO_6 (1 << 6)
8 #define EM_GPIO_7 (1 << 7)
10 #define EM_GPO_0 (1 << 0)
11 #define EM_GPO_1 (1 << 1)
12 #define EM_GPO_2 (1 << 2)
13 #define EM_GPO_3 (1 << 3)
15 /* em2800 registers */
16 #define EM2800_R08_AUDIOSRC 0x08
18 /* em28xx registers */
20 #define EM28XX_R00_CHIPCFG 0x00
22 /* em28xx Chip Configuration 0x00 */
23 #define EM28XX_CHIPCFG_VENDOR_AUDIO 0x80
24 #define EM28XX_CHIPCFG_I2S_VOLUME_CAPABLE 0x40
25 #define EM28XX_CHIPCFG_I2S_5_SAMPRATES 0x30
26 #define EM28XX_CHIPCFG_I2S_3_SAMPRATES 0x20
27 #define EM28XX_CHIPCFG_AC97 0x10
28 #define EM28XX_CHIPCFG_AUDIOMASK 0x30
30 /* GPIO/GPO registers */
31 #define EM2880_R04_GPO 0x04 /* em2880-em2883 only */
32 #define EM28XX_R08_GPIO 0x08 /* em2820 or upper */
34 #define EM28XX_R06_I2C_CLK 0x06
36 /* em28xx I2C Clock Register (0x06) */
37 #define EM28XX_I2C_CLK_ACK_LAST_READ 0x80
38 #define EM28XX_I2C_CLK_WAIT_ENABLE 0x40
39 #define EM28XX_I2C_EEPROM_ON_BOARD 0x08
40 #define EM28XX_I2C_EEPROM_KEY_VALID 0x04
41 #define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c busses */
42 #define EM28XX_I2C_FREQ_1_5_MHZ 0x03 /* bus frequency (bits [1-0]) */
43 #define EM28XX_I2C_FREQ_25_KHZ 0x02
44 #define EM28XX_I2C_FREQ_400_KHZ 0x01
45 #define EM28XX_I2C_FREQ_100_KHZ 0x00
48 #define EM28XX_R0A_CHIPID 0x0a
49 #define EM28XX_R0C_USBSUSP 0x0c /* */
51 #define EM28XX_R0E_AUDIOSRC 0x0e
52 #define EM28XX_R0F_XCLK 0x0f
54 /* em28xx XCLK Register (0x0f) */
55 #define EM28XX_XCLK_AUDIO_UNMUTE 0x80 /* otherwise audio muted */
56 #define EM28XX_XCLK_I2S_MSB_TIMING 0x40 /* otherwise standard timing */
57 #define EM28XX_XCLK_IR_RC5_MODE 0x20 /* otherwise NEC mode */
58 #define EM28XX_XCLK_IR_NEC_CHK_PARITY 0x10
59 #define EM28XX_XCLK_FREQUENCY_30MHZ 0x00 /* Freq. select (bits [3-0]) */
60 #define EM28XX_XCLK_FREQUENCY_15MHZ 0x01
61 #define EM28XX_XCLK_FREQUENCY_10MHZ 0x02
62 #define EM28XX_XCLK_FREQUENCY_7_5MHZ 0x03
63 #define EM28XX_XCLK_FREQUENCY_6MHZ 0x04
64 #define EM28XX_XCLK_FREQUENCY_5MHZ 0x05
65 #define EM28XX_XCLK_FREQUENCY_4_3MHZ 0x06
66 #define EM28XX_XCLK_FREQUENCY_12MHZ 0x07
67 #define EM28XX_XCLK_FREQUENCY_20MHZ 0x08
68 #define EM28XX_XCLK_FREQUENCY_20MHZ_2 0x09
69 #define EM28XX_XCLK_FREQUENCY_48MHZ 0x0a
70 #define EM28XX_XCLK_FREQUENCY_24MHZ 0x0b
72 #define EM28XX_R10_VINMODE 0x10
73 #define EM28XX_R11_VINCTRL 0x11
74 #define EM28XX_R12_VINENABLE 0x12 /* */
76 #define EM28XX_R14_GAMMA 0x14
77 #define EM28XX_R15_RGAIN 0x15
78 #define EM28XX_R16_GGAIN 0x16
79 #define EM28XX_R17_BGAIN 0x17
80 #define EM28XX_R18_ROFFSET 0x18
81 #define EM28XX_R19_GOFFSET 0x19
82 #define EM28XX_R1A_BOFFSET 0x1a
84 #define EM28XX_R1B_OFLOW 0x1b
85 #define EM28XX_R1C_HSTART 0x1c
86 #define EM28XX_R1D_VSTART 0x1d
87 #define EM28XX_R1E_CWIDTH 0x1e
88 #define EM28XX_R1F_CHEIGHT 0x1f
90 #define EM28XX_R20_YGAIN 0x20
91 #define EM28XX_R21_YOFFSET 0x21
92 #define EM28XX_R22_UVGAIN 0x22
93 #define EM28XX_R23_UOFFSET 0x23
94 #define EM28XX_R24_VOFFSET 0x24
95 #define EM28XX_R25_SHARPNESS 0x25
97 #define EM28XX_R26_COMPR 0x26
98 #define EM28XX_R27_OUTFMT 0x27
100 #define EM28XX_R28_XMIN 0x28
101 #define EM28XX_R29_XMAX 0x29
102 #define EM28XX_R2A_YMIN 0x2a
103 #define EM28XX_R2B_YMAX 0x2b
105 #define EM28XX_R30_HSCALELOW 0x30
106 #define EM28XX_R31_HSCALEHIGH 0x31
107 #define EM28XX_R32_VSCALELOW 0x32
108 #define EM28XX_R33_VSCALEHIGH 0x33
110 #define EM28XX_R40_AC97LSB 0x40
111 #define EM28XX_R41_AC97MSB 0x41
112 #define EM28XX_R42_AC97ADDR 0x42
113 #define EM28XX_R43_AC97BUSY 0x43
115 #define EM28XX_R45_IR 0x45
116 /* 0x45 bit 7 - parity bit
122 /* em2874 registers */
123 #define EM2874_R50_IR_CONFIG 0x50
124 #define EM2874_R51_IR 0x51
125 #define EM2874_R5F_TS_ENABLE 0x5f
126 #define EM2874_R80_GPIO 0x80
128 /* em2874 IR config register (0x50) */
129 #define EM2874_IR_NEC 0x00
130 #define EM2874_IR_RC5 0x04
131 #define EM2874_IR_RC5_MODE_0 0x08
132 #define EM2874_IR_RC5_MODE_6A 0x0b
134 /* em2874 Transport Stream Enable Register (0x5f) */
135 #define EM2874_TS1_CAPTURE_ENABLE (1 << 0)
136 #define EM2874_TS1_FILTER_ENABLE (1 << 1)
137 #define EM2874_TS1_NULL_DISCARD (1 << 2)
138 #define EM2874_TS2_CAPTURE_ENABLE (1 << 4)
139 #define EM2874_TS2_FILTER_ENABLE (1 << 5)
140 #define EM2874_TS2_NULL_DISCARD (1 << 6)
142 /* register settings */
143 #define EM2800_AUDIO_SRC_TUNER 0x0d
144 #define EM2800_AUDIO_SRC_LINE 0x0c
145 #define EM28XX_AUDIO_SRC_TUNER 0xc0
146 #define EM28XX_AUDIO_SRC_LINE 0x80
148 /* FIXME: Need to be populated with the other chip ID's */
149 enum em28xx_chip_id {
160 * Registers used by em202 and other AC97 chips
163 /* Standard AC97 registers */
164 #define AC97_RESET 0x00
167 #define AC97_MASTER_VOL 0x02
168 #define AC97_LINE_LEVEL_VOL 0x04 /* Some devices use for headphones */
169 #define AC97_MASTER_MONO_VOL 0x06
172 #define AC97_PC_BEEP_VOL 0x0a
173 #define AC97_PHONE_VOL 0x0c
174 #define AC97_MIC_VOL 0x0e
175 #define AC97_LINEIN_VOL 0x10
176 #define AC97_CD_VOL 0x12
177 #define AC97_VIDEO_VOL 0x14
178 #define AC97_AUX_VOL 0x16
179 #define AC97_PCM_OUT_VOL 0x18
181 /* capture registers */
182 #define AC97_RECORD_SELECT 0x1a
183 #define AC97_RECORD_GAIN 0x1c
185 /* control registers */
186 #define AC97_GENERAL_PURPOSE 0x20
187 #define AC97_3D_CTRL 0x22
188 #define AC97_AUD_INT_AND_PAG 0x24
189 #define AC97_POWER_DOWN_CTRL 0x26
190 #define AC97_EXT_AUD_ID 0x28
191 #define AC97_EXT_AUD_CTRL 0x2a
193 /* Supported rate varies for each AC97 device
194 if write an unsupported value, it will return the closest one
196 #define AC97_PCM_OUT_FRONT_SRATE 0x2c
197 #define AC97_PCM_OUT_SURR_SRATE 0x2e
198 #define AC97_PCM_OUT_LFE_SRATE 0x30
199 #define AC97_PCM_IN_SRATE 0x32
201 /* For devices with more than 2 channels, extra output volumes */
202 #define AC97_LFE_MASTER_VOL 0x36
203 #define AC97_SURR_MASTER_VOL 0x38
205 /* Digital SPDIF output control */
206 #define AC97_SPDIF_OUT_CTRL 0x3a
208 /* Vendor ID identifier */
209 #define AC97_VENDOR_ID1 0x7c
210 #define AC97_VENDOR_ID2 0x7e
212 /* EMP202 vendor registers */
213 #define EM202_EXT_MODEM_CTRL 0x3e
214 #define EM202_GPIO_CONF 0x4c
215 #define EM202_GPIO_POLARITY 0x4e
216 #define EM202_GPIO_STICKY 0x50
217 #define EM202_GPIO_MASK 0x52
218 #define EM202_GPIO_STATUS 0x54
219 #define EM202_SPDIF_OUT_SEL 0x6a
220 #define EM202_ANTIPOP 0x72
221 #define EM202_EAPD_GPIO_ACCESS 0x74