2 * Driver for MT9P031 CMOS Image Sensor from Aptina
4 * Copyright (C) 2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com>
6 * Copyright (C) 2011, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8 * Based on the MT9V032 driver and Bastian Hecht's code.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/module.h>
18 #include <linux/i2c.h>
19 #include <linux/log2.h>
21 #include <linux/slab.h>
22 #include <media/v4l2-subdev.h>
23 #include <linux/videodev2.h>
25 #include <media/mt9p031.h>
26 #include <media/v4l2-chip-ident.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-subdev.h>
31 #define MT9P031_PIXEL_ARRAY_WIDTH 2752
32 #define MT9P031_PIXEL_ARRAY_HEIGHT 2004
34 #define MT9P031_CHIP_VERSION 0x00
35 #define MT9P031_CHIP_VERSION_VALUE 0x1801
36 #define MT9P031_ROW_START 0x01
37 #define MT9P031_ROW_START_MIN 0
38 #define MT9P031_ROW_START_MAX 2004
39 #define MT9P031_ROW_START_DEF 54
40 #define MT9P031_COLUMN_START 0x02
41 #define MT9P031_COLUMN_START_MIN 0
42 #define MT9P031_COLUMN_START_MAX 2750
43 #define MT9P031_COLUMN_START_DEF 16
44 #define MT9P031_WINDOW_HEIGHT 0x03
45 #define MT9P031_WINDOW_HEIGHT_MIN 2
46 #define MT9P031_WINDOW_HEIGHT_MAX 2006
47 #define MT9P031_WINDOW_HEIGHT_DEF 1944
48 #define MT9P031_WINDOW_WIDTH 0x04
49 #define MT9P031_WINDOW_WIDTH_MIN 2
50 #define MT9P031_WINDOW_WIDTH_MAX 2752
51 #define MT9P031_WINDOW_WIDTH_DEF 2592
52 #define MT9P031_HORIZONTAL_BLANK 0x05
53 #define MT9P031_HORIZONTAL_BLANK_MIN 0
54 #define MT9P031_HORIZONTAL_BLANK_MAX 4095
55 #define MT9P031_VERTICAL_BLANK 0x06
56 #define MT9P031_VERTICAL_BLANK_MIN 0
57 #define MT9P031_VERTICAL_BLANK_MAX 4095
58 #define MT9P031_VERTICAL_BLANK_DEF 25
59 #define MT9P031_OUTPUT_CONTROL 0x07
60 #define MT9P031_OUTPUT_CONTROL_CEN 2
61 #define MT9P031_OUTPUT_CONTROL_SYN 1
62 #define MT9P031_OUTPUT_CONTROL_DEF 0x1f82
63 #define MT9P031_SHUTTER_WIDTH_UPPER 0x08
64 #define MT9P031_SHUTTER_WIDTH_LOWER 0x09
65 #define MT9P031_SHUTTER_WIDTH_MIN 1
66 #define MT9P031_SHUTTER_WIDTH_MAX 1048575
67 #define MT9P031_SHUTTER_WIDTH_DEF 1943
68 #define MT9P031_PLL_CONTROL 0x10
69 #define MT9P031_PLL_CONTROL_PWROFF 0x0050
70 #define MT9P031_PLL_CONTROL_PWRON 0x0051
71 #define MT9P031_PLL_CONTROL_USEPLL 0x0052
72 #define MT9P031_PLL_CONFIG_1 0x11
73 #define MT9P031_PLL_CONFIG_2 0x12
74 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a
75 #define MT9P031_FRAME_RESTART 0x0b
76 #define MT9P031_SHUTTER_DELAY 0x0c
77 #define MT9P031_RST 0x0d
78 #define MT9P031_RST_ENABLE 1
79 #define MT9P031_RST_DISABLE 0
80 #define MT9P031_READ_MODE_1 0x1e
81 #define MT9P031_READ_MODE_2 0x20
82 #define MT9P031_READ_MODE_2_ROW_MIR (1 << 15)
83 #define MT9P031_READ_MODE_2_COL_MIR (1 << 14)
84 #define MT9P031_READ_MODE_2_ROW_BLC (1 << 6)
85 #define MT9P031_ROW_ADDRESS_MODE 0x22
86 #define MT9P031_COLUMN_ADDRESS_MODE 0x23
87 #define MT9P031_GLOBAL_GAIN 0x35
88 #define MT9P031_GLOBAL_GAIN_MIN 8
89 #define MT9P031_GLOBAL_GAIN_MAX 1024
90 #define MT9P031_GLOBAL_GAIN_DEF 8
91 #define MT9P031_GLOBAL_GAIN_MULT (1 << 6)
92 #define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b
93 #define MT9P031_TEST_PATTERN 0xa0
94 #define MT9P031_TEST_PATTERN_SHIFT 3
95 #define MT9P031_TEST_PATTERN_ENABLE (1 << 0)
96 #define MT9P031_TEST_PATTERN_DISABLE (0 << 0)
97 #define MT9P031_TEST_PATTERN_GREEN 0xa1
98 #define MT9P031_TEST_PATTERN_RED 0xa2
99 #define MT9P031_TEST_PATTERN_BLUE 0xa3
101 struct mt9p031_pll_divs {
110 struct v4l2_subdev subdev;
111 struct media_pad pad;
112 struct v4l2_rect crop; /* Sensor window */
113 struct v4l2_mbus_framefmt format;
114 struct v4l2_ctrl_handler ctrls;
115 struct mt9p031_platform_data *pdata;
116 struct mutex power_lock; /* lock to protect power_count */
121 const struct mt9p031_pll_divs *pll;
123 /* Registers cache */
128 static struct mt9p031 *to_mt9p031(struct v4l2_subdev *sd)
130 return container_of(sd, struct mt9p031, subdev);
133 static int mt9p031_read(struct i2c_client *client, u8 reg)
135 return i2c_smbus_read_word_swapped(client, reg);
138 static int mt9p031_write(struct i2c_client *client, u8 reg, u16 data)
140 return i2c_smbus_write_word_swapped(client, reg, data);
143 static int mt9p031_set_output_control(struct mt9p031 *mt9p031, u16 clear,
146 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
147 u16 value = (mt9p031->output_control & ~clear) | set;
150 ret = mt9p031_write(client, MT9P031_OUTPUT_CONTROL, value);
154 mt9p031->output_control = value;
158 static int mt9p031_set_mode2(struct mt9p031 *mt9p031, u16 clear, u16 set)
160 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
161 u16 value = (mt9p031->mode2 & ~clear) | set;
164 ret = mt9p031_write(client, MT9P031_READ_MODE_2, value);
168 mt9p031->mode2 = value;
172 static int mt9p031_reset(struct mt9p031 *mt9p031)
174 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
177 /* Disable chip output, synchronous option update */
178 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_ENABLE);
181 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_DISABLE);
185 return mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN,
190 * This static table uses ext_freq and vdd_io values to select suitable
191 * PLL dividers m, n and p1 which have been calculated as specifiec in p36
192 * of Aptina's mt9p031 datasheet. New values should be added here.
194 static const struct mt9p031_pll_divs mt9p031_divs[] = {
195 /* ext_freq target_freq m n p1 */
196 {21000000, 48000000, 26, 2, 6}
199 static int mt9p031_pll_get_divs(struct mt9p031 *mt9p031)
201 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
204 for (i = 0; i < ARRAY_SIZE(mt9p031_divs); i++) {
205 if (mt9p031_divs[i].ext_freq == mt9p031->pdata->ext_freq &&
206 mt9p031_divs[i].target_freq == mt9p031->pdata->target_freq) {
207 mt9p031->pll = &mt9p031_divs[i];
212 dev_err(&client->dev, "Couldn't find PLL dividers for ext_freq = %d, "
213 "target_freq = %d\n", mt9p031->pdata->ext_freq,
214 mt9p031->pdata->target_freq);
218 static int mt9p031_pll_enable(struct mt9p031 *mt9p031)
220 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
223 ret = mt9p031_write(client, MT9P031_PLL_CONTROL,
224 MT9P031_PLL_CONTROL_PWRON);
228 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_1,
229 (mt9p031->pll->m << 8) | (mt9p031->pll->n - 1));
233 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll->p1 - 1);
237 usleep_range(1000, 2000);
238 ret = mt9p031_write(client, MT9P031_PLL_CONTROL,
239 MT9P031_PLL_CONTROL_PWRON |
240 MT9P031_PLL_CONTROL_USEPLL);
244 static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031)
246 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
248 return mt9p031_write(client, MT9P031_PLL_CONTROL,
249 MT9P031_PLL_CONTROL_PWROFF);
252 static int mt9p031_power_on(struct mt9p031 *mt9p031)
254 /* Ensure RESET_BAR is low */
255 if (mt9p031->pdata->reset) {
256 mt9p031->pdata->reset(&mt9p031->subdev, 1);
257 usleep_range(1000, 2000);
261 if (mt9p031->pdata->set_xclk)
262 mt9p031->pdata->set_xclk(&mt9p031->subdev,
263 mt9p031->pdata->ext_freq);
265 /* Now RESET_BAR must be high */
266 if (mt9p031->pdata->reset) {
267 mt9p031->pdata->reset(&mt9p031->subdev, 0);
268 usleep_range(1000, 2000);
274 static void mt9p031_power_off(struct mt9p031 *mt9p031)
276 if (mt9p031->pdata->reset) {
277 mt9p031->pdata->reset(&mt9p031->subdev, 1);
278 usleep_range(1000, 2000);
281 if (mt9p031->pdata->set_xclk)
282 mt9p031->pdata->set_xclk(&mt9p031->subdev, 0);
285 static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on)
287 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
291 mt9p031_power_off(mt9p031);
295 ret = mt9p031_power_on(mt9p031);
299 ret = mt9p031_reset(mt9p031);
301 dev_err(&client->dev, "Failed to reset the camera\n");
305 return v4l2_ctrl_handler_setup(&mt9p031->ctrls);
308 /* -----------------------------------------------------------------------------
309 * V4L2 subdev video operations
312 static int mt9p031_set_params(struct mt9p031 *mt9p031)
314 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
315 struct v4l2_mbus_framefmt *format = &mt9p031->format;
316 const struct v4l2_rect *crop = &mt9p031->crop;
325 /* Windows position and size.
327 * TODO: Make sure the start coordinates and window size match the
328 * skipping, binning and mirroring (see description of registers 2 and 4
329 * in table 13, and Binning section on page 41).
331 ret = mt9p031_write(client, MT9P031_COLUMN_START, crop->left);
334 ret = mt9p031_write(client, MT9P031_ROW_START, crop->top);
337 ret = mt9p031_write(client, MT9P031_WINDOW_WIDTH, crop->width - 1);
340 ret = mt9p031_write(client, MT9P031_WINDOW_HEIGHT, crop->height - 1);
344 /* Row and column binning and skipping. Use the maximum binning value
345 * compatible with the skipping settings.
347 xskip = DIV_ROUND_CLOSEST(crop->width, format->width);
348 yskip = DIV_ROUND_CLOSEST(crop->height, format->height);
349 xbin = 1 << (ffs(xskip) - 1);
350 ybin = 1 << (ffs(yskip) - 1);
352 ret = mt9p031_write(client, MT9P031_COLUMN_ADDRESS_MODE,
353 ((xbin - 1) << 4) | (xskip - 1));
356 ret = mt9p031_write(client, MT9P031_ROW_ADDRESS_MODE,
357 ((ybin - 1) << 4) | (yskip - 1));
361 /* Blanking - use minimum value for horizontal blanking and default
362 * value for vertical blanking.
364 hblank = 346 * ybin + 64 + (80 >> max_t(unsigned int, xbin, 3));
365 vblank = MT9P031_VERTICAL_BLANK_DEF;
367 ret = mt9p031_write(client, MT9P031_HORIZONTAL_BLANK, hblank);
370 ret = mt9p031_write(client, MT9P031_VERTICAL_BLANK, vblank);
377 static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable)
379 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
383 /* Stop sensor readout */
384 ret = mt9p031_set_output_control(mt9p031,
385 MT9P031_OUTPUT_CONTROL_CEN, 0);
389 return mt9p031_pll_disable(mt9p031);
392 ret = mt9p031_set_params(mt9p031);
396 /* Switch to master "normal" mode */
397 ret = mt9p031_set_output_control(mt9p031, 0,
398 MT9P031_OUTPUT_CONTROL_CEN);
402 return mt9p031_pll_enable(mt9p031);
405 static int mt9p031_enum_mbus_code(struct v4l2_subdev *subdev,
406 struct v4l2_subdev_fh *fh,
407 struct v4l2_subdev_mbus_code_enum *code)
409 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
411 if (code->pad || code->index)
414 code->code = mt9p031->format.code;
418 static int mt9p031_enum_frame_size(struct v4l2_subdev *subdev,
419 struct v4l2_subdev_fh *fh,
420 struct v4l2_subdev_frame_size_enum *fse)
422 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
424 if (fse->index >= 8 || fse->code != mt9p031->format.code)
427 fse->min_width = MT9P031_WINDOW_WIDTH_DEF
428 / min_t(unsigned int, 7, fse->index + 1);
429 fse->max_width = fse->min_width;
430 fse->min_height = MT9P031_WINDOW_HEIGHT_DEF / (fse->index + 1);
431 fse->max_height = fse->min_height;
436 static struct v4l2_mbus_framefmt *
437 __mt9p031_get_pad_format(struct mt9p031 *mt9p031, struct v4l2_subdev_fh *fh,
438 unsigned int pad, u32 which)
441 case V4L2_SUBDEV_FORMAT_TRY:
442 return v4l2_subdev_get_try_format(fh, pad);
443 case V4L2_SUBDEV_FORMAT_ACTIVE:
444 return &mt9p031->format;
450 static struct v4l2_rect *
451 __mt9p031_get_pad_crop(struct mt9p031 *mt9p031, struct v4l2_subdev_fh *fh,
452 unsigned int pad, u32 which)
455 case V4L2_SUBDEV_FORMAT_TRY:
456 return v4l2_subdev_get_try_crop(fh, pad);
457 case V4L2_SUBDEV_FORMAT_ACTIVE:
458 return &mt9p031->crop;
464 static int mt9p031_get_format(struct v4l2_subdev *subdev,
465 struct v4l2_subdev_fh *fh,
466 struct v4l2_subdev_format *fmt)
468 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
470 fmt->format = *__mt9p031_get_pad_format(mt9p031, fh, fmt->pad,
475 static int mt9p031_set_format(struct v4l2_subdev *subdev,
476 struct v4l2_subdev_fh *fh,
477 struct v4l2_subdev_format *format)
479 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
480 struct v4l2_mbus_framefmt *__format;
481 struct v4l2_rect *__crop;
487 __crop = __mt9p031_get_pad_crop(mt9p031, fh, format->pad,
490 /* Clamp the width and height to avoid dividing by zero. */
491 width = clamp_t(unsigned int, ALIGN(format->format.width, 2),
492 max(__crop->width / 7, MT9P031_WINDOW_WIDTH_MIN),
494 height = clamp_t(unsigned int, ALIGN(format->format.height, 2),
495 max(__crop->height / 8, MT9P031_WINDOW_HEIGHT_MIN),
498 hratio = DIV_ROUND_CLOSEST(__crop->width, width);
499 vratio = DIV_ROUND_CLOSEST(__crop->height, height);
501 __format = __mt9p031_get_pad_format(mt9p031, fh, format->pad,
503 __format->width = __crop->width / hratio;
504 __format->height = __crop->height / vratio;
506 format->format = *__format;
511 static int mt9p031_get_crop(struct v4l2_subdev *subdev,
512 struct v4l2_subdev_fh *fh,
513 struct v4l2_subdev_crop *crop)
515 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
517 crop->rect = *__mt9p031_get_pad_crop(mt9p031, fh, crop->pad,
522 static int mt9p031_set_crop(struct v4l2_subdev *subdev,
523 struct v4l2_subdev_fh *fh,
524 struct v4l2_subdev_crop *crop)
526 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
527 struct v4l2_mbus_framefmt *__format;
528 struct v4l2_rect *__crop;
529 struct v4l2_rect rect;
531 /* Clamp the crop rectangle boundaries and align them to a multiple of 2
532 * pixels to ensure a GRBG Bayer pattern.
534 rect.left = clamp(ALIGN(crop->rect.left, 2), MT9P031_COLUMN_START_MIN,
535 MT9P031_COLUMN_START_MAX);
536 rect.top = clamp(ALIGN(crop->rect.top, 2), MT9P031_ROW_START_MIN,
537 MT9P031_ROW_START_MAX);
538 rect.width = clamp(ALIGN(crop->rect.width, 2),
539 MT9P031_WINDOW_WIDTH_MIN,
540 MT9P031_WINDOW_WIDTH_MAX);
541 rect.height = clamp(ALIGN(crop->rect.height, 2),
542 MT9P031_WINDOW_HEIGHT_MIN,
543 MT9P031_WINDOW_HEIGHT_MAX);
545 rect.width = min(rect.width, MT9P031_PIXEL_ARRAY_WIDTH - rect.left);
546 rect.height = min(rect.height, MT9P031_PIXEL_ARRAY_HEIGHT - rect.top);
548 __crop = __mt9p031_get_pad_crop(mt9p031, fh, crop->pad, crop->which);
550 if (rect.width != __crop->width || rect.height != __crop->height) {
551 /* Reset the output image size if the crop rectangle size has
554 __format = __mt9p031_get_pad_format(mt9p031, fh, crop->pad,
556 __format->width = rect.width;
557 __format->height = rect.height;
566 /* -----------------------------------------------------------------------------
567 * V4L2 subdev control operations
570 #define V4L2_CID_TEST_PATTERN (V4L2_CID_USER_BASE | 0x1001)
572 static int mt9p031_s_ctrl(struct v4l2_ctrl *ctrl)
574 struct mt9p031 *mt9p031 =
575 container_of(ctrl->handler, struct mt9p031, ctrls);
576 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
581 case V4L2_CID_EXPOSURE:
582 ret = mt9p031_write(client, MT9P031_SHUTTER_WIDTH_UPPER,
583 (ctrl->val >> 16) & 0xffff);
587 return mt9p031_write(client, MT9P031_SHUTTER_WIDTH_LOWER,
591 /* Gain is controlled by 2 analog stages and a digital stage.
592 * Valid values for the 3 stages are
595 * ------------------------------------------
596 * First analog stage x1 x2 1
597 * Second analog stage x1 x4 0.125
598 * Digital stage x1 x16 0.125
600 * To minimize noise, the gain stages should be used in the
601 * second analog stage, first analog stage, digital stage order.
602 * Gain from a previous stage should be pushed to its maximum
603 * value before the next stage is used.
605 if (ctrl->val <= 32) {
607 } else if (ctrl->val <= 64) {
609 data = (1 << 6) | (ctrl->val >> 1);
612 data = ((ctrl->val - 64) << 5) | (1 << 6) | 32;
615 return mt9p031_write(client, MT9P031_GLOBAL_GAIN, data);
619 return mt9p031_set_mode2(mt9p031,
620 0, MT9P031_READ_MODE_2_COL_MIR);
622 return mt9p031_set_mode2(mt9p031,
623 MT9P031_READ_MODE_2_COL_MIR, 0);
627 return mt9p031_set_mode2(mt9p031,
628 0, MT9P031_READ_MODE_2_ROW_MIR);
630 return mt9p031_set_mode2(mt9p031,
631 MT9P031_READ_MODE_2_ROW_MIR, 0);
633 case V4L2_CID_TEST_PATTERN:
635 ret = mt9p031_set_mode2(mt9p031,
636 0, MT9P031_READ_MODE_2_ROW_BLC);
640 return mt9p031_write(client, MT9P031_TEST_PATTERN,
641 MT9P031_TEST_PATTERN_DISABLE);
644 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0);
647 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_RED, 0x0a50);
650 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_BLUE, 0x0aa0);
654 ret = mt9p031_set_mode2(mt9p031, MT9P031_READ_MODE_2_ROW_BLC,
658 ret = mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 0);
662 return mt9p031_write(client, MT9P031_TEST_PATTERN,
663 ((ctrl->val - 1) << MT9P031_TEST_PATTERN_SHIFT)
664 | MT9P031_TEST_PATTERN_ENABLE);
669 static struct v4l2_ctrl_ops mt9p031_ctrl_ops = {
670 .s_ctrl = mt9p031_s_ctrl,
673 static const char * const mt9p031_test_pattern_menu[] = {
676 "Horizontal Gradient",
679 "Classic Test Pattern",
681 "Monochrome Horizontal Bars",
682 "Monochrome Vertical Bars",
683 "Vertical Color Bars",
686 static const struct v4l2_ctrl_config mt9p031_ctrls[] = {
688 .ops = &mt9p031_ctrl_ops,
689 .id = V4L2_CID_TEST_PATTERN,
690 .type = V4L2_CTRL_TYPE_MENU,
691 .name = "Test Pattern",
693 .max = ARRAY_SIZE(mt9p031_test_pattern_menu) - 1,
698 .qmenu = mt9p031_test_pattern_menu,
702 /* -----------------------------------------------------------------------------
703 * V4L2 subdev core operations
706 static int mt9p031_set_power(struct v4l2_subdev *subdev, int on)
708 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
711 mutex_lock(&mt9p031->power_lock);
713 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
714 * update the power state.
716 if (mt9p031->power_count == !on) {
717 ret = __mt9p031_set_power(mt9p031, !!on);
722 /* Update the power count. */
723 mt9p031->power_count += on ? 1 : -1;
724 WARN_ON(mt9p031->power_count < 0);
727 mutex_unlock(&mt9p031->power_lock);
731 /* -----------------------------------------------------------------------------
732 * V4L2 subdev internal operations
735 static int mt9p031_registered(struct v4l2_subdev *subdev)
737 struct i2c_client *client = v4l2_get_subdevdata(subdev);
738 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
742 ret = mt9p031_power_on(mt9p031);
744 dev_err(&client->dev, "MT9P031 power up failed\n");
748 /* Read out the chip version register */
749 data = mt9p031_read(client, MT9P031_CHIP_VERSION);
750 if (data != MT9P031_CHIP_VERSION_VALUE) {
751 dev_err(&client->dev, "MT9P031 not detected, wrong version "
756 mt9p031_power_off(mt9p031);
758 dev_info(&client->dev, "MT9P031 detected at address 0x%02x\n",
764 static int mt9p031_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
766 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
767 struct v4l2_mbus_framefmt *format;
768 struct v4l2_rect *crop;
770 crop = v4l2_subdev_get_try_crop(fh, 0);
771 crop->left = MT9P031_COLUMN_START_DEF;
772 crop->top = MT9P031_ROW_START_DEF;
773 crop->width = MT9P031_WINDOW_WIDTH_DEF;
774 crop->height = MT9P031_WINDOW_HEIGHT_DEF;
776 format = v4l2_subdev_get_try_format(fh, 0);
778 if (mt9p031->pdata->version == MT9P031_MONOCHROME_VERSION)
779 format->code = V4L2_MBUS_FMT_Y12_1X12;
781 format->code = V4L2_MBUS_FMT_SGRBG12_1X12;
783 format->width = MT9P031_WINDOW_WIDTH_DEF;
784 format->height = MT9P031_WINDOW_HEIGHT_DEF;
785 format->field = V4L2_FIELD_NONE;
786 format->colorspace = V4L2_COLORSPACE_SRGB;
790 return mt9p031_set_power(subdev, 1);
793 static int mt9p031_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
795 return mt9p031_set_power(subdev, 0);
798 static struct v4l2_subdev_core_ops mt9p031_subdev_core_ops = {
799 .s_power = mt9p031_set_power,
802 static struct v4l2_subdev_video_ops mt9p031_subdev_video_ops = {
803 .s_stream = mt9p031_s_stream,
806 static struct v4l2_subdev_pad_ops mt9p031_subdev_pad_ops = {
807 .enum_mbus_code = mt9p031_enum_mbus_code,
808 .enum_frame_size = mt9p031_enum_frame_size,
809 .get_fmt = mt9p031_get_format,
810 .set_fmt = mt9p031_set_format,
811 .get_crop = mt9p031_get_crop,
812 .set_crop = mt9p031_set_crop,
815 static struct v4l2_subdev_ops mt9p031_subdev_ops = {
816 .core = &mt9p031_subdev_core_ops,
817 .video = &mt9p031_subdev_video_ops,
818 .pad = &mt9p031_subdev_pad_ops,
821 static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = {
822 .registered = mt9p031_registered,
823 .open = mt9p031_open,
824 .close = mt9p031_close,
827 /* -----------------------------------------------------------------------------
828 * Driver initialization and probing
831 static int mt9p031_probe(struct i2c_client *client,
832 const struct i2c_device_id *did)
834 struct mt9p031_platform_data *pdata = client->dev.platform_data;
835 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
836 struct mt9p031 *mt9p031;
841 dev_err(&client->dev, "No platform data\n");
845 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
846 dev_warn(&client->dev,
847 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
851 mt9p031 = kzalloc(sizeof(*mt9p031), GFP_KERNEL);
855 mt9p031->pdata = pdata;
856 mt9p031->output_control = MT9P031_OUTPUT_CONTROL_DEF;
857 mt9p031->mode2 = MT9P031_READ_MODE_2_ROW_BLC;
859 v4l2_ctrl_handler_init(&mt9p031->ctrls, ARRAY_SIZE(mt9p031_ctrls) + 4);
861 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
862 V4L2_CID_EXPOSURE, MT9P031_SHUTTER_WIDTH_MIN,
863 MT9P031_SHUTTER_WIDTH_MAX, 1,
864 MT9P031_SHUTTER_WIDTH_DEF);
865 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
866 V4L2_CID_GAIN, MT9P031_GLOBAL_GAIN_MIN,
867 MT9P031_GLOBAL_GAIN_MAX, 1, MT9P031_GLOBAL_GAIN_DEF);
868 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
869 V4L2_CID_HFLIP, 0, 1, 1, 0);
870 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
871 V4L2_CID_VFLIP, 0, 1, 1, 0);
873 for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i)
874 v4l2_ctrl_new_custom(&mt9p031->ctrls, &mt9p031_ctrls[i], NULL);
876 mt9p031->subdev.ctrl_handler = &mt9p031->ctrls;
878 if (mt9p031->ctrls.error)
879 printk(KERN_INFO "%s: control initialization error %d\n",
880 __func__, mt9p031->ctrls.error);
882 mutex_init(&mt9p031->power_lock);
883 v4l2_i2c_subdev_init(&mt9p031->subdev, client, &mt9p031_subdev_ops);
884 mt9p031->subdev.internal_ops = &mt9p031_subdev_internal_ops;
886 mt9p031->pad.flags = MEDIA_PAD_FL_SOURCE;
887 ret = media_entity_init(&mt9p031->subdev.entity, 1, &mt9p031->pad, 0);
891 mt9p031->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
893 mt9p031->crop.width = MT9P031_WINDOW_WIDTH_DEF;
894 mt9p031->crop.height = MT9P031_WINDOW_HEIGHT_DEF;
895 mt9p031->crop.left = MT9P031_COLUMN_START_DEF;
896 mt9p031->crop.top = MT9P031_ROW_START_DEF;
898 if (mt9p031->pdata->version == MT9P031_MONOCHROME_VERSION)
899 mt9p031->format.code = V4L2_MBUS_FMT_Y12_1X12;
901 mt9p031->format.code = V4L2_MBUS_FMT_SGRBG12_1X12;
903 mt9p031->format.width = MT9P031_WINDOW_WIDTH_DEF;
904 mt9p031->format.height = MT9P031_WINDOW_HEIGHT_DEF;
905 mt9p031->format.field = V4L2_FIELD_NONE;
906 mt9p031->format.colorspace = V4L2_COLORSPACE_SRGB;
908 ret = mt9p031_pll_get_divs(mt9p031);
912 v4l2_ctrl_handler_free(&mt9p031->ctrls);
913 media_entity_cleanup(&mt9p031->subdev.entity);
920 static int mt9p031_remove(struct i2c_client *client)
922 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
923 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
925 v4l2_ctrl_handler_free(&mt9p031->ctrls);
926 v4l2_device_unregister_subdev(subdev);
927 media_entity_cleanup(&subdev->entity);
933 static const struct i2c_device_id mt9p031_id[] = {
937 MODULE_DEVICE_TABLE(i2c, mt9p031_id);
939 static struct i2c_driver mt9p031_i2c_driver = {
943 .probe = mt9p031_probe,
944 .remove = mt9p031_remove,
945 .id_table = mt9p031_id,
948 static int __init mt9p031_mod_init(void)
950 return i2c_add_driver(&mt9p031_i2c_driver);
953 static void __exit mt9p031_mod_exit(void)
955 i2c_del_driver(&mt9p031_i2c_driver);
958 module_init(mt9p031_mod_init);
959 module_exit(mt9p031_mod_exit);
961 MODULE_DESCRIPTION("Aptina MT9P031 Camera driver");
962 MODULE_AUTHOR("Bastian Hecht <hechtb@gmail.com>");
963 MODULE_LICENSE("GPL v2");