2 * V4L2 SoC Camera driver for OMAP1 Camera Interface
4 * Copyright (C) 2010, Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
6 * Based on V4L2 Driver for i.MXL/i.MXL camera (CSI) host
7 * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
8 * Copyright (C) 2009, Darius Augulis <augulis.darius@gmail.com>
10 * Based on PXA SoC camera driver
11 * Copyright (C) 2006, Sascha Hauer, Pengutronix
12 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
14 * Hardware specific bits initialy based on former work by Matt Callow
15 * drivers/media/video/omap/omap1510cam.c
16 * Copyright (C) 2006 Matt Callow
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
24 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
30 #include <media/omap1_camera.h>
31 #include <media/soc_camera.h>
32 #include <media/soc_mediabus.h>
33 #include <media/videobuf-dma-contig.h>
34 #include <media/videobuf-dma-sg.h>
39 #define DRIVER_NAME "omap1-camera"
40 #define DRIVER_VERSION "0.0.2"
44 * ---------------------------------------------------------------------------
45 * OMAP1 Camera Interface registers
46 * ---------------------------------------------------------------------------
49 #define REG_CTRLCLOCK 0x00
50 #define REG_IT_STATUS 0x04
52 #define REG_STATUS 0x0C
53 #define REG_CAMDATA 0x10
55 #define REG_PEAK_COUNTER 0x18
57 /* CTRLCLOCK bit shifts */
58 #define LCLK_EN BIT(7)
59 #define DPLL_EN BIT(6)
60 #define MCLK_EN BIT(5)
61 #define CAMEXCLK_EN BIT(4)
63 #define FOSCMOD_SHIFT 0
64 #define FOSCMOD_MASK (0x7 << FOSCMOD_SHIFT)
65 #define FOSCMOD_12MHz 0x0
66 #define FOSCMOD_6MHz 0x2
67 #define FOSCMOD_9_6MHz 0x4
68 #define FOSCMOD_24MHz 0x5
69 #define FOSCMOD_8MHz 0x6
71 /* IT_STATUS bit shifts */
72 #define DATA_TRANSFER BIT(5)
73 #define FIFO_FULL BIT(4)
80 #define RAZ_FIFO BIT(18)
81 #define EN_FIFO_FULL BIT(17)
82 #define EN_NIRQ BIT(16)
83 #define THRESHOLD_SHIFT 9
84 #define THRESHOLD_MASK (0x7f << THRESHOLD_SHIFT)
86 #define EN_H_DOWN BIT(7)
87 #define EN_H_UP BIT(6)
88 #define EN_V_DOWN BIT(5)
89 #define EN_V_UP BIT(4)
90 #define ORDERCAMD BIT(3)
92 #define IRQ_MASK (EN_V_UP | EN_V_DOWN | EN_H_UP | EN_H_DOWN | \
93 EN_NIRQ | EN_FIFO_FULL)
95 /* STATUS bit shifts */
96 #define HSTATUS BIT(1)
97 #define VSTATUS BIT(0)
100 #define CAM_RST BIT(0)
102 /* end of OMAP1 Camera Interface registers */
105 #define SOCAM_BUS_FLAGS (SOCAM_MASTER | \
106 SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_HIGH | \
107 SOCAM_PCLK_SAMPLE_RISING | SOCAM_PCLK_SAMPLE_FALLING | \
108 SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATAWIDTH_8)
111 #define FIFO_SIZE ((THRESHOLD_MASK >> THRESHOLD_SHIFT) + 1)
112 #define FIFO_SHIFT __fls(FIFO_SIZE)
114 #define DMA_BURST_SHIFT (1 + OMAP_DMA_DATA_BURST_4)
115 #define DMA_BURST_SIZE (1 << DMA_BURST_SHIFT)
117 #define DMA_ELEMENT_SHIFT OMAP_DMA_DATA_TYPE_S32
118 #define DMA_ELEMENT_SIZE (1 << DMA_ELEMENT_SHIFT)
120 #define DMA_FRAME_SHIFT_CONTIG (FIFO_SHIFT - 1)
121 #define DMA_FRAME_SHIFT_SG DMA_BURST_SHIFT
123 #define DMA_FRAME_SHIFT(x) ((x) == OMAP1_CAM_DMA_CONTIG ? \
124 DMA_FRAME_SHIFT_CONTIG : \
126 #define DMA_FRAME_SIZE(x) (1 << DMA_FRAME_SHIFT(x))
127 #define DMA_SYNC OMAP_DMA_SYNC_FRAME
128 #define THRESHOLD_LEVEL DMA_FRAME_SIZE
131 #define MAX_VIDEO_MEM 4 /* arbitrary video memory limit in MB */
138 /* buffer for one video frame */
139 struct omap1_cam_buf {
140 struct videobuf_buffer vb;
141 enum v4l2_mbus_pixelcode code;
143 struct scatterlist *sgbuf;
146 enum videobuf_state result;
149 struct omap1_cam_dev {
150 struct soc_camera_host soc_host;
151 struct soc_camera_device *icd;
159 struct omap1_cam_platform_data *pdata;
160 struct resource *res;
161 unsigned long pflags;
162 unsigned long camexclk;
164 struct list_head capture;
166 /* lock used to protect videobuf */
169 /* Pointers to DMA buffers */
170 struct omap1_cam_buf *active;
171 struct omap1_cam_buf *ready;
173 enum omap1_cam_vb_mode vb_mode;
174 int (*mmap_mapper)(struct videobuf_queue *q,
175 struct videobuf_buffer *buf,
176 struct vm_area_struct *vma);
182 static void cam_write(struct omap1_cam_dev *pcdev, u16 reg, u32 val)
184 pcdev->reg_cache[reg / sizeof(u32)] = val;
185 __raw_writel(val, pcdev->base + reg);
188 static u32 cam_read(struct omap1_cam_dev *pcdev, u16 reg, bool from_cache)
190 return !from_cache ? __raw_readl(pcdev->base + reg) :
191 pcdev->reg_cache[reg / sizeof(u32)];
194 #define CAM_READ(pcdev, reg) \
195 cam_read(pcdev, REG_##reg, false)
196 #define CAM_WRITE(pcdev, reg, val) \
197 cam_write(pcdev, REG_##reg, val)
198 #define CAM_READ_CACHE(pcdev, reg) \
199 cam_read(pcdev, REG_##reg, true)
202 * Videobuf operations
204 static int omap1_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
207 struct soc_camera_device *icd = vq->priv_data;
208 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
209 icd->current_fmt->host_fmt);
210 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
211 struct omap1_cam_dev *pcdev = ici->priv;
213 if (bytes_per_line < 0)
214 return bytes_per_line;
216 *size = bytes_per_line * icd->user_height;
218 if (!*count || *count < OMAP1_CAMERA_MIN_BUF_COUNT(pcdev->vb_mode))
219 *count = OMAP1_CAMERA_MIN_BUF_COUNT(pcdev->vb_mode);
221 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
222 *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size;
225 "%s: count=%d, size=%d\n", __func__, *count, *size);
230 static void free_buffer(struct videobuf_queue *vq, struct omap1_cam_buf *buf,
231 enum omap1_cam_vb_mode vb_mode)
233 struct videobuf_buffer *vb = &buf->vb;
235 BUG_ON(in_interrupt());
237 videobuf_waiton(vq, vb, 0, 0);
239 if (vb_mode == OMAP1_CAM_DMA_CONTIG) {
240 videobuf_dma_contig_free(vq, vb);
242 struct soc_camera_device *icd = vq->priv_data;
243 struct device *dev = icd->parent;
244 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
246 videobuf_dma_unmap(dev, dma);
247 videobuf_dma_free(dma);
250 vb->state = VIDEOBUF_NEEDS_INIT;
253 static int omap1_videobuf_prepare(struct videobuf_queue *vq,
254 struct videobuf_buffer *vb, enum v4l2_field field)
256 struct soc_camera_device *icd = vq->priv_data;
257 struct omap1_cam_buf *buf = container_of(vb, struct omap1_cam_buf, vb);
258 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
259 icd->current_fmt->host_fmt);
260 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
261 struct omap1_cam_dev *pcdev = ici->priv;
264 if (bytes_per_line < 0)
265 return bytes_per_line;
267 WARN_ON(!list_empty(&vb->queue));
269 BUG_ON(NULL == icd->current_fmt);
273 if (buf->code != icd->current_fmt->code || vb->field != field ||
274 vb->width != icd->user_width ||
275 vb->height != icd->user_height) {
276 buf->code = icd->current_fmt->code;
277 vb->width = icd->user_width;
278 vb->height = icd->user_height;
280 vb->state = VIDEOBUF_NEEDS_INIT;
283 vb->size = bytes_per_line * vb->height;
285 if (vb->baddr && vb->bsize < vb->size) {
290 if (vb->state == VIDEOBUF_NEEDS_INIT) {
291 ret = videobuf_iolock(vq, vb, NULL);
295 vb->state = VIDEOBUF_PREPARED;
301 free_buffer(vq, buf, pcdev->vb_mode);
307 static void set_dma_dest_params(int dma_ch, struct omap1_cam_buf *buf,
308 enum omap1_cam_vb_mode vb_mode)
311 unsigned int block_size;
313 if (vb_mode == OMAP1_CAM_DMA_CONTIG) {
314 dma_addr = videobuf_to_dma_contig(&buf->vb);
315 block_size = buf->vb.size;
317 if (WARN_ON(!buf->sgbuf)) {
318 buf->result = VIDEOBUF_ERROR;
321 dma_addr = sg_dma_address(buf->sgbuf);
322 if (WARN_ON(!dma_addr)) {
324 buf->result = VIDEOBUF_ERROR;
327 block_size = sg_dma_len(buf->sgbuf);
328 if (WARN_ON(!block_size)) {
330 buf->result = VIDEOBUF_ERROR;
333 if (unlikely(buf->bytes_left < block_size))
334 block_size = buf->bytes_left;
335 if (WARN_ON(dma_addr & (DMA_FRAME_SIZE(vb_mode) *
336 DMA_ELEMENT_SIZE - 1))) {
337 dma_addr = ALIGN(dma_addr, DMA_FRAME_SIZE(vb_mode) *
339 block_size &= ~(DMA_FRAME_SIZE(vb_mode) *
340 DMA_ELEMENT_SIZE - 1);
342 buf->bytes_left -= block_size;
346 omap_set_dma_dest_params(dma_ch,
347 OMAP_DMA_PORT_EMIFF, OMAP_DMA_AMODE_POST_INC, dma_addr, 0, 0);
348 omap_set_dma_transfer_params(dma_ch,
349 OMAP_DMA_DATA_TYPE_S32, DMA_FRAME_SIZE(vb_mode),
350 block_size >> (DMA_FRAME_SHIFT(vb_mode) + DMA_ELEMENT_SHIFT),
354 static struct omap1_cam_buf *prepare_next_vb(struct omap1_cam_dev *pcdev)
356 struct omap1_cam_buf *buf;
359 * If there is already a buffer pointed out by the pcdev->ready,
360 * (re)use it, otherwise try to fetch and configure a new one.
364 if (list_empty(&pcdev->capture))
366 buf = list_entry(pcdev->capture.next,
367 struct omap1_cam_buf, vb.queue);
368 buf->vb.state = VIDEOBUF_ACTIVE;
370 list_del_init(&buf->vb.queue);
373 if (pcdev->vb_mode == OMAP1_CAM_DMA_CONTIG) {
375 * In CONTIG mode, we can safely enter next buffer parameters
376 * into the DMA programming register set after the DMA
377 * has already been activated on the previous buffer
379 set_dma_dest_params(pcdev->dma_ch, buf, pcdev->vb_mode);
382 * In SG mode, the above is not safe since there are probably
383 * a bunch of sgbufs from previous sglist still pending.
384 * Instead, mark the sglist fresh for the upcoming
393 static struct scatterlist *try_next_sgbuf(int dma_ch, struct omap1_cam_buf *buf)
395 struct scatterlist *sgbuf;
397 if (likely(buf->sgbuf)) {
398 /* current sglist is active */
399 if (unlikely(!buf->bytes_left)) {
400 /* indicate sglist complete */
403 /* process next sgbuf */
404 sgbuf = sg_next(buf->sgbuf);
405 if (WARN_ON(!sgbuf)) {
406 buf->result = VIDEOBUF_ERROR;
407 } else if (WARN_ON(!sg_dma_len(sgbuf))) {
409 buf->result = VIDEOBUF_ERROR;
414 /* sglist is fresh, initialize it before using */
415 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
418 if (!(WARN_ON(!sgbuf))) {
421 buf->bytes_left = buf->vb.size;
422 buf->result = VIDEOBUF_DONE;
427 * Put our next sgbuf parameters (address, size)
428 * into the DMA programming register set.
430 set_dma_dest_params(dma_ch, buf, OMAP1_CAM_DMA_SG);
435 static void start_capture(struct omap1_cam_dev *pcdev)
437 struct omap1_cam_buf *buf = pcdev->active;
438 u32 ctrlclock = CAM_READ_CACHE(pcdev, CTRLCLOCK);
439 u32 mode = CAM_READ_CACHE(pcdev, MODE) & ~EN_V_DOWN;
445 * Enable start of frame interrupt, which we will use for activating
446 * our end of frame watchdog when capture actually starts.
450 if (unlikely(ctrlclock & LCLK_EN))
451 /* stop pixel clock before FIFO reset */
452 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~LCLK_EN);
454 CAM_WRITE(pcdev, MODE, mode | RAZ_FIFO);
456 omap_start_dma(pcdev->dma_ch);
458 if (pcdev->vb_mode == OMAP1_CAM_DMA_SG) {
460 * In SG mode, it's a good moment for fetching next sgbuf
461 * from the current sglist and, if available, already putting
462 * its parameters into the DMA programming register set.
464 try_next_sgbuf(pcdev->dma_ch, buf);
467 /* (re)enable pixel clock */
468 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock | LCLK_EN);
469 /* release FIFO reset */
470 CAM_WRITE(pcdev, MODE, mode);
473 static void suspend_capture(struct omap1_cam_dev *pcdev)
475 u32 ctrlclock = CAM_READ_CACHE(pcdev, CTRLCLOCK);
477 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~LCLK_EN);
478 omap_stop_dma(pcdev->dma_ch);
481 static void disable_capture(struct omap1_cam_dev *pcdev)
483 u32 mode = CAM_READ_CACHE(pcdev, MODE);
485 CAM_WRITE(pcdev, MODE, mode & ~(IRQ_MASK | DMA));
488 static void omap1_videobuf_queue(struct videobuf_queue *vq,
489 struct videobuf_buffer *vb)
491 struct soc_camera_device *icd = vq->priv_data;
492 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
493 struct omap1_cam_dev *pcdev = ici->priv;
494 struct omap1_cam_buf *buf;
497 list_add_tail(&vb->queue, &pcdev->capture);
498 vb->state = VIDEOBUF_QUEUED;
502 * Capture in progress, so don't touch pcdev->ready even if
503 * empty. Since the transfer of the DMA programming register set
504 * content to the DMA working register set is done automatically
505 * by the DMA hardware, this can pretty well happen while we
506 * are keeping the lock here. Leave fetching it from the queue
507 * to be done when a next DMA interrupt occures instead.
512 WARN_ON(pcdev->ready);
514 buf = prepare_next_vb(pcdev);
522 "%s: capture not active, setup FIFO, start DMA\n", __func__);
523 mode = CAM_READ_CACHE(pcdev, MODE) & ~THRESHOLD_MASK;
524 mode |= THRESHOLD_LEVEL(pcdev->vb_mode) << THRESHOLD_SHIFT;
525 CAM_WRITE(pcdev, MODE, mode | EN_FIFO_FULL | DMA);
527 if (pcdev->vb_mode == OMAP1_CAM_DMA_SG) {
529 * In SG mode, the above prepare_next_vb() didn't actually
530 * put anything into the DMA programming register set,
531 * so we have to do it now, before activating DMA.
533 try_next_sgbuf(pcdev->dma_ch, buf);
536 start_capture(pcdev);
539 static void omap1_videobuf_release(struct videobuf_queue *vq,
540 struct videobuf_buffer *vb)
542 struct omap1_cam_buf *buf =
543 container_of(vb, struct omap1_cam_buf, vb);
544 struct soc_camera_device *icd = vq->priv_data;
545 struct device *dev = icd->parent;
546 struct soc_camera_host *ici = to_soc_camera_host(dev);
547 struct omap1_cam_dev *pcdev = ici->priv;
551 dev_dbg(dev, "%s (done)\n", __func__);
553 case VIDEOBUF_ACTIVE:
554 dev_dbg(dev, "%s (active)\n", __func__);
556 case VIDEOBUF_QUEUED:
557 dev_dbg(dev, "%s (queued)\n", __func__);
559 case VIDEOBUF_PREPARED:
560 dev_dbg(dev, "%s (prepared)\n", __func__);
563 dev_dbg(dev, "%s (unknown %d)\n", __func__, vb->state);
567 free_buffer(vq, buf, pcdev->vb_mode);
570 static void videobuf_done(struct omap1_cam_dev *pcdev,
571 enum videobuf_state result)
573 struct omap1_cam_buf *buf = pcdev->active;
574 struct videobuf_buffer *vb;
575 struct device *dev = pcdev->icd->parent;
578 suspend_capture(pcdev);
579 disable_capture(pcdev);
583 if (result == VIDEOBUF_ERROR)
584 suspend_capture(pcdev);
587 if (waitqueue_active(&vb->done)) {
588 if (!pcdev->ready && result != VIDEOBUF_ERROR) {
590 * No next buffer has been entered into the DMA
591 * programming register set on time (could be done only
592 * while the previous DMA interurpt was processed, not
593 * later), so the last DMA block, be it a whole buffer
594 * if in CONTIG or its last sgbuf if in SG mode, is
595 * about to be reused by the just autoreinitialized DMA
596 * engine, and overwritten with next frame data. Best we
597 * can do is stopping the capture as soon as possible,
598 * hopefully before the next frame start.
600 suspend_capture(pcdev);
603 do_gettimeofday(&vb->ts);
604 if (result != VIDEOBUF_ERROR)
608 /* shift in next buffer */
615 * No next buffer was ready on time (see above), so
616 * indicate error condition to force capture restart or
617 * stop, depending on next buffer already queued or not.
619 result = VIDEOBUF_ERROR;
620 prepare_next_vb(pcdev);
626 } else if (pcdev->ready) {
628 * In both CONTIG and SG mode, the DMA engine has possibly
629 * been already autoreinitialized with the preprogrammed
630 * pcdev->ready buffer. We can either accept this fact
631 * and just swap the buffers, or provoke an error condition
632 * and restart capture. The former seems less intrusive.
634 dev_dbg(dev, "%s: nobody waiting on videobuf, swap with next\n",
636 pcdev->active = pcdev->ready;
638 if (pcdev->vb_mode == OMAP1_CAM_DMA_SG) {
640 * In SG mode, we have to make sure that the buffer we
641 * are putting back into the pcdev->ready is marked
651 * No next buffer has been entered into
652 * the DMA programming register set on time.
654 if (pcdev->vb_mode == OMAP1_CAM_DMA_CONTIG) {
656 * In CONTIG mode, the DMA engine has already been
657 * reinitialized with the current buffer. Best we can do
658 * is not touching it.
661 "%s: nobody waiting on videobuf, reuse it\n",
665 * In SG mode, the DMA engine has just been
666 * autoreinitialized with the last sgbuf from the
667 * current list. Restart capture in order to transfer
668 * next frame start into the first sgbuf, not the last
671 if (result != VIDEOBUF_ERROR) {
672 suspend_capture(pcdev);
673 result = VIDEOBUF_ERROR;
679 dev_dbg(dev, "%s: no more videobufs, stop capture\n", __func__);
680 disable_capture(pcdev);
684 if (pcdev->vb_mode == OMAP1_CAM_DMA_CONTIG) {
686 * In CONTIG mode, the current buffer parameters had already
687 * been entered into the DMA programming register set while the
688 * buffer was fetched with prepare_next_vb(), they may have also
689 * been transferred into the runtime set and already active if
690 * the DMA still running.
693 /* In SG mode, extra steps are required */
694 if (result == VIDEOBUF_ERROR)
695 /* make sure we (re)use sglist from start on error */
699 * In any case, enter the next sgbuf parameters into the DMA
700 * programming register set. They will be used either during
701 * nearest DMA autoreinitialization or, in case of an error,
702 * on DMA startup below.
704 try_next_sgbuf(pcdev->dma_ch, buf);
707 if (result == VIDEOBUF_ERROR) {
708 dev_dbg(dev, "%s: videobuf error; reset FIFO, restart DMA\n",
710 start_capture(pcdev);
712 * In SG mode, the above also resulted in the next sgbuf
713 * parameters being entered into the DMA programming register
714 * set, making them ready for next DMA autoreinitialization.
719 * Finally, try fetching next buffer.
720 * In CONTIG mode, it will also enter it into the DMA programming
721 * register set, making it ready for next DMA autoreinitialization.
723 prepare_next_vb(pcdev);
726 static void dma_isr(int channel, unsigned short status, void *data)
728 struct omap1_cam_dev *pcdev = data;
729 struct omap1_cam_buf *buf = pcdev->active;
732 spin_lock_irqsave(&pcdev->lock, flags);
735 suspend_capture(pcdev);
736 disable_capture(pcdev);
740 if (pcdev->vb_mode == OMAP1_CAM_DMA_CONTIG) {
742 * In CONTIG mode, assume we have just managed to collect the
743 * whole frame, hopefully before our end of frame watchdog is
744 * triggered. Then, all we have to do is disabling the watchdog
745 * for this frame, and calling videobuf_done() with success
748 CAM_WRITE(pcdev, MODE,
749 CAM_READ_CACHE(pcdev, MODE) & ~EN_V_DOWN);
750 videobuf_done(pcdev, VIDEOBUF_DONE);
753 * In SG mode, we have to process every sgbuf from the current
754 * sglist, one after another.
758 * Current sglist not completed yet, try fetching next
759 * sgbuf, hopefully putting it into the DMA programming
760 * register set, making it ready for next DMA
761 * autoreinitialization.
763 try_next_sgbuf(pcdev->dma_ch, buf);
768 * No more sgbufs left in the current sglist. This
769 * doesn't mean that the whole videobuffer is already
770 * complete, but only that the last sgbuf from the
771 * current sglist is about to be filled. It will be
772 * ready on next DMA interrupt, signalled with the
773 * buf->sgbuf set back to NULL.
775 if (buf->result != VIDEOBUF_ERROR) {
777 * Video frame collected without errors so far,
778 * we can prepare for collecting a next one
779 * as soon as DMA gets autoreinitialized
780 * after the current (last) sgbuf is completed.
782 buf = prepare_next_vb(pcdev);
786 try_next_sgbuf(pcdev->dma_ch, buf);
790 /* end of videobuf */
791 videobuf_done(pcdev, buf->result);
795 spin_unlock_irqrestore(&pcdev->lock, flags);
798 static irqreturn_t cam_isr(int irq, void *data)
800 struct omap1_cam_dev *pcdev = data;
801 struct device *dev = pcdev->icd->parent;
802 struct omap1_cam_buf *buf = pcdev->active;
806 it_status = CAM_READ(pcdev, IT_STATUS);
810 spin_lock_irqsave(&pcdev->lock, flags);
813 dev_warn(dev, "%s: unhandled camera interrupt, status == %#x\n",
814 __func__, it_status);
815 suspend_capture(pcdev);
816 disable_capture(pcdev);
820 if (unlikely(it_status & FIFO_FULL)) {
821 dev_warn(dev, "%s: FIFO overflow\n", __func__);
823 } else if (it_status & V_DOWN) {
824 /* end of video frame watchdog */
825 if (pcdev->vb_mode == OMAP1_CAM_DMA_CONTIG) {
827 * In CONTIG mode, the watchdog is disabled with
828 * successful DMA end of block interrupt, and reenabled
829 * on next frame start. If we get here, there is nothing
830 * to check, we must be out of sync.
833 if (buf->sgcount == 2) {
835 * If exactly 2 sgbufs from the next sglist have
836 * been programmed into the DMA engine (the
837 * first one already transferred into the DMA
838 * runtime register set, the second one still
839 * in the programming set), then we are in sync.
844 dev_notice(dev, "%s: unexpected end of video frame\n",
847 } else if (it_status & V_UP) {
850 if (pcdev->vb_mode == OMAP1_CAM_DMA_CONTIG) {
852 * In CONTIG mode, we need this interrupt every frame
853 * in oredr to reenable our end of frame watchdog.
855 mode = CAM_READ_CACHE(pcdev, MODE);
858 * In SG mode, the below enabled end of frame watchdog
859 * is kept on permanently, so we can turn this one shot
862 mode = CAM_READ_CACHE(pcdev, MODE) & ~EN_V_UP;
865 if (!(mode & EN_V_DOWN)) {
866 /* (re)enable end of frame watchdog interrupt */
869 CAM_WRITE(pcdev, MODE, mode);
873 dev_warn(dev, "%s: unhandled camera interrupt, status == %#x\n",
874 __func__, it_status);
878 videobuf_done(pcdev, VIDEOBUF_ERROR);
880 spin_unlock_irqrestore(&pcdev->lock, flags);
884 static struct videobuf_queue_ops omap1_videobuf_ops = {
885 .buf_setup = omap1_videobuf_setup,
886 .buf_prepare = omap1_videobuf_prepare,
887 .buf_queue = omap1_videobuf_queue,
888 .buf_release = omap1_videobuf_release,
893 * SOC Camera host operations
896 static void sensor_reset(struct omap1_cam_dev *pcdev, bool reset)
898 /* apply/release camera sensor reset if requested by platform data */
899 if (pcdev->pflags & OMAP1_CAMERA_RST_HIGH)
900 CAM_WRITE(pcdev, GPIO, reset);
901 else if (pcdev->pflags & OMAP1_CAMERA_RST_LOW)
902 CAM_WRITE(pcdev, GPIO, !reset);
906 * The following two functions absolutely depend on the fact, that
907 * there can be only one camera on OMAP1 camera sensor interface
909 static int omap1_cam_add_device(struct soc_camera_device *icd)
911 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
912 struct omap1_cam_dev *pcdev = ici->priv;
918 clk_enable(pcdev->clk);
920 /* setup sensor clock */
921 ctrlclock = CAM_READ(pcdev, CTRLCLOCK);
922 ctrlclock &= ~(CAMEXCLK_EN | MCLK_EN | DPLL_EN);
923 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock);
925 ctrlclock &= ~FOSCMOD_MASK;
926 switch (pcdev->camexclk) {
928 ctrlclock |= CAMEXCLK_EN | FOSCMOD_6MHz;
931 ctrlclock |= CAMEXCLK_EN | FOSCMOD_8MHz | DPLL_EN;
934 ctrlclock |= CAMEXCLK_EN | FOSCMOD_9_6MHz | DPLL_EN;
937 ctrlclock |= CAMEXCLK_EN | FOSCMOD_12MHz;
940 ctrlclock |= CAMEXCLK_EN | FOSCMOD_24MHz | DPLL_EN;
944 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~DPLL_EN);
946 /* enable internal clock */
947 ctrlclock |= MCLK_EN;
948 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock);
950 sensor_reset(pcdev, false);
954 dev_dbg(icd->parent, "OMAP1 Camera driver attached to camera %d\n",
959 static void omap1_cam_remove_device(struct soc_camera_device *icd)
961 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
962 struct omap1_cam_dev *pcdev = ici->priv;
965 BUG_ON(icd != pcdev->icd);
967 suspend_capture(pcdev);
968 disable_capture(pcdev);
970 sensor_reset(pcdev, true);
972 /* disable and release system clocks */
973 ctrlclock = CAM_READ_CACHE(pcdev, CTRLCLOCK);
974 ctrlclock &= ~(MCLK_EN | DPLL_EN | CAMEXCLK_EN);
975 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock);
977 ctrlclock = (ctrlclock & ~FOSCMOD_MASK) | FOSCMOD_12MHz;
978 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock);
979 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock | MCLK_EN);
981 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~MCLK_EN);
983 clk_disable(pcdev->clk);
988 "OMAP1 Camera driver detached from camera %d\n", icd->devnum);
991 /* Duplicate standard formats based on host capability of byte swapping */
992 static const struct soc_mbus_lookup omap1_cam_formats[] = {
994 .code = V4L2_MBUS_FMT_UYVY8_2X8,
996 .fourcc = V4L2_PIX_FMT_YUYV,
998 .bits_per_sample = 8,
999 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1000 .order = SOC_MBUS_ORDER_BE,
1003 .code = V4L2_MBUS_FMT_VYUY8_2X8,
1005 .fourcc = V4L2_PIX_FMT_YVYU,
1007 .bits_per_sample = 8,
1008 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1009 .order = SOC_MBUS_ORDER_BE,
1012 .code = V4L2_MBUS_FMT_YUYV8_2X8,
1014 .fourcc = V4L2_PIX_FMT_UYVY,
1016 .bits_per_sample = 8,
1017 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1018 .order = SOC_MBUS_ORDER_BE,
1021 .code = V4L2_MBUS_FMT_YVYU8_2X8,
1023 .fourcc = V4L2_PIX_FMT_VYUY,
1025 .bits_per_sample = 8,
1026 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1027 .order = SOC_MBUS_ORDER_BE,
1030 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE,
1032 .fourcc = V4L2_PIX_FMT_RGB555,
1034 .bits_per_sample = 8,
1035 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1036 .order = SOC_MBUS_ORDER_BE,
1039 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
1041 .fourcc = V4L2_PIX_FMT_RGB555X,
1043 .bits_per_sample = 8,
1044 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1045 .order = SOC_MBUS_ORDER_BE,
1048 .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
1050 .fourcc = V4L2_PIX_FMT_RGB565,
1052 .bits_per_sample = 8,
1053 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1054 .order = SOC_MBUS_ORDER_BE,
1057 .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
1059 .fourcc = V4L2_PIX_FMT_RGB565X,
1061 .bits_per_sample = 8,
1062 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1063 .order = SOC_MBUS_ORDER_BE,
1068 static int omap1_cam_get_formats(struct soc_camera_device *icd,
1069 unsigned int idx, struct soc_camera_format_xlate *xlate)
1071 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1072 struct device *dev = icd->parent;
1073 int formats = 0, ret;
1074 enum v4l2_mbus_pixelcode code;
1075 const struct soc_mbus_pixelfmt *fmt;
1077 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1079 /* No more formats */
1082 fmt = soc_mbus_get_fmtdesc(code);
1084 dev_warn(dev, "%s: unsupported format code #%d: %d\n", __func__,
1089 /* Check support for the requested bits-per-sample */
1090 if (fmt->bits_per_sample != 8)
1094 case V4L2_MBUS_FMT_YUYV8_2X8:
1095 case V4L2_MBUS_FMT_YVYU8_2X8:
1096 case V4L2_MBUS_FMT_UYVY8_2X8:
1097 case V4L2_MBUS_FMT_VYUY8_2X8:
1098 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE:
1099 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
1100 case V4L2_MBUS_FMT_RGB565_2X8_BE:
1101 case V4L2_MBUS_FMT_RGB565_2X8_LE:
1104 xlate->host_fmt = soc_mbus_find_fmtdesc(code,
1106 ARRAY_SIZE(omap1_cam_formats));
1110 "%s: providing format %s as byte swapped code #%d\n",
1111 __func__, xlate->host_fmt->name, code);
1116 "%s: providing format %s in pass-through mode\n",
1117 __func__, fmt->name);
1121 xlate->host_fmt = fmt;
1129 static bool is_dma_aligned(s32 bytes_per_line, unsigned int height,
1130 enum omap1_cam_vb_mode vb_mode)
1132 int size = bytes_per_line * height;
1134 return IS_ALIGNED(bytes_per_line, DMA_ELEMENT_SIZE) &&
1135 IS_ALIGNED(size, DMA_FRAME_SIZE(vb_mode) * DMA_ELEMENT_SIZE);
1138 static int dma_align(int *width, int *height,
1139 const struct soc_mbus_pixelfmt *fmt,
1140 enum omap1_cam_vb_mode vb_mode, bool enlarge)
1142 s32 bytes_per_line = soc_mbus_bytes_per_line(*width, fmt);
1144 if (bytes_per_line < 0)
1145 return bytes_per_line;
1147 if (!is_dma_aligned(bytes_per_line, *height, vb_mode)) {
1148 unsigned int pxalign = __fls(bytes_per_line / *width);
1149 unsigned int salign = DMA_FRAME_SHIFT(vb_mode) +
1150 DMA_ELEMENT_SHIFT - pxalign;
1151 unsigned int incr = enlarge << salign;
1153 v4l_bound_align_image(width, 1, *width + incr, 0,
1154 height, 1, *height + incr, 0, salign);
1160 #define subdev_call_with_sense(pcdev, dev, icd, sd, function, args...) \
1162 struct soc_camera_sense sense = { \
1163 .master_clock = pcdev->camexclk, \
1164 .pixel_clock_max = 0, \
1169 sense.pixel_clock_max = pcdev->pdata->lclk_khz_max * 1000; \
1170 icd->sense = &sense; \
1171 __ret = v4l2_subdev_call(sd, video, function, ##args); \
1172 icd->sense = NULL; \
1174 if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { \
1175 if (sense.pixel_clock > sense.pixel_clock_max) { \
1177 "%s: pixel clock %lu set by the camera too high!\n", \
1178 __func__, sense.pixel_clock); \
1185 static int set_mbus_format(struct omap1_cam_dev *pcdev, struct device *dev,
1186 struct soc_camera_device *icd, struct v4l2_subdev *sd,
1187 struct v4l2_mbus_framefmt *mf,
1188 const struct soc_camera_format_xlate *xlate)
1191 int ret = subdev_call_with_sense(pcdev, dev, icd, sd, s_mbus_fmt, mf);
1194 dev_err(dev, "%s: s_mbus_fmt failed\n", __func__);
1198 if (mf->code != xlate->code) {
1199 dev_err(dev, "%s: unexpected pixel code change\n", __func__);
1203 bytes_per_line = soc_mbus_bytes_per_line(mf->width, xlate->host_fmt);
1204 if (bytes_per_line < 0) {
1205 dev_err(dev, "%s: soc_mbus_bytes_per_line() failed\n",
1207 return bytes_per_line;
1210 if (!is_dma_aligned(bytes_per_line, mf->height, pcdev->vb_mode)) {
1211 dev_err(dev, "%s: resulting geometry %ux%u not DMA aligned\n",
1212 __func__, mf->width, mf->height);
1218 static int omap1_cam_set_crop(struct soc_camera_device *icd,
1219 struct v4l2_crop *crop)
1221 struct v4l2_rect *rect = &crop->c;
1222 const struct soc_camera_format_xlate *xlate = icd->current_fmt;
1223 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1224 struct device *dev = icd->parent;
1225 struct soc_camera_host *ici = to_soc_camera_host(dev);
1226 struct omap1_cam_dev *pcdev = ici->priv;
1227 struct v4l2_mbus_framefmt mf;
1230 ret = subdev_call_with_sense(pcdev, dev, icd, sd, s_crop, crop);
1232 dev_warn(dev, "%s: failed to crop to %ux%u@%u:%u\n", __func__,
1233 rect->width, rect->height, rect->left, rect->top);
1237 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
1239 dev_warn(dev, "%s: failed to fetch current format\n", __func__);
1243 ret = dma_align(&mf.width, &mf.height, xlate->host_fmt, pcdev->vb_mode,
1246 dev_err(dev, "%s: failed to align %ux%u %s with DMA\n",
1247 __func__, mf.width, mf.height,
1248 xlate->host_fmt->name);
1253 /* sensor returned geometry not DMA aligned, trying to fix */
1254 ret = set_mbus_format(pcdev, dev, icd, sd, &mf, xlate);
1256 dev_err(dev, "%s: failed to set format\n", __func__);
1261 icd->user_width = mf.width;
1262 icd->user_height = mf.height;
1267 static int omap1_cam_set_fmt(struct soc_camera_device *icd,
1268 struct v4l2_format *f)
1270 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1271 const struct soc_camera_format_xlate *xlate;
1272 struct device *dev = icd->parent;
1273 struct soc_camera_host *ici = to_soc_camera_host(dev);
1274 struct omap1_cam_dev *pcdev = ici->priv;
1275 struct v4l2_pix_format *pix = &f->fmt.pix;
1276 struct v4l2_mbus_framefmt mf;
1279 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1281 dev_warn(dev, "%s: format %#x not found\n", __func__,
1286 mf.width = pix->width;
1287 mf.height = pix->height;
1288 mf.field = pix->field;
1289 mf.colorspace = pix->colorspace;
1290 mf.code = xlate->code;
1292 ret = dma_align(&mf.width, &mf.height, xlate->host_fmt, pcdev->vb_mode,
1295 dev_err(dev, "%s: failed to align %ux%u %s with DMA\n",
1296 __func__, pix->width, pix->height,
1297 xlate->host_fmt->name);
1301 ret = set_mbus_format(pcdev, dev, icd, sd, &mf, xlate);
1303 dev_err(dev, "%s: failed to set format\n", __func__);
1307 pix->width = mf.width;
1308 pix->height = mf.height;
1309 pix->field = mf.field;
1310 pix->colorspace = mf.colorspace;
1311 icd->current_fmt = xlate;
1316 static int omap1_cam_try_fmt(struct soc_camera_device *icd,
1317 struct v4l2_format *f)
1319 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1320 const struct soc_camera_format_xlate *xlate;
1321 struct v4l2_pix_format *pix = &f->fmt.pix;
1322 struct v4l2_mbus_framefmt mf;
1324 /* TODO: limit to mx1 hardware capabilities */
1326 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1328 dev_warn(icd->parent, "Format %#x not found\n",
1333 mf.width = pix->width;
1334 mf.height = pix->height;
1335 mf.field = pix->field;
1336 mf.colorspace = pix->colorspace;
1337 mf.code = xlate->code;
1339 /* limit to sensor capabilities */
1340 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1344 pix->width = mf.width;
1345 pix->height = mf.height;
1346 pix->field = mf.field;
1347 pix->colorspace = mf.colorspace;
1352 static bool sg_mode;
1355 * Local mmap_mapper wrapper,
1356 * used for detecting videobuf-dma-contig buffer allocation failures
1357 * and switching to videobuf-dma-sg automatically for future attempts.
1359 static int omap1_cam_mmap_mapper(struct videobuf_queue *q,
1360 struct videobuf_buffer *buf,
1361 struct vm_area_struct *vma)
1363 struct soc_camera_device *icd = q->priv_data;
1364 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1365 struct omap1_cam_dev *pcdev = ici->priv;
1368 ret = pcdev->mmap_mapper(q, buf, vma);
1376 static void omap1_cam_init_videobuf(struct videobuf_queue *q,
1377 struct soc_camera_device *icd)
1379 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1380 struct omap1_cam_dev *pcdev = ici->priv;
1383 videobuf_queue_dma_contig_init(q, &omap1_videobuf_ops,
1384 icd->parent, &pcdev->lock,
1385 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
1386 sizeof(struct omap1_cam_buf), icd, &icd->video_lock);
1388 videobuf_queue_sg_init(q, &omap1_videobuf_ops,
1389 icd->parent, &pcdev->lock,
1390 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
1391 sizeof(struct omap1_cam_buf), icd, &icd->video_lock);
1393 /* use videobuf mode (auto)selected with the module parameter */
1394 pcdev->vb_mode = sg_mode ? OMAP1_CAM_DMA_SG : OMAP1_CAM_DMA_CONTIG;
1397 * Ensure we substitute the videobuf-dma-contig version of the
1398 * mmap_mapper() callback with our own wrapper, used for switching
1399 * automatically to videobuf-dma-sg on buffer allocation failure.
1401 if (!sg_mode && q->int_ops->mmap_mapper != omap1_cam_mmap_mapper) {
1402 pcdev->mmap_mapper = q->int_ops->mmap_mapper;
1403 q->int_ops->mmap_mapper = omap1_cam_mmap_mapper;
1407 static int omap1_cam_reqbufs(struct soc_camera_device *icd,
1408 struct v4l2_requestbuffers *p)
1413 * This is for locking debugging only. I removed spinlocks and now I
1414 * check whether .prepare is ever called on a linked buffer, or whether
1415 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1416 * it hadn't triggered
1418 for (i = 0; i < p->count; i++) {
1419 struct omap1_cam_buf *buf = container_of(icd->vb_vidq.bufs[i],
1420 struct omap1_cam_buf, vb);
1422 INIT_LIST_HEAD(&buf->vb.queue);
1428 static int omap1_cam_querycap(struct soc_camera_host *ici,
1429 struct v4l2_capability *cap)
1431 /* cap->name is set by the friendly caller:-> */
1432 strlcpy(cap->card, "OMAP1 Camera", sizeof(cap->card));
1433 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1438 static int omap1_cam_set_bus_param(struct soc_camera_device *icd,
1441 struct device *dev = icd->parent;
1442 struct soc_camera_host *ici = to_soc_camera_host(dev);
1443 struct omap1_cam_dev *pcdev = ici->priv;
1444 const struct soc_camera_format_xlate *xlate;
1445 const struct soc_mbus_pixelfmt *fmt;
1446 unsigned long camera_flags, common_flags;
1447 u32 ctrlclock, mode;
1450 camera_flags = icd->ops->query_bus_param(icd);
1452 common_flags = soc_camera_bus_param_compatible(camera_flags,
1457 /* Make choices, possibly based on platform configuration */
1458 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1459 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1460 if (!pcdev->pdata ||
1461 pcdev->pdata->flags & OMAP1_CAMERA_LCLK_RISING)
1462 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1464 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1467 ret = icd->ops->set_bus_param(icd, common_flags);
1471 ctrlclock = CAM_READ_CACHE(pcdev, CTRLCLOCK);
1472 if (ctrlclock & LCLK_EN)
1473 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~LCLK_EN);
1475 if (common_flags & SOCAM_PCLK_SAMPLE_RISING) {
1476 dev_dbg(dev, "CTRLCLOCK_REG |= POLCLK\n");
1477 ctrlclock |= POLCLK;
1479 dev_dbg(dev, "CTRLCLOCK_REG &= ~POLCLK\n");
1480 ctrlclock &= ~POLCLK;
1482 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock & ~LCLK_EN);
1484 if (ctrlclock & LCLK_EN)
1485 CAM_WRITE(pcdev, CTRLCLOCK, ctrlclock);
1487 /* select bus endianess */
1488 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1489 fmt = xlate->host_fmt;
1491 mode = CAM_READ(pcdev, MODE) & ~(RAZ_FIFO | IRQ_MASK | DMA);
1492 if (fmt->order == SOC_MBUS_ORDER_LE) {
1493 dev_dbg(dev, "MODE_REG &= ~ORDERCAMD\n");
1494 CAM_WRITE(pcdev, MODE, mode & ~ORDERCAMD);
1496 dev_dbg(dev, "MODE_REG |= ORDERCAMD\n");
1497 CAM_WRITE(pcdev, MODE, mode | ORDERCAMD);
1503 static unsigned int omap1_cam_poll(struct file *file, poll_table *pt)
1505 struct soc_camera_device *icd = file->private_data;
1506 struct omap1_cam_buf *buf;
1508 buf = list_entry(icd->vb_vidq.stream.next, struct omap1_cam_buf,
1511 poll_wait(file, &buf->vb.done, pt);
1513 if (buf->vb.state == VIDEOBUF_DONE ||
1514 buf->vb.state == VIDEOBUF_ERROR)
1515 return POLLIN | POLLRDNORM;
1520 static struct soc_camera_host_ops omap1_host_ops = {
1521 .owner = THIS_MODULE,
1522 .add = omap1_cam_add_device,
1523 .remove = omap1_cam_remove_device,
1524 .get_formats = omap1_cam_get_formats,
1525 .set_crop = omap1_cam_set_crop,
1526 .set_fmt = omap1_cam_set_fmt,
1527 .try_fmt = omap1_cam_try_fmt,
1528 .init_videobuf = omap1_cam_init_videobuf,
1529 .reqbufs = omap1_cam_reqbufs,
1530 .querycap = omap1_cam_querycap,
1531 .set_bus_param = omap1_cam_set_bus_param,
1532 .poll = omap1_cam_poll,
1535 static int __init omap1_cam_probe(struct platform_device *pdev)
1537 struct omap1_cam_dev *pcdev;
1538 struct resource *res;
1544 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1545 irq = platform_get_irq(pdev, 0);
1546 if (!res || (int)irq <= 0) {
1551 clk = clk_get(&pdev->dev, "armper_ck");
1557 pcdev = kzalloc(sizeof(*pcdev) + resource_size(res), GFP_KERNEL);
1559 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1567 pcdev->pdata = pdev->dev.platform_data;
1568 pcdev->pflags = pcdev->pdata->flags;
1571 pcdev->camexclk = pcdev->pdata->camexclk_khz * 1000;
1573 switch (pcdev->camexclk) {
1581 dev_warn(&pdev->dev,
1582 "Incorrect sensor clock frequency %ld kHz, "
1583 "should be one of 0, 6, 8, 9.6, 12 or 24 MHz, "
1584 "please correct your platform data\n",
1585 pcdev->pdata->camexclk_khz);
1586 pcdev->camexclk = 0;
1588 dev_info(&pdev->dev,
1589 "Not providing sensor clock\n");
1592 INIT_LIST_HEAD(&pcdev->capture);
1593 spin_lock_init(&pcdev->lock);
1596 * Request the region.
1598 if (!request_mem_region(res->start, resource_size(res), DRIVER_NAME)) {
1603 base = ioremap(res->start, resource_size(res));
1611 sensor_reset(pcdev, true);
1613 err = omap_request_dma(OMAP_DMA_CAMERA_IF_RX, DRIVER_NAME,
1614 dma_isr, (void *)pcdev, &pcdev->dma_ch);
1616 dev_err(&pdev->dev, "Can't request DMA for OMAP1 Camera\n");
1620 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_ch);
1622 /* preconfigure DMA */
1623 omap_set_dma_src_params(pcdev->dma_ch, OMAP_DMA_PORT_TIPB,
1624 OMAP_DMA_AMODE_CONSTANT, res->start + REG_CAMDATA,
1626 omap_set_dma_dest_burst_mode(pcdev->dma_ch, OMAP_DMA_DATA_BURST_4);
1627 /* setup DMA autoinitialization */
1628 omap_dma_link_lch(pcdev->dma_ch, pcdev->dma_ch);
1630 err = request_irq(pcdev->irq, cam_isr, 0, DRIVER_NAME, pcdev);
1632 dev_err(&pdev->dev, "Camera interrupt register failed\n");
1636 pcdev->soc_host.drv_name = DRIVER_NAME;
1637 pcdev->soc_host.ops = &omap1_host_ops;
1638 pcdev->soc_host.priv = pcdev;
1639 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1640 pcdev->soc_host.nr = pdev->id;
1642 err = soc_camera_host_register(&pcdev->soc_host);
1646 dev_info(&pdev->dev, "OMAP1 Camera Interface driver loaded\n");
1651 free_irq(pcdev->irq, pcdev);
1653 omap_free_dma(pcdev->dma_ch);
1657 release_mem_region(res->start, resource_size(res));
1666 static int __exit omap1_cam_remove(struct platform_device *pdev)
1668 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1669 struct omap1_cam_dev *pcdev = container_of(soc_host,
1670 struct omap1_cam_dev, soc_host);
1671 struct resource *res;
1673 free_irq(pcdev->irq, pcdev);
1675 omap_free_dma(pcdev->dma_ch);
1677 soc_camera_host_unregister(soc_host);
1679 iounmap(pcdev->base);
1682 release_mem_region(res->start, resource_size(res));
1684 clk_put(pcdev->clk);
1688 dev_info(&pdev->dev, "OMAP1 Camera Interface driver unloaded\n");
1693 static struct platform_driver omap1_cam_driver = {
1695 .name = DRIVER_NAME,
1697 .probe = omap1_cam_probe,
1698 .remove = __exit_p(omap1_cam_remove),
1701 static int __init omap1_cam_init(void)
1703 return platform_driver_register(&omap1_cam_driver);
1705 module_init(omap1_cam_init);
1707 static void __exit omap1_cam_exit(void)
1709 platform_driver_unregister(&omap1_cam_driver);
1711 module_exit(omap1_cam_exit);
1713 module_param(sg_mode, bool, 0644);
1714 MODULE_PARM_DESC(sg_mode, "videobuf mode, 0: dma-contig (default), 1: dma-sg");
1716 MODULE_DESCRIPTION("OMAP1 Camera Interface driver");
1717 MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1718 MODULE_LICENSE("GPL v2");
1719 MODULE_LICENSE(DRIVER_VERSION);
1720 MODULE_ALIAS("platform:" DRIVER_NAME);