drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <asm/semaphore.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38
  39 struct usb_device_id pvr2_device_table[] = {
  40         [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
  41 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  42         [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
  43 #endif
  44         { }
  45 };
  46
  47 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
  48
  49 static const char *pvr2_device_names[] = {
  50         [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
  51 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  52         [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
  53 #endif
  54 };
  55
  56 struct pvr2_string_table {
  57         const char **lst;
  58         unsigned int cnt;
  59 };
  60
  61 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  62 // Names of other client modules to request for 24xxx model hardware
  63 static const char *pvr2_client_24xxx[] = {
  64         "cx25840",
  65         "tuner",
  66         "wm8775",
  67 };
  68 #endif
  69
  70 // Names of other client modules to request for 29xxx model hardware
  71 static const char *pvr2_client_29xxx[] = {
  72         "msp3400",
  73         "saa7115",
  74         "tuner",
  75 };
  76
  77 static struct pvr2_string_table pvr2_client_lists[] = {
  78         [PVR2_HDW_TYPE_29XXX] = {
  79                 pvr2_client_29xxx,
  80                 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
  81         },
  82 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  83         [PVR2_HDW_TYPE_24XXX] = {
  84                 pvr2_client_24xxx,
  85                 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
  86         },
  87 #endif
  88 };
  89
  90 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = 0};
  91 DECLARE_MUTEX(pvr2_unit_sem);
  92
  93 static int ctlchg = 0;
  94 static int initusbreset = 1;
  95 static int procreload = 0;
  96 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  97 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  98 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  99 static int init_pause_msec = 0;
 100
 101 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
 102 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
 103 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
 104 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
 105 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
 106 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
 107 module_param(procreload, int, S_IRUGO|S_IWUSR);
 108 MODULE_PARM_DESC(procreload,
 109                  "Attempt init failure recovery with firmware reload");
 110 module_param_array(tuner,    int, NULL, 0444);
 111 MODULE_PARM_DESC(tuner,"specify installed tuner type");
 112 module_param_array(video_std,    int, NULL, 0444);
 113 MODULE_PARM_DESC(video_std,"specify initial video standard");
 114 module_param_array(tolerance,    int, NULL, 0444);
 115 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
 116
 117 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 118 #define PVR2_CTL_READ_ENDPOINT   0x81
 119
 120 #define PVR2_GPIO_IN 0x9008
 121 #define PVR2_GPIO_OUT 0x900c
 122 #define PVR2_GPIO_DIR 0x9020
 123
 124 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 125
 126 #define PVR2_FIRMWARE_ENDPOINT   0x02
 127
 128 /* size of a firmware chunk */
 129 #define FIRMWARE_CHUNK_SIZE 0x2000
 130
 131 /* Define the list of additional controls we'll dynamically construct based
 132    on query of the cx2341x module. */
 133 struct pvr2_mpeg_ids {
 134         const char *strid;
 135         int id;
 136 };
 137 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 138         {
 139                 .strid = "audio_layer",
 140                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 141         },{
 142                 .strid = "audio_bitrate",
 143                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 144         },{
 145                 /* Already using audio_mode elsewhere :-( */
 146                 .strid = "mpeg_audio_mode",
 147                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 148         },{
 149                 .strid = "mpeg_audio_mode_extension",
 150                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 151         },{
 152                 .strid = "audio_emphasis",
 153                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 154         },{
 155                 .strid = "audio_crc",
 156                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 157         },{
 158                 .strid = "video_aspect",
 159                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 160         },{
 161                 .strid = "video_b_frames",
 162                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 163         },{
 164                 .strid = "video_gop_size",
 165                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 166         },{
 167                 .strid = "video_gop_closure",
 168                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 169         },{
 170                 .strid = "video_pulldown",
 171                 .id = V4L2_CID_MPEG_VIDEO_PULLDOWN,
 172         },{
 173                 .strid = "video_bitrate_mode",
 174                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 175         },{
 176                 .strid = "video_bitrate",
 177                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 178         },{
 179                 .strid = "video_bitrate_peak",
 180                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 181         },{
 182                 .strid = "video_temporal_decimation",
 183                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 184         },{
 185                 .strid = "stream_type",
 186                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 187         },{
 188                 .strid = "video_spatial_filter_mode",
 189                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 190         },{
 191                 .strid = "video_spatial_filter",
 192                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 193         },{
 194                 .strid = "video_luma_spatial_filter_type",
 195                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 196         },{
 197                 .strid = "video_chroma_spatial_filter_type",
 198                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 199         },{
 200                 .strid = "video_temporal_filter_mode",
 201                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 202         },{
 203                 .strid = "video_temporal_filter",
 204                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 205         },{
 206                 .strid = "video_median_filter_type",
 207                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 208         },{
 209                 .strid = "video_luma_median_filter_top",
 210                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 211         },{
 212                 .strid = "video_luma_median_filter_bottom",
 213                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 214         },{
 215                 .strid = "video_chroma_median_filter_top",
 216                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 217         },{
 218                 .strid = "video_chroma_median_filter_bottom",
 219                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 220         }
 221 };
 222 #define MPEGDEF_COUNT (sizeof(mpeg_ids)/sizeof(mpeg_ids[0]))
 223
 224 static const char *control_values_srate[] = {
 225         [PVR2_CVAL_SRATE_48]   = "48KHz",
 226         [PVR2_CVAL_SRATE_44_1] = "44.1KHz",
 227 };
 228
 229
 230
 231
 232 static const char *control_values_input[] = {
 233         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 234         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 235         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 236         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 237 };
 238
 239
 240 static const char *control_values_audiomode[] = {
 241         [V4L2_TUNER_MODE_MONO]   = "Mono",
 242         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 243         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 244         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 245         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 246 };
 247
 248
 249 static const char *control_values_hsm[] = {
 250         [PVR2_CVAL_HSM_FAIL] = "Fail",
 251         [PVR2_CVAL_HSM_HIGH] = "High",
 252         [PVR2_CVAL_HSM_FULL] = "Full",
 253 };
 254
 255
 256 static const char *control_values_subsystem[] = {
 257         [PVR2_SUBSYS_B_ENC_FIRMWARE]  = "enc_firmware",
 258         [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
 259         [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
 260         [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
 261         [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
 262 };
 263
 264
 265 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 266 {
 267         struct pvr2_hdw *hdw = cptr->hdw;
 268         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 269                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 270         } else {
 271                 *vp = 0;
 272         }
 273         return 0;
 274 }
 275
 276 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 277 {
 278         struct pvr2_hdw *hdw = cptr->hdw;
 279         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 280                 hdw->freqTable[hdw->freqProgSlot-1] = v;
 281         }
 282         return 0;
 283 }
 284
 285 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 286 {
 287         *vp = cptr->hdw->freqProgSlot;
 288         return 0;
 289 }
 290
 291 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 292 {
 293         struct pvr2_hdw *hdw = cptr->hdw;
 294         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 295                 hdw->freqProgSlot = v;
 296         }
 297         return 0;
 298 }
 299
 300 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 301 {
 302         *vp = cptr->hdw->freqSlot;
 303         return 0;
 304 }
 305
 306 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
 307 {
 308         unsigned freq = 0;
 309         struct pvr2_hdw *hdw = cptr->hdw;
 310         hdw->freqSlot = v;
 311         if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
 312                 freq = hdw->freqTable[hdw->freqSlot-1];
 313         }
 314         if (freq && (freq != hdw->freqVal)) {
 315                 hdw->freqVal = freq;
 316                 hdw->freqDirty = !0;
 317         }
 318         return 0;
 319 }
 320
 321 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 322 {
 323         *vp = cptr->hdw->freqVal;
 324         return 0;
 325 }
 326
 327 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 328 {
 329         return cptr->hdw->freqDirty != 0;
 330 }
 331
 332 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 333 {
 334         cptr->hdw->freqDirty = 0;
 335 }
 336
 337 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 338 {
 339         struct pvr2_hdw *hdw = cptr->hdw;
 340         hdw->freqVal = v;
 341         hdw->freqDirty = !0;
 342         hdw->freqSlot = 0;
 343         return 0;
 344 }
 345
 346 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 347 {
 348         return cptr->hdw->enc_stale != 0;
 349 }
 350
 351 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 352 {
 353         cptr->hdw->enc_stale = 0;
 354 }
 355
 356 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 357 {
 358         int ret;
 359         struct v4l2_ext_controls cs;
 360         struct v4l2_ext_control c1;
 361         memset(&cs,0,sizeof(cs));
 362         memset(&c1,0,sizeof(c1));
 363         cs.controls = &c1;
 364         cs.count = 1;
 365         c1.id = cptr->info->v4l_id;
 366         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
 367                                 VIDIOC_G_EXT_CTRLS);
 368         if (ret) return ret;
 369         *vp = c1.value;
 370         return 0;
 371 }
 372
 373 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 374 {
 375         int ret;
 376         struct v4l2_ext_controls cs;
 377         struct v4l2_ext_control c1;
 378         memset(&cs,0,sizeof(cs));
 379         memset(&c1,0,sizeof(c1));
 380         cs.controls = &c1;
 381         cs.count = 1;
 382         c1.id = cptr->info->v4l_id;
 383         c1.value = v;
 384         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
 385                                 VIDIOC_S_EXT_CTRLS);
 386         if (ret) return ret;
 387         cptr->hdw->enc_stale = !0;
 388         return 0;
 389 }
 390
 391 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 392 {
 393         struct v4l2_queryctrl qctrl;
 394         struct pvr2_ctl_info *info;
 395         qctrl.id = cptr->info->v4l_id;
 396         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 397         /* Strip out the const so we can adjust a function pointer.  It's
 398            OK to do this here because we know this is a dynamically created
 399            control, so the underlying storage for the info pointer is (a)
 400            private to us, and (b) not in read-only storage.  Either we do
 401            this or we significantly complicate the underlying control
 402            implementation. */
 403         info = (struct pvr2_ctl_info *)(cptr->info);
 404         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 405                 if (info->set_value) {
 406                         info->set_value = 0;
 407                 }
 408         } else {
 409                 if (!(info->set_value)) {
 410                         info->set_value = ctrl_cx2341x_set;
 411                 }
 412         }
 413         return qctrl.flags;
 414 }
 415
 416 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 417 {
 418         *vp = cptr->hdw->flag_streaming_enabled;
 419         return 0;
 420 }
 421
 422 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 423 {
 424         int result = pvr2_hdw_is_hsm(cptr->hdw);
 425         *vp = PVR2_CVAL_HSM_FULL;
 426         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 427         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 428         return 0;
 429 }
 430
 431 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 432 {
 433         *vp = cptr->hdw->std_mask_avail;
 434         return 0;
 435 }
 436
 437 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 438 {
 439         struct pvr2_hdw *hdw = cptr->hdw;
 440         v4l2_std_id ns;
 441         ns = hdw->std_mask_avail;
 442         ns = (ns & ~m) | (v & m);
 443         if (ns == hdw->std_mask_avail) return 0;
 444         hdw->std_mask_avail = ns;
 445         pvr2_hdw_internal_set_std_avail(hdw);
 446         pvr2_hdw_internal_find_stdenum(hdw);
 447         return 0;
 448 }
 449
 450 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 451                                char *bufPtr,unsigned int bufSize,
 452                                unsigned int *len)
 453 {
 454         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 455         return 0;
 456 }
 457
 458 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 459                                const char *bufPtr,unsigned int bufSize,
 460                                int *mskp,int *valp)
 461 {
 462         int ret;
 463         v4l2_std_id id;
 464         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 465         if (ret < 0) return ret;
 466         if (mskp) *mskp = id;
 467         if (valp) *valp = id;
 468         return 0;
 469 }
 470
 471 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 472 {
 473         *vp = cptr->hdw->std_mask_cur;
 474         return 0;
 475 }
 476
 477 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 478 {
 479         struct pvr2_hdw *hdw = cptr->hdw;
 480         v4l2_std_id ns;
 481         ns = hdw->std_mask_cur;
 482         ns = (ns & ~m) | (v & m);
 483         if (ns == hdw->std_mask_cur) return 0;
 484         hdw->std_mask_cur = ns;
 485         hdw->std_dirty = !0;
 486         pvr2_hdw_internal_find_stdenum(hdw);
 487         return 0;
 488 }
 489
 490 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 491 {
 492         return cptr->hdw->std_dirty != 0;
 493 }
 494
 495 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 496 {
 497         cptr->hdw->std_dirty = 0;
 498 }
 499
 500 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 501 {
 502         *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
 503                 PVR2_SIGNAL_OK) ? 1 : 0);
 504         return 0;
 505 }
 506
 507 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
 508 {
 509         *vp = cptr->hdw->subsys_enabled_mask;
 510         return 0;
 511 }
 512
 513 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
 514 {
 515         pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
 516         return 0;
 517 }
 518
 519 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
 520 {
 521         *vp = cptr->hdw->subsys_stream_mask;
 522         return 0;
 523 }
 524
 525 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
 526 {
 527         pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
 528         return 0;
 529 }
 530
 531 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 532 {
 533         struct pvr2_hdw *hdw = cptr->hdw;
 534         if (v < 0) return -EINVAL;
 535         if (v > hdw->std_enum_cnt) return -EINVAL;
 536         hdw->std_enum_cur = v;
 537         if (!v) return 0;
 538         v--;
 539         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 540         hdw->std_mask_cur = hdw->std_defs[v].id;
 541         hdw->std_dirty = !0;
 542         return 0;
 543 }
 544
 545
 546 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 547 {
 548         *vp = cptr->hdw->std_enum_cur;
 549         return 0;
 550 }
 551
 552
 553 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 554 {
 555         return cptr->hdw->std_dirty != 0;
 556 }
 557
 558
 559 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 560 {
 561         cptr->hdw->std_dirty = 0;
 562 }
 563
 564
 565 #define DEFINT(vmin,vmax) \
 566         .type = pvr2_ctl_int, \
 567         .def.type_int.min_value = vmin, \
 568         .def.type_int.max_value = vmax
 569
 570 #define DEFENUM(tab) \
 571         .type = pvr2_ctl_enum, \
 572         .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
 573         .def.type_enum.value_names = tab
 574
 575 #define DEFBOOL \
 576         .type = pvr2_ctl_bool
 577
 578 #define DEFMASK(msk,tab) \
 579         .type = pvr2_ctl_bitmask, \
 580         .def.type_bitmask.valid_bits = msk, \
 581         .def.type_bitmask.bit_names = tab
 582
 583 #define DEFREF(vname) \
 584         .set_value = ctrl_set_##vname, \
 585         .get_value = ctrl_get_##vname, \
 586         .is_dirty = ctrl_isdirty_##vname, \
 587         .clear_dirty = ctrl_cleardirty_##vname
 588
 589
 590 #define VCREATE_FUNCS(vname) \
 591 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 592 {*vp = cptr->hdw->vname##_val; return 0;} \
 593 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 594 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 595 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 596 {return cptr->hdw->vname##_dirty != 0;} \
 597 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 598 {cptr->hdw->vname##_dirty = 0;}
 599
 600 VCREATE_FUNCS(brightness)
 601 VCREATE_FUNCS(contrast)
 602 VCREATE_FUNCS(saturation)
 603 VCREATE_FUNCS(hue)
 604 VCREATE_FUNCS(volume)
 605 VCREATE_FUNCS(balance)
 606 VCREATE_FUNCS(bass)
 607 VCREATE_FUNCS(treble)
 608 VCREATE_FUNCS(mute)
 609 VCREATE_FUNCS(input)
 610 VCREATE_FUNCS(audiomode)
 611 VCREATE_FUNCS(res_hor)
 612 VCREATE_FUNCS(res_ver)
 613 VCREATE_FUNCS(srate)
 614
 615 #define MIN_FREQ 55250000L
 616 #define MAX_FREQ 850000000L
 617
 618 /* Table definition of all controls which can be manipulated */
 619 static const struct pvr2_ctl_info control_defs[] = {
 620         {
 621                 .v4l_id = V4L2_CID_BRIGHTNESS,
 622                 .desc = "Brightness",
 623                 .name = "brightness",
 624                 .default_value = 128,
 625                 DEFREF(brightness),
 626                 DEFINT(0,255),
 627         },{
 628                 .v4l_id = V4L2_CID_CONTRAST,
 629                 .desc = "Contrast",
 630                 .name = "contrast",
 631                 .default_value = 68,
 632                 DEFREF(contrast),
 633                 DEFINT(0,127),
 634         },{
 635                 .v4l_id = V4L2_CID_SATURATION,
 636                 .desc = "Saturation",
 637                 .name = "saturation",
 638                 .default_value = 64,
 639                 DEFREF(saturation),
 640                 DEFINT(0,127),
 641         },{
 642                 .v4l_id = V4L2_CID_HUE,
 643                 .desc = "Hue",
 644                 .name = "hue",
 645                 .default_value = 0,
 646                 DEFREF(hue),
 647                 DEFINT(-128,127),
 648         },{
 649                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 650                 .desc = "Volume",
 651                 .name = "volume",
 652                 .default_value = 65535,
 653                 DEFREF(volume),
 654                 DEFINT(0,65535),
 655         },{
 656                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 657                 .desc = "Balance",
 658                 .name = "balance",
 659                 .default_value = 0,
 660                 DEFREF(balance),
 661                 DEFINT(-32768,32767),
 662         },{
 663                 .v4l_id = V4L2_CID_AUDIO_BASS,
 664                 .desc = "Bass",
 665                 .name = "bass",
 666                 .default_value = 0,
 667                 DEFREF(bass),
 668                 DEFINT(-32768,32767),
 669         },{
 670                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 671                 .desc = "Treble",
 672                 .name = "treble",
 673                 .default_value = 0,
 674                 DEFREF(treble),
 675                 DEFINT(-32768,32767),
 676         },{
 677                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 678                 .desc = "Mute",
 679                 .name = "mute",
 680                 .default_value = 0,
 681                 DEFREF(mute),
 682                 DEFBOOL,
 683         },{
 684                 .desc = "Video Source",
 685                 .name = "input",
 686                 .internal_id = PVR2_CID_INPUT,
 687                 .default_value = PVR2_CVAL_INPUT_TV,
 688                 DEFREF(input),
 689                 DEFENUM(control_values_input),
 690         },{
 691                 .desc = "Audio Mode",
 692                 .name = "audio_mode",
 693                 .internal_id = PVR2_CID_AUDIOMODE,
 694                 .default_value = V4L2_TUNER_MODE_STEREO,
 695                 DEFREF(audiomode),
 696                 DEFENUM(control_values_audiomode),
 697         },{
 698                 .desc = "Horizontal capture resolution",
 699                 .name = "resolution_hor",
 700                 .internal_id = PVR2_CID_HRES,
 701                 .default_value = 720,
 702                 DEFREF(res_hor),
 703                 DEFINT(320,720),
 704         },{
 705                 .desc = "Vertical capture resolution",
 706                 .name = "resolution_ver",
 707                 .internal_id = PVR2_CID_VRES,
 708                 .default_value = 480,
 709                 DEFREF(res_ver),
 710                 DEFINT(200,625),
 711         },{
 712                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
 713                 .desc = "Sample rate",
 714                 .name = "srate",
 715                 .default_value = PVR2_CVAL_SRATE_48,
 716                 DEFREF(srate),
 717                 DEFENUM(control_values_srate),
 718         },{
 719                 .desc = "Tuner Frequency (Hz)",
 720                 .name = "frequency",
 721                 .internal_id = PVR2_CID_FREQUENCY,
 722                 .default_value = 175250000L,
 723                 .set_value = ctrl_freq_set,
 724                 .get_value = ctrl_freq_get,
 725                 .is_dirty = ctrl_freq_is_dirty,
 726                 .clear_dirty = ctrl_freq_clear_dirty,
 727                 DEFINT(MIN_FREQ,MAX_FREQ),
 728         },{
 729                 .desc = "Channel",
 730                 .name = "channel",
 731                 .set_value = ctrl_channel_set,
 732                 .get_value = ctrl_channel_get,
 733                 DEFINT(0,FREQTABLE_SIZE),
 734         },{
 735                 .desc = "Channel Program Frequency",
 736                 .name = "freq_table_value",
 737                 .set_value = ctrl_channelfreq_set,
 738                 .get_value = ctrl_channelfreq_get,
 739                 DEFINT(MIN_FREQ,MAX_FREQ),
 740         },{
 741                 .desc = "Channel Program ID",
 742                 .name = "freq_table_channel",
 743                 .set_value = ctrl_channelprog_set,
 744                 .get_value = ctrl_channelprog_get,
 745                 DEFINT(0,FREQTABLE_SIZE),
 746         },{
 747                 .desc = "Streaming Enabled",
 748                 .name = "streaming_enabled",
 749                 .get_value = ctrl_streamingenabled_get,
 750                 DEFBOOL,
 751         },{
 752                 .desc = "USB Speed",
 753                 .name = "usb_speed",
 754                 .get_value = ctrl_hsm_get,
 755                 DEFENUM(control_values_hsm),
 756         },{
 757                 .desc = "Signal Present",
 758                 .name = "signal_present",
 759                 .get_value = ctrl_signal_get,
 760                 DEFBOOL,
 761         },{
 762                 .desc = "Video Standards Available Mask",
 763                 .name = "video_standard_mask_available",
 764                 .internal_id = PVR2_CID_STDAVAIL,
 765                 .skip_init = !0,
 766                 .get_value = ctrl_stdavail_get,
 767                 .set_value = ctrl_stdavail_set,
 768                 .val_to_sym = ctrl_std_val_to_sym,
 769                 .sym_to_val = ctrl_std_sym_to_val,
 770                 .type = pvr2_ctl_bitmask,
 771         },{
 772                 .desc = "Video Standards In Use Mask",
 773                 .name = "video_standard_mask_active",
 774                 .internal_id = PVR2_CID_STDCUR,
 775                 .skip_init = !0,
 776                 .get_value = ctrl_stdcur_get,
 777                 .set_value = ctrl_stdcur_set,
 778                 .is_dirty = ctrl_stdcur_is_dirty,
 779                 .clear_dirty = ctrl_stdcur_clear_dirty,
 780                 .val_to_sym = ctrl_std_val_to_sym,
 781                 .sym_to_val = ctrl_std_sym_to_val,
 782                 .type = pvr2_ctl_bitmask,
 783         },{
 784                 .desc = "Subsystem enabled mask",
 785                 .name = "debug_subsys_mask",
 786                 .skip_init = !0,
 787                 .get_value = ctrl_subsys_get,
 788                 .set_value = ctrl_subsys_set,
 789                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 790         },{
 791                 .desc = "Subsystem stream mask",
 792                 .name = "debug_subsys_stream_mask",
 793                 .skip_init = !0,
 794                 .get_value = ctrl_subsys_stream_get,
 795                 .set_value = ctrl_subsys_stream_set,
 796                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 797         },{
 798                 .desc = "Video Standard Name",
 799                 .name = "video_standard",
 800                 .internal_id = PVR2_CID_STDENUM,
 801                 .skip_init = !0,
 802                 .get_value = ctrl_stdenumcur_get,
 803                 .set_value = ctrl_stdenumcur_set,
 804                 .is_dirty = ctrl_stdenumcur_is_dirty,
 805                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 806                 .type = pvr2_ctl_enum,
 807         }
 808 };
 809
 810 #define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
 811
 812
 813 const char *pvr2_config_get_name(enum pvr2_config cfg)
 814 {
 815         switch (cfg) {
 816         case pvr2_config_empty: return "empty";
 817         case pvr2_config_mpeg: return "mpeg";
 818         case pvr2_config_vbi: return "vbi";
 819         case pvr2_config_radio: return "radio";
 820         }
 821         return "<unknown>";
 822 }
 823
 824
 825 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
 826 {
 827         return hdw->usb_dev;
 828 }
 829
 830
 831 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
 832 {
 833         return hdw->serial_number;
 834 }
 835
 836
 837 struct pvr2_hdw *pvr2_hdw_find(int unit_number)
 838 {
 839         if (unit_number < 0) return 0;
 840         if (unit_number >= PVR_NUM) return 0;
 841         return unit_pointers[unit_number];
 842 }
 843
 844
 845 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
 846 {
 847         return hdw->unit_number;
 848 }
 849
 850
 851 /* Attempt to locate one of the given set of files.  Messages are logged
 852    appropriate to what has been found.  The return value will be 0 or
 853    greater on success (it will be the index of the file name found) and
 854    fw_entry will be filled in.  Otherwise a negative error is returned on
 855    failure.  If the return value is -ENOENT then no viable firmware file
 856    could be located. */
 857 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
 858                                 const struct firmware **fw_entry,
 859                                 const char *fwtypename,
 860                                 unsigned int fwcount,
 861                                 const char *fwnames[])
 862 {
 863         unsigned int idx;
 864         int ret = -EINVAL;
 865         for (idx = 0; idx < fwcount; idx++) {
 866                 ret = request_firmware(fw_entry,
 867                                        fwnames[idx],
 868                                        &hdw->usb_dev->dev);
 869                 if (!ret) {
 870                         trace_firmware("Located %s firmware: %s;"
 871                                        " uploading...",
 872                                        fwtypename,
 873                                        fwnames[idx]);
 874                         return idx;
 875                 }
 876                 if (ret == -ENOENT) continue;
 877                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 878                            "request_firmware fatal error with code=%d",ret);
 879                 return ret;
 880         }
 881         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 882                    "***WARNING***"
 883                    " Device %s firmware"
 884                    " seems to be missing.",
 885                    fwtypename);
 886         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 887                    "Did you install the pvrusb2 firmware files"
 888                    " in their proper location?");
 889         if (fwcount == 1) {
 890                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 891                            "request_firmware unable to locate %s file %s",
 892                            fwtypename,fwnames[0]);
 893         } else {
 894                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 895                            "request_firmware unable to locate"
 896                            " one of the following %s files:",
 897                            fwtypename);
 898                 for (idx = 0; idx < fwcount; idx++) {
 899                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 900                                    "request_firmware: Failed to find %s",
 901                                    fwnames[idx]);
 902                 }
 903         }
 904         return ret;
 905 }
 906
 907
 908 /*
 909  * pvr2_upload_firmware1().
 910  *
 911  * Send the 8051 firmware to the device.  After the upload, arrange for
 912  * device to re-enumerate.
 913  *
 914  * NOTE : the pointer to the firmware data given by request_firmware()
 915  * is not suitable for an usb transaction.
 916  *
 917  */
 918 int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
 919 {
 920         const struct firmware *fw_entry = 0;
 921         void  *fw_ptr;
 922         unsigned int pipe;
 923         int ret;
 924         u16 address;
 925         static const char *fw_files_29xxx[] = {
 926                 "v4l-pvrusb2-29xxx-01.fw",
 927         };
 928 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 929         static const char *fw_files_24xxx[] = {
 930                 "v4l-pvrusb2-24xxx-01.fw",
 931         };
 932 #endif
 933         static const struct pvr2_string_table fw_file_defs[] = {
 934                 [PVR2_HDW_TYPE_29XXX] = {
 935                         fw_files_29xxx,
 936                         sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
 937                 },
 938 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 939                 [PVR2_HDW_TYPE_24XXX] = {
 940                         fw_files_24xxx,
 941                         sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
 942                 },
 943 #endif
 944         };
 945         hdw->fw1_state = FW1_STATE_FAILED; // default result
 946
 947         trace_firmware("pvr2_upload_firmware1");
 948
 949         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
 950                                    fw_file_defs[hdw->hdw_type].cnt,
 951                                    fw_file_defs[hdw->hdw_type].lst);
 952         if (ret < 0) {
 953                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
 954                 return ret;
 955         }
 956
 957         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
 958         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
 959
 960         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
 961
 962         if (fw_entry->size != 0x2000){
 963                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
 964                 release_firmware(fw_entry);
 965                 return -ENOMEM;
 966         }
 967
 968         fw_ptr = kmalloc(0x800, GFP_KERNEL);
 969         if (fw_ptr == NULL){
 970                 release_firmware(fw_entry);
 971                 return -ENOMEM;
 972         }
 973
 974         /* We have to hold the CPU during firmware upload. */
 975         pvr2_hdw_cpureset_assert(hdw,1);
 976
 977         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
 978            chunk. */
 979
 980         ret = 0;
 981         for(address = 0; address < fw_entry->size; address += 0x800) {
 982                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
 983                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
 984                                        0, fw_ptr, 0x800, HZ);
 985         }
 986
 987         trace_firmware("Upload done, releasing device's CPU");
 988
 989         /* Now release the CPU.  It will disconnect and reconnect later. */
 990         pvr2_hdw_cpureset_assert(hdw,0);
 991
 992         kfree(fw_ptr);
 993         release_firmware(fw_entry);
 994
 995         trace_firmware("Upload done (%d bytes sent)",ret);
 996
 997         /* We should have written 8192 bytes */
 998         if (ret == 8192) {
 999                 hdw->fw1_state = FW1_STATE_RELOAD;
1000                 return 0;
1001         }
1002
1003         return -EIO;
1004 }
1005
1006
1007 /*
1008  * pvr2_upload_firmware2()
1009  *
1010  * This uploads encoder firmware on endpoint 2.
1011  *
1012  */
1013
1014 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1015 {
1016         const struct firmware *fw_entry = 0;
1017         void  *fw_ptr;
1018         unsigned int pipe, fw_len, fw_done;
1019         int actual_length;
1020         int ret = 0;
1021         int fwidx;
1022         static const char *fw_files[] = {
1023                 CX2341X_FIRM_ENC_FILENAME,
1024         };
1025
1026         trace_firmware("pvr2_upload_firmware2");
1027
1028         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1029                                    sizeof(fw_files)/sizeof(fw_files[0]),
1030                                    fw_files);
1031         if (ret < 0) return ret;
1032         fwidx = ret;
1033         ret = 0;
1034         /* Since we're about to completely reinitialize the encoder,
1035            invalidate our cached copy of its configuration state.  Next
1036            time we configure the encoder, then we'll fully configure it. */
1037         hdw->enc_cur_valid = 0;
1038
1039         /* First prepare firmware loading */
1040         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1041         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1042         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1043         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1044         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1045         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1046         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1047         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1048         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1049         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1050         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1051         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1052         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1053         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1054         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1055         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1056         ret |= pvr2_write_u8(hdw, 0x52, 0);
1057         ret |= pvr2_write_u16(hdw, 0x0600, 0);
1058
1059         if (ret) {
1060                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1061                            "firmware2 upload prep failed, ret=%d",ret);
1062                 release_firmware(fw_entry);
1063                 return ret;
1064         }
1065
1066         /* Now send firmware */
1067
1068         fw_len = fw_entry->size;
1069
1070         if (fw_len % FIRMWARE_CHUNK_SIZE) {
1071                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1072                            "size of %s firmware"
1073                            " must be a multiple of 8192B",
1074                            fw_files[fwidx]);
1075                 release_firmware(fw_entry);
1076                 return -1;
1077         }
1078
1079         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1080         if (fw_ptr == NULL){
1081                 release_firmware(fw_entry);
1082                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1083                            "failed to allocate memory for firmware2 upload");
1084                 return -ENOMEM;
1085         }
1086
1087         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1088
1089         for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1090              fw_done += FIRMWARE_CHUNK_SIZE ) {
1091                 int i;
1092                 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1093                 /* Usbsnoop log  shows that we must swap bytes... */
1094                 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1095                         ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1096
1097                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1098                                     FIRMWARE_CHUNK_SIZE,
1099                                     &actual_length, HZ);
1100                 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1101         }
1102
1103         trace_firmware("upload of %s : %i / %i ",
1104                        fw_files[fwidx],fw_done,fw_len);
1105
1106         kfree(fw_ptr);
1107         release_firmware(fw_entry);
1108
1109         if (ret) {
1110                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1111                            "firmware2 upload transfer failure");
1112                 return ret;
1113         }
1114
1115         /* Finish upload */
1116
1117         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1118         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1119         ret |= pvr2_write_u16(hdw, 0x0600, 0);
1120
1121         if (ret) {
1122                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1123                            "firmware2 upload post-proc failure");
1124         } else {
1125                 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1126         }
1127         return ret;
1128 }
1129
1130
1131 #define FIRMWARE_RECOVERY_BITS \
1132         ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1133          (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1134          (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1135          (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1136
1137 /*
1138
1139   This single function is key to pretty much everything.  The pvrusb2
1140   device can logically be viewed as a series of subsystems which can be
1141   stopped / started or unconfigured / configured.  To get things streaming,
1142   one must configure everything and start everything, but there may be
1143   various reasons over time to deconfigure something or stop something.
1144   This function handles all of this activity.  Everything EVERYWHERE that
1145   must affect a subsystem eventually comes here to do the work.
1146
1147   The current state of all subsystems is represented by a single bit mask,
1148   known as subsys_enabled_mask.  The bit positions are defined by the
1149   PVR2_SUBSYS_xxxx macros, with one subsystem per bit position.  At any
1150   time the set of configured or active subsystems can be queried just by
1151   looking at that mask.  To change bits in that mask, this function here
1152   must be called.  The "msk" argument indicates which bit positions to
1153   change, and the "val" argument defines the new values for the positions
1154   defined by "msk".
1155
1156   There is a priority ordering of starting / stopping things, and for
1157   multiple requested changes, this function implements that ordering.
1158   (Thus we will act on a request to load encoder firmware before we
1159   configure the encoder.)  In addition to priority ordering, there is a
1160   recovery strategy implemented here.  If a particular step fails and we
1161   detect that failure, this function will clear the affected subsystem bits
1162   and restart.  Thus we have a means for recovering from a dead encoder:
1163   Clear all bits that correspond to subsystems that we need to restart /
1164   reconfigure and start over.
1165
1166 */
1167 void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1168                                      unsigned long msk,unsigned long val)
1169 {
1170         unsigned long nmsk;
1171         unsigned long vmsk;
1172         int ret;
1173         unsigned int tryCount = 0;
1174
1175         if (!hdw->flag_ok) return;
1176
1177         msk &= PVR2_SUBSYS_ALL;
1178         nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1179         nmsk &= PVR2_SUBSYS_ALL;
1180
1181         for (;;) {
1182                 tryCount++;
1183                 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1184                       PVR2_SUBSYS_ALL)) break;
1185                 if (tryCount > 4) {
1186                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1187                                    "Too many retries when configuring device;"
1188                                    " giving up");
1189                         pvr2_hdw_render_useless(hdw);
1190                         break;
1191                 }
1192                 if (tryCount > 1) {
1193                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1194                                    "Retrying device reconfiguration");
1195                 }
1196                 pvr2_trace(PVR2_TRACE_INIT,
1197                            "subsys mask changing 0x%lx:0x%lx"
1198                            " from 0x%lx to 0x%lx",
1199                            msk,val,hdw->subsys_enabled_mask,nmsk);
1200
1201                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1202                         hdw->subsys_enabled_mask;
1203                 if (vmsk) {
1204                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1205                                 pvr2_trace(PVR2_TRACE_CTL,
1206                                            "/*---TRACE_CTL----*/"
1207                                            " pvr2_encoder_stop");
1208                                 ret = pvr2_encoder_stop(hdw);
1209                                 if (ret) {
1210                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1211                                                    "Error recovery initiated");
1212                                         hdw->subsys_enabled_mask &=
1213                                                 ~FIRMWARE_RECOVERY_BITS;
1214                                         continue;
1215                                 }
1216                         }
1217                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1218                                 pvr2_trace(PVR2_TRACE_CTL,
1219                                            "/*---TRACE_CTL----*/"
1220                                            " pvr2_hdw_cmd_usbstream(0)");
1221                                 pvr2_hdw_cmd_usbstream(hdw,0);
1222                         }
1223                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1224                                 pvr2_trace(PVR2_TRACE_CTL,
1225                                            "/*---TRACE_CTL----*/"
1226                                            " decoder disable");
1227                                 if (hdw->decoder_ctrl) {
1228                                         hdw->decoder_ctrl->enable(
1229                                                 hdw->decoder_ctrl->ctxt,0);
1230                                 } else {
1231                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1232                                                    "WARNING:"
1233                                                    " No decoder present");
1234                                 }
1235                                 hdw->subsys_enabled_mask &=
1236                                         ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1237                         }
1238                         if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1239                                 hdw->subsys_enabled_mask &=
1240                                         ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1241                         }
1242                 }
1243                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1244                 if (vmsk) {
1245                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1246                                 pvr2_trace(PVR2_TRACE_CTL,
1247                                            "/*---TRACE_CTL----*/"
1248                                            " pvr2_upload_firmware2");
1249                                 ret = pvr2_upload_firmware2(hdw);
1250                                 if (ret) {
1251                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1252                                                    "Failure uploading encoder"
1253                                                    " firmware");
1254                                         pvr2_hdw_render_useless(hdw);
1255                                         break;
1256                                 }
1257                         }
1258                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1259                                 pvr2_trace(PVR2_TRACE_CTL,
1260                                            "/*---TRACE_CTL----*/"
1261                                            " pvr2_encoder_configure");
1262                                 ret = pvr2_encoder_configure(hdw);
1263                                 if (ret) {
1264                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1265                                                    "Error recovery initiated");
1266                                         hdw->subsys_enabled_mask &=
1267                                                 ~FIRMWARE_RECOVERY_BITS;
1268                                         continue;
1269                                 }
1270                         }
1271                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1272                                 pvr2_trace(PVR2_TRACE_CTL,
1273                                            "/*---TRACE_CTL----*/"
1274                                            " decoder enable");
1275                                 if (hdw->decoder_ctrl) {
1276                                         hdw->decoder_ctrl->enable(
1277                                                 hdw->decoder_ctrl->ctxt,!0);
1278                                 } else {
1279                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1280                                                    "WARNING:"
1281                                                    " No decoder present");
1282                                 }
1283                                 hdw->subsys_enabled_mask |=
1284                                         (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1285                         }
1286                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1287                                 pvr2_trace(PVR2_TRACE_CTL,
1288                                            "/*---TRACE_CTL----*/"
1289                                            " pvr2_hdw_cmd_usbstream(1)");
1290                                 pvr2_hdw_cmd_usbstream(hdw,!0);
1291                         }
1292                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1293                                 pvr2_trace(PVR2_TRACE_CTL,
1294                                            "/*---TRACE_CTL----*/"
1295                                            " pvr2_encoder_start");
1296                                 ret = pvr2_encoder_start(hdw);
1297                                 if (ret) {
1298                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1299                                                    "Error recovery initiated");
1300                                         hdw->subsys_enabled_mask &=
1301                                                 ~FIRMWARE_RECOVERY_BITS;
1302                                         continue;
1303                                 }
1304                         }
1305                 }
1306         }
1307 }
1308
1309
1310 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1311                              unsigned long msk,unsigned long val)
1312 {
1313         LOCK_TAKE(hdw->big_lock); do {
1314                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1315         } while (0); LOCK_GIVE(hdw->big_lock);
1316 }
1317
1318
1319 void pvr2_hdw_subsys_bit_set(struct pvr2_hdw *hdw,unsigned long msk)
1320 {
1321         pvr2_hdw_subsys_bit_chg(hdw,msk,msk);
1322 }
1323
1324
1325 void pvr2_hdw_subsys_bit_clr(struct pvr2_hdw *hdw,unsigned long msk)
1326 {
1327         pvr2_hdw_subsys_bit_chg(hdw,msk,0);
1328 }
1329
1330
1331 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1332 {
1333         return hdw->subsys_enabled_mask;
1334 }
1335
1336
1337 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1338 {
1339         return hdw->subsys_stream_mask;
1340 }
1341
1342
1343 void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1344                                             unsigned long msk,
1345                                             unsigned long val)
1346 {
1347         unsigned long val2;
1348         msk &= PVR2_SUBSYS_ALL;
1349         val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1350         pvr2_trace(PVR2_TRACE_INIT,
1351                    "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1352                    msk,val,hdw->subsys_stream_mask,val2);
1353         hdw->subsys_stream_mask = val2;
1354 }
1355
1356
1357 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1358                                     unsigned long msk,
1359                                     unsigned long val)
1360 {
1361         LOCK_TAKE(hdw->big_lock); do {
1362                 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1363         } while (0); LOCK_GIVE(hdw->big_lock);
1364 }
1365
1366
1367 int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1368 {
1369         if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1370         if (enableFl) {
1371                 pvr2_trace(PVR2_TRACE_START_STOP,
1372                            "/*--TRACE_STREAM--*/ enable");
1373                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1374         } else {
1375                 pvr2_trace(PVR2_TRACE_START_STOP,
1376                            "/*--TRACE_STREAM--*/ disable");
1377                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1378         }
1379         if (!hdw->flag_ok) return -EIO;
1380         hdw->flag_streaming_enabled = enableFl != 0;
1381         return 0;
1382 }
1383
1384
1385 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1386 {
1387         return hdw->flag_streaming_enabled != 0;
1388 }
1389
1390
1391 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1392 {
1393         int ret;
1394         LOCK_TAKE(hdw->big_lock); do {
1395                 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1396         } while (0); LOCK_GIVE(hdw->big_lock);
1397         return ret;
1398 }
1399
1400
1401 int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1402                                      enum pvr2_config config)
1403 {
1404         unsigned long sm = hdw->subsys_enabled_mask;
1405         if (!hdw->flag_ok) return -EIO;
1406         pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1407         hdw->config = config;
1408         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1409         return 0;
1410 }
1411
1412
1413 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1414 {
1415         int ret;
1416         if (!hdw->flag_ok) return -EIO;
1417         LOCK_TAKE(hdw->big_lock);
1418         ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1419         LOCK_GIVE(hdw->big_lock);
1420         return ret;
1421 }
1422
1423
1424 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1425 {
1426         int unit_number = hdw->unit_number;
1427         int tp = -1;
1428         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1429                 tp = tuner[unit_number];
1430         }
1431         if (tp < 0) return -EINVAL;
1432         hdw->tuner_type = tp;
1433         return 0;
1434 }
1435
1436
1437 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1438 {
1439         int unit_number = hdw->unit_number;
1440         int tp = 0;
1441         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1442                 tp = video_std[unit_number];
1443         }
1444         return tp;
1445 }
1446
1447
1448 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1449 {
1450         int unit_number = hdw->unit_number;
1451         int tp = 0;
1452         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1453                 tp = tolerance[unit_number];
1454         }
1455         return tp;
1456 }
1457
1458
1459 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1460 {
1461         /* Try a harmless request to fetch the eeprom's address over
1462            endpoint 1.  See what happens.  Only the full FX2 image can
1463            respond to this.  If this probe fails then likely the FX2
1464            firmware needs be loaded. */
1465         int result;
1466         LOCK_TAKE(hdw->ctl_lock); do {
1467                 hdw->cmd_buffer[0] = 0xeb;
1468                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1469                                            hdw->cmd_buffer,1,
1470                                            hdw->cmd_buffer,1);
1471                 if (result < 0) break;
1472         } while(0); LOCK_GIVE(hdw->ctl_lock);
1473         if (result) {
1474                 pvr2_trace(PVR2_TRACE_INIT,
1475                            "Probe of device endpoint 1 result status %d",
1476                            result);
1477         } else {
1478                 pvr2_trace(PVR2_TRACE_INIT,
1479                            "Probe of device endpoint 1 succeeded");
1480         }
1481         return result == 0;
1482 }
1483
1484 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1485 {
1486         char buf[40];
1487         unsigned int bcnt;
1488         v4l2_std_id std1,std2;
1489
1490         std1 = get_default_standard(hdw);
1491
1492         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1493         pvr2_trace(PVR2_TRACE_INIT,
1494                    "Supported video standard(s) reported by eeprom: %.*s",
1495                    bcnt,buf);
1496
1497         hdw->std_mask_avail = hdw->std_mask_eeprom;
1498
1499         std2 = std1 & ~hdw->std_mask_avail;
1500         if (std2) {
1501                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1502                 pvr2_trace(PVR2_TRACE_INIT,
1503                            "Expanding supported video standards"
1504                            " to include: %.*s",
1505                            bcnt,buf);
1506                 hdw->std_mask_avail |= std2;
1507         }
1508
1509         pvr2_hdw_internal_set_std_avail(hdw);
1510
1511         if (std1) {
1512                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1513                 pvr2_trace(PVR2_TRACE_INIT,
1514                            "Initial video standard forced to %.*s",
1515                            bcnt,buf);
1516                 hdw->std_mask_cur = std1;
1517                 hdw->std_dirty = !0;
1518                 pvr2_hdw_internal_find_stdenum(hdw);
1519                 return;
1520         }
1521
1522         if (hdw->std_enum_cnt > 1) {
1523                 // Autoselect the first listed standard
1524                 hdw->std_enum_cur = 1;
1525                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1526                 hdw->std_dirty = !0;
1527                 pvr2_trace(PVR2_TRACE_INIT,
1528                            "Initial video standard auto-selected to %s",
1529                            hdw->std_defs[hdw->std_enum_cur-1].name);
1530                 return;
1531         }
1532
1533         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1534                    "Unable to select a viable initial video standard");
1535 }
1536
1537
1538 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1539 {
1540         int ret;
1541         unsigned int idx;
1542         struct pvr2_ctrl *cptr;
1543         int reloadFl = 0;
1544         if (!reloadFl) {
1545                 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1546                             == 0);
1547                 if (reloadFl) {
1548                         pvr2_trace(PVR2_TRACE_INIT,
1549                                    "USB endpoint config looks strange"
1550                                    "; possibly firmware needs to be loaded");
1551                 }
1552         }
1553         if (!reloadFl) {
1554                 reloadFl = !pvr2_hdw_check_firmware(hdw);
1555                 if (reloadFl) {
1556                         pvr2_trace(PVR2_TRACE_INIT,
1557                                    "Check for FX2 firmware failed"
1558                                    "; possibly firmware needs to be loaded");
1559                 }
1560         }
1561         if (reloadFl) {
1562                 if (pvr2_upload_firmware1(hdw) != 0) {
1563                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1564                                    "Failure uploading firmware1");
1565                 }
1566                 return;
1567         }
1568         hdw->fw1_state = FW1_STATE_OK;
1569
1570         if (initusbreset) {
1571                 pvr2_hdw_device_reset(hdw);
1572         }
1573         if (!pvr2_hdw_dev_ok(hdw)) return;
1574
1575         for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1576                 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1577         }
1578
1579         pvr2_hdw_cmd_powerup(hdw);
1580         if (!pvr2_hdw_dev_ok(hdw)) return;
1581
1582         if (pvr2_upload_firmware2(hdw)){
1583                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1584                 pvr2_hdw_render_useless(hdw);
1585                 return;
1586         }
1587
1588         // This step MUST happen after the earlier powerup step.
1589         pvr2_i2c_core_init(hdw);
1590         if (!pvr2_hdw_dev_ok(hdw)) return;
1591
1592         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1593                 cptr = hdw->controls + idx;
1594                 if (cptr->info->skip_init) continue;
1595                 if (!cptr->info->set_value) continue;
1596                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1597         }
1598
1599         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1600         // thread-safe against the normal pvr2_send_request() mechanism.
1601         // (We should make it thread safe).
1602
1603         ret = pvr2_hdw_get_eeprom_addr(hdw);
1604         if (!pvr2_hdw_dev_ok(hdw)) return;
1605         if (ret < 0) {
1606                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1607                            "Unable to determine location of eeprom, skipping");
1608         } else {
1609                 hdw->eeprom_addr = ret;
1610                 pvr2_eeprom_analyze(hdw);
1611                 if (!pvr2_hdw_dev_ok(hdw)) return;
1612         }
1613
1614         pvr2_hdw_setup_std(hdw);
1615
1616         if (!get_default_tuner_type(hdw)) {
1617                 pvr2_trace(PVR2_TRACE_INIT,
1618                            "pvr2_hdw_setup: Tuner type overridden to %d",
1619                            hdw->tuner_type);
1620         }
1621
1622         hdw->tuner_updated = !0;
1623         pvr2_i2c_core_check_stale(hdw);
1624         hdw->tuner_updated = 0;
1625
1626         if (!pvr2_hdw_dev_ok(hdw)) return;
1627
1628         pvr2_hdw_commit_ctl_internal(hdw);
1629         if (!pvr2_hdw_dev_ok(hdw)) return;
1630
1631         hdw->vid_stream = pvr2_stream_create();
1632         if (!pvr2_hdw_dev_ok(hdw)) return;
1633         pvr2_trace(PVR2_TRACE_INIT,
1634                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1635         if (hdw->vid_stream) {
1636                 idx = get_default_error_tolerance(hdw);
1637                 if (idx) {
1638                         pvr2_trace(PVR2_TRACE_INIT,
1639                                    "pvr2_hdw_setup: video stream %p"
1640                                    " setting tolerance %u",
1641                                    hdw->vid_stream,idx);
1642                 }
1643                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1644                                   PVR2_VID_ENDPOINT,idx);
1645         }
1646
1647         if (!pvr2_hdw_dev_ok(hdw)) return;
1648
1649         /* Make sure everything is up to date */
1650         pvr2_i2c_core_sync(hdw);
1651
1652         if (!pvr2_hdw_dev_ok(hdw)) return;
1653
1654         hdw->flag_init_ok = !0;
1655 }
1656
1657
1658 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1659 {
1660         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1661         LOCK_TAKE(hdw->big_lock); do {
1662                 pvr2_hdw_setup_low(hdw);
1663                 pvr2_trace(PVR2_TRACE_INIT,
1664                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1665                            hdw,hdw->flag_ok,hdw->flag_init_ok);
1666                 if (pvr2_hdw_dev_ok(hdw)) {
1667                         if (pvr2_hdw_init_ok(hdw)) {
1668                                 pvr2_trace(
1669                                         PVR2_TRACE_INFO,
1670                                         "Device initialization"
1671                                         " completed successfully.");
1672                                 break;
1673                         }
1674                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1675                                 pvr2_trace(
1676                                         PVR2_TRACE_INFO,
1677                                         "Device microcontroller firmware"
1678                                         " (re)loaded; it should now reset"
1679                                         " and reconnect.");
1680                                 break;
1681                         }
1682                         pvr2_trace(
1683                                 PVR2_TRACE_ERROR_LEGS,
1684                                 "Device initialization was not successful.");
1685                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1686                                 pvr2_trace(
1687                                         PVR2_TRACE_ERROR_LEGS,
1688                                         "Giving up since device"
1689                                         " microcontroller firmware"
1690                                         " appears to be missing.");
1691                                 break;
1692                         }
1693                 }
1694                 if (procreload) {
1695                         pvr2_trace(
1696                                 PVR2_TRACE_ERROR_LEGS,
1697                                 "Attempting pvrusb2 recovery by reloading"
1698                                 " primary firmware.");
1699                         pvr2_trace(
1700                                 PVR2_TRACE_ERROR_LEGS,
1701                                 "If this works, device should disconnect"
1702                                 " and reconnect in a sane state.");
1703                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1704                         pvr2_upload_firmware1(hdw);
1705                 } else {
1706                         pvr2_trace(
1707                                 PVR2_TRACE_ERROR_LEGS,
1708                                 "***WARNING*** pvrusb2 device hardware"
1709                                 " appears to be jammed"
1710                                 " and I can't clear it.");
1711                         pvr2_trace(
1712                                 PVR2_TRACE_ERROR_LEGS,
1713                                 "You might need to power cycle"
1714                                 " the pvrusb2 device"
1715                                 " in order to recover.");
1716                 }
1717         } while (0); LOCK_GIVE(hdw->big_lock);
1718         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1719         return hdw->flag_init_ok;
1720 }
1721
1722
1723 /* Create and return a structure for interacting with the underlying
1724    hardware */
1725 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1726                                  const struct usb_device_id *devid)
1727 {
1728         unsigned int idx,cnt1,cnt2;
1729         struct pvr2_hdw *hdw;
1730         unsigned int hdw_type;
1731         int valid_std_mask;
1732         struct pvr2_ctrl *cptr;
1733         __u8 ifnum;
1734         struct v4l2_queryctrl qctrl;
1735         struct pvr2_ctl_info *ciptr;
1736
1737         hdw_type = devid - pvr2_device_table;
1738         if (hdw_type >=
1739             sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1740                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1741                            "Bogus device type of %u reported",hdw_type);
1742                 return 0;
1743         }
1744
1745         hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1746         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1747                    hdw,pvr2_device_names[hdw_type]);
1748         if (!hdw) goto fail;
1749         memset(hdw,0,sizeof(*hdw));
1750         cx2341x_fill_defaults(&hdw->enc_ctl_state);
1751
1752         hdw->control_cnt = CTRLDEF_COUNT;
1753         hdw->control_cnt += MPEGDEF_COUNT;
1754         hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1755                                 GFP_KERNEL);
1756         if (!hdw->controls) goto fail;
1757         memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
1758         hdw->hdw_type = hdw_type;
1759         for (idx = 0; idx < hdw->control_cnt; idx++) {
1760                 cptr = hdw->controls + idx;
1761                 cptr->hdw = hdw;
1762         }
1763         for (idx = 0; idx < 32; idx++) {
1764                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1765         }
1766         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1767                 cptr = hdw->controls + idx;
1768                 cptr->info = control_defs+idx;
1769         }
1770         /* Define and configure additional controls from cx2341x module. */
1771         hdw->mpeg_ctrl_info = kmalloc(
1772                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1773         if (!hdw->mpeg_ctrl_info) goto fail;
1774         memset(hdw->mpeg_ctrl_info,0,
1775                sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT);
1776         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1777                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1778                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1779                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1780                 ciptr->name = mpeg_ids[idx].strid;
1781                 ciptr->v4l_id = mpeg_ids[idx].id;
1782                 ciptr->skip_init = !0;
1783                 ciptr->get_value = ctrl_cx2341x_get;
1784                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1785                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1786                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1787                 qctrl.id = ciptr->v4l_id;
1788                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1789                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1790                         ciptr->set_value = ctrl_cx2341x_set;
1791                 }
1792                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1793                         PVR2_CTLD_INFO_DESC_SIZE);
1794                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1795                 ciptr->default_value = qctrl.default_value;
1796                 switch (qctrl.type) {
1797                 default:
1798                 case V4L2_CTRL_TYPE_INTEGER:
1799                         ciptr->type = pvr2_ctl_int;
1800                         ciptr->def.type_int.min_value = qctrl.minimum;
1801                         ciptr->def.type_int.max_value = qctrl.maximum;
1802                         break;
1803                 case V4L2_CTRL_TYPE_BOOLEAN:
1804                         ciptr->type = pvr2_ctl_bool;
1805                         break;
1806                 case V4L2_CTRL_TYPE_MENU:
1807                         ciptr->type = pvr2_ctl_enum;
1808                         ciptr->def.type_enum.value_names =
1809                                 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1810                         for (cnt1 = 0;
1811                              ciptr->def.type_enum.value_names[cnt1] != NULL;
1812                              cnt1++) { }
1813                         ciptr->def.type_enum.count = cnt1;
1814                         break;
1815                 }
1816                 cptr->info = ciptr;
1817         }
1818
1819         // Initialize video standard enum dynamic control
1820         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1821         if (cptr) {
1822                 memcpy(&hdw->std_info_enum,cptr->info,
1823                        sizeof(hdw->std_info_enum));
1824                 cptr->info = &hdw->std_info_enum;
1825
1826         }
1827         // Initialize control data regarding video standard masks
1828         valid_std_mask = pvr2_std_get_usable();
1829         for (idx = 0; idx < 32; idx++) {
1830                 if (!(valid_std_mask & (1 << idx))) continue;
1831                 cnt1 = pvr2_std_id_to_str(
1832                         hdw->std_mask_names[idx],
1833                         sizeof(hdw->std_mask_names[idx])-1,
1834                         1 << idx);
1835                 hdw->std_mask_names[idx][cnt1] = 0;
1836         }
1837         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1838         if (cptr) {
1839                 memcpy(&hdw->std_info_avail,cptr->info,
1840                        sizeof(hdw->std_info_avail));
1841                 cptr->info = &hdw->std_info_avail;
1842                 hdw->std_info_avail.def.type_bitmask.bit_names =
1843                         hdw->std_mask_ptrs;
1844                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1845                         valid_std_mask;
1846         }
1847         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1848         if (cptr) {
1849                 memcpy(&hdw->std_info_cur,cptr->info,
1850                        sizeof(hdw->std_info_cur));
1851                 cptr->info = &hdw->std_info_cur;
1852                 hdw->std_info_cur.def.type_bitmask.bit_names =
1853                         hdw->std_mask_ptrs;
1854                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1855                         valid_std_mask;
1856         }
1857
1858         hdw->eeprom_addr = -1;
1859         hdw->unit_number = -1;
1860         hdw->v4l_minor_number = -1;
1861         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1862         if (!hdw->ctl_write_buffer) goto fail;
1863         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1864         if (!hdw->ctl_read_buffer) goto fail;
1865         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1866         if (!hdw->ctl_write_urb) goto fail;
1867         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1868         if (!hdw->ctl_read_urb) goto fail;
1869
1870         down(&pvr2_unit_sem); do {
1871                 for (idx = 0; idx < PVR_NUM; idx++) {
1872                         if (unit_pointers[idx]) continue;
1873                         hdw->unit_number = idx;
1874                         unit_pointers[idx] = hdw;
1875                         break;
1876                 }
1877         } while (0); up(&pvr2_unit_sem);
1878
1879         cnt1 = 0;
1880         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1881         cnt1 += cnt2;
1882         if (hdw->unit_number >= 0) {
1883                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1884                                  ('a' + hdw->unit_number));
1885                 cnt1 += cnt2;
1886         }
1887         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1888         hdw->name[cnt1] = 0;
1889
1890         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1891                    hdw->unit_number,hdw->name);
1892
1893         hdw->tuner_type = -1;
1894         hdw->flag_ok = !0;
1895         /* Initialize the mask of subsystems that we will shut down when we
1896            stop streaming. */
1897         hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1898         hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1899
1900         pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1901                    hdw->subsys_stream_mask);
1902
1903         hdw->usb_intf = intf;
1904         hdw->usb_dev = interface_to_usbdev(intf);
1905
1906         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1907         usb_set_interface(hdw->usb_dev,ifnum,0);
1908
1909         mutex_init(&hdw->ctl_lock_mutex);
1910         mutex_init(&hdw->big_lock_mutex);
1911
1912         return hdw;
1913  fail:
1914         if (hdw) {
1915                 if (hdw->ctl_read_urb) usb_free_urb(hdw->ctl_read_urb);
1916                 if (hdw->ctl_write_urb) usb_free_urb(hdw->ctl_write_urb);
1917                 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1918                 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1919                 if (hdw->controls) kfree(hdw->controls);
1920                 if (hdw->mpeg_ctrl_info) kfree(hdw->mpeg_ctrl_info);
1921                 kfree(hdw);
1922         }
1923         return 0;
1924 }
1925
1926
1927 /* Remove _all_ associations between this driver and the underlying USB
1928    layer. */
1929 void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1930 {
1931         if (hdw->flag_disconnected) return;
1932         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1933         if (hdw->ctl_read_urb) {
1934                 usb_kill_urb(hdw->ctl_read_urb);
1935                 usb_free_urb(hdw->ctl_read_urb);
1936                 hdw->ctl_read_urb = 0;
1937         }
1938         if (hdw->ctl_write_urb) {
1939                 usb_kill_urb(hdw->ctl_write_urb);
1940                 usb_free_urb(hdw->ctl_write_urb);
1941                 hdw->ctl_write_urb = 0;
1942         }
1943         if (hdw->ctl_read_buffer) {
1944                 kfree(hdw->ctl_read_buffer);
1945                 hdw->ctl_read_buffer = 0;
1946         }
1947         if (hdw->ctl_write_buffer) {
1948                 kfree(hdw->ctl_write_buffer);
1949                 hdw->ctl_write_buffer = 0;
1950         }
1951         pvr2_hdw_render_useless_unlocked(hdw);
1952         hdw->flag_disconnected = !0;
1953         hdw->usb_dev = 0;
1954         hdw->usb_intf = 0;
1955 }
1956
1957
1958 /* Destroy hardware interaction structure */
1959 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
1960 {
1961         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
1962         if (hdw->fw_buffer) {
1963                 kfree(hdw->fw_buffer);
1964                 hdw->fw_buffer = 0;
1965         }
1966         if (hdw->vid_stream) {
1967                 pvr2_stream_destroy(hdw->vid_stream);
1968                 hdw->vid_stream = 0;
1969         }
1970         if (hdw->audio_stat) {
1971                 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
1972         }
1973         if (hdw->decoder_ctrl) {
1974                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
1975         }
1976         pvr2_i2c_core_done(hdw);
1977         pvr2_hdw_remove_usb_stuff(hdw);
1978         down(&pvr2_unit_sem); do {
1979                 if ((hdw->unit_number >= 0) &&
1980                     (hdw->unit_number < PVR_NUM) &&
1981                     (unit_pointers[hdw->unit_number] == hdw)) {
1982                         unit_pointers[hdw->unit_number] = 0;
1983                 }
1984         } while (0); up(&pvr2_unit_sem);
1985         if (hdw->controls) kfree(hdw->controls);
1986         if (hdw->mpeg_ctrl_info) kfree(hdw->mpeg_ctrl_info);
1987         if (hdw->std_defs) kfree(hdw->std_defs);
1988         if (hdw->std_enum_names) kfree(hdw->std_enum_names);
1989         kfree(hdw);
1990 }
1991
1992
1993 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
1994 {
1995         return hdw->flag_init_ok;
1996 }
1997
1998
1999 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2000 {
2001         return (hdw && hdw->flag_ok);
2002 }
2003
2004
2005 /* Called when hardware has been unplugged */
2006 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2007 {
2008         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2009         LOCK_TAKE(hdw->big_lock);
2010         LOCK_TAKE(hdw->ctl_lock);
2011         pvr2_hdw_remove_usb_stuff(hdw);
2012         LOCK_GIVE(hdw->ctl_lock);
2013         LOCK_GIVE(hdw->big_lock);
2014 }
2015
2016
2017 // Attempt to autoselect an appropriate value for std_enum_cur given
2018 // whatever is currently in std_mask_cur
2019 void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2020 {
2021         unsigned int idx;
2022         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2023                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2024                         hdw->std_enum_cur = idx;
2025                         return;
2026                 }
2027         }
2028         hdw->std_enum_cur = 0;
2029 }
2030
2031
2032 // Calculate correct set of enumerated standards based on currently known
2033 // set of available standards bits.
2034 void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2035 {
2036         struct v4l2_standard *newstd;
2037         unsigned int std_cnt;
2038         unsigned int idx;
2039
2040         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2041
2042         if (hdw->std_defs) {
2043                 kfree(hdw->std_defs);
2044                 hdw->std_defs = 0;
2045         }
2046         hdw->std_enum_cnt = 0;
2047         if (hdw->std_enum_names) {
2048                 kfree(hdw->std_enum_names);
2049                 hdw->std_enum_names = 0;
2050         }
2051
2052         if (!std_cnt) {
2053                 pvr2_trace(
2054                         PVR2_TRACE_ERROR_LEGS,
2055                         "WARNING: Failed to identify any viable standards");
2056         }
2057         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2058         hdw->std_enum_names[0] = "none";
2059         for (idx = 0; idx < std_cnt; idx++) {
2060                 hdw->std_enum_names[idx+1] =
2061                         newstd[idx].name;
2062         }
2063         // Set up the dynamic control for this standard
2064         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2065         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2066         hdw->std_defs = newstd;
2067         hdw->std_enum_cnt = std_cnt+1;
2068         hdw->std_enum_cur = 0;
2069         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2070 }
2071
2072
2073 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2074                                struct v4l2_standard *std,
2075                                unsigned int idx)
2076 {
2077         int ret = -EINVAL;
2078         if (!idx) return ret;
2079         LOCK_TAKE(hdw->big_lock); do {
2080                 if (idx >= hdw->std_enum_cnt) break;
2081                 idx--;
2082                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2083                 ret = 0;
2084         } while (0); LOCK_GIVE(hdw->big_lock);
2085         return ret;
2086 }
2087
2088
2089 /* Get the number of defined controls */
2090 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2091 {
2092         return hdw->control_cnt;
2093 }
2094
2095
2096 /* Retrieve a control handle given its index (0..count-1) */
2097 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2098                                              unsigned int idx)
2099 {
2100         if (idx >= hdw->control_cnt) return 0;
2101         return hdw->controls + idx;
2102 }
2103
2104
2105 /* Retrieve a control handle given its index (0..count-1) */
2106 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2107                                           unsigned int ctl_id)
2108 {
2109         struct pvr2_ctrl *cptr;
2110         unsigned int idx;
2111         int i;
2112
2113         /* This could be made a lot more efficient, but for now... */
2114         for (idx = 0; idx < hdw->control_cnt; idx++) {
2115                 cptr = hdw->controls + idx;
2116                 i = cptr->info->internal_id;
2117                 if (i && (i == ctl_id)) return cptr;
2118         }
2119         return 0;
2120 }
2121
2122
2123 /* Given a V4L ID, retrieve the control structure associated with it. */
2124 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2125 {
2126         struct pvr2_ctrl *cptr;
2127         unsigned int idx;
2128         int i;
2129
2130         /* This could be made a lot more efficient, but for now... */
2131         for (idx = 0; idx < hdw->control_cnt; idx++) {
2132                 cptr = hdw->controls + idx;
2133                 i = cptr->info->v4l_id;
2134                 if (i && (i == ctl_id)) return cptr;
2135         }
2136         return 0;
2137 }
2138
2139
2140 /* Given a V4L ID for its immediate predecessor, retrieve the control
2141    structure associated with it. */
2142 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2143                                             unsigned int ctl_id)
2144 {
2145         struct pvr2_ctrl *cptr,*cp2;
2146         unsigned int idx;
2147         int i;
2148
2149         /* This could be made a lot more efficient, but for now... */
2150         cp2 = 0;
2151         for (idx = 0; idx < hdw->control_cnt; idx++) {
2152                 cptr = hdw->controls + idx;
2153                 i = cptr->info->v4l_id;
2154                 if (!i) continue;
2155                 if (i <= ctl_id) continue;
2156                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2157                 cp2 = cptr;
2158         }
2159         return cp2;
2160         return 0;
2161 }
2162
2163
2164 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2165 {
2166         switch (tp) {
2167         case pvr2_ctl_int: return "integer";
2168         case pvr2_ctl_enum: return "enum";
2169         case pvr2_ctl_bool: return "boolean";
2170         case pvr2_ctl_bitmask: return "bitmask";
2171         }
2172         return "";
2173 }
2174
2175
2176 /* Commit all control changes made up to this point.  Subsystems can be
2177    indirectly affected by these changes.  For a given set of things being
2178    committed, we'll clear the affected subsystem bits and then once we're
2179    done committing everything we'll make a request to restore the subsystem
2180    state(s) back to their previous value before this function was called.
2181    Thus we can automatically reconfigure affected pieces of the driver as
2182    controls are changed. */
2183 int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2184 {
2185         unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2186         unsigned long stale_subsys_mask = 0;
2187         unsigned int idx;
2188         struct pvr2_ctrl *cptr;
2189         int value;
2190         int commit_flag = 0;
2191         char buf[100];
2192         unsigned int bcnt,ccnt;
2193
2194         for (idx = 0; idx < hdw->control_cnt; idx++) {
2195                 cptr = hdw->controls + idx;
2196                 if (cptr->info->is_dirty == 0) continue;
2197                 if (!cptr->info->is_dirty(cptr)) continue;
2198                 if (!commit_flag) {
2199                         commit_flag = !0;
2200                 }
2201
2202                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2203                                  cptr->info->name);
2204                 value = 0;
2205                 cptr->info->get_value(cptr,&value);
2206                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2207                                                 buf+bcnt,
2208                                                 sizeof(buf)-bcnt,&ccnt);
2209                 bcnt += ccnt;
2210                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2211                                   get_ctrl_typename(cptr->info->type));
2212                 pvr2_trace(PVR2_TRACE_CTL,
2213                            "/*--TRACE_COMMIT--*/ %.*s",
2214                            bcnt,buf);
2215         }
2216
2217         if (!commit_flag) {
2218                 /* Nothing has changed */
2219                 return 0;
2220         }
2221
2222         /* When video standard changes, reset the hres and vres values -
2223            but if the user has pending changes there, then let the changes
2224            take priority. */
2225         if (hdw->std_dirty) {
2226                 /* Rewrite the vertical resolution to be appropriate to the
2227                    video standard that has been selected. */
2228                 int nvres;
2229                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2230                         nvres = 480;
2231                 } else {
2232                         nvres = 576;
2233                 }
2234                 if (nvres != hdw->res_ver_val) {
2235                         hdw->res_ver_val = nvres;
2236                         hdw->res_ver_dirty = !0;
2237                 }
2238         }
2239
2240         if (hdw->std_dirty ||
2241             0) {
2242                 /* If any of this changes, then the encoder needs to be
2243                    reconfigured, and we need to reset the stream. */
2244                 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2245                 stale_subsys_mask |= hdw->subsys_stream_mask;
2246         }
2247
2248         if (hdw->srate_dirty) {
2249                 /* Write new sample rate into control structure since
2250                  * the master copy is stale.  We must track srate
2251                  * separate from the mpeg control structure because
2252                  * other logic also uses this value. */
2253                 struct v4l2_ext_controls cs;
2254                 struct v4l2_ext_control c1;
2255                 memset(&cs,0,sizeof(cs));
2256                 memset(&c1,0,sizeof(c1));
2257                 cs.controls = &c1;
2258                 cs.count = 1;
2259                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2260                 c1.value = hdw->srate_val;
2261                 cx2341x_ext_ctrls(&hdw->enc_ctl_state,&cs,VIDIOC_S_EXT_CTRLS);
2262         }
2263
2264         /* Scan i2c core at this point - before we clear all the dirty
2265            bits.  Various parts of the i2c core will notice dirty bits as
2266            appropriate and arrange to broadcast or directly send updates to
2267            the client drivers in order to keep everything in sync */
2268         pvr2_i2c_core_check_stale(hdw);
2269
2270         for (idx = 0; idx < hdw->control_cnt; idx++) {
2271                 cptr = hdw->controls + idx;
2272                 if (!cptr->info->clear_dirty) continue;
2273                 cptr->info->clear_dirty(cptr);
2274         }
2275
2276         /* Now execute i2c core update */
2277         pvr2_i2c_core_sync(hdw);
2278
2279         pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2280         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2281
2282         return 0;
2283 }
2284
2285
2286 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2287 {
2288         LOCK_TAKE(hdw->big_lock); do {
2289                 pvr2_hdw_commit_ctl_internal(hdw);
2290         } while (0); LOCK_GIVE(hdw->big_lock);
2291         return 0;
2292 }
2293
2294
2295 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2296 {
2297         LOCK_TAKE(hdw->big_lock); do {
2298                 pvr2_i2c_core_sync(hdw);
2299         } while (0); LOCK_GIVE(hdw->big_lock);
2300 }
2301
2302
2303 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2304                                  void (*func)(void *),
2305                                  void *data)
2306 {
2307         LOCK_TAKE(hdw->big_lock); do {
2308                 hdw->poll_trigger_func = func;
2309                 hdw->poll_trigger_data = data;
2310         } while (0); LOCK_GIVE(hdw->big_lock);
2311 }
2312
2313
2314 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2315 {
2316         if (hdw->poll_trigger_func) {
2317                 hdw->poll_trigger_func(hdw->poll_trigger_data);
2318         }
2319 }
2320
2321
2322 void pvr2_hdw_poll_trigger(struct pvr2_hdw *hdw)
2323 {
2324         LOCK_TAKE(hdw->big_lock); do {
2325                 pvr2_hdw_poll_trigger_unlocked(hdw);
2326         } while (0); LOCK_GIVE(hdw->big_lock);
2327 }
2328
2329
2330 /* Return name for this driver instance */
2331 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2332 {
2333         return hdw->name;
2334 }
2335
2336
2337 /* Return bit mask indicating signal status */
2338 unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2339 {
2340         unsigned int msk = 0;
2341         switch (hdw->input_val) {
2342         case PVR2_CVAL_INPUT_TV:
2343         case PVR2_CVAL_INPUT_RADIO:
2344                 if (hdw->decoder_ctrl &&
2345                     hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2346                         msk |= PVR2_SIGNAL_OK;
2347                         if (hdw->audio_stat &&
2348                             hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2349                                 if (hdw->flag_stereo) {
2350                                         msk |= PVR2_SIGNAL_STEREO;
2351                                 }
2352                                 if (hdw->flag_bilingual) {
2353                                         msk |= PVR2_SIGNAL_SAP;
2354                                 }
2355                         }
2356                 }
2357                 break;
2358         default:
2359                 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2360         }
2361         return msk;
2362 }
2363
2364
2365 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2366 {
2367         int result;
2368         LOCK_TAKE(hdw->ctl_lock); do {
2369                 hdw->cmd_buffer[0] = 0x0b;
2370                 result = pvr2_send_request(hdw,
2371                                            hdw->cmd_buffer,1,
2372                                            hdw->cmd_buffer,1);
2373                 if (result < 0) break;
2374                 result = (hdw->cmd_buffer[0] != 0);
2375         } while(0); LOCK_GIVE(hdw->ctl_lock);
2376         return result;
2377 }
2378
2379
2380 /* Return bit mask indicating signal status */
2381 unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2382 {
2383         unsigned int msk = 0;
2384         LOCK_TAKE(hdw->big_lock); do {
2385                 msk = pvr2_hdw_get_signal_status_internal(hdw);
2386         } while (0); LOCK_GIVE(hdw->big_lock);
2387         return msk;
2388 }
2389
2390
2391 /* Get handle to video output stream */
2392 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2393 {
2394         return hp->vid_stream;
2395 }
2396
2397
2398 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2399 {
2400         int nr = pvr2_hdw_get_unit_number(hdw);
2401         LOCK_TAKE(hdw->big_lock); do {
2402                 hdw->log_requested = !0;
2403                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2404                 pvr2_i2c_core_check_stale(hdw);
2405                 hdw->log_requested = 0;
2406                 pvr2_i2c_core_sync(hdw);
2407                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2408                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2409                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2410         } while (0); LOCK_GIVE(hdw->big_lock);
2411 }
2412
2413 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2414 {
2415         int ret;
2416         u16 address;
2417         unsigned int pipe;
2418         LOCK_TAKE(hdw->big_lock); do {
2419                 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2420
2421                 if (!enable_flag) {
2422                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2423                                    "Cleaning up after CPU firmware fetch");
2424                         kfree(hdw->fw_buffer);
2425                         hdw->fw_buffer = 0;
2426                         hdw->fw_size = 0;
2427                         /* Now release the CPU.  It will disconnect and
2428                            reconnect later. */
2429                         pvr2_hdw_cpureset_assert(hdw,0);
2430                         break;
2431                 }
2432
2433                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2434                            "Preparing to suck out CPU firmware");
2435                 hdw->fw_size = 0x2000;
2436                 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2437                 if (!hdw->fw_buffer) {
2438                         hdw->fw_size = 0;
2439                         break;
2440                 }
2441
2442                 memset(hdw->fw_buffer,0,hdw->fw_size);
2443
2444                 /* We have to hold the CPU during firmware upload. */
2445                 pvr2_hdw_cpureset_assert(hdw,1);
2446
2447                 /* download the firmware from address 0000-1fff in 2048
2448                    (=0x800) bytes chunk. */
2449
2450                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2451                 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2452                 for(address = 0; address < hdw->fw_size; address += 0x800) {
2453                         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2454                                               address,0,
2455                                               hdw->fw_buffer+address,0x800,HZ);
2456                         if (ret < 0) break;
2457                 }
2458
2459                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2460
2461         } while (0); LOCK_GIVE(hdw->big_lock);
2462 }
2463
2464
2465 /* Return true if we're in a mode for retrieval CPU firmware */
2466 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2467 {
2468         return hdw->fw_buffer != 0;
2469 }
2470
2471
2472 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2473                        char *buf,unsigned int cnt)
2474 {
2475         int ret = -EINVAL;
2476         LOCK_TAKE(hdw->big_lock); do {
2477                 if (!buf) break;
2478                 if (!cnt) break;
2479
2480                 if (!hdw->fw_buffer) {
2481                         ret = -EIO;
2482                         break;
2483                 }
2484
2485                 if (offs >= hdw->fw_size) {
2486                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2487                                    "Read firmware data offs=%d EOF",
2488                                    offs);
2489                         ret = 0;
2490                         break;
2491                 }
2492
2493                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2494
2495                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2496
2497                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2498                            "Read firmware data offs=%d cnt=%d",
2499                            offs,cnt);
2500                 ret = cnt;
2501         } while (0); LOCK_GIVE(hdw->big_lock);
2502
2503         return ret;
2504 }
2505
2506
2507 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2508 {
2509         return hdw->v4l_minor_number;
2510 }
2511
2512
2513 /* Store the v4l minor device number */
2514 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2515 {
2516         hdw->v4l_minor_number = v;
2517 }
2518
2519
2520 void pvr2_reset_ctl_endpoints(struct pvr2_hdw *hdw)
2521 {
2522         if (!hdw->usb_dev) return;
2523         usb_settoggle(hdw->usb_dev, PVR2_CTL_WRITE_ENDPOINT & 0xf,
2524                       !(PVR2_CTL_WRITE_ENDPOINT & USB_DIR_IN), 0);
2525         usb_settoggle(hdw->usb_dev, PVR2_CTL_READ_ENDPOINT & 0xf,
2526                       !(PVR2_CTL_READ_ENDPOINT & USB_DIR_IN), 0);
2527         usb_clear_halt(hdw->usb_dev,
2528                        usb_rcvbulkpipe(hdw->usb_dev,
2529                                        PVR2_CTL_READ_ENDPOINT & 0x7f));
2530         usb_clear_halt(hdw->usb_dev,
2531                        usb_sndbulkpipe(hdw->usb_dev,
2532                                        PVR2_CTL_WRITE_ENDPOINT & 0x7f));
2533 }
2534
2535
2536 static void pvr2_ctl_write_complete(struct urb *urb, struct pt_regs *regs)
2537 {
2538         struct pvr2_hdw *hdw = urb->context;
2539         hdw->ctl_write_pend_flag = 0;
2540         if (hdw->ctl_read_pend_flag) return;
2541         complete(&hdw->ctl_done);
2542 }
2543
2544
2545 static void pvr2_ctl_read_complete(struct urb *urb, struct pt_regs *regs)
2546 {
2547         struct pvr2_hdw *hdw = urb->context;
2548         hdw->ctl_read_pend_flag = 0;
2549         if (hdw->ctl_write_pend_flag) return;
2550         complete(&hdw->ctl_done);
2551 }
2552
2553
2554 static void pvr2_ctl_timeout(unsigned long data)
2555 {
2556         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2557         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2558                 hdw->ctl_timeout_flag = !0;
2559                 if (hdw->ctl_write_pend_flag && hdw->ctl_write_urb) {
2560                         usb_unlink_urb(hdw->ctl_write_urb);
2561                 }
2562                 if (hdw->ctl_read_pend_flag && hdw->ctl_read_urb) {
2563                         usb_unlink_urb(hdw->ctl_read_urb);
2564                 }
2565         }
2566 }
2567
2568
2569 int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2570                          unsigned int timeout,int probe_fl,
2571                          void *write_data,unsigned int write_len,
2572                          void *read_data,unsigned int read_len)
2573 {
2574         unsigned int idx;
2575         int status = 0;
2576         struct timer_list timer;
2577         if (!hdw->ctl_lock_held) {
2578                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2579                            "Attempted to execute control transfer"
2580                            " without lock!!");
2581                 return -EDEADLK;
2582         }
2583         if ((!hdw->flag_ok) && !probe_fl) {
2584                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2585                            "Attempted to execute control transfer"
2586                            " when device not ok");
2587                 return -EIO;
2588         }
2589         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2590                 if (!probe_fl) {
2591                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2592                                    "Attempted to execute control transfer"
2593                                    " when USB is disconnected");
2594                 }
2595                 return -ENOTTY;
2596         }
2597
2598         /* Ensure that we have sane parameters */
2599         if (!write_data) write_len = 0;
2600         if (!read_data) read_len = 0;
2601         if (write_len > PVR2_CTL_BUFFSIZE) {
2602                 pvr2_trace(
2603                         PVR2_TRACE_ERROR_LEGS,
2604                         "Attempted to execute %d byte"
2605                         " control-write transfer (limit=%d)",
2606                         write_len,PVR2_CTL_BUFFSIZE);
2607                 return -EINVAL;
2608         }
2609         if (read_len > PVR2_CTL_BUFFSIZE) {
2610                 pvr2_trace(
2611                         PVR2_TRACE_ERROR_LEGS,
2612                         "Attempted to execute %d byte"
2613                         " control-read transfer (limit=%d)",
2614                         write_len,PVR2_CTL_BUFFSIZE);
2615                 return -EINVAL;
2616         }
2617         if ((!write_len) && (!read_len)) {
2618                 pvr2_trace(
2619                         PVR2_TRACE_ERROR_LEGS,
2620                         "Attempted to execute null control transfer?");
2621                 return -EINVAL;
2622         }
2623
2624
2625         hdw->cmd_debug_state = 1;
2626         if (write_len) {
2627                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2628         } else {
2629                 hdw->cmd_debug_code = 0;
2630         }
2631         hdw->cmd_debug_write_len = write_len;
2632         hdw->cmd_debug_read_len = read_len;
2633
2634         /* Initialize common stuff */
2635         init_completion(&hdw->ctl_done);
2636         hdw->ctl_timeout_flag = 0;
2637         hdw->ctl_write_pend_flag = 0;
2638         hdw->ctl_read_pend_flag = 0;
2639         init_timer(&timer);
2640         timer.expires = jiffies + timeout;
2641         timer.data = (unsigned long)hdw;
2642         timer.function = pvr2_ctl_timeout;
2643
2644         if (write_len) {
2645                 hdw->cmd_debug_state = 2;
2646                 /* Transfer write data to internal buffer */
2647                 for (idx = 0; idx < write_len; idx++) {
2648                         hdw->ctl_write_buffer[idx] =
2649                                 ((unsigned char *)write_data)[idx];
2650                 }
2651                 /* Initiate a write request */
2652                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2653                                   hdw->usb_dev,
2654                                   usb_sndbulkpipe(hdw->usb_dev,
2655                                                   PVR2_CTL_WRITE_ENDPOINT),
2656                                   hdw->ctl_write_buffer,
2657                                   write_len,
2658                                   pvr2_ctl_write_complete,
2659                                   hdw);
2660                 hdw->ctl_write_urb->actual_length = 0;
2661                 hdw->ctl_write_pend_flag = !0;
2662                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2663                 if (status < 0) {
2664                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2665                                    "Failed to submit write-control"
2666                                    " URB status=%d",status);
2667                         hdw->ctl_write_pend_flag = 0;
2668                         goto done;
2669                 }
2670         }
2671
2672         if (read_len) {
2673                 hdw->cmd_debug_state = 3;
2674                 memset(hdw->ctl_read_buffer,0x43,read_len);
2675                 /* Initiate a read request */
2676                 usb_fill_bulk_urb(hdw->ctl_read_urb,
2677                                   hdw->usb_dev,
2678                                   usb_rcvbulkpipe(hdw->usb_dev,
2679                                                   PVR2_CTL_READ_ENDPOINT),
2680                                   hdw->ctl_read_buffer,
2681                                   read_len,
2682                                   pvr2_ctl_read_complete,
2683                                   hdw);
2684                 hdw->ctl_read_urb->actual_length = 0;
2685                 hdw->ctl_read_pend_flag = !0;
2686                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2687                 if (status < 0) {
2688                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2689                                    "Failed to submit read-control"
2690                                    " URB status=%d",status);
2691                         hdw->ctl_read_pend_flag = 0;
2692                         goto done;
2693                 }
2694         }
2695
2696         /* Start timer */
2697         add_timer(&timer);
2698
2699         /* Now wait for all I/O to complete */
2700         hdw->cmd_debug_state = 4;
2701         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2702                 wait_for_completion(&hdw->ctl_done);
2703         }
2704         hdw->cmd_debug_state = 5;
2705
2706         /* Stop timer */
2707         del_timer_sync(&timer);
2708
2709         hdw->cmd_debug_state = 6;
2710         status = 0;
2711
2712         if (hdw->ctl_timeout_flag) {
2713                 status = -ETIMEDOUT;
2714                 if (!probe_fl) {
2715                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2716                                    "Timed out control-write");
2717                 }
2718                 goto done;
2719         }
2720
2721         if (write_len) {
2722                 /* Validate results of write request */
2723                 if ((hdw->ctl_write_urb->status != 0) &&
2724                     (hdw->ctl_write_urb->status != -ENOENT) &&
2725                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2726                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
2727                         /* USB subsystem is reporting some kind of failure
2728                            on the write */
2729                         status = hdw->ctl_write_urb->status;
2730                         if (!probe_fl) {
2731                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2732                                            "control-write URB failure,"
2733                                            " status=%d",
2734                                            status);
2735                         }
2736                         goto done;
2737                 }
2738                 if (hdw->ctl_write_urb->actual_length < write_len) {
2739                         /* Failed to write enough data */
2740                         status = -EIO;
2741                         if (!probe_fl) {
2742                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2743                                            "control-write URB short,"
2744                                            " expected=%d got=%d",
2745                                            write_len,
2746                                            hdw->ctl_write_urb->actual_length);
2747                         }
2748                         goto done;
2749                 }
2750         }
2751         if (read_len) {
2752                 /* Validate results of read request */
2753                 if ((hdw->ctl_read_urb->status != 0) &&
2754                     (hdw->ctl_read_urb->status != -ENOENT) &&
2755                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2756                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
2757                         /* USB subsystem is reporting some kind of failure
2758                            on the read */
2759                         status = hdw->ctl_read_urb->status;
2760                         if (!probe_fl) {
2761                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2762                                            "control-read URB failure,"
2763                                            " status=%d",
2764                                            status);
2765                         }
2766                         goto done;
2767                 }
2768                 if (hdw->ctl_read_urb->actual_length < read_len) {
2769                         /* Failed to read enough data */
2770                         status = -EIO;
2771                         if (!probe_fl) {
2772                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2773                                            "control-read URB short,"
2774                                            " expected=%d got=%d",
2775                                            read_len,
2776                                            hdw->ctl_read_urb->actual_length);
2777                         }
2778                         goto done;
2779                 }
2780                 /* Transfer retrieved data out from internal buffer */
2781                 for (idx = 0; idx < read_len; idx++) {
2782                         ((unsigned char *)read_data)[idx] =
2783                                 hdw->ctl_read_buffer[idx];
2784                 }
2785         }
2786
2787  done:
2788
2789         hdw->cmd_debug_state = 0;
2790         if ((status < 0) && (!probe_fl)) {
2791                 pvr2_hdw_render_useless_unlocked(hdw);
2792         }
2793         return status;
2794 }
2795
2796
2797 int pvr2_send_request(struct pvr2_hdw *hdw,
2798                       void *write_data,unsigned int write_len,
2799                       void *read_data,unsigned int read_len)
2800 {
2801         return pvr2_send_request_ex(hdw,HZ*4,0,
2802                                     write_data,write_len,
2803                                     read_data,read_len);
2804 }
2805
2806 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2807 {
2808         int ret;
2809
2810         LOCK_TAKE(hdw->ctl_lock);
2811
2812         hdw->cmd_buffer[0] = 0x04;  /* write register prefix */
2813         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2814         hdw->cmd_buffer[5] = 0;
2815         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2816         hdw->cmd_buffer[7] = reg & 0xff;
2817
2818
2819         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2820
2821         LOCK_GIVE(hdw->ctl_lock);
2822
2823         return ret;
2824 }
2825
2826
2827 int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2828 {
2829         int ret = 0;
2830
2831         LOCK_TAKE(hdw->ctl_lock);
2832
2833         hdw->cmd_buffer[0] = 0x05;  /* read register prefix */
2834         hdw->cmd_buffer[1] = 0;
2835         hdw->cmd_buffer[2] = 0;
2836         hdw->cmd_buffer[3] = 0;
2837         hdw->cmd_buffer[4] = 0;
2838         hdw->cmd_buffer[5] = 0;
2839         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2840         hdw->cmd_buffer[7] = reg & 0xff;
2841
2842         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2843         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2844
2845         LOCK_GIVE(hdw->ctl_lock);
2846
2847         return ret;
2848 }
2849
2850
2851 int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2852 {
2853         int ret;
2854
2855         LOCK_TAKE(hdw->ctl_lock);
2856
2857         hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2858         hdw->cmd_buffer[1] = data & 0xff;
2859
2860         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2861
2862         LOCK_GIVE(hdw->ctl_lock);
2863
2864         return ret;
2865 }
2866
2867
2868 int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2869 {
2870         int ret;
2871
2872         LOCK_TAKE(hdw->ctl_lock);
2873
2874         hdw->cmd_buffer[0] = data;
2875
2876         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2877
2878         LOCK_GIVE(hdw->ctl_lock);
2879
2880         return ret;
2881 }
2882
2883
2884 void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2885 {
2886         if (!hdw->flag_ok) return;
2887         pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2888         hdw->flag_ok = 0;
2889         if (hdw->vid_stream) {
2890                 pvr2_stream_setup(hdw->vid_stream,0,0,0);
2891         }
2892         hdw->flag_streaming_enabled = 0;
2893         hdw->subsys_enabled_mask = 0;
2894 }
2895
2896
2897 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2898 {
2899         LOCK_TAKE(hdw->ctl_lock);
2900         pvr2_hdw_render_useless_unlocked(hdw);
2901         LOCK_GIVE(hdw->ctl_lock);
2902 }
2903
2904
2905 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2906 {
2907         int ret;
2908         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2909         ret = usb_lock_device_for_reset(hdw->usb_dev,0);
2910         if (ret == 1) {
2911                 ret = usb_reset_device(hdw->usb_dev);
2912                 usb_unlock_device(hdw->usb_dev);
2913         } else {
2914                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2915                            "Failed to lock USB device ret=%d",ret);
2916         }
2917         if (init_pause_msec) {
2918                 pvr2_trace(PVR2_TRACE_INFO,
2919                            "Waiting %u msec for hardware to settle",
2920                            init_pause_msec);
2921                 msleep(init_pause_msec);
2922         }
2923
2924 }
2925
2926
2927 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2928 {
2929         char da[1];
2930         unsigned int pipe;
2931         int ret;
2932
2933         if (!hdw->usb_dev) return;
2934
2935         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2936
2937         da[0] = val ? 0x01 : 0x00;
2938
2939         /* Write the CPUCS register on the 8051.  The lsb of the register
2940            is the reset bit; a 1 asserts reset while a 0 clears it. */
2941         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2942         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2943         if (ret < 0) {
2944                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2945                            "cpureset_assert(%d) error=%d",val,ret);
2946                 pvr2_hdw_render_useless(hdw);
2947         }
2948 }
2949
2950
2951 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2952 {
2953         int status;
2954         LOCK_TAKE(hdw->ctl_lock); do {
2955                 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2956                 hdw->flag_ok = !0;
2957                 hdw->cmd_buffer[0] = 0xdd;
2958                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2959         } while (0); LOCK_GIVE(hdw->ctl_lock);
2960         return status;
2961 }
2962
2963
2964 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2965 {
2966         int status;
2967         LOCK_TAKE(hdw->ctl_lock); do {
2968                 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2969                 hdw->cmd_buffer[0] = 0xde;
2970                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2971         } while (0); LOCK_GIVE(hdw->ctl_lock);
2972         return status;
2973 }
2974
2975
2976 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
2977 {
2978         if (!hdw->decoder_ctrl) {
2979                 pvr2_trace(PVR2_TRACE_INIT,
2980                            "Unable to reset decoder: nothing attached");
2981                 return -ENOTTY;
2982         }
2983
2984         if (!hdw->decoder_ctrl->force_reset) {
2985                 pvr2_trace(PVR2_TRACE_INIT,
2986                            "Unable to reset decoder: not implemented");
2987                 return -ENOTTY;
2988         }
2989
2990         pvr2_trace(PVR2_TRACE_INIT,
2991                    "Requesting decoder reset");
2992         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
2993         return 0;
2994 }
2995
2996
2997 int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
2998 {
2999         int status;
3000         LOCK_TAKE(hdw->ctl_lock); do {
3001                 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
3002                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
3003         } while (0); LOCK_GIVE(hdw->ctl_lock);
3004         if (!status) {
3005                 hdw->subsys_enabled_mask =
3006                         ((hdw->subsys_enabled_mask &
3007                           ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
3008                          (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
3009         }
3010         return status;
3011 }
3012
3013
3014 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
3015                              struct pvr2_hdw_debug_info *ptr)
3016 {
3017         ptr->big_lock_held = hdw->big_lock_held;
3018         ptr->ctl_lock_held = hdw->ctl_lock_held;
3019         ptr->flag_ok = hdw->flag_ok;
3020         ptr->flag_disconnected = hdw->flag_disconnected;
3021         ptr->flag_init_ok = hdw->flag_init_ok;
3022         ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
3023         ptr->subsys_flags = hdw->subsys_enabled_mask;
3024         ptr->cmd_debug_state = hdw->cmd_debug_state;
3025         ptr->cmd_code = hdw->cmd_debug_code;
3026         ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3027         ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3028         ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3029         ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3030         ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3031         ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3032         ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3033 }
3034
3035
3036 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3037 {
3038         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3039 }
3040
3041
3042 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3043 {
3044         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3045 }
3046
3047
3048 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3049 {
3050         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3051 }
3052
3053
3054 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3055 {
3056         u32 cval,nval;
3057         int ret;
3058         if (~msk) {
3059                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3060                 if (ret) return ret;
3061                 nval = (cval & ~msk) | (val & msk);
3062                 pvr2_trace(PVR2_TRACE_GPIO,
3063                            "GPIO direction changing 0x%x:0x%x"
3064                            " from 0x%x to 0x%x",
3065                            msk,val,cval,nval);
3066         } else {
3067                 nval = val;
3068                 pvr2_trace(PVR2_TRACE_GPIO,
3069                            "GPIO direction changing to 0x%x",nval);
3070         }
3071         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3072 }
3073
3074
3075 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3076 {
3077         u32 cval,nval;
3078         int ret;
3079         if (~msk) {
3080                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3081                 if (ret) return ret;
3082                 nval = (cval & ~msk) | (val & msk);
3083                 pvr2_trace(PVR2_TRACE_GPIO,
3084                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3085                            msk,val,cval,nval);
3086         } else {
3087                 nval = val;
3088                 pvr2_trace(PVR2_TRACE_GPIO,
3089                            "GPIO output changing to 0x%x",nval);
3090         }
3091         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3092 }
3093
3094
3095 int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
3096 {
3097         int result;
3098         LOCK_TAKE(hdw->ctl_lock); do {
3099                 hdw->cmd_buffer[0] = 0xeb;
3100                 result = pvr2_send_request(hdw,
3101                                            hdw->cmd_buffer,1,
3102                                            hdw->cmd_buffer,1);
3103                 if (result < 0) break;
3104                 result = hdw->cmd_buffer[0];
3105         } while(0); LOCK_GIVE(hdw->ctl_lock);
3106         return result;
3107 }
3108
3109
3110 /*
3111   Stuff for Emacs to see, in order to encourage consistent editing style:
3112   *** Local Variables: ***
3113   *** mode: c ***
3114   *** fill-column: 75 ***
3115   *** tab-width: 8 ***
3116   *** c-basic-offset: 8 ***
3117   *** End: ***
3118   */