drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <asm/semaphore.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38
  39 struct usb_device_id pvr2_device_table[] = {
  40         [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
  41 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  42         [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
  43 #endif
  44         { }
  45 };
  46
  47 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
  48
  49 static const char *pvr2_device_names[] = {
  50         [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
  51 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  52         [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
  53 #endif
  54 };
  55
  56 struct pvr2_string_table {
  57         const char **lst;
  58         unsigned int cnt;
  59 };
  60
  61 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  62 // Names of other client modules to request for 24xxx model hardware
  63 static const char *pvr2_client_24xxx[] = {
  64         "cx25840",
  65         "tuner",
  66         "tda9887",
  67         "wm8775",
  68 };
  69 #endif
  70
  71 // Names of other client modules to request for 29xxx model hardware
  72 static const char *pvr2_client_29xxx[] = {
  73         "msp3400",
  74         "saa7115",
  75         "tuner",
  76         "tda9887",
  77 };
  78
  79 static struct pvr2_string_table pvr2_client_lists[] = {
  80         [PVR2_HDW_TYPE_29XXX] = {
  81                 pvr2_client_29xxx,
  82                 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
  83         },
  84 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  85         [PVR2_HDW_TYPE_24XXX] = {
  86                 pvr2_client_24xxx,
  87                 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
  88         },
  89 #endif
  90 };
  91
  92 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = 0};
  93 DECLARE_MUTEX(pvr2_unit_sem);
  94
  95 static int ctlchg = 0;
  96 static int initusbreset = 1;
  97 static int procreload = 0;
  98 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  99 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
 100 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
 101 static int init_pause_msec = 0;
 102
 103 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
 104 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
 105 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
 106 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
 107 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
 108 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
 109 module_param(procreload, int, S_IRUGO|S_IWUSR);
 110 MODULE_PARM_DESC(procreload,
 111                  "Attempt init failure recovery with firmware reload");
 112 module_param_array(tuner,    int, NULL, 0444);
 113 MODULE_PARM_DESC(tuner,"specify installed tuner type");
 114 module_param_array(video_std,    int, NULL, 0444);
 115 MODULE_PARM_DESC(video_std,"specify initial video standard");
 116 module_param_array(tolerance,    int, NULL, 0444);
 117 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
 118
 119 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 120 #define PVR2_CTL_READ_ENDPOINT   0x81
 121
 122 #define PVR2_GPIO_IN 0x9008
 123 #define PVR2_GPIO_OUT 0x900c
 124 #define PVR2_GPIO_DIR 0x9020
 125
 126 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 127
 128 #define PVR2_FIRMWARE_ENDPOINT   0x02
 129
 130 /* size of a firmware chunk */
 131 #define FIRMWARE_CHUNK_SIZE 0x2000
 132
 133
 134 static const char *control_values_srate[] = {
 135         [PVR2_CVAL_SRATE_48]   = "48KHz",
 136         [PVR2_CVAL_SRATE_44_1] = "44.1KHz",
 137 };
 138
 139
 140 static const char *control_values_audiobitrate[] = {
 141         [PVR2_CVAL_AUDIOBITRATE_384] = "384kb/s",
 142         [PVR2_CVAL_AUDIOBITRATE_320] = "320kb/s",
 143         [PVR2_CVAL_AUDIOBITRATE_256] = "256kb/s",
 144         [PVR2_CVAL_AUDIOBITRATE_224] = "224kb/s",
 145         [PVR2_CVAL_AUDIOBITRATE_192] = "192kb/s",
 146         [PVR2_CVAL_AUDIOBITRATE_160] = "160kb/s",
 147         [PVR2_CVAL_AUDIOBITRATE_128] = "128kb/s",
 148         [PVR2_CVAL_AUDIOBITRATE_112] = "112kb/s",
 149         [PVR2_CVAL_AUDIOBITRATE_96]  = "96kb/s",
 150         [PVR2_CVAL_AUDIOBITRATE_80]  = "80kb/s",
 151         [PVR2_CVAL_AUDIOBITRATE_64]  = "64kb/s",
 152         [PVR2_CVAL_AUDIOBITRATE_56]  = "56kb/s",
 153         [PVR2_CVAL_AUDIOBITRATE_48]  = "48kb/s",
 154         [PVR2_CVAL_AUDIOBITRATE_32]  = "32kb/s",
 155         [PVR2_CVAL_AUDIOBITRATE_VBR] = "VBR",
 156 };
 157
 158
 159 static const char *control_values_audioemphasis[] = {
 160         [PVR2_CVAL_AUDIOEMPHASIS_NONE]  = "None",
 161         [PVR2_CVAL_AUDIOEMPHASIS_50_15] = "50/15us",
 162         [PVR2_CVAL_AUDIOEMPHASIS_CCITT] = "CCITT J.17",
 163 };
 164
 165
 166 static const char *control_values_input[] = {
 167         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 168         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 169         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 170         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 171 };
 172
 173
 174 static const char *control_values_audiomode[] = {
 175         [V4L2_TUNER_MODE_MONO]   = "Mono",
 176         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 177         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 178         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 179         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 180 };
 181
 182
 183 static const char *control_values_hsm[] = {
 184         [PVR2_CVAL_HSM_FAIL] = "Fail",
 185         [PVR2_CVAL_HSM_HIGH] = "High",
 186         [PVR2_CVAL_HSM_FULL] = "Full",
 187 };
 188
 189
 190 static const char *control_values_subsystem[] = {
 191         [PVR2_SUBSYS_B_ENC_FIRMWARE]  = "enc_firmware",
 192         [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
 193         [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
 194         [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
 195         [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
 196 };
 197
 198
 199 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 200 {
 201         struct pvr2_hdw *hdw = cptr->hdw;
 202         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 203                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 204         } else {
 205                 *vp = 0;
 206         }
 207         return 0;
 208 }
 209
 210 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 211 {
 212         struct pvr2_hdw *hdw = cptr->hdw;
 213         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 214                 hdw->freqTable[hdw->freqProgSlot-1] = v;
 215         }
 216         return 0;
 217 }
 218
 219 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 220 {
 221         *vp = cptr->hdw->freqProgSlot;
 222         return 0;
 223 }
 224
 225 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 226 {
 227         struct pvr2_hdw *hdw = cptr->hdw;
 228         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 229                 hdw->freqProgSlot = v;
 230         }
 231         return 0;
 232 }
 233
 234 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 235 {
 236         *vp = cptr->hdw->freqSlot;
 237         return 0;
 238 }
 239
 240 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
 241 {
 242         unsigned freq = 0;
 243         struct pvr2_hdw *hdw = cptr->hdw;
 244         hdw->freqSlot = v;
 245         if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
 246                 freq = hdw->freqTable[hdw->freqSlot-1];
 247         }
 248         if (freq && (freq != hdw->freqVal)) {
 249                 hdw->freqVal = freq;
 250                 hdw->freqDirty = !0;
 251         }
 252         return 0;
 253 }
 254
 255 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 256 {
 257         *vp = cptr->hdw->freqVal;
 258         return 0;
 259 }
 260
 261 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 262 {
 263         return cptr->hdw->freqDirty != 0;
 264 }
 265
 266 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 267 {
 268         cptr->hdw->freqDirty = 0;
 269 }
 270
 271 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 272 {
 273         struct pvr2_hdw *hdw = cptr->hdw;
 274         hdw->freqVal = v;
 275         hdw->freqDirty = !0;
 276         hdw->freqSlot = 0;
 277         return 0;
 278 }
 279
 280 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 281 {
 282         *vp = cptr->hdw->flag_streaming_enabled;
 283         return 0;
 284 }
 285
 286 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 287 {
 288         int result = pvr2_hdw_is_hsm(cptr->hdw);
 289         *vp = PVR2_CVAL_HSM_FULL;
 290         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 291         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 292         return 0;
 293 }
 294
 295 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 296 {
 297         *vp = cptr->hdw->std_mask_avail;
 298         return 0;
 299 }
 300
 301 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 302 {
 303         struct pvr2_hdw *hdw = cptr->hdw;
 304         v4l2_std_id ns;
 305         ns = hdw->std_mask_avail;
 306         ns = (ns & ~m) | (v & m);
 307         if (ns == hdw->std_mask_avail) return 0;
 308         hdw->std_mask_avail = ns;
 309         pvr2_hdw_internal_set_std_avail(hdw);
 310         pvr2_hdw_internal_find_stdenum(hdw);
 311         return 0;
 312 }
 313
 314 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 315                                char *bufPtr,unsigned int bufSize,
 316                                unsigned int *len)
 317 {
 318         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 319         return 0;
 320 }
 321
 322 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 323                                const char *bufPtr,unsigned int bufSize,
 324                                int *mskp,int *valp)
 325 {
 326         int ret;
 327         v4l2_std_id id;
 328         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 329         if (ret < 0) return ret;
 330         if (mskp) *mskp = id;
 331         if (valp) *valp = id;
 332         return 0;
 333 }
 334
 335 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 336 {
 337         *vp = cptr->hdw->std_mask_cur;
 338         return 0;
 339 }
 340
 341 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 342 {
 343         struct pvr2_hdw *hdw = cptr->hdw;
 344         v4l2_std_id ns;
 345         ns = hdw->std_mask_cur;
 346         ns = (ns & ~m) | (v & m);
 347         if (ns == hdw->std_mask_cur) return 0;
 348         hdw->std_mask_cur = ns;
 349         hdw->std_dirty = !0;
 350         pvr2_hdw_internal_find_stdenum(hdw);
 351         return 0;
 352 }
 353
 354 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 355 {
 356         return cptr->hdw->std_dirty != 0;
 357 }
 358
 359 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 360 {
 361         cptr->hdw->std_dirty = 0;
 362 }
 363
 364 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 365 {
 366         *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
 367                 PVR2_SIGNAL_OK) ? 1 : 0);
 368         return 0;
 369 }
 370
 371 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
 372 {
 373         *vp = cptr->hdw->subsys_enabled_mask;
 374         return 0;
 375 }
 376
 377 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
 378 {
 379         pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
 380         return 0;
 381 }
 382
 383 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
 384 {
 385         *vp = cptr->hdw->subsys_stream_mask;
 386         return 0;
 387 }
 388
 389 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
 390 {
 391         pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
 392         return 0;
 393 }
 394
 395 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 396 {
 397         struct pvr2_hdw *hdw = cptr->hdw;
 398         if (v < 0) return -EINVAL;
 399         if (v > hdw->std_enum_cnt) return -EINVAL;
 400         hdw->std_enum_cur = v;
 401         if (!v) return 0;
 402         v--;
 403         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 404         hdw->std_mask_cur = hdw->std_defs[v].id;
 405         hdw->std_dirty = !0;
 406         return 0;
 407 }
 408
 409
 410 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 411 {
 412         *vp = cptr->hdw->std_enum_cur;
 413         return 0;
 414 }
 415
 416
 417 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 418 {
 419         return cptr->hdw->std_dirty != 0;
 420 }
 421
 422
 423 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 424 {
 425         cptr->hdw->std_dirty = 0;
 426 }
 427
 428
 429 #define DEFINT(vmin,vmax) \
 430         .type = pvr2_ctl_int, \
 431         .def.type_int.min_value = vmin, \
 432         .def.type_int.max_value = vmax
 433
 434 #define DEFENUM(tab) \
 435         .type = pvr2_ctl_enum, \
 436         .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
 437         .def.type_enum.value_names = tab
 438
 439 #define DEFBOOL \
 440         .type = pvr2_ctl_bool
 441
 442 #define DEFMASK(msk,tab) \
 443         .type = pvr2_ctl_bitmask, \
 444         .def.type_bitmask.valid_bits = msk, \
 445         .def.type_bitmask.bit_names = tab
 446
 447 #define DEFREF(vname) \
 448         .set_value = ctrl_set_##vname, \
 449         .get_value = ctrl_get_##vname, \
 450         .is_dirty = ctrl_isdirty_##vname, \
 451         .clear_dirty = ctrl_cleardirty_##vname
 452
 453
 454 #define VCREATE_FUNCS(vname) \
 455 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 456 {*vp = cptr->hdw->vname##_val; return 0;} \
 457 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 458 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 459 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 460 {return cptr->hdw->vname##_dirty != 0;} \
 461 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 462 {cptr->hdw->vname##_dirty = 0;}
 463
 464 VCREATE_FUNCS(brightness)
 465 VCREATE_FUNCS(contrast)
 466 VCREATE_FUNCS(saturation)
 467 VCREATE_FUNCS(hue)
 468 VCREATE_FUNCS(volume)
 469 VCREATE_FUNCS(balance)
 470 VCREATE_FUNCS(bass)
 471 VCREATE_FUNCS(treble)
 472 VCREATE_FUNCS(mute)
 473 VCREATE_FUNCS(input)
 474 VCREATE_FUNCS(audiomode)
 475 VCREATE_FUNCS(res_hor)
 476 VCREATE_FUNCS(res_ver)
 477 VCREATE_FUNCS(srate)
 478 VCREATE_FUNCS(audiobitrate)
 479 VCREATE_FUNCS(audiocrc)
 480 VCREATE_FUNCS(audioemphasis)
 481 VCREATE_FUNCS(vbr)
 482 VCREATE_FUNCS(videobitrate)
 483 VCREATE_FUNCS(videopeak)
 484 VCREATE_FUNCS(interlace)
 485 VCREATE_FUNCS(audiolayer)
 486
 487 #define MIN_FREQ 55250000L
 488 #define MAX_FREQ 850000000L
 489
 490 /* Table definition of all controls which can be manipulated */
 491 static const struct pvr2_ctl_info control_defs[] = {
 492         {
 493                 .v4l_id = V4L2_CID_BRIGHTNESS,
 494                 .desc = "Brightness",
 495                 .name = "brightness",
 496                 .default_value = 128,
 497                 DEFREF(brightness),
 498                 DEFINT(0,255),
 499         },{
 500                 .v4l_id = V4L2_CID_CONTRAST,
 501                 .desc = "Contrast",
 502                 .name = "contrast",
 503                 .default_value = 68,
 504                 DEFREF(contrast),
 505                 DEFINT(0,127),
 506         },{
 507                 .v4l_id = V4L2_CID_SATURATION,
 508                 .desc = "Saturation",
 509                 .name = "saturation",
 510                 .default_value = 64,
 511                 DEFREF(saturation),
 512                 DEFINT(0,127),
 513         },{
 514                 .v4l_id = V4L2_CID_HUE,
 515                 .desc = "Hue",
 516                 .name = "hue",
 517                 .default_value = 0,
 518                 DEFREF(hue),
 519                 DEFINT(-128,127),
 520         },{
 521                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 522                 .desc = "Volume",
 523                 .name = "volume",
 524                 .default_value = 65535,
 525                 DEFREF(volume),
 526                 DEFINT(0,65535),
 527         },{
 528                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 529                 .desc = "Balance",
 530                 .name = "balance",
 531                 .default_value = 0,
 532                 DEFREF(balance),
 533                 DEFINT(-32768,32767),
 534         },{
 535                 .v4l_id = V4L2_CID_AUDIO_BASS,
 536                 .desc = "Bass",
 537                 .name = "bass",
 538                 .default_value = 0,
 539                 DEFREF(bass),
 540                 DEFINT(-32768,32767),
 541         },{
 542                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 543                 .desc = "Treble",
 544                 .name = "treble",
 545                 .default_value = 0,
 546                 DEFREF(treble),
 547                 DEFINT(-32768,32767),
 548         },{
 549                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 550                 .desc = "Mute",
 551                 .name = "mute",
 552                 .default_value = 0,
 553                 DEFREF(mute),
 554                 DEFBOOL,
 555         },{
 556                 .desc = "Video Source",
 557                 .name = "input",
 558                 .internal_id = PVR2_CID_INPUT,
 559                 .default_value = PVR2_CVAL_INPUT_TV,
 560                 DEFREF(input),
 561                 DEFENUM(control_values_input),
 562         },{
 563                 .desc = "Audio Mode",
 564                 .name = "audio_mode",
 565                 .internal_id = PVR2_CID_AUDIOMODE,
 566                 .default_value = V4L2_TUNER_MODE_STEREO,
 567                 DEFREF(audiomode),
 568                 DEFENUM(control_values_audiomode),
 569         },{
 570                 .desc = "Horizontal capture resolution",
 571                 .name = "resolution_hor",
 572                 .internal_id = PVR2_CID_HRES,
 573                 .default_value = 720,
 574                 DEFREF(res_hor),
 575                 DEFINT(320,720),
 576         },{
 577                 .desc = "Vertical capture resolution",
 578                 .name = "resolution_ver",
 579                 .internal_id = PVR2_CID_VRES,
 580                 .default_value = 480,
 581                 DEFREF(res_ver),
 582                 DEFINT(200,625),
 583         },{
 584                 .v4l_id = V4L2_CID_PVR_SRATE,
 585                 .desc = "Sample rate",
 586                 .name = "srate",
 587                 .default_value = PVR2_CVAL_SRATE_48,
 588                 DEFREF(srate),
 589                 DEFENUM(control_values_srate),
 590         },{
 591                 .v4l_id = V4L2_CID_PVR_AUDIOBITRATE,
 592                 .desc = "Audio Bitrate",
 593                 .name = "audio_bitrate",
 594                 .default_value = PVR2_CVAL_AUDIOBITRATE_224,
 595                 DEFREF(audiobitrate),
 596                 DEFENUM(control_values_audiobitrate),
 597         },{
 598                 .v4l_id = V4L2_CID_PVR_AUDIOCRC,
 599                 .desc = "Audio CRC",
 600                 .name = "audio_crc",
 601                 .default_value = 1,
 602                 DEFREF(audiocrc),
 603                 DEFBOOL,
 604         },{
 605                 .v4l_id = V4L2_CID_PVR_AUDIOEMPHASIS,
 606                 .desc = "Audio Emphasis",
 607                 .name = "audio_emphasis",
 608                 .default_value = PVR2_CVAL_AUDIOEMPHASIS_NONE,
 609                 DEFREF(audioemphasis),
 610                 DEFENUM(control_values_audioemphasis),
 611         },{
 612                 .v4l_id = V4L2_CID_PVR_VBR,
 613                 .desc = "Variable video bitrate",
 614                 .name = "vbr",
 615                 .default_value = 0,
 616                 DEFREF(vbr),
 617                 DEFBOOL,
 618         },{
 619                 .v4l_id = V4L2_CID_PVR_VIDEOBITRATE,
 620                 .desc = "Average video bitrate",
 621                 .name = "video_average_bitrate",
 622                 .default_value = 6000000,
 623                 DEFREF(videobitrate),
 624                 DEFINT(500000,20000000),
 625         },{
 626                 .v4l_id = V4L2_CID_PVR_VIDEOPEAK,
 627                 .desc = "Peak video bitrate",
 628                 .name = "video_peak_bitrate",
 629                 .default_value = 6000000,
 630                 DEFREF(videopeak),
 631                 DEFINT(500000,20000000),
 632         },{
 633                 .desc = "Interlace mode",
 634                 .name = "interlace",
 635                 .internal_id = PVR2_CID_INTERLACE,
 636                 .default_value = 0,
 637                 DEFREF(interlace),
 638                 DEFBOOL,
 639         },{
 640                 .desc = "Audio Layer",
 641                 .name = "audio_layer",
 642                 .default_value = 2,
 643                 DEFREF(audiolayer),
 644                 DEFINT(0,3),
 645         },{
 646                 .desc = "Tuner Frequency (Hz)",
 647                 .name = "frequency",
 648                 .internal_id = PVR2_CID_FREQUENCY,
 649                 .default_value = 175250000L,
 650                 .set_value = ctrl_freq_set,
 651                 .get_value = ctrl_freq_get,
 652                 .is_dirty = ctrl_freq_is_dirty,
 653                 .clear_dirty = ctrl_freq_clear_dirty,
 654                 DEFINT(MIN_FREQ,MAX_FREQ),
 655         },{
 656                 .desc = "Channel",
 657                 .name = "channel",
 658                 .set_value = ctrl_channel_set,
 659                 .get_value = ctrl_channel_get,
 660                 DEFINT(0,FREQTABLE_SIZE),
 661         },{
 662                 .desc = "Channel Program Frequency",
 663                 .name = "freq_table_value",
 664                 .set_value = ctrl_channelfreq_set,
 665                 .get_value = ctrl_channelfreq_get,
 666                 DEFINT(MIN_FREQ,MAX_FREQ),
 667         },{
 668                 .desc = "Channel Program ID",
 669                 .name = "freq_table_channel",
 670                 .set_value = ctrl_channelprog_set,
 671                 .get_value = ctrl_channelprog_get,
 672                 DEFINT(0,FREQTABLE_SIZE),
 673         },{
 674                 .desc = "Streaming Enabled",
 675                 .name = "streaming_enabled",
 676                 .get_value = ctrl_streamingenabled_get,
 677                 DEFBOOL,
 678         },{
 679                 .desc = "USB Speed",
 680                 .name = "usb_speed",
 681                 .get_value = ctrl_hsm_get,
 682                 DEFENUM(control_values_hsm),
 683         },{
 684                 .desc = "Signal Present",
 685                 .name = "signal_present",
 686                 .get_value = ctrl_signal_get,
 687                 DEFBOOL,
 688         },{
 689                 .desc = "Video Standards Available Mask",
 690                 .name = "video_standard_mask_available",
 691                 .internal_id = PVR2_CID_STDAVAIL,
 692                 .skip_init = !0,
 693                 .get_value = ctrl_stdavail_get,
 694                 .set_value = ctrl_stdavail_set,
 695                 .val_to_sym = ctrl_std_val_to_sym,
 696                 .sym_to_val = ctrl_std_sym_to_val,
 697                 .type = pvr2_ctl_bitmask,
 698         },{
 699                 .desc = "Video Standards In Use Mask",
 700                 .name = "video_standard_mask_active",
 701                 .internal_id = PVR2_CID_STDCUR,
 702                 .skip_init = !0,
 703                 .get_value = ctrl_stdcur_get,
 704                 .set_value = ctrl_stdcur_set,
 705                 .is_dirty = ctrl_stdcur_is_dirty,
 706                 .clear_dirty = ctrl_stdcur_clear_dirty,
 707                 .val_to_sym = ctrl_std_val_to_sym,
 708                 .sym_to_val = ctrl_std_sym_to_val,
 709                 .type = pvr2_ctl_bitmask,
 710         },{
 711                 .desc = "Subsystem enabled mask",
 712                 .name = "debug_subsys_mask",
 713                 .skip_init = !0,
 714                 .get_value = ctrl_subsys_get,
 715                 .set_value = ctrl_subsys_set,
 716                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 717         },{
 718                 .desc = "Subsystem stream mask",
 719                 .name = "debug_subsys_stream_mask",
 720                 .skip_init = !0,
 721                 .get_value = ctrl_subsys_stream_get,
 722                 .set_value = ctrl_subsys_stream_set,
 723                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 724         },{
 725                 .desc = "Video Standard Name",
 726                 .name = "video_standard",
 727                 .internal_id = PVR2_CID_STDENUM,
 728                 .skip_init = !0,
 729                 .get_value = ctrl_stdenumcur_get,
 730                 .set_value = ctrl_stdenumcur_set,
 731                 .is_dirty = ctrl_stdenumcur_is_dirty,
 732                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 733                 .type = pvr2_ctl_enum,
 734         }
 735 };
 736
 737 #define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
 738
 739
 740 const char *pvr2_config_get_name(enum pvr2_config cfg)
 741 {
 742         switch (cfg) {
 743         case pvr2_config_empty: return "empty";
 744         case pvr2_config_mpeg: return "mpeg";
 745         case pvr2_config_vbi: return "vbi";
 746         case pvr2_config_radio: return "radio";
 747         }
 748         return "<unknown>";
 749 }
 750
 751
 752 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
 753 {
 754         return hdw->usb_dev;
 755 }
 756
 757
 758 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
 759 {
 760         return hdw->serial_number;
 761 }
 762
 763
 764 struct pvr2_hdw *pvr2_hdw_find(int unit_number)
 765 {
 766         if (unit_number < 0) return 0;
 767         if (unit_number >= PVR_NUM) return 0;
 768         return unit_pointers[unit_number];
 769 }
 770
 771
 772 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
 773 {
 774         return hdw->unit_number;
 775 }
 776
 777
 778 /* Attempt to locate one of the given set of files.  Messages are logged
 779    appropriate to what has been found.  The return value will be 0 or
 780    greater on success (it will be the index of the file name found) and
 781    fw_entry will be filled in.  Otherwise a negative error is returned on
 782    failure.  If the return value is -ENOENT then no viable firmware file
 783    could be located. */
 784 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
 785                                 const struct firmware **fw_entry,
 786                                 const char *fwtypename,
 787                                 unsigned int fwcount,
 788                                 const char *fwnames[])
 789 {
 790         unsigned int idx;
 791         int ret = -EINVAL;
 792         for (idx = 0; idx < fwcount; idx++) {
 793                 ret = request_firmware(fw_entry,
 794                                        fwnames[idx],
 795                                        &hdw->usb_dev->dev);
 796                 if (!ret) {
 797                         trace_firmware("Located %s firmware: %s;"
 798                                        " uploading...",
 799                                        fwtypename,
 800                                        fwnames[idx]);
 801                         return idx;
 802                 }
 803                 if (ret == -ENOENT) continue;
 804                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 805                            "request_firmware fatal error with code=%d",ret);
 806                 return ret;
 807         }
 808         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 809                    "***WARNING***"
 810                    " Device %s firmware"
 811                    " seems to be missing.",
 812                    fwtypename);
 813         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 814                    "Did you install the pvrusb2 firmware files"
 815                    " in their proper location?");
 816         if (fwcount == 1) {
 817                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 818                            "request_firmware unable to locate %s file %s",
 819                            fwtypename,fwnames[0]);
 820         } else {
 821                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 822                            "request_firmware unable to locate"
 823                            " one of the following %s files:",
 824                            fwtypename);
 825                 for (idx = 0; idx < fwcount; idx++) {
 826                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 827                                    "request_firmware: Failed to find %s",
 828                                    fwnames[idx]);
 829                 }
 830         }
 831         return ret;
 832 }
 833
 834
 835 /*
 836  * pvr2_upload_firmware1().
 837  *
 838  * Send the 8051 firmware to the device.  After the upload, arrange for
 839  * device to re-enumerate.
 840  *
 841  * NOTE : the pointer to the firmware data given by request_firmware()
 842  * is not suitable for an usb transaction.
 843  *
 844  */
 845 int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
 846 {
 847         const struct firmware *fw_entry = 0;
 848         void  *fw_ptr;
 849         unsigned int pipe;
 850         int ret;
 851         u16 address;
 852         static const char *fw_files_29xxx[] = {
 853                 "v4l-pvrusb2-29xxx-01.fw",
 854         };
 855 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 856         static const char *fw_files_24xxx[] = {
 857                 "v4l-pvrusb2-24xxx-01.fw",
 858         };
 859 #endif
 860         static const struct pvr2_string_table fw_file_defs[] = {
 861                 [PVR2_HDW_TYPE_29XXX] = {
 862                         fw_files_29xxx,
 863                         sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
 864                 },
 865 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 866                 [PVR2_HDW_TYPE_24XXX] = {
 867                         fw_files_24xxx,
 868                         sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
 869                 },
 870 #endif
 871         };
 872         hdw->fw1_state = FW1_STATE_FAILED; // default result
 873
 874         trace_firmware("pvr2_upload_firmware1");
 875
 876         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
 877                                    fw_file_defs[hdw->hdw_type].cnt,
 878                                    fw_file_defs[hdw->hdw_type].lst);
 879         if (ret < 0) {
 880                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
 881                 return ret;
 882         }
 883
 884         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
 885         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
 886
 887         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
 888
 889         if (fw_entry->size != 0x2000){
 890                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
 891                 release_firmware(fw_entry);
 892                 return -ENOMEM;
 893         }
 894
 895         fw_ptr = kmalloc(0x800, GFP_KERNEL);
 896         if (fw_ptr == NULL){
 897                 release_firmware(fw_entry);
 898                 return -ENOMEM;
 899         }
 900
 901         /* We have to hold the CPU during firmware upload. */
 902         pvr2_hdw_cpureset_assert(hdw,1);
 903
 904         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
 905            chunk. */
 906
 907         ret = 0;
 908         for(address = 0; address < fw_entry->size; address += 0x800) {
 909                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
 910                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
 911                                        0, fw_ptr, 0x800, HZ);
 912         }
 913
 914         trace_firmware("Upload done, releasing device's CPU");
 915
 916         /* Now release the CPU.  It will disconnect and reconnect later. */
 917         pvr2_hdw_cpureset_assert(hdw,0);
 918
 919         kfree(fw_ptr);
 920         release_firmware(fw_entry);
 921
 922         trace_firmware("Upload done (%d bytes sent)",ret);
 923
 924         /* We should have written 8192 bytes */
 925         if (ret == 8192) {
 926                 hdw->fw1_state = FW1_STATE_RELOAD;
 927                 return 0;
 928         }
 929
 930         return -EIO;
 931 }
 932
 933
 934 /*
 935  * pvr2_upload_firmware2()
 936  *
 937  * This uploads encoder firmware on endpoint 2.
 938  *
 939  */
 940
 941 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
 942 {
 943         const struct firmware *fw_entry = 0;
 944         void  *fw_ptr;
 945         unsigned int pipe, fw_len, fw_done;
 946         int actual_length;
 947         int ret = 0;
 948         int fwidx;
 949         static const char *fw_files[] = {
 950                 CX2341X_FIRM_ENC_FILENAME,
 951         };
 952
 953         trace_firmware("pvr2_upload_firmware2");
 954
 955         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
 956                                    sizeof(fw_files)/sizeof(fw_files[0]),
 957                                    fw_files);
 958         if (ret < 0) return ret;
 959         fwidx = ret;
 960         ret = 0;
 961
 962         /* First prepare firmware loading */
 963         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
 964         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
 965         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
 966         ret |= pvr2_hdw_cmd_deep_reset(hdw);
 967         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
 968         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
 969         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
 970         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
 971         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
 972         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
 973         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
 974         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
 975         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
 976         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
 977         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
 978         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
 979         ret |= pvr2_write_u8(hdw, 0x52, 0);
 980         ret |= pvr2_write_u16(hdw, 0x0600, 0);
 981
 982         if (ret) {
 983                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 984                            "firmware2 upload prep failed, ret=%d",ret);
 985                 release_firmware(fw_entry);
 986                 return ret;
 987         }
 988
 989         /* Now send firmware */
 990
 991         fw_len = fw_entry->size;
 992
 993         if (fw_len % FIRMWARE_CHUNK_SIZE) {
 994                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 995                            "size of %s firmware"
 996                            " must be a multiple of 8192B",
 997                            fw_files[fwidx]);
 998                 release_firmware(fw_entry);
 999                 return -1;
1000         }
1001
1002         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1003         if (fw_ptr == NULL){
1004                 release_firmware(fw_entry);
1005                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1006                            "failed to allocate memory for firmware2 upload");
1007                 return -ENOMEM;
1008         }
1009
1010         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1011
1012         for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1013              fw_done += FIRMWARE_CHUNK_SIZE ) {
1014                 int i;
1015                 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1016                 /* Usbsnoop log  shows that we must swap bytes... */
1017                 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1018                         ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1019
1020                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1021                                     FIRMWARE_CHUNK_SIZE,
1022                                     &actual_length, HZ);
1023                 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1024         }
1025
1026         trace_firmware("upload of %s : %i / %i ",
1027                        fw_files[fwidx],fw_done,fw_len);
1028
1029         kfree(fw_ptr);
1030         release_firmware(fw_entry);
1031
1032         if (ret) {
1033                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1034                            "firmware2 upload transfer failure");
1035                 return ret;
1036         }
1037
1038         /* Finish upload */
1039
1040         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1041         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1042         ret |= pvr2_write_u16(hdw, 0x0600, 0);
1043
1044         if (ret) {
1045                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1046                            "firmware2 upload post-proc failure");
1047         } else {
1048                 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1049         }
1050         return ret;
1051 }
1052
1053
1054 #define FIRMWARE_RECOVERY_BITS \
1055         ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1056          (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1057          (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1058          (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1059
1060 /*
1061
1062   This single function is key to pretty much everything.  The pvrusb2
1063   device can logically be viewed as a series of subsystems which can be
1064   stopped / started or unconfigured / configured.  To get things streaming,
1065   one must configure everything and start everything, but there may be
1066   various reasons over time to deconfigure something or stop something.
1067   This function handles all of this activity.  Everything EVERYWHERE that
1068   must affect a subsystem eventually comes here to do the work.
1069
1070   The current state of all subsystems is represented by a single bit mask,
1071   known as subsys_enabled_mask.  The bit positions are defined by the
1072   PVR2_SUBSYS_xxxx macros, with one subsystem per bit position.  At any
1073   time the set of configured or active subsystems can be queried just by
1074   looking at that mask.  To change bits in that mask, this function here
1075   must be called.  The "msk" argument indicates which bit positions to
1076   change, and the "val" argument defines the new values for the positions
1077   defined by "msk".
1078
1079   There is a priority ordering of starting / stopping things, and for
1080   multiple requested changes, this function implements that ordering.
1081   (Thus we will act on a request to load encoder firmware before we
1082   configure the encoder.)  In addition to priority ordering, there is a
1083   recovery strategy implemented here.  If a particular step fails and we
1084   detect that failure, this function will clear the affected subsystem bits
1085   and restart.  Thus we have a means for recovering from a dead encoder:
1086   Clear all bits that correspond to subsystems that we need to restart /
1087   reconfigure and start over.
1088
1089 */
1090 void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1091                                      unsigned long msk,unsigned long val)
1092 {
1093         unsigned long nmsk;
1094         unsigned long vmsk;
1095         int ret;
1096         unsigned int tryCount = 0;
1097
1098         if (!hdw->flag_ok) return;
1099
1100         msk &= PVR2_SUBSYS_ALL;
1101
1102         for (;;) {
1103                 tryCount++;
1104                 vmsk = hdw->subsys_enabled_mask & PVR2_SUBSYS_ALL;
1105                 nmsk = (vmsk & ~msk) | (val & msk);
1106                 if (!(nmsk ^ vmsk)) break;
1107                 if (tryCount > 4) {
1108                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1109                                    "Too many retries when configuring device;"
1110                                    " giving up");
1111                         pvr2_hdw_render_useless(hdw);
1112                         break;
1113                 }
1114                 if (tryCount > 1) {
1115                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1116                                    "Retrying device reconfiguration");
1117                 }
1118                 pvr2_trace(PVR2_TRACE_INIT,
1119                            "subsys mask changing 0x%lx:0x%lx"
1120                            " from 0x%lx to 0x%lx",
1121                            msk,val,hdw->subsys_enabled_mask,nmsk);
1122
1123                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1124                         hdw->subsys_enabled_mask;
1125                 if (vmsk) {
1126                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1127                                 pvr2_trace(PVR2_TRACE_CTL,
1128                                            "/*---TRACE_CTL----*/"
1129                                            " pvr2_encoder_stop");
1130                                 ret = pvr2_encoder_stop(hdw);
1131                                 if (ret) {
1132                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1133                                                    "Error recovery initiated");
1134                                         hdw->subsys_enabled_mask &=
1135                                                 ~FIRMWARE_RECOVERY_BITS;
1136                                         continue;
1137                                 }
1138                         }
1139                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1140                                 pvr2_trace(PVR2_TRACE_CTL,
1141                                            "/*---TRACE_CTL----*/"
1142                                            " pvr2_hdw_cmd_usbstream(0)");
1143                                 pvr2_hdw_cmd_usbstream(hdw,0);
1144                         }
1145                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1146                                 pvr2_trace(PVR2_TRACE_CTL,
1147                                            "/*---TRACE_CTL----*/"
1148                                            " decoder disable");
1149                                 if (hdw->decoder_ctrl) {
1150                                         hdw->decoder_ctrl->enable(
1151                                                 hdw->decoder_ctrl->ctxt,0);
1152                                 } else {
1153                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1154                                                    "WARNING:"
1155                                                    " No decoder present");
1156                                 }
1157                                 hdw->subsys_enabled_mask &=
1158                                         ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1159                         }
1160                         if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1161                                 hdw->subsys_enabled_mask &=
1162                                         ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1163                         }
1164                 }
1165                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1166                 if (vmsk) {
1167                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1168                                 pvr2_trace(PVR2_TRACE_CTL,
1169                                            "/*---TRACE_CTL----*/"
1170                                            " pvr2_upload_firmware2");
1171                                 ret = pvr2_upload_firmware2(hdw);
1172                                 if (ret) {
1173                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1174                                                    "Failure uploading encoder"
1175                                                    " firmware");
1176                                         pvr2_hdw_render_useless(hdw);
1177                                         break;
1178                                 }
1179                         }
1180                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1181                                 pvr2_trace(PVR2_TRACE_CTL,
1182                                            "/*---TRACE_CTL----*/"
1183                                            " pvr2_encoder_configure");
1184                                 ret = pvr2_encoder_configure(hdw);
1185                                 if (ret) {
1186                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1187                                                    "Error recovery initiated");
1188                                         hdw->subsys_enabled_mask &=
1189                                                 ~FIRMWARE_RECOVERY_BITS;
1190                                         continue;
1191                                 }
1192                         }
1193                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1194                                 pvr2_trace(PVR2_TRACE_CTL,
1195                                            "/*---TRACE_CTL----*/"
1196                                            " decoder enable");
1197                                 if (hdw->decoder_ctrl) {
1198                                         hdw->decoder_ctrl->enable(
1199                                                 hdw->decoder_ctrl->ctxt,!0);
1200                                 } else {
1201                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1202                                                    "WARNING:"
1203                                                    " No decoder present");
1204                                 }
1205                                 hdw->subsys_enabled_mask |=
1206                                         (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1207                         }
1208                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1209                                 pvr2_trace(PVR2_TRACE_CTL,
1210                                            "/*---TRACE_CTL----*/"
1211                                            " pvr2_hdw_cmd_usbstream(1)");
1212                                 pvr2_hdw_cmd_usbstream(hdw,!0);
1213                         }
1214                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1215                                 pvr2_trace(PVR2_TRACE_CTL,
1216                                            "/*---TRACE_CTL----*/"
1217                                            " pvr2_encoder_start");
1218                                 ret = pvr2_encoder_start(hdw);
1219                                 if (ret) {
1220                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1221                                                    "Error recovery initiated");
1222                                         hdw->subsys_enabled_mask &=
1223                                                 ~FIRMWARE_RECOVERY_BITS;
1224                                         continue;
1225                                 }
1226                         }
1227                 }
1228         }
1229 }
1230
1231
1232 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1233                              unsigned long msk,unsigned long val)
1234 {
1235         LOCK_TAKE(hdw->big_lock); do {
1236                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1237         } while (0); LOCK_GIVE(hdw->big_lock);
1238 }
1239
1240
1241 void pvr2_hdw_subsys_bit_set(struct pvr2_hdw *hdw,unsigned long msk)
1242 {
1243         pvr2_hdw_subsys_bit_chg(hdw,msk,msk);
1244 }
1245
1246
1247 void pvr2_hdw_subsys_bit_clr(struct pvr2_hdw *hdw,unsigned long msk)
1248 {
1249         pvr2_hdw_subsys_bit_chg(hdw,msk,0);
1250 }
1251
1252
1253 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1254 {
1255         return hdw->subsys_enabled_mask;
1256 }
1257
1258
1259 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1260 {
1261         return hdw->subsys_stream_mask;
1262 }
1263
1264
1265 void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1266                                             unsigned long msk,
1267                                             unsigned long val)
1268 {
1269         unsigned long val2;
1270         msk &= PVR2_SUBSYS_ALL;
1271         val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1272         pvr2_trace(PVR2_TRACE_INIT,
1273                    "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1274                    msk,val,hdw->subsys_stream_mask,val2);
1275         hdw->subsys_stream_mask = val2;
1276 }
1277
1278
1279 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1280                                     unsigned long msk,
1281                                     unsigned long val)
1282 {
1283         LOCK_TAKE(hdw->big_lock); do {
1284                 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1285         } while (0); LOCK_GIVE(hdw->big_lock);
1286 }
1287
1288
1289 int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1290 {
1291         if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1292         if (enableFl) {
1293                 pvr2_trace(PVR2_TRACE_START_STOP,
1294                            "/*--TRACE_STREAM--*/ enable");
1295                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1296         } else {
1297                 pvr2_trace(PVR2_TRACE_START_STOP,
1298                            "/*--TRACE_STREAM--*/ disable");
1299                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1300         }
1301         if (!hdw->flag_ok) return -EIO;
1302         hdw->flag_streaming_enabled = enableFl != 0;
1303         return 0;
1304 }
1305
1306
1307 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1308 {
1309         return hdw->flag_streaming_enabled != 0;
1310 }
1311
1312
1313 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1314 {
1315         int ret;
1316         LOCK_TAKE(hdw->big_lock); do {
1317                 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1318         } while (0); LOCK_GIVE(hdw->big_lock);
1319         return ret;
1320 }
1321
1322
1323 int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1324                                      enum pvr2_config config)
1325 {
1326         unsigned long sm = hdw->subsys_enabled_mask;
1327         if (!hdw->flag_ok) return -EIO;
1328         pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1329         hdw->config = config;
1330         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1331         return 0;
1332 }
1333
1334
1335 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1336 {
1337         int ret;
1338         if (!hdw->flag_ok) return -EIO;
1339         LOCK_TAKE(hdw->big_lock);
1340         ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1341         LOCK_GIVE(hdw->big_lock);
1342         return ret;
1343 }
1344
1345
1346 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1347 {
1348         int unit_number = hdw->unit_number;
1349         int tp = -1;
1350         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1351                 tp = tuner[unit_number];
1352         }
1353         if (tp < 0) return -EINVAL;
1354         hdw->tuner_type = tp;
1355         return 0;
1356 }
1357
1358
1359 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1360 {
1361         int unit_number = hdw->unit_number;
1362         int tp = 0;
1363         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1364                 tp = video_std[unit_number];
1365         }
1366         return tp;
1367 }
1368
1369
1370 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1371 {
1372         int unit_number = hdw->unit_number;
1373         int tp = 0;
1374         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1375                 tp = tolerance[unit_number];
1376         }
1377         return tp;
1378 }
1379
1380
1381 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1382 {
1383         /* Try a harmless request to fetch the eeprom's address over
1384            endpoint 1.  See what happens.  Only the full FX2 image can
1385            respond to this.  If this probe fails then likely the FX2
1386            firmware needs be loaded. */
1387         int result;
1388         LOCK_TAKE(hdw->ctl_lock); do {
1389                 hdw->cmd_buffer[0] = 0xeb;
1390                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1391                                            hdw->cmd_buffer,1,
1392                                            hdw->cmd_buffer,1);
1393                 if (result < 0) break;
1394         } while(0); LOCK_GIVE(hdw->ctl_lock);
1395         if (result) {
1396                 pvr2_trace(PVR2_TRACE_INIT,
1397                            "Probe of device endpoint 1 result status %d",
1398                            result);
1399         } else {
1400                 pvr2_trace(PVR2_TRACE_INIT,
1401                            "Probe of device endpoint 1 succeeded");
1402         }
1403         return result == 0;
1404 }
1405
1406 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1407 {
1408         char buf[40];
1409         unsigned int bcnt;
1410         v4l2_std_id std1,std2;
1411
1412         std1 = get_default_standard(hdw);
1413
1414         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1415         pvr2_trace(PVR2_TRACE_INIT,
1416                    "Supported video standard(s) reported by eeprom: %.*s",
1417                    bcnt,buf);
1418
1419         hdw->std_mask_avail = hdw->std_mask_eeprom;
1420
1421         std2 = std1 & ~hdw->std_mask_avail;
1422         if (std2) {
1423                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1424                 pvr2_trace(PVR2_TRACE_INIT,
1425                            "Expanding supported video standards"
1426                            " to include: %.*s",
1427                            bcnt,buf);
1428                 hdw->std_mask_avail |= std2;
1429         }
1430
1431         pvr2_hdw_internal_set_std_avail(hdw);
1432
1433         if (std1) {
1434                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1435                 pvr2_trace(PVR2_TRACE_INIT,
1436                            "Initial video standard forced to %.*s",
1437                            bcnt,buf);
1438                 hdw->std_mask_cur = std1;
1439                 hdw->std_dirty = !0;
1440                 pvr2_hdw_internal_find_stdenum(hdw);
1441                 return;
1442         }
1443
1444         if (hdw->std_enum_cnt > 1) {
1445                 // Autoselect the first listed standard
1446                 hdw->std_enum_cur = 1;
1447                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1448                 hdw->std_dirty = !0;
1449                 pvr2_trace(PVR2_TRACE_INIT,
1450                            "Initial video standard auto-selected to %s",
1451                            hdw->std_defs[hdw->std_enum_cur-1].name);
1452                 return;
1453         }
1454
1455         pvr2_trace(PVR2_TRACE_EEPROM,
1456                    "Unable to select a viable initial video standard");
1457 }
1458
1459
1460 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1461 {
1462         int ret;
1463         unsigned int idx;
1464         struct pvr2_ctrl *cptr;
1465         int reloadFl = 0;
1466         if (!reloadFl) {
1467                 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1468                             == 0);
1469                 if (reloadFl) {
1470                         pvr2_trace(PVR2_TRACE_INIT,
1471                                    "USB endpoint config looks strange"
1472                                    "; possibly firmware needs to be loaded");
1473                 }
1474         }
1475         if (!reloadFl) {
1476                 reloadFl = !pvr2_hdw_check_firmware(hdw);
1477                 if (reloadFl) {
1478                         pvr2_trace(PVR2_TRACE_INIT,
1479                                    "Check for FX2 firmware failed"
1480                                    "; possibly firmware needs to be loaded");
1481                 }
1482         }
1483         if (reloadFl) {
1484                 if (pvr2_upload_firmware1(hdw) != 0) {
1485                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1486                                    "Failure uploading firmware1");
1487                 }
1488                 return;
1489         }
1490         hdw->fw1_state = FW1_STATE_OK;
1491
1492         if (initusbreset) {
1493                 pvr2_hdw_device_reset(hdw);
1494         }
1495         if (!pvr2_hdw_dev_ok(hdw)) return;
1496
1497         for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1498                 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1499         }
1500
1501         pvr2_hdw_cmd_powerup(hdw);
1502         if (!pvr2_hdw_dev_ok(hdw)) return;
1503
1504         if (pvr2_upload_firmware2(hdw)){
1505                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1506                 pvr2_hdw_render_useless(hdw);
1507                 return;
1508         }
1509
1510         // This step MUST happen after the earlier powerup step.
1511         pvr2_i2c_core_init(hdw);
1512         if (!pvr2_hdw_dev_ok(hdw)) return;
1513
1514         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1515                 cptr = hdw->controls + idx;
1516                 if (cptr->info->skip_init) continue;
1517                 if (!cptr->info->set_value) continue;
1518                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1519         }
1520
1521         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1522         // thread-safe against the normal pvr2_send_request() mechanism.
1523         // (We should make it thread safe).
1524
1525         ret = pvr2_hdw_get_eeprom_addr(hdw);
1526         if (!pvr2_hdw_dev_ok(hdw)) return;
1527         if (ret < 0) {
1528                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1529                            "Unable to determine location of eeprom, skipping");
1530         } else {
1531                 hdw->eeprom_addr = ret;
1532                 pvr2_eeprom_analyze(hdw);
1533                 if (!pvr2_hdw_dev_ok(hdw)) return;
1534         }
1535
1536         pvr2_hdw_setup_std(hdw);
1537
1538         if (!get_default_tuner_type(hdw)) {
1539                 pvr2_trace(PVR2_TRACE_INIT,
1540                            "pvr2_hdw_setup: Tuner type overridden to %d",
1541                            hdw->tuner_type);
1542         }
1543
1544         hdw->tuner_updated = !0;
1545         pvr2_i2c_core_check_stale(hdw);
1546         hdw->tuner_updated = 0;
1547
1548         if (!pvr2_hdw_dev_ok(hdw)) return;
1549
1550         pvr2_hdw_commit_ctl_internal(hdw);
1551         if (!pvr2_hdw_dev_ok(hdw)) return;
1552
1553         hdw->vid_stream = pvr2_stream_create();
1554         if (!pvr2_hdw_dev_ok(hdw)) return;
1555         pvr2_trace(PVR2_TRACE_INIT,
1556                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1557         if (hdw->vid_stream) {
1558                 idx = get_default_error_tolerance(hdw);
1559                 if (idx) {
1560                         pvr2_trace(PVR2_TRACE_INIT,
1561                                    "pvr2_hdw_setup: video stream %p"
1562                                    " setting tolerance %u",
1563                                    hdw->vid_stream,idx);
1564                 }
1565                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1566                                   PVR2_VID_ENDPOINT,idx);
1567         }
1568
1569         if (!pvr2_hdw_dev_ok(hdw)) return;
1570
1571         /* Make sure everything is up to date */
1572         pvr2_i2c_core_sync(hdw);
1573
1574         if (!pvr2_hdw_dev_ok(hdw)) return;
1575
1576         hdw->flag_init_ok = !0;
1577 }
1578
1579
1580 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1581 {
1582         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1583         LOCK_TAKE(hdw->big_lock); do {
1584                 pvr2_hdw_setup_low(hdw);
1585                 pvr2_trace(PVR2_TRACE_INIT,
1586                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1587                            hdw,hdw->flag_ok,hdw->flag_init_ok);
1588                 if (pvr2_hdw_dev_ok(hdw)) {
1589                         if (pvr2_hdw_init_ok(hdw)) {
1590                                 pvr2_trace(
1591                                         PVR2_TRACE_INFO,
1592                                         "Device initialization"
1593                                         " completed successfully.");
1594                                 break;
1595                         }
1596                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1597                                 pvr2_trace(
1598                                         PVR2_TRACE_INFO,
1599                                         "Device microcontroller firmware"
1600                                         " (re)loaded; it should now reset"
1601                                         " and reconnect.");
1602                                 break;
1603                         }
1604                         pvr2_trace(
1605                                 PVR2_TRACE_ERROR_LEGS,
1606                                 "Device initialization was not successful.");
1607                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1608                                 pvr2_trace(
1609                                         PVR2_TRACE_ERROR_LEGS,
1610                                         "Giving up since device"
1611                                         " microcontroller firmware"
1612                                         " appears to be missing.");
1613                                 break;
1614                         }
1615                 }
1616                 if (procreload) {
1617                         pvr2_trace(
1618                                 PVR2_TRACE_ERROR_LEGS,
1619                                 "Attempting pvrusb2 recovery by reloading"
1620                                 " primary firmware.");
1621                         pvr2_trace(
1622                                 PVR2_TRACE_ERROR_LEGS,
1623                                 "If this works, device should disconnect"
1624                                 " and reconnect in a sane state.");
1625                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1626                         pvr2_upload_firmware1(hdw);
1627                 } else {
1628                         pvr2_trace(
1629                                 PVR2_TRACE_ERROR_LEGS,
1630                                 "***WARNING*** pvrusb2 device hardware"
1631                                 " appears to be jammed"
1632                                 " and I can't clear it.");
1633                         pvr2_trace(
1634                                 PVR2_TRACE_ERROR_LEGS,
1635                                 "You might need to power cycle"
1636                                 " the pvrusb2 device"
1637                                 " in order to recover.");
1638                 }
1639         } while (0); LOCK_GIVE(hdw->big_lock);
1640         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1641         return hdw->flag_init_ok;
1642 }
1643
1644
1645 /* Create and return a structure for interacting with the underlying
1646    hardware */
1647 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1648                                  const struct usb_device_id *devid)
1649 {
1650         unsigned int idx,cnt1,cnt2;
1651         struct pvr2_hdw *hdw;
1652         unsigned int hdw_type;
1653         int valid_std_mask;
1654         struct pvr2_ctrl *cptr;
1655         __u8 ifnum;
1656
1657         hdw_type = devid - pvr2_device_table;
1658         if (hdw_type >=
1659             sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1660                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1661                            "Bogus device type of %u reported",hdw_type);
1662                 return 0;
1663         }
1664
1665         hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1666         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1667                    hdw,pvr2_device_names[hdw_type]);
1668         if (!hdw) goto fail;
1669         memset(hdw,0,sizeof(*hdw));
1670
1671         hdw->control_cnt = CTRLDEF_COUNT;
1672         hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1673                                 GFP_KERNEL);
1674         if (!hdw->controls) goto fail;
1675         memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
1676         hdw->hdw_type = hdw_type;
1677         for (idx = 0; idx < hdw->control_cnt; idx++) {
1678                 cptr = hdw->controls + idx;
1679                 cptr->hdw = hdw;
1680         }
1681         for (idx = 0; idx < 32; idx++) {
1682                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1683         }
1684         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1685                 cptr = hdw->controls + idx;
1686                 cptr->info = control_defs+idx;
1687         }
1688
1689         // Initialize video standard enum dynamic control
1690         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1691         if (cptr) {
1692                 memcpy(&hdw->std_info_enum,cptr->info,
1693                        sizeof(hdw->std_info_enum));
1694                 cptr->info = &hdw->std_info_enum;
1695
1696         }
1697         // Initialize control data regarding video standard masks
1698         valid_std_mask = pvr2_std_get_usable();
1699         for (idx = 0; idx < 32; idx++) {
1700                 if (!(valid_std_mask & (1 << idx))) continue;
1701                 cnt1 = pvr2_std_id_to_str(
1702                         hdw->std_mask_names[idx],
1703                         sizeof(hdw->std_mask_names[idx])-1,
1704                         1 << idx);
1705                 hdw->std_mask_names[idx][cnt1] = 0;
1706         }
1707         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1708         if (cptr) {
1709                 memcpy(&hdw->std_info_avail,cptr->info,
1710                        sizeof(hdw->std_info_avail));
1711                 cptr->info = &hdw->std_info_avail;
1712                 hdw->std_info_avail.def.type_bitmask.bit_names =
1713                         hdw->std_mask_ptrs;
1714                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1715                         valid_std_mask;
1716         }
1717         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1718         if (cptr) {
1719                 memcpy(&hdw->std_info_cur,cptr->info,
1720                        sizeof(hdw->std_info_cur));
1721                 cptr->info = &hdw->std_info_cur;
1722                 hdw->std_info_cur.def.type_bitmask.bit_names =
1723                         hdw->std_mask_ptrs;
1724                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1725                         valid_std_mask;
1726         }
1727
1728         hdw->eeprom_addr = -1;
1729         hdw->unit_number = -1;
1730         hdw->v4l_minor_number = -1;
1731         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1732         if (!hdw->ctl_write_buffer) goto fail;
1733         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1734         if (!hdw->ctl_read_buffer) goto fail;
1735         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1736         if (!hdw->ctl_write_urb) goto fail;
1737         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1738         if (!hdw->ctl_read_urb) goto fail;
1739
1740         down(&pvr2_unit_sem); do {
1741                 for (idx = 0; idx < PVR_NUM; idx++) {
1742                         if (unit_pointers[idx]) continue;
1743                         hdw->unit_number = idx;
1744                         unit_pointers[idx] = hdw;
1745                         break;
1746                 }
1747         } while (0); up(&pvr2_unit_sem);
1748
1749         cnt1 = 0;
1750         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1751         cnt1 += cnt2;
1752         if (hdw->unit_number >= 0) {
1753                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1754                                  ('a' + hdw->unit_number));
1755                 cnt1 += cnt2;
1756         }
1757         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1758         hdw->name[cnt1] = 0;
1759
1760         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1761                    hdw->unit_number,hdw->name);
1762
1763         hdw->tuner_type = -1;
1764         hdw->flag_ok = !0;
1765         /* Initialize the mask of subsystems that we will shut down when we
1766            stop streaming. */
1767         hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1768         hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1769
1770         pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1771                    hdw->subsys_stream_mask);
1772
1773         hdw->usb_intf = intf;
1774         hdw->usb_dev = interface_to_usbdev(intf);
1775
1776         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1777         usb_set_interface(hdw->usb_dev,ifnum,0);
1778
1779         mutex_init(&hdw->ctl_lock_mutex);
1780         mutex_init(&hdw->big_lock_mutex);
1781
1782         return hdw;
1783  fail:
1784         if (hdw) {
1785                 if (hdw->ctl_read_urb) usb_free_urb(hdw->ctl_read_urb);
1786                 if (hdw->ctl_write_urb) usb_free_urb(hdw->ctl_write_urb);
1787                 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1788                 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1789                 if (hdw->controls) kfree(hdw->controls);
1790                 kfree(hdw);
1791         }
1792         return 0;
1793 }
1794
1795
1796 /* Remove _all_ associations between this driver and the underlying USB
1797    layer. */
1798 void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1799 {
1800         if (hdw->flag_disconnected) return;
1801         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1802         if (hdw->ctl_read_urb) {
1803                 usb_kill_urb(hdw->ctl_read_urb);
1804                 usb_free_urb(hdw->ctl_read_urb);
1805                 hdw->ctl_read_urb = 0;
1806         }
1807         if (hdw->ctl_write_urb) {
1808                 usb_kill_urb(hdw->ctl_write_urb);
1809                 usb_free_urb(hdw->ctl_write_urb);
1810                 hdw->ctl_write_urb = 0;
1811         }
1812         if (hdw->ctl_read_buffer) {
1813                 kfree(hdw->ctl_read_buffer);
1814                 hdw->ctl_read_buffer = 0;
1815         }
1816         if (hdw->ctl_write_buffer) {
1817                 kfree(hdw->ctl_write_buffer);
1818                 hdw->ctl_write_buffer = 0;
1819         }
1820         pvr2_hdw_render_useless_unlocked(hdw);
1821         hdw->flag_disconnected = !0;
1822         hdw->usb_dev = 0;
1823         hdw->usb_intf = 0;
1824 }
1825
1826
1827 /* Destroy hardware interaction structure */
1828 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
1829 {
1830         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
1831         if (hdw->fw_buffer) {
1832                 kfree(hdw->fw_buffer);
1833                 hdw->fw_buffer = 0;
1834         }
1835         if (hdw->vid_stream) {
1836                 pvr2_stream_destroy(hdw->vid_stream);
1837                 hdw->vid_stream = 0;
1838         }
1839         if (hdw->audio_stat) {
1840                 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
1841         }
1842         if (hdw->decoder_ctrl) {
1843                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
1844         }
1845         pvr2_i2c_core_done(hdw);
1846         pvr2_hdw_remove_usb_stuff(hdw);
1847         down(&pvr2_unit_sem); do {
1848                 if ((hdw->unit_number >= 0) &&
1849                     (hdw->unit_number < PVR_NUM) &&
1850                     (unit_pointers[hdw->unit_number] == hdw)) {
1851                         unit_pointers[hdw->unit_number] = 0;
1852                 }
1853         } while (0); up(&pvr2_unit_sem);
1854         if (hdw->controls) kfree(hdw->controls);
1855         if (hdw->std_defs) kfree(hdw->std_defs);
1856         if (hdw->std_enum_names) kfree(hdw->std_enum_names);
1857         kfree(hdw);
1858 }
1859
1860
1861 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
1862 {
1863         return hdw->flag_init_ok;
1864 }
1865
1866
1867 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
1868 {
1869         return (hdw && hdw->flag_ok);
1870 }
1871
1872
1873 /* Called when hardware has been unplugged */
1874 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
1875 {
1876         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
1877         LOCK_TAKE(hdw->big_lock);
1878         LOCK_TAKE(hdw->ctl_lock);
1879         pvr2_hdw_remove_usb_stuff(hdw);
1880         LOCK_GIVE(hdw->ctl_lock);
1881         LOCK_GIVE(hdw->big_lock);
1882 }
1883
1884
1885 // Attempt to autoselect an appropriate value for std_enum_cur given
1886 // whatever is currently in std_mask_cur
1887 void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
1888 {
1889         unsigned int idx;
1890         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
1891                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
1892                         hdw->std_enum_cur = idx;
1893                         return;
1894                 }
1895         }
1896         hdw->std_enum_cur = 0;
1897 }
1898
1899
1900 // Calculate correct set of enumerated standards based on currently known
1901 // set of available standards bits.
1902 void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
1903 {
1904         struct v4l2_standard *newstd;
1905         unsigned int std_cnt;
1906         unsigned int idx;
1907
1908         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
1909
1910         if (hdw->std_defs) {
1911                 kfree(hdw->std_defs);
1912                 hdw->std_defs = 0;
1913         }
1914         hdw->std_enum_cnt = 0;
1915         if (hdw->std_enum_names) {
1916                 kfree(hdw->std_enum_names);
1917                 hdw->std_enum_names = 0;
1918         }
1919
1920         if (!std_cnt) {
1921                 pvr2_trace(
1922                         PVR2_TRACE_ERROR_LEGS,
1923                         "WARNING: Failed to identify any viable standards");
1924         }
1925         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
1926         hdw->std_enum_names[0] = "none";
1927         for (idx = 0; idx < std_cnt; idx++) {
1928                 hdw->std_enum_names[idx+1] =
1929                         newstd[idx].name;
1930         }
1931         // Set up the dynamic control for this standard
1932         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
1933         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
1934         hdw->std_defs = newstd;
1935         hdw->std_enum_cnt = std_cnt+1;
1936         hdw->std_enum_cur = 0;
1937         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1938 }
1939
1940
1941 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
1942                                struct v4l2_standard *std,
1943                                unsigned int idx)
1944 {
1945         int ret = -EINVAL;
1946         if (!idx) return ret;
1947         LOCK_TAKE(hdw->big_lock); do {
1948                 if (idx >= hdw->std_enum_cnt) break;
1949                 idx--;
1950                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
1951                 ret = 0;
1952         } while (0); LOCK_GIVE(hdw->big_lock);
1953         return ret;
1954 }
1955
1956
1957 /* Get the number of defined controls */
1958 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
1959 {
1960         return hdw->control_cnt;
1961 }
1962
1963
1964 /* Retrieve a control handle given its index (0..count-1) */
1965 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
1966                                              unsigned int idx)
1967 {
1968         if (idx >= hdw->control_cnt) return 0;
1969         return hdw->controls + idx;
1970 }
1971
1972
1973 /* Retrieve a control handle given its index (0..count-1) */
1974 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
1975                                           unsigned int ctl_id)
1976 {
1977         struct pvr2_ctrl *cptr;
1978         unsigned int idx;
1979         int i;
1980
1981         /* This could be made a lot more efficient, but for now... */
1982         for (idx = 0; idx < hdw->control_cnt; idx++) {
1983                 cptr = hdw->controls + idx;
1984                 i = cptr->info->internal_id;
1985                 if (i && (i == ctl_id)) return cptr;
1986         }
1987         return 0;
1988 }
1989
1990
1991 /* Given a V4L ID, retrieve the control structure associated with it. */
1992 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
1993 {
1994         struct pvr2_ctrl *cptr;
1995         unsigned int idx;
1996         int i;
1997
1998         /* This could be made a lot more efficient, but for now... */
1999         for (idx = 0; idx < hdw->control_cnt; idx++) {
2000                 cptr = hdw->controls + idx;
2001                 i = cptr->info->v4l_id;
2002                 if (i && (i == ctl_id)) return cptr;
2003         }
2004         return 0;
2005 }
2006
2007
2008 /* Given a V4L ID for its immediate predecessor, retrieve the control
2009    structure associated with it. */
2010 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2011                                             unsigned int ctl_id)
2012 {
2013         struct pvr2_ctrl *cptr,*cp2;
2014         unsigned int idx;
2015         int i;
2016
2017         /* This could be made a lot more efficient, but for now... */
2018         cp2 = 0;
2019         for (idx = 0; idx < hdw->control_cnt; idx++) {
2020                 cptr = hdw->controls + idx;
2021                 i = cptr->info->v4l_id;
2022                 if (!i) continue;
2023                 if (i <= ctl_id) continue;
2024                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2025                 cp2 = cptr;
2026         }
2027         return cp2;
2028         return 0;
2029 }
2030
2031
2032 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2033 {
2034         switch (tp) {
2035         case pvr2_ctl_int: return "integer";
2036         case pvr2_ctl_enum: return "enum";
2037         case pvr2_ctl_bool: return "boolean";
2038         case pvr2_ctl_bitmask: return "bitmask";
2039         }
2040         return "";
2041 }
2042
2043
2044 /* Commit all control changes made up to this point.  Subsystems can be
2045    indirectly affected by these changes.  For a given set of things being
2046    committed, we'll clear the affected subsystem bits and then once we're
2047    done committing everything we'll make a request to restore the subsystem
2048    state(s) back to their previous value before this function was called.
2049    Thus we can automatically reconfigure affected pieces of the driver as
2050    controls are changed. */
2051 int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2052 {
2053         unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2054         unsigned long stale_subsys_mask = 0;
2055         unsigned int idx;
2056         struct pvr2_ctrl *cptr;
2057         int value;
2058         int commit_flag = 0;
2059         char buf[100];
2060         unsigned int bcnt,ccnt;
2061
2062         for (idx = 0; idx < hdw->control_cnt; idx++) {
2063                 cptr = hdw->controls + idx;
2064                 if (cptr->info->is_dirty == 0) continue;
2065                 if (!cptr->info->is_dirty(cptr)) continue;
2066                 if (!commit_flag) {
2067                         commit_flag = !0;
2068                 }
2069
2070                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2071                                  cptr->info->name);
2072                 value = 0;
2073                 cptr->info->get_value(cptr,&value);
2074                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2075                                                 buf+bcnt,
2076                                                 sizeof(buf)-bcnt,&ccnt);
2077                 bcnt += ccnt;
2078                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2079                                   get_ctrl_typename(cptr->info->type));
2080                 pvr2_trace(PVR2_TRACE_CTL,
2081                            "/*--TRACE_COMMIT--*/ %.*s",
2082                            bcnt,buf);
2083         }
2084
2085         if (!commit_flag) {
2086                 /* Nothing has changed */
2087                 return 0;
2088         }
2089
2090         /* When video standard changes, reset the hres and vres values -
2091            but if the user has pending changes there, then let the changes
2092            take priority. */
2093         if (hdw->std_dirty) {
2094                 /* Rewrite the vertical resolution to be appropriate to the
2095                    video standard that has been selected. */
2096                 int nvres;
2097                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2098                         nvres = 480;
2099                 } else {
2100                         nvres = 576;
2101                 }
2102                 if (nvres != hdw->res_ver_val) {
2103                         hdw->res_ver_val = nvres;
2104                         hdw->res_ver_dirty = !0;
2105                 }
2106                 if (!hdw->interlace_val) {
2107                         hdw->interlace_val = 0;
2108                         hdw->interlace_dirty = !0;
2109                 }
2110         }
2111
2112         if (hdw->std_dirty ||
2113             hdw->interlace_dirty ||
2114             hdw->vbr_dirty ||
2115             hdw->videobitrate_dirty ||
2116             hdw->videopeak_dirty ||
2117             hdw->audiobitrate_dirty ||
2118             hdw->audiolayer_dirty ||
2119             hdw->audiocrc_dirty ||
2120             hdw->audioemphasis_dirty ||
2121             hdw->srate_dirty ||
2122             hdw->res_ver_dirty ||
2123             hdw->res_hor_dirty) {
2124                 /* If any of this changes, then the encoder needs to be
2125                    reconfigured, and we need to reset the stream. */
2126                 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2127                 stale_subsys_mask |= hdw->subsys_stream_mask;
2128         }
2129
2130
2131         /* Scan i2c core at this point - before we clear all the dirty
2132            bits.  Various parts of the i2c core will notice dirty bits as
2133            appropriate and arrange to broadcast or directly send updates to
2134            the client drivers in order to keep everything in sync */
2135         pvr2_i2c_core_check_stale(hdw);
2136
2137         for (idx = 0; idx < hdw->control_cnt; idx++) {
2138                 cptr = hdw->controls + idx;
2139                 if (!cptr->info->clear_dirty) continue;
2140                 cptr->info->clear_dirty(cptr);
2141         }
2142
2143         /* Now execute i2c core update */
2144         pvr2_i2c_core_sync(hdw);
2145
2146         pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2147         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2148
2149         return 0;
2150 }
2151
2152
2153 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2154 {
2155         LOCK_TAKE(hdw->big_lock); do {
2156                 pvr2_hdw_commit_ctl_internal(hdw);
2157         } while (0); LOCK_GIVE(hdw->big_lock);
2158         return 0;
2159 }
2160
2161
2162 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2163 {
2164         LOCK_TAKE(hdw->big_lock); do {
2165                 pvr2_i2c_core_sync(hdw);
2166         } while (0); LOCK_GIVE(hdw->big_lock);
2167 }
2168
2169
2170 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2171                                  void (*func)(void *),
2172                                  void *data)
2173 {
2174         LOCK_TAKE(hdw->big_lock); do {
2175                 hdw->poll_trigger_func = func;
2176                 hdw->poll_trigger_data = data;
2177         } while (0); LOCK_GIVE(hdw->big_lock);
2178 }
2179
2180
2181 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2182 {
2183         if (hdw->poll_trigger_func) {
2184                 hdw->poll_trigger_func(hdw->poll_trigger_data);
2185         }
2186 }
2187
2188
2189 void pvr2_hdw_poll_trigger(struct pvr2_hdw *hdw)
2190 {
2191         LOCK_TAKE(hdw->big_lock); do {
2192                 pvr2_hdw_poll_trigger_unlocked(hdw);
2193         } while (0); LOCK_GIVE(hdw->big_lock);
2194 }
2195
2196
2197 /* Return name for this driver instance */
2198 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2199 {
2200         return hdw->name;
2201 }
2202
2203
2204 /* Return bit mask indicating signal status */
2205 unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2206 {
2207         unsigned int msk = 0;
2208         switch (hdw->input_val) {
2209         case PVR2_CVAL_INPUT_TV:
2210         case PVR2_CVAL_INPUT_RADIO:
2211                 if (hdw->decoder_ctrl &&
2212                     hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2213                         msk |= PVR2_SIGNAL_OK;
2214                         if (hdw->audio_stat &&
2215                             hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2216                                 if (hdw->flag_stereo) {
2217                                         msk |= PVR2_SIGNAL_STEREO;
2218                                 }
2219                                 if (hdw->flag_bilingual) {
2220                                         msk |= PVR2_SIGNAL_SAP;
2221                                 }
2222                         }
2223                 }
2224                 break;
2225         default:
2226                 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2227         }
2228         return msk;
2229 }
2230
2231
2232 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2233 {
2234         int result;
2235         LOCK_TAKE(hdw->ctl_lock); do {
2236                 hdw->cmd_buffer[0] = 0x0b;
2237                 result = pvr2_send_request(hdw,
2238                                            hdw->cmd_buffer,1,
2239                                            hdw->cmd_buffer,1);
2240                 if (result < 0) break;
2241                 result = (hdw->cmd_buffer[0] != 0);
2242         } while(0); LOCK_GIVE(hdw->ctl_lock);
2243         return result;
2244 }
2245
2246
2247 /* Return bit mask indicating signal status */
2248 unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2249 {
2250         unsigned int msk = 0;
2251         LOCK_TAKE(hdw->big_lock); do {
2252                 msk = pvr2_hdw_get_signal_status_internal(hdw);
2253         } while (0); LOCK_GIVE(hdw->big_lock);
2254         return msk;
2255 }
2256
2257
2258 /* Get handle to video output stream */
2259 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2260 {
2261         return hp->vid_stream;
2262 }
2263
2264
2265 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2266 {
2267         int nr = pvr2_hdw_get_unit_number(hdw);
2268         LOCK_TAKE(hdw->big_lock); do {
2269                 hdw->log_requested = !0;
2270                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2271                 pvr2_i2c_core_check_stale(hdw);
2272                 hdw->log_requested = 0;
2273                 pvr2_i2c_core_sync(hdw);
2274                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2275         } while (0); LOCK_GIVE(hdw->big_lock);
2276 }
2277
2278 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2279 {
2280         int ret;
2281         u16 address;
2282         unsigned int pipe;
2283         LOCK_TAKE(hdw->big_lock); do {
2284                 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2285
2286                 if (!enable_flag) {
2287                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2288                                    "Cleaning up after CPU firmware fetch");
2289                         kfree(hdw->fw_buffer);
2290                         hdw->fw_buffer = 0;
2291                         hdw->fw_size = 0;
2292                         /* Now release the CPU.  It will disconnect and
2293                            reconnect later. */
2294                         pvr2_hdw_cpureset_assert(hdw,0);
2295                         break;
2296                 }
2297
2298                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2299                            "Preparing to suck out CPU firmware");
2300                 hdw->fw_size = 0x2000;
2301                 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2302                 if (!hdw->fw_buffer) {
2303                         hdw->fw_size = 0;
2304                         break;
2305                 }
2306
2307                 memset(hdw->fw_buffer,0,hdw->fw_size);
2308
2309                 /* We have to hold the CPU during firmware upload. */
2310                 pvr2_hdw_cpureset_assert(hdw,1);
2311
2312                 /* download the firmware from address 0000-1fff in 2048
2313                    (=0x800) bytes chunk. */
2314
2315                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2316                 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2317                 for(address = 0; address < hdw->fw_size; address += 0x800) {
2318                         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2319                                               address,0,
2320                                               hdw->fw_buffer+address,0x800,HZ);
2321                         if (ret < 0) break;
2322                 }
2323
2324                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2325
2326         } while (0); LOCK_GIVE(hdw->big_lock);
2327 }
2328
2329
2330 /* Return true if we're in a mode for retrieval CPU firmware */
2331 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2332 {
2333         return hdw->fw_buffer != 0;
2334 }
2335
2336
2337 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2338                        char *buf,unsigned int cnt)
2339 {
2340         int ret = -EINVAL;
2341         LOCK_TAKE(hdw->big_lock); do {
2342                 if (!buf) break;
2343                 if (!cnt) break;
2344
2345                 if (!hdw->fw_buffer) {
2346                         ret = -EIO;
2347                         break;
2348                 }
2349
2350                 if (offs >= hdw->fw_size) {
2351                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2352                                    "Read firmware data offs=%d EOF",
2353                                    offs);
2354                         ret = 0;
2355                         break;
2356                 }
2357
2358                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2359
2360                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2361
2362                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2363                            "Read firmware data offs=%d cnt=%d",
2364                            offs,cnt);
2365                 ret = cnt;
2366         } while (0); LOCK_GIVE(hdw->big_lock);
2367
2368         return ret;
2369 }
2370
2371
2372 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2373 {
2374         return hdw->v4l_minor_number;
2375 }
2376
2377
2378 /* Store the v4l minor device number */
2379 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2380 {
2381         hdw->v4l_minor_number = v;
2382 }
2383
2384
2385 void pvr2_reset_ctl_endpoints(struct pvr2_hdw *hdw)
2386 {
2387         if (!hdw->usb_dev) return;
2388         usb_settoggle(hdw->usb_dev, PVR2_CTL_WRITE_ENDPOINT & 0xf,
2389                       !(PVR2_CTL_WRITE_ENDPOINT & USB_DIR_IN), 0);
2390         usb_settoggle(hdw->usb_dev, PVR2_CTL_READ_ENDPOINT & 0xf,
2391                       !(PVR2_CTL_READ_ENDPOINT & USB_DIR_IN), 0);
2392         usb_clear_halt(hdw->usb_dev,
2393                        usb_rcvbulkpipe(hdw->usb_dev,
2394                                        PVR2_CTL_READ_ENDPOINT & 0x7f));
2395         usb_clear_halt(hdw->usb_dev,
2396                        usb_sndbulkpipe(hdw->usb_dev,
2397                                        PVR2_CTL_WRITE_ENDPOINT & 0x7f));
2398 }
2399
2400
2401 static void pvr2_ctl_write_complete(struct urb *urb, struct pt_regs *regs)
2402 {
2403         struct pvr2_hdw *hdw = urb->context;
2404         hdw->ctl_write_pend_flag = 0;
2405         if (hdw->ctl_read_pend_flag) return;
2406         complete(&hdw->ctl_done);
2407 }
2408
2409
2410 static void pvr2_ctl_read_complete(struct urb *urb, struct pt_regs *regs)
2411 {
2412         struct pvr2_hdw *hdw = urb->context;
2413         hdw->ctl_read_pend_flag = 0;
2414         if (hdw->ctl_write_pend_flag) return;
2415         complete(&hdw->ctl_done);
2416 }
2417
2418
2419 static void pvr2_ctl_timeout(unsigned long data)
2420 {
2421         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2422         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2423                 hdw->ctl_timeout_flag = !0;
2424                 if (hdw->ctl_write_pend_flag && hdw->ctl_write_urb) {
2425                         usb_unlink_urb(hdw->ctl_write_urb);
2426                 }
2427                 if (hdw->ctl_read_pend_flag && hdw->ctl_read_urb) {
2428                         usb_unlink_urb(hdw->ctl_read_urb);
2429                 }
2430         }
2431 }
2432
2433
2434 int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2435                          unsigned int timeout,int probe_fl,
2436                          void *write_data,unsigned int write_len,
2437                          void *read_data,unsigned int read_len)
2438 {
2439         unsigned int idx;
2440         int status = 0;
2441         struct timer_list timer;
2442         if (!hdw->ctl_lock_held) {
2443                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2444                            "Attempted to execute control transfer"
2445                            " without lock!!");
2446                 return -EDEADLK;
2447         }
2448         if ((!hdw->flag_ok) && !probe_fl) {
2449                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2450                            "Attempted to execute control transfer"
2451                            " when device not ok");
2452                 return -EIO;
2453         }
2454         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2455                 if (!probe_fl) {
2456                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2457                                    "Attempted to execute control transfer"
2458                                    " when USB is disconnected");
2459                 }
2460                 return -ENOTTY;
2461         }
2462
2463         /* Ensure that we have sane parameters */
2464         if (!write_data) write_len = 0;
2465         if (!read_data) read_len = 0;
2466         if (write_len > PVR2_CTL_BUFFSIZE) {
2467                 pvr2_trace(
2468                         PVR2_TRACE_ERROR_LEGS,
2469                         "Attempted to execute %d byte"
2470                         " control-write transfer (limit=%d)",
2471                         write_len,PVR2_CTL_BUFFSIZE);
2472                 return -EINVAL;
2473         }
2474         if (read_len > PVR2_CTL_BUFFSIZE) {
2475                 pvr2_trace(
2476                         PVR2_TRACE_ERROR_LEGS,
2477                         "Attempted to execute %d byte"
2478                         " control-read transfer (limit=%d)",
2479                         write_len,PVR2_CTL_BUFFSIZE);
2480                 return -EINVAL;
2481         }
2482         if ((!write_len) && (!read_len)) {
2483                 pvr2_trace(
2484                         PVR2_TRACE_ERROR_LEGS,
2485                         "Attempted to execute null control transfer?");
2486                 return -EINVAL;
2487         }
2488
2489
2490         hdw->cmd_debug_state = 1;
2491         if (write_len) {
2492                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2493         } else {
2494                 hdw->cmd_debug_code = 0;
2495         }
2496         hdw->cmd_debug_write_len = write_len;
2497         hdw->cmd_debug_read_len = read_len;
2498
2499         /* Initialize common stuff */
2500         init_completion(&hdw->ctl_done);
2501         hdw->ctl_timeout_flag = 0;
2502         hdw->ctl_write_pend_flag = 0;
2503         hdw->ctl_read_pend_flag = 0;
2504         init_timer(&timer);
2505         timer.expires = jiffies + timeout;
2506         timer.data = (unsigned long)hdw;
2507         timer.function = pvr2_ctl_timeout;
2508
2509         if (write_len) {
2510                 hdw->cmd_debug_state = 2;
2511                 /* Transfer write data to internal buffer */
2512                 for (idx = 0; idx < write_len; idx++) {
2513                         hdw->ctl_write_buffer[idx] =
2514                                 ((unsigned char *)write_data)[idx];
2515                 }
2516                 /* Initiate a write request */
2517                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2518                                   hdw->usb_dev,
2519                                   usb_sndbulkpipe(hdw->usb_dev,
2520                                                   PVR2_CTL_WRITE_ENDPOINT),
2521                                   hdw->ctl_write_buffer,
2522                                   write_len,
2523                                   pvr2_ctl_write_complete,
2524                                   hdw);
2525                 hdw->ctl_write_urb->actual_length = 0;
2526                 hdw->ctl_write_pend_flag = !0;
2527                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2528                 if (status < 0) {
2529                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2530                                    "Failed to submit write-control"
2531                                    " URB status=%d",status);
2532                         hdw->ctl_write_pend_flag = 0;
2533                         goto done;
2534                 }
2535         }
2536
2537         if (read_len) {
2538                 hdw->cmd_debug_state = 3;
2539                 memset(hdw->ctl_read_buffer,0x43,read_len);
2540                 /* Initiate a read request */
2541                 usb_fill_bulk_urb(hdw->ctl_read_urb,
2542                                   hdw->usb_dev,
2543                                   usb_rcvbulkpipe(hdw->usb_dev,
2544                                                   PVR2_CTL_READ_ENDPOINT),
2545                                   hdw->ctl_read_buffer,
2546                                   read_len,
2547                                   pvr2_ctl_read_complete,
2548                                   hdw);
2549                 hdw->ctl_read_urb->actual_length = 0;
2550                 hdw->ctl_read_pend_flag = !0;
2551                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2552                 if (status < 0) {
2553                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2554                                    "Failed to submit read-control"
2555                                    " URB status=%d",status);
2556                         hdw->ctl_read_pend_flag = 0;
2557                         goto done;
2558                 }
2559         }
2560
2561         /* Start timer */
2562         add_timer(&timer);
2563
2564         /* Now wait for all I/O to complete */
2565         hdw->cmd_debug_state = 4;
2566         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2567                 wait_for_completion(&hdw->ctl_done);
2568         }
2569         hdw->cmd_debug_state = 5;
2570
2571         /* Stop timer */
2572         del_timer_sync(&timer);
2573
2574         hdw->cmd_debug_state = 6;
2575         status = 0;
2576
2577         if (hdw->ctl_timeout_flag) {
2578                 status = -ETIMEDOUT;
2579                 if (!probe_fl) {
2580                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2581                                    "Timed out control-write");
2582                 }
2583                 goto done;
2584         }
2585
2586         if (write_len) {
2587                 /* Validate results of write request */
2588                 if ((hdw->ctl_write_urb->status != 0) &&
2589                     (hdw->ctl_write_urb->status != -ENOENT) &&
2590                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2591                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
2592                         /* USB subsystem is reporting some kind of failure
2593                            on the write */
2594                         status = hdw->ctl_write_urb->status;
2595                         if (!probe_fl) {
2596                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2597                                            "control-write URB failure,"
2598                                            " status=%d",
2599                                            status);
2600                         }
2601                         goto done;
2602                 }
2603                 if (hdw->ctl_write_urb->actual_length < write_len) {
2604                         /* Failed to write enough data */
2605                         status = -EIO;
2606                         if (!probe_fl) {
2607                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2608                                            "control-write URB short,"
2609                                            " expected=%d got=%d",
2610                                            write_len,
2611                                            hdw->ctl_write_urb->actual_length);
2612                         }
2613                         goto done;
2614                 }
2615         }
2616         if (read_len) {
2617                 /* Validate results of read request */
2618                 if ((hdw->ctl_read_urb->status != 0) &&
2619                     (hdw->ctl_read_urb->status != -ENOENT) &&
2620                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2621                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
2622                         /* USB subsystem is reporting some kind of failure
2623                            on the read */
2624                         status = hdw->ctl_read_urb->status;
2625                         if (!probe_fl) {
2626                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2627                                            "control-read URB failure,"
2628                                            " status=%d",
2629                                            status);
2630                         }
2631                         goto done;
2632                 }
2633                 if (hdw->ctl_read_urb->actual_length < read_len) {
2634                         /* Failed to read enough data */
2635                         status = -EIO;
2636                         if (!probe_fl) {
2637                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2638                                            "control-read URB short,"
2639                                            " expected=%d got=%d",
2640                                            read_len,
2641                                            hdw->ctl_read_urb->actual_length);
2642                         }
2643                         goto done;
2644                 }
2645                 /* Transfer retrieved data out from internal buffer */
2646                 for (idx = 0; idx < read_len; idx++) {
2647                         ((unsigned char *)read_data)[idx] =
2648                                 hdw->ctl_read_buffer[idx];
2649                 }
2650         }
2651
2652  done:
2653
2654         hdw->cmd_debug_state = 0;
2655         if ((status < 0) && (!probe_fl)) {
2656                 pvr2_hdw_render_useless_unlocked(hdw);
2657         }
2658         return status;
2659 }
2660
2661
2662 int pvr2_send_request(struct pvr2_hdw *hdw,
2663                       void *write_data,unsigned int write_len,
2664                       void *read_data,unsigned int read_len)
2665 {
2666         return pvr2_send_request_ex(hdw,HZ*4,0,
2667                                     write_data,write_len,
2668                                     read_data,read_len);
2669 }
2670
2671 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2672 {
2673         int ret;
2674
2675         LOCK_TAKE(hdw->ctl_lock);
2676
2677         hdw->cmd_buffer[0] = 0x04;  /* write register prefix */
2678         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2679         hdw->cmd_buffer[5] = 0;
2680         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2681         hdw->cmd_buffer[7] = reg & 0xff;
2682
2683
2684         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2685
2686         LOCK_GIVE(hdw->ctl_lock);
2687
2688         return ret;
2689 }
2690
2691
2692 int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2693 {
2694         int ret = 0;
2695
2696         LOCK_TAKE(hdw->ctl_lock);
2697
2698         hdw->cmd_buffer[0] = 0x05;  /* read register prefix */
2699         hdw->cmd_buffer[1] = 0;
2700         hdw->cmd_buffer[2] = 0;
2701         hdw->cmd_buffer[3] = 0;
2702         hdw->cmd_buffer[4] = 0;
2703         hdw->cmd_buffer[5] = 0;
2704         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2705         hdw->cmd_buffer[7] = reg & 0xff;
2706
2707         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2708         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2709
2710         LOCK_GIVE(hdw->ctl_lock);
2711
2712         return ret;
2713 }
2714
2715
2716 int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2717 {
2718         int ret;
2719
2720         LOCK_TAKE(hdw->ctl_lock);
2721
2722         hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2723         hdw->cmd_buffer[1] = data & 0xff;
2724
2725         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2726
2727         LOCK_GIVE(hdw->ctl_lock);
2728
2729         return ret;
2730 }
2731
2732
2733 int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2734 {
2735         int ret;
2736
2737         LOCK_TAKE(hdw->ctl_lock);
2738
2739         hdw->cmd_buffer[0] = data;
2740
2741         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2742
2743         LOCK_GIVE(hdw->ctl_lock);
2744
2745         return ret;
2746 }
2747
2748
2749 void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2750 {
2751         if (!hdw->flag_ok) return;
2752         pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2753         hdw->flag_ok = 0;
2754         if (hdw->vid_stream) {
2755                 pvr2_stream_setup(hdw->vid_stream,0,0,0);
2756         }
2757         hdw->flag_streaming_enabled = 0;
2758         hdw->subsys_enabled_mask = 0;
2759 }
2760
2761
2762 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2763 {
2764         LOCK_TAKE(hdw->ctl_lock);
2765         pvr2_hdw_render_useless_unlocked(hdw);
2766         LOCK_GIVE(hdw->ctl_lock);
2767 }
2768
2769
2770 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2771 {
2772         int ret;
2773         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2774         ret = usb_lock_device_for_reset(hdw->usb_dev,0);
2775         if (ret == 1) {
2776                 ret = usb_reset_device(hdw->usb_dev);
2777                 usb_unlock_device(hdw->usb_dev);
2778         } else {
2779                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2780                            "Failed to lock USB device ret=%d",ret);
2781         }
2782         if (init_pause_msec) {
2783                 pvr2_trace(PVR2_TRACE_INFO,
2784                            "Waiting %u msec for hardware to settle",
2785                            init_pause_msec);
2786                 msleep(init_pause_msec);
2787         }
2788
2789 }
2790
2791
2792 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2793 {
2794         char da[1];
2795         unsigned int pipe;
2796         int ret;
2797
2798         if (!hdw->usb_dev) return;
2799
2800         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2801
2802         da[0] = val ? 0x01 : 0x00;
2803
2804         /* Write the CPUCS register on the 8051.  The lsb of the register
2805            is the reset bit; a 1 asserts reset while a 0 clears it. */
2806         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2807         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2808         if (ret < 0) {
2809                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2810                            "cpureset_assert(%d) error=%d",val,ret);
2811                 pvr2_hdw_render_useless(hdw);
2812         }
2813 }
2814
2815
2816 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2817 {
2818         int status;
2819         LOCK_TAKE(hdw->ctl_lock); do {
2820                 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2821                 hdw->flag_ok = !0;
2822                 hdw->cmd_buffer[0] = 0xdd;
2823                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2824         } while (0); LOCK_GIVE(hdw->ctl_lock);
2825         return status;
2826 }
2827
2828
2829 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2830 {
2831         int status;
2832         LOCK_TAKE(hdw->ctl_lock); do {
2833                 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2834                 hdw->cmd_buffer[0] = 0xde;
2835                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2836         } while (0); LOCK_GIVE(hdw->ctl_lock);
2837         return status;
2838 }
2839
2840
2841 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
2842 {
2843         if (!hdw->decoder_ctrl) {
2844                 pvr2_trace(PVR2_TRACE_INIT,
2845                            "Unable to reset decoder: nothing attached");
2846                 return -ENOTTY;
2847         }
2848
2849         if (!hdw->decoder_ctrl->force_reset) {
2850                 pvr2_trace(PVR2_TRACE_INIT,
2851                            "Unable to reset decoder: not implemented");
2852                 return -ENOTTY;
2853         }
2854
2855         pvr2_trace(PVR2_TRACE_INIT,
2856                    "Requesting decoder reset");
2857         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
2858         return 0;
2859 }
2860
2861
2862 int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
2863 {
2864         int status;
2865         LOCK_TAKE(hdw->ctl_lock); do {
2866                 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
2867                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2868         } while (0); LOCK_GIVE(hdw->ctl_lock);
2869         if (!status) {
2870                 hdw->subsys_enabled_mask =
2871                         ((hdw->subsys_enabled_mask &
2872                           ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
2873                          (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
2874         }
2875         return status;
2876 }
2877
2878
2879 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
2880                              struct pvr2_hdw_debug_info *ptr)
2881 {
2882         ptr->big_lock_held = hdw->big_lock_held;
2883         ptr->ctl_lock_held = hdw->ctl_lock_held;
2884         ptr->flag_ok = hdw->flag_ok;
2885         ptr->flag_disconnected = hdw->flag_disconnected;
2886         ptr->flag_init_ok = hdw->flag_init_ok;
2887         ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
2888         ptr->subsys_flags = hdw->subsys_enabled_mask;
2889         ptr->cmd_debug_state = hdw->cmd_debug_state;
2890         ptr->cmd_code = hdw->cmd_debug_code;
2891         ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
2892         ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
2893         ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
2894         ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
2895         ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
2896         ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
2897         ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
2898 }
2899
2900
2901 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
2902 {
2903         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
2904 }
2905
2906
2907 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
2908 {
2909         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
2910 }
2911
2912
2913 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
2914 {
2915         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
2916 }
2917
2918
2919 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
2920 {
2921         u32 cval,nval;
2922         int ret;
2923         if (~msk) {
2924                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
2925                 if (ret) return ret;
2926                 nval = (cval & ~msk) | (val & msk);
2927                 pvr2_trace(PVR2_TRACE_GPIO,
2928                            "GPIO direction changing 0x%x:0x%x"
2929                            " from 0x%x to 0x%x",
2930                            msk,val,cval,nval);
2931         } else {
2932                 nval = val;
2933                 pvr2_trace(PVR2_TRACE_GPIO,
2934                            "GPIO direction changing to 0x%x",nval);
2935         }
2936         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
2937 }
2938
2939
2940 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
2941 {
2942         u32 cval,nval;
2943         int ret;
2944         if (~msk) {
2945                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
2946                 if (ret) return ret;
2947                 nval = (cval & ~msk) | (val & msk);
2948                 pvr2_trace(PVR2_TRACE_GPIO,
2949                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
2950                            msk,val,cval,nval);
2951         } else {
2952                 nval = val;
2953                 pvr2_trace(PVR2_TRACE_GPIO,
2954                            "GPIO output changing to 0x%x",nval);
2955         }
2956         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
2957 }
2958
2959
2960 int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
2961 {
2962         int result;
2963         LOCK_TAKE(hdw->ctl_lock); do {
2964                 hdw->cmd_buffer[0] = 0xeb;
2965                 result = pvr2_send_request(hdw,
2966                                            hdw->cmd_buffer,1,
2967                                            hdw->cmd_buffer,1);
2968                 if (result < 0) break;
2969                 result = hdw->cmd_buffer[0];
2970         } while(0); LOCK_GIVE(hdw->ctl_lock);
2971         return result;
2972 }
2973
2974
2975 /*
2976   Stuff for Emacs to see, in order to encourage consistent editing style:
2977   *** Local Variables: ***
2978   *** mode: c ***
2979   *** fill-column: 75 ***
2980   *** tab-width: 8 ***
2981   *** c-basic-offset: 8 ***
2982   *** End: ***
2983   */