5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/errno.h>
23 #include <linux/string.h>
24 #include <linux/slab.h>
25 #include <linux/firmware.h>
26 #include <linux/videodev2.h>
27 #include <asm/semaphore.h>
29 #include "pvrusb2-std.h"
30 #include "pvrusb2-util.h"
31 #include "pvrusb2-hdw.h"
32 #include "pvrusb2-i2c-core.h"
33 #include "pvrusb2-tuner.h"
34 #include "pvrusb2-eeprom.h"
35 #include "pvrusb2-hdw-internal.h"
36 #include "pvrusb2-encoder.h"
37 #include "pvrusb2-debug.h"
39 struct usb_device_id pvr2_device_table[] = {
40 [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
41 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
42 [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
47 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
49 static const char *pvr2_device_names[] = {
50 [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
51 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
52 [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
56 struct pvr2_string_table {
61 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
62 // Names of other client modules to request for 24xxx model hardware
63 static const char *pvr2_client_24xxx[] = {
71 // Names of other client modules to request for 29xxx model hardware
72 static const char *pvr2_client_29xxx[] = {
79 static struct pvr2_string_table pvr2_client_lists[] = {
80 [PVR2_HDW_TYPE_29XXX] = {
82 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
84 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
85 [PVR2_HDW_TYPE_24XXX] = {
87 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
92 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = 0};
93 DECLARE_MUTEX(pvr2_unit_sem);
95 static int ctlchg = 0;
96 static int initusbreset = 1;
97 static int procreload = 0;
98 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
99 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
100 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
101 static int init_pause_msec = 0;
103 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
104 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
105 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
106 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
107 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
108 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
109 module_param(procreload, int, S_IRUGO|S_IWUSR);
110 MODULE_PARM_DESC(procreload,
111 "Attempt init failure recovery with firmware reload");
112 module_param_array(tuner, int, NULL, 0444);
113 MODULE_PARM_DESC(tuner,"specify installed tuner type");
114 module_param_array(video_std, int, NULL, 0444);
115 MODULE_PARM_DESC(video_std,"specify initial video standard");
116 module_param_array(tolerance, int, NULL, 0444);
117 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
119 #define PVR2_CTL_WRITE_ENDPOINT 0x01
120 #define PVR2_CTL_READ_ENDPOINT 0x81
122 #define PVR2_GPIO_IN 0x9008
123 #define PVR2_GPIO_OUT 0x900c
124 #define PVR2_GPIO_DIR 0x9020
126 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
128 #define PVR2_FIRMWARE_ENDPOINT 0x02
130 /* size of a firmware chunk */
131 #define FIRMWARE_CHUNK_SIZE 0x2000
134 static const char *control_values_srate[] = {
135 [PVR2_CVAL_SRATE_48] = "48KHz",
136 [PVR2_CVAL_SRATE_44_1] = "44.1KHz",
140 static const char *control_values_audiobitrate[] = {
141 [PVR2_CVAL_AUDIOBITRATE_384] = "384kb/s",
142 [PVR2_CVAL_AUDIOBITRATE_320] = "320kb/s",
143 [PVR2_CVAL_AUDIOBITRATE_256] = "256kb/s",
144 [PVR2_CVAL_AUDIOBITRATE_224] = "224kb/s",
145 [PVR2_CVAL_AUDIOBITRATE_192] = "192kb/s",
146 [PVR2_CVAL_AUDIOBITRATE_160] = "160kb/s",
147 [PVR2_CVAL_AUDIOBITRATE_128] = "128kb/s",
148 [PVR2_CVAL_AUDIOBITRATE_112] = "112kb/s",
149 [PVR2_CVAL_AUDIOBITRATE_96] = "96kb/s",
150 [PVR2_CVAL_AUDIOBITRATE_80] = "80kb/s",
151 [PVR2_CVAL_AUDIOBITRATE_64] = "64kb/s",
152 [PVR2_CVAL_AUDIOBITRATE_56] = "56kb/s",
153 [PVR2_CVAL_AUDIOBITRATE_48] = "48kb/s",
154 [PVR2_CVAL_AUDIOBITRATE_32] = "32kb/s",
155 [PVR2_CVAL_AUDIOBITRATE_VBR] = "VBR",
159 static const char *control_values_audioemphasis[] = {
160 [PVR2_CVAL_AUDIOEMPHASIS_NONE] = "None",
161 [PVR2_CVAL_AUDIOEMPHASIS_50_15] = "50/15us",
162 [PVR2_CVAL_AUDIOEMPHASIS_CCITT] = "CCITT J.17",
166 static const char *control_values_input[] = {
167 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
168 [PVR2_CVAL_INPUT_RADIO] = "radio",
169 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
170 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
174 static const char *control_values_audiomode[] = {
175 [V4L2_TUNER_MODE_MONO] = "Mono",
176 [V4L2_TUNER_MODE_STEREO] = "Stereo",
177 [V4L2_TUNER_MODE_LANG1] = "Lang1",
178 [V4L2_TUNER_MODE_LANG2] = "Lang2",
179 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
183 static const char *control_values_hsm[] = {
184 [PVR2_CVAL_HSM_FAIL] = "Fail",
185 [PVR2_CVAL_HSM_HIGH] = "High",
186 [PVR2_CVAL_HSM_FULL] = "Full",
190 static const char *control_values_subsystem[] = {
191 [PVR2_SUBSYS_B_ENC_FIRMWARE] = "enc_firmware",
192 [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
193 [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
194 [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
195 [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
199 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
201 struct pvr2_hdw *hdw = cptr->hdw;
202 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
203 *vp = hdw->freqTable[hdw->freqProgSlot-1];
210 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
212 struct pvr2_hdw *hdw = cptr->hdw;
213 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
214 hdw->freqTable[hdw->freqProgSlot-1] = v;
219 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
221 *vp = cptr->hdw->freqProgSlot;
225 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
227 struct pvr2_hdw *hdw = cptr->hdw;
228 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
229 hdw->freqProgSlot = v;
234 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
236 *vp = cptr->hdw->freqSlot;
240 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
243 struct pvr2_hdw *hdw = cptr->hdw;
245 if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
246 freq = hdw->freqTable[hdw->freqSlot-1];
248 if (freq && (freq != hdw->freqVal)) {
255 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
257 *vp = cptr->hdw->freqVal;
261 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
263 return cptr->hdw->freqDirty != 0;
266 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
268 cptr->hdw->freqDirty = 0;
271 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
273 struct pvr2_hdw *hdw = cptr->hdw;
280 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
282 *vp = cptr->hdw->flag_streaming_enabled;
286 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
288 int result = pvr2_hdw_is_hsm(cptr->hdw);
289 *vp = PVR2_CVAL_HSM_FULL;
290 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
291 if (result) *vp = PVR2_CVAL_HSM_HIGH;
295 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
297 *vp = cptr->hdw->std_mask_avail;
301 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
303 struct pvr2_hdw *hdw = cptr->hdw;
305 ns = hdw->std_mask_avail;
306 ns = (ns & ~m) | (v & m);
307 if (ns == hdw->std_mask_avail) return 0;
308 hdw->std_mask_avail = ns;
309 pvr2_hdw_internal_set_std_avail(hdw);
310 pvr2_hdw_internal_find_stdenum(hdw);
314 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
315 char *bufPtr,unsigned int bufSize,
318 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
322 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
323 const char *bufPtr,unsigned int bufSize,
328 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
329 if (ret < 0) return ret;
330 if (mskp) *mskp = id;
331 if (valp) *valp = id;
335 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
337 *vp = cptr->hdw->std_mask_cur;
341 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
343 struct pvr2_hdw *hdw = cptr->hdw;
345 ns = hdw->std_mask_cur;
346 ns = (ns & ~m) | (v & m);
347 if (ns == hdw->std_mask_cur) return 0;
348 hdw->std_mask_cur = ns;
350 pvr2_hdw_internal_find_stdenum(hdw);
354 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
356 return cptr->hdw->std_dirty != 0;
359 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
361 cptr->hdw->std_dirty = 0;
364 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
366 *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
367 PVR2_SIGNAL_OK) ? 1 : 0);
371 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
373 *vp = cptr->hdw->subsys_enabled_mask;
377 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
379 pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
383 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
385 *vp = cptr->hdw->subsys_stream_mask;
389 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
391 pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
395 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
397 struct pvr2_hdw *hdw = cptr->hdw;
398 if (v < 0) return -EINVAL;
399 if (v > hdw->std_enum_cnt) return -EINVAL;
400 hdw->std_enum_cur = v;
403 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
404 hdw->std_mask_cur = hdw->std_defs[v].id;
410 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
412 *vp = cptr->hdw->std_enum_cur;
417 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
419 return cptr->hdw->std_dirty != 0;
423 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
425 cptr->hdw->std_dirty = 0;
429 #define DEFINT(vmin,vmax) \
430 .type = pvr2_ctl_int, \
431 .def.type_int.min_value = vmin, \
432 .def.type_int.max_value = vmax
434 #define DEFENUM(tab) \
435 .type = pvr2_ctl_enum, \
436 .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
437 .def.type_enum.value_names = tab
440 .type = pvr2_ctl_bool
442 #define DEFMASK(msk,tab) \
443 .type = pvr2_ctl_bitmask, \
444 .def.type_bitmask.valid_bits = msk, \
445 .def.type_bitmask.bit_names = tab
447 #define DEFREF(vname) \
448 .set_value = ctrl_set_##vname, \
449 .get_value = ctrl_get_##vname, \
450 .is_dirty = ctrl_isdirty_##vname, \
451 .clear_dirty = ctrl_cleardirty_##vname
454 #define VCREATE_FUNCS(vname) \
455 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
456 {*vp = cptr->hdw->vname##_val; return 0;} \
457 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
458 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
459 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
460 {return cptr->hdw->vname##_dirty != 0;} \
461 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
462 {cptr->hdw->vname##_dirty = 0;}
464 VCREATE_FUNCS(brightness)
465 VCREATE_FUNCS(contrast)
466 VCREATE_FUNCS(saturation)
468 VCREATE_FUNCS(volume)
469 VCREATE_FUNCS(balance)
471 VCREATE_FUNCS(treble)
474 VCREATE_FUNCS(audiomode)
475 VCREATE_FUNCS(res_hor)
476 VCREATE_FUNCS(res_ver)
478 VCREATE_FUNCS(audiobitrate)
479 VCREATE_FUNCS(audiocrc)
480 VCREATE_FUNCS(audioemphasis)
482 VCREATE_FUNCS(videobitrate)
483 VCREATE_FUNCS(videopeak)
484 VCREATE_FUNCS(interlace)
485 VCREATE_FUNCS(audiolayer)
487 #define MIN_FREQ 55250000L
488 #define MAX_FREQ 850000000L
490 /* Table definition of all controls which can be manipulated */
491 static const struct pvr2_ctl_info control_defs[] = {
493 .v4l_id = V4L2_CID_BRIGHTNESS,
494 .desc = "Brightness",
495 .name = "brightness",
496 .default_value = 128,
500 .v4l_id = V4L2_CID_CONTRAST,
507 .v4l_id = V4L2_CID_SATURATION,
508 .desc = "Saturation",
509 .name = "saturation",
514 .v4l_id = V4L2_CID_HUE,
521 .v4l_id = V4L2_CID_AUDIO_VOLUME,
524 .default_value = 65535,
528 .v4l_id = V4L2_CID_AUDIO_BALANCE,
533 DEFINT(-32768,32767),
535 .v4l_id = V4L2_CID_AUDIO_BASS,
540 DEFINT(-32768,32767),
542 .v4l_id = V4L2_CID_AUDIO_TREBLE,
547 DEFINT(-32768,32767),
549 .v4l_id = V4L2_CID_AUDIO_MUTE,
556 .desc = "Video Source",
558 .internal_id = PVR2_CID_INPUT,
559 .default_value = PVR2_CVAL_INPUT_TV,
561 DEFENUM(control_values_input),
563 .desc = "Audio Mode",
564 .name = "audio_mode",
565 .internal_id = PVR2_CID_AUDIOMODE,
566 .default_value = V4L2_TUNER_MODE_STEREO,
568 DEFENUM(control_values_audiomode),
570 .desc = "Horizontal capture resolution",
571 .name = "resolution_hor",
572 .internal_id = PVR2_CID_HRES,
573 .default_value = 720,
577 .desc = "Vertical capture resolution",
578 .name = "resolution_ver",
579 .internal_id = PVR2_CID_VRES,
580 .default_value = 480,
584 .v4l_id = V4L2_CID_PVR_SRATE,
585 .desc = "Sample rate",
587 .default_value = PVR2_CVAL_SRATE_48,
589 DEFENUM(control_values_srate),
591 .v4l_id = V4L2_CID_PVR_AUDIOBITRATE,
592 .desc = "Audio Bitrate",
593 .name = "audio_bitrate",
594 .default_value = PVR2_CVAL_AUDIOBITRATE_224,
595 DEFREF(audiobitrate),
596 DEFENUM(control_values_audiobitrate),
598 .v4l_id = V4L2_CID_PVR_AUDIOCRC,
605 .v4l_id = V4L2_CID_PVR_AUDIOEMPHASIS,
606 .desc = "Audio Emphasis",
607 .name = "audio_emphasis",
608 .default_value = PVR2_CVAL_AUDIOEMPHASIS_NONE,
609 DEFREF(audioemphasis),
610 DEFENUM(control_values_audioemphasis),
612 .v4l_id = V4L2_CID_PVR_VBR,
613 .desc = "Variable video bitrate",
619 .v4l_id = V4L2_CID_PVR_VIDEOBITRATE,
620 .desc = "Average video bitrate",
621 .name = "video_average_bitrate",
622 .default_value = 6000000,
623 DEFREF(videobitrate),
624 DEFINT(500000,20000000),
626 .v4l_id = V4L2_CID_PVR_VIDEOPEAK,
627 .desc = "Peak video bitrate",
628 .name = "video_peak_bitrate",
629 .default_value = 6000000,
631 DEFINT(500000,20000000),
633 .desc = "Interlace mode",
635 .internal_id = PVR2_CID_INTERLACE,
640 .desc = "Audio Layer",
641 .name = "audio_layer",
646 .desc = "Tuner Frequency (Hz)",
648 .internal_id = PVR2_CID_FREQUENCY,
649 .default_value = 175250000L,
650 .set_value = ctrl_freq_set,
651 .get_value = ctrl_freq_get,
652 .is_dirty = ctrl_freq_is_dirty,
653 .clear_dirty = ctrl_freq_clear_dirty,
654 DEFINT(MIN_FREQ,MAX_FREQ),
658 .set_value = ctrl_channel_set,
659 .get_value = ctrl_channel_get,
660 DEFINT(0,FREQTABLE_SIZE),
662 .desc = "Channel Program Frequency",
663 .name = "freq_table_value",
664 .set_value = ctrl_channelfreq_set,
665 .get_value = ctrl_channelfreq_get,
666 DEFINT(MIN_FREQ,MAX_FREQ),
668 .desc = "Channel Program ID",
669 .name = "freq_table_channel",
670 .set_value = ctrl_channelprog_set,
671 .get_value = ctrl_channelprog_get,
672 DEFINT(0,FREQTABLE_SIZE),
674 .desc = "Streaming Enabled",
675 .name = "streaming_enabled",
676 .get_value = ctrl_streamingenabled_get,
681 .get_value = ctrl_hsm_get,
682 DEFENUM(control_values_hsm),
684 .desc = "Signal Present",
685 .name = "signal_present",
686 .get_value = ctrl_signal_get,
689 .desc = "Video Standards Available Mask",
690 .name = "video_standard_mask_available",
691 .internal_id = PVR2_CID_STDAVAIL,
693 .get_value = ctrl_stdavail_get,
694 .set_value = ctrl_stdavail_set,
695 .val_to_sym = ctrl_std_val_to_sym,
696 .sym_to_val = ctrl_std_sym_to_val,
697 .type = pvr2_ctl_bitmask,
699 .desc = "Video Standards In Use Mask",
700 .name = "video_standard_mask_active",
701 .internal_id = PVR2_CID_STDCUR,
703 .get_value = ctrl_stdcur_get,
704 .set_value = ctrl_stdcur_set,
705 .is_dirty = ctrl_stdcur_is_dirty,
706 .clear_dirty = ctrl_stdcur_clear_dirty,
707 .val_to_sym = ctrl_std_val_to_sym,
708 .sym_to_val = ctrl_std_sym_to_val,
709 .type = pvr2_ctl_bitmask,
711 .desc = "Subsystem enabled mask",
712 .name = "debug_subsys_mask",
714 .get_value = ctrl_subsys_get,
715 .set_value = ctrl_subsys_set,
716 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
718 .desc = "Subsystem stream mask",
719 .name = "debug_subsys_stream_mask",
721 .get_value = ctrl_subsys_stream_get,
722 .set_value = ctrl_subsys_stream_set,
723 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
725 .desc = "Video Standard Name",
726 .name = "video_standard",
727 .internal_id = PVR2_CID_STDENUM,
729 .get_value = ctrl_stdenumcur_get,
730 .set_value = ctrl_stdenumcur_set,
731 .is_dirty = ctrl_stdenumcur_is_dirty,
732 .clear_dirty = ctrl_stdenumcur_clear_dirty,
733 .type = pvr2_ctl_enum,
737 #define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
740 const char *pvr2_config_get_name(enum pvr2_config cfg)
743 case pvr2_config_empty: return "empty";
744 case pvr2_config_mpeg: return "mpeg";
745 case pvr2_config_vbi: return "vbi";
746 case pvr2_config_radio: return "radio";
752 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
758 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
760 return hdw->serial_number;
764 struct pvr2_hdw *pvr2_hdw_find(int unit_number)
766 if (unit_number < 0) return 0;
767 if (unit_number >= PVR_NUM) return 0;
768 return unit_pointers[unit_number];
772 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
774 return hdw->unit_number;
778 /* Attempt to locate one of the given set of files. Messages are logged
779 appropriate to what has been found. The return value will be 0 or
780 greater on success (it will be the index of the file name found) and
781 fw_entry will be filled in. Otherwise a negative error is returned on
782 failure. If the return value is -ENOENT then no viable firmware file
784 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
785 const struct firmware **fw_entry,
786 const char *fwtypename,
787 unsigned int fwcount,
788 const char *fwnames[])
792 for (idx = 0; idx < fwcount; idx++) {
793 ret = request_firmware(fw_entry,
797 trace_firmware("Located %s firmware: %s;"
803 if (ret == -ENOENT) continue;
804 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
805 "request_firmware fatal error with code=%d",ret);
808 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
810 " Device %s firmware"
811 " seems to be missing.",
813 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
814 "Did you install the pvrusb2 firmware files"
815 " in their proper location?");
817 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
818 "request_firmware unable to locate %s file %s",
819 fwtypename,fwnames[0]);
821 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
822 "request_firmware unable to locate"
823 " one of the following %s files:",
825 for (idx = 0; idx < fwcount; idx++) {
826 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
827 "request_firmware: Failed to find %s",
836 * pvr2_upload_firmware1().
838 * Send the 8051 firmware to the device. After the upload, arrange for
839 * device to re-enumerate.
841 * NOTE : the pointer to the firmware data given by request_firmware()
842 * is not suitable for an usb transaction.
845 int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
847 const struct firmware *fw_entry = 0;
852 static const char *fw_files_29xxx[] = {
853 "v4l-pvrusb2-29xxx-01.fw",
855 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
856 static const char *fw_files_24xxx[] = {
857 "v4l-pvrusb2-24xxx-01.fw",
860 static const struct pvr2_string_table fw_file_defs[] = {
861 [PVR2_HDW_TYPE_29XXX] = {
863 sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
865 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
866 [PVR2_HDW_TYPE_24XXX] = {
868 sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
872 hdw->fw1_state = FW1_STATE_FAILED; // default result
874 trace_firmware("pvr2_upload_firmware1");
876 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
877 fw_file_defs[hdw->hdw_type].cnt,
878 fw_file_defs[hdw->hdw_type].lst);
880 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
884 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
885 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
887 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
889 if (fw_entry->size != 0x2000){
890 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
891 release_firmware(fw_entry);
895 fw_ptr = kmalloc(0x800, GFP_KERNEL);
897 release_firmware(fw_entry);
901 /* We have to hold the CPU during firmware upload. */
902 pvr2_hdw_cpureset_assert(hdw,1);
904 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
908 for(address = 0; address < fw_entry->size; address += 0x800) {
909 memcpy(fw_ptr, fw_entry->data + address, 0x800);
910 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
911 0, fw_ptr, 0x800, HZ);
914 trace_firmware("Upload done, releasing device's CPU");
916 /* Now release the CPU. It will disconnect and reconnect later. */
917 pvr2_hdw_cpureset_assert(hdw,0);
920 release_firmware(fw_entry);
922 trace_firmware("Upload done (%d bytes sent)",ret);
924 /* We should have written 8192 bytes */
926 hdw->fw1_state = FW1_STATE_RELOAD;
935 * pvr2_upload_firmware2()
937 * This uploads encoder firmware on endpoint 2.
941 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
943 const struct firmware *fw_entry = 0;
945 unsigned int pipe, fw_len, fw_done;
949 static const char *fw_files[] = {
950 CX2341X_FIRM_ENC_FILENAME,
953 trace_firmware("pvr2_upload_firmware2");
955 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
956 sizeof(fw_files)/sizeof(fw_files[0]),
958 if (ret < 0) return ret;
962 /* First prepare firmware loading */
963 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
964 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
965 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
966 ret |= pvr2_hdw_cmd_deep_reset(hdw);
967 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
968 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
969 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
970 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
971 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
972 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
973 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
974 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
975 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
976 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
977 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
978 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
979 ret |= pvr2_write_u8(hdw, 0x52, 0);
980 ret |= pvr2_write_u16(hdw, 0x0600, 0);
983 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
984 "firmware2 upload prep failed, ret=%d",ret);
985 release_firmware(fw_entry);
989 /* Now send firmware */
991 fw_len = fw_entry->size;
993 if (fw_len % FIRMWARE_CHUNK_SIZE) {
994 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
995 "size of %s firmware"
996 " must be a multiple of 8192B",
998 release_firmware(fw_entry);
1002 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1003 if (fw_ptr == NULL){
1004 release_firmware(fw_entry);
1005 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1006 "failed to allocate memory for firmware2 upload");
1010 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1012 for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1013 fw_done += FIRMWARE_CHUNK_SIZE ) {
1015 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1016 /* Usbsnoop log shows that we must swap bytes... */
1017 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1018 ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1020 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1021 FIRMWARE_CHUNK_SIZE,
1022 &actual_length, HZ);
1023 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1026 trace_firmware("upload of %s : %i / %i ",
1027 fw_files[fwidx],fw_done,fw_len);
1030 release_firmware(fw_entry);
1033 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1034 "firmware2 upload transfer failure");
1040 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1041 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1042 ret |= pvr2_write_u16(hdw, 0x0600, 0);
1045 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1046 "firmware2 upload post-proc failure");
1048 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1054 #define FIRMWARE_RECOVERY_BITS \
1055 ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1056 (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1057 (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1058 (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1062 This single function is key to pretty much everything. The pvrusb2
1063 device can logically be viewed as a series of subsystems which can be
1064 stopped / started or unconfigured / configured. To get things streaming,
1065 one must configure everything and start everything, but there may be
1066 various reasons over time to deconfigure something or stop something.
1067 This function handles all of this activity. Everything EVERYWHERE that
1068 must affect a subsystem eventually comes here to do the work.
1070 The current state of all subsystems is represented by a single bit mask,
1071 known as subsys_enabled_mask. The bit positions are defined by the
1072 PVR2_SUBSYS_xxxx macros, with one subsystem per bit position. At any
1073 time the set of configured or active subsystems can be queried just by
1074 looking at that mask. To change bits in that mask, this function here
1075 must be called. The "msk" argument indicates which bit positions to
1076 change, and the "val" argument defines the new values for the positions
1079 There is a priority ordering of starting / stopping things, and for
1080 multiple requested changes, this function implements that ordering.
1081 (Thus we will act on a request to load encoder firmware before we
1082 configure the encoder.) In addition to priority ordering, there is a
1083 recovery strategy implemented here. If a particular step fails and we
1084 detect that failure, this function will clear the affected subsystem bits
1085 and restart. Thus we have a means for recovering from a dead encoder:
1086 Clear all bits that correspond to subsystems that we need to restart /
1087 reconfigure and start over.
1090 void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1091 unsigned long msk,unsigned long val)
1096 unsigned int tryCount = 0;
1098 if (!hdw->flag_ok) return;
1100 msk &= PVR2_SUBSYS_ALL;
1101 nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1102 nmsk &= PVR2_SUBSYS_ALL;
1106 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1107 PVR2_SUBSYS_ALL)) break;
1109 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1110 "Too many retries when configuring device;"
1112 pvr2_hdw_render_useless(hdw);
1116 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1117 "Retrying device reconfiguration");
1119 pvr2_trace(PVR2_TRACE_INIT,
1120 "subsys mask changing 0x%lx:0x%lx"
1121 " from 0x%lx to 0x%lx",
1122 msk,val,hdw->subsys_enabled_mask,nmsk);
1124 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1125 hdw->subsys_enabled_mask;
1127 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1128 pvr2_trace(PVR2_TRACE_CTL,
1129 "/*---TRACE_CTL----*/"
1130 " pvr2_encoder_stop");
1131 ret = pvr2_encoder_stop(hdw);
1133 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1134 "Error recovery initiated");
1135 hdw->subsys_enabled_mask &=
1136 ~FIRMWARE_RECOVERY_BITS;
1140 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1141 pvr2_trace(PVR2_TRACE_CTL,
1142 "/*---TRACE_CTL----*/"
1143 " pvr2_hdw_cmd_usbstream(0)");
1144 pvr2_hdw_cmd_usbstream(hdw,0);
1146 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1147 pvr2_trace(PVR2_TRACE_CTL,
1148 "/*---TRACE_CTL----*/"
1149 " decoder disable");
1150 if (hdw->decoder_ctrl) {
1151 hdw->decoder_ctrl->enable(
1152 hdw->decoder_ctrl->ctxt,0);
1154 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1156 " No decoder present");
1158 hdw->subsys_enabled_mask &=
1159 ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1161 if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1162 hdw->subsys_enabled_mask &=
1163 ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1166 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1168 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1169 pvr2_trace(PVR2_TRACE_CTL,
1170 "/*---TRACE_CTL----*/"
1171 " pvr2_upload_firmware2");
1172 ret = pvr2_upload_firmware2(hdw);
1174 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1175 "Failure uploading encoder"
1177 pvr2_hdw_render_useless(hdw);
1181 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1182 pvr2_trace(PVR2_TRACE_CTL,
1183 "/*---TRACE_CTL----*/"
1184 " pvr2_encoder_configure");
1185 ret = pvr2_encoder_configure(hdw);
1187 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1188 "Error recovery initiated");
1189 hdw->subsys_enabled_mask &=
1190 ~FIRMWARE_RECOVERY_BITS;
1194 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1195 pvr2_trace(PVR2_TRACE_CTL,
1196 "/*---TRACE_CTL----*/"
1198 if (hdw->decoder_ctrl) {
1199 hdw->decoder_ctrl->enable(
1200 hdw->decoder_ctrl->ctxt,!0);
1202 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1204 " No decoder present");
1206 hdw->subsys_enabled_mask |=
1207 (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1209 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1210 pvr2_trace(PVR2_TRACE_CTL,
1211 "/*---TRACE_CTL----*/"
1212 " pvr2_hdw_cmd_usbstream(1)");
1213 pvr2_hdw_cmd_usbstream(hdw,!0);
1215 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1216 pvr2_trace(PVR2_TRACE_CTL,
1217 "/*---TRACE_CTL----*/"
1218 " pvr2_encoder_start");
1219 ret = pvr2_encoder_start(hdw);
1221 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1222 "Error recovery initiated");
1223 hdw->subsys_enabled_mask &=
1224 ~FIRMWARE_RECOVERY_BITS;
1233 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1234 unsigned long msk,unsigned long val)
1236 LOCK_TAKE(hdw->big_lock); do {
1237 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1238 } while (0); LOCK_GIVE(hdw->big_lock);
1242 void pvr2_hdw_subsys_bit_set(struct pvr2_hdw *hdw,unsigned long msk)
1244 pvr2_hdw_subsys_bit_chg(hdw,msk,msk);
1248 void pvr2_hdw_subsys_bit_clr(struct pvr2_hdw *hdw,unsigned long msk)
1250 pvr2_hdw_subsys_bit_chg(hdw,msk,0);
1254 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1256 return hdw->subsys_enabled_mask;
1260 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1262 return hdw->subsys_stream_mask;
1266 void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1271 msk &= PVR2_SUBSYS_ALL;
1272 val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1273 pvr2_trace(PVR2_TRACE_INIT,
1274 "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1275 msk,val,hdw->subsys_stream_mask,val2);
1276 hdw->subsys_stream_mask = val2;
1280 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1284 LOCK_TAKE(hdw->big_lock); do {
1285 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1286 } while (0); LOCK_GIVE(hdw->big_lock);
1290 int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1292 if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1294 pvr2_trace(PVR2_TRACE_START_STOP,
1295 "/*--TRACE_STREAM--*/ enable");
1296 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1298 pvr2_trace(PVR2_TRACE_START_STOP,
1299 "/*--TRACE_STREAM--*/ disable");
1300 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1302 if (!hdw->flag_ok) return -EIO;
1303 hdw->flag_streaming_enabled = enableFl != 0;
1308 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1310 return hdw->flag_streaming_enabled != 0;
1314 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1317 LOCK_TAKE(hdw->big_lock); do {
1318 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1319 } while (0); LOCK_GIVE(hdw->big_lock);
1324 int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1325 enum pvr2_config config)
1327 unsigned long sm = hdw->subsys_enabled_mask;
1328 if (!hdw->flag_ok) return -EIO;
1329 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1330 hdw->config = config;
1331 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1336 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1339 if (!hdw->flag_ok) return -EIO;
1340 LOCK_TAKE(hdw->big_lock);
1341 ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1342 LOCK_GIVE(hdw->big_lock);
1347 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1349 int unit_number = hdw->unit_number;
1351 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1352 tp = tuner[unit_number];
1354 if (tp < 0) return -EINVAL;
1355 hdw->tuner_type = tp;
1360 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1362 int unit_number = hdw->unit_number;
1364 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1365 tp = video_std[unit_number];
1371 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1373 int unit_number = hdw->unit_number;
1375 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1376 tp = tolerance[unit_number];
1382 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1384 /* Try a harmless request to fetch the eeprom's address over
1385 endpoint 1. See what happens. Only the full FX2 image can
1386 respond to this. If this probe fails then likely the FX2
1387 firmware needs be loaded. */
1389 LOCK_TAKE(hdw->ctl_lock); do {
1390 hdw->cmd_buffer[0] = 0xeb;
1391 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1394 if (result < 0) break;
1395 } while(0); LOCK_GIVE(hdw->ctl_lock);
1397 pvr2_trace(PVR2_TRACE_INIT,
1398 "Probe of device endpoint 1 result status %d",
1401 pvr2_trace(PVR2_TRACE_INIT,
1402 "Probe of device endpoint 1 succeeded");
1407 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1411 v4l2_std_id std1,std2;
1413 std1 = get_default_standard(hdw);
1415 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1416 pvr2_trace(PVR2_TRACE_INIT,
1417 "Supported video standard(s) reported by eeprom: %.*s",
1420 hdw->std_mask_avail = hdw->std_mask_eeprom;
1422 std2 = std1 & ~hdw->std_mask_avail;
1424 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1425 pvr2_trace(PVR2_TRACE_INIT,
1426 "Expanding supported video standards"
1427 " to include: %.*s",
1429 hdw->std_mask_avail |= std2;
1432 pvr2_hdw_internal_set_std_avail(hdw);
1435 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1436 pvr2_trace(PVR2_TRACE_INIT,
1437 "Initial video standard forced to %.*s",
1439 hdw->std_mask_cur = std1;
1440 hdw->std_dirty = !0;
1441 pvr2_hdw_internal_find_stdenum(hdw);
1445 if (hdw->std_enum_cnt > 1) {
1446 // Autoselect the first listed standard
1447 hdw->std_enum_cur = 1;
1448 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1449 hdw->std_dirty = !0;
1450 pvr2_trace(PVR2_TRACE_INIT,
1451 "Initial video standard auto-selected to %s",
1452 hdw->std_defs[hdw->std_enum_cur-1].name);
1456 pvr2_trace(PVR2_TRACE_EEPROM,
1457 "Unable to select a viable initial video standard");
1461 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1465 struct pvr2_ctrl *cptr;
1468 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1471 pvr2_trace(PVR2_TRACE_INIT,
1472 "USB endpoint config looks strange"
1473 "; possibly firmware needs to be loaded");
1477 reloadFl = !pvr2_hdw_check_firmware(hdw);
1479 pvr2_trace(PVR2_TRACE_INIT,
1480 "Check for FX2 firmware failed"
1481 "; possibly firmware needs to be loaded");
1485 if (pvr2_upload_firmware1(hdw) != 0) {
1486 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1487 "Failure uploading firmware1");
1491 hdw->fw1_state = FW1_STATE_OK;
1494 pvr2_hdw_device_reset(hdw);
1496 if (!pvr2_hdw_dev_ok(hdw)) return;
1498 for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1499 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1502 pvr2_hdw_cmd_powerup(hdw);
1503 if (!pvr2_hdw_dev_ok(hdw)) return;
1505 if (pvr2_upload_firmware2(hdw)){
1506 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1507 pvr2_hdw_render_useless(hdw);
1511 // This step MUST happen after the earlier powerup step.
1512 pvr2_i2c_core_init(hdw);
1513 if (!pvr2_hdw_dev_ok(hdw)) return;
1515 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1516 cptr = hdw->controls + idx;
1517 if (cptr->info->skip_init) continue;
1518 if (!cptr->info->set_value) continue;
1519 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1522 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1523 // thread-safe against the normal pvr2_send_request() mechanism.
1524 // (We should make it thread safe).
1526 ret = pvr2_hdw_get_eeprom_addr(hdw);
1527 if (!pvr2_hdw_dev_ok(hdw)) return;
1529 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1530 "Unable to determine location of eeprom, skipping");
1532 hdw->eeprom_addr = ret;
1533 pvr2_eeprom_analyze(hdw);
1534 if (!pvr2_hdw_dev_ok(hdw)) return;
1537 pvr2_hdw_setup_std(hdw);
1539 if (!get_default_tuner_type(hdw)) {
1540 pvr2_trace(PVR2_TRACE_INIT,
1541 "pvr2_hdw_setup: Tuner type overridden to %d",
1545 hdw->tuner_updated = !0;
1546 pvr2_i2c_core_check_stale(hdw);
1547 hdw->tuner_updated = 0;
1549 if (!pvr2_hdw_dev_ok(hdw)) return;
1551 pvr2_hdw_commit_ctl_internal(hdw);
1552 if (!pvr2_hdw_dev_ok(hdw)) return;
1554 hdw->vid_stream = pvr2_stream_create();
1555 if (!pvr2_hdw_dev_ok(hdw)) return;
1556 pvr2_trace(PVR2_TRACE_INIT,
1557 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1558 if (hdw->vid_stream) {
1559 idx = get_default_error_tolerance(hdw);
1561 pvr2_trace(PVR2_TRACE_INIT,
1562 "pvr2_hdw_setup: video stream %p"
1563 " setting tolerance %u",
1564 hdw->vid_stream,idx);
1566 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1567 PVR2_VID_ENDPOINT,idx);
1570 if (!pvr2_hdw_dev_ok(hdw)) return;
1572 /* Make sure everything is up to date */
1573 pvr2_i2c_core_sync(hdw);
1575 if (!pvr2_hdw_dev_ok(hdw)) return;
1577 hdw->flag_init_ok = !0;
1581 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1583 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1584 LOCK_TAKE(hdw->big_lock); do {
1585 pvr2_hdw_setup_low(hdw);
1586 pvr2_trace(PVR2_TRACE_INIT,
1587 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1588 hdw,hdw->flag_ok,hdw->flag_init_ok);
1589 if (pvr2_hdw_dev_ok(hdw)) {
1590 if (pvr2_hdw_init_ok(hdw)) {
1593 "Device initialization"
1594 " completed successfully.");
1597 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1600 "Device microcontroller firmware"
1601 " (re)loaded; it should now reset"
1606 PVR2_TRACE_ERROR_LEGS,
1607 "Device initialization was not successful.");
1608 if (hdw->fw1_state == FW1_STATE_MISSING) {
1610 PVR2_TRACE_ERROR_LEGS,
1611 "Giving up since device"
1612 " microcontroller firmware"
1613 " appears to be missing.");
1619 PVR2_TRACE_ERROR_LEGS,
1620 "Attempting pvrusb2 recovery by reloading"
1621 " primary firmware.");
1623 PVR2_TRACE_ERROR_LEGS,
1624 "If this works, device should disconnect"
1625 " and reconnect in a sane state.");
1626 hdw->fw1_state = FW1_STATE_UNKNOWN;
1627 pvr2_upload_firmware1(hdw);
1630 PVR2_TRACE_ERROR_LEGS,
1631 "***WARNING*** pvrusb2 device hardware"
1632 " appears to be jammed"
1633 " and I can't clear it.");
1635 PVR2_TRACE_ERROR_LEGS,
1636 "You might need to power cycle"
1637 " the pvrusb2 device"
1638 " in order to recover.");
1640 } while (0); LOCK_GIVE(hdw->big_lock);
1641 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1642 return hdw->flag_init_ok;
1646 /* Create and return a structure for interacting with the underlying
1648 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1649 const struct usb_device_id *devid)
1651 unsigned int idx,cnt1,cnt2;
1652 struct pvr2_hdw *hdw;
1653 unsigned int hdw_type;
1655 struct pvr2_ctrl *cptr;
1658 hdw_type = devid - pvr2_device_table;
1660 sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1661 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1662 "Bogus device type of %u reported",hdw_type);
1666 hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1667 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1668 hdw,pvr2_device_names[hdw_type]);
1669 if (!hdw) goto fail;
1670 memset(hdw,0,sizeof(*hdw));
1672 hdw->control_cnt = CTRLDEF_COUNT;
1673 hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1675 if (!hdw->controls) goto fail;
1676 memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
1677 hdw->hdw_type = hdw_type;
1678 for (idx = 0; idx < hdw->control_cnt; idx++) {
1679 cptr = hdw->controls + idx;
1682 for (idx = 0; idx < 32; idx++) {
1683 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1685 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1686 cptr = hdw->controls + idx;
1687 cptr->info = control_defs+idx;
1690 // Initialize video standard enum dynamic control
1691 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1693 memcpy(&hdw->std_info_enum,cptr->info,
1694 sizeof(hdw->std_info_enum));
1695 cptr->info = &hdw->std_info_enum;
1698 // Initialize control data regarding video standard masks
1699 valid_std_mask = pvr2_std_get_usable();
1700 for (idx = 0; idx < 32; idx++) {
1701 if (!(valid_std_mask & (1 << idx))) continue;
1702 cnt1 = pvr2_std_id_to_str(
1703 hdw->std_mask_names[idx],
1704 sizeof(hdw->std_mask_names[idx])-1,
1706 hdw->std_mask_names[idx][cnt1] = 0;
1708 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1710 memcpy(&hdw->std_info_avail,cptr->info,
1711 sizeof(hdw->std_info_avail));
1712 cptr->info = &hdw->std_info_avail;
1713 hdw->std_info_avail.def.type_bitmask.bit_names =
1715 hdw->std_info_avail.def.type_bitmask.valid_bits =
1718 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1720 memcpy(&hdw->std_info_cur,cptr->info,
1721 sizeof(hdw->std_info_cur));
1722 cptr->info = &hdw->std_info_cur;
1723 hdw->std_info_cur.def.type_bitmask.bit_names =
1725 hdw->std_info_avail.def.type_bitmask.valid_bits =
1729 hdw->eeprom_addr = -1;
1730 hdw->unit_number = -1;
1731 hdw->v4l_minor_number = -1;
1732 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1733 if (!hdw->ctl_write_buffer) goto fail;
1734 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1735 if (!hdw->ctl_read_buffer) goto fail;
1736 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1737 if (!hdw->ctl_write_urb) goto fail;
1738 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1739 if (!hdw->ctl_read_urb) goto fail;
1741 down(&pvr2_unit_sem); do {
1742 for (idx = 0; idx < PVR_NUM; idx++) {
1743 if (unit_pointers[idx]) continue;
1744 hdw->unit_number = idx;
1745 unit_pointers[idx] = hdw;
1748 } while (0); up(&pvr2_unit_sem);
1751 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1753 if (hdw->unit_number >= 0) {
1754 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1755 ('a' + hdw->unit_number));
1758 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1759 hdw->name[cnt1] = 0;
1761 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1762 hdw->unit_number,hdw->name);
1764 hdw->tuner_type = -1;
1766 /* Initialize the mask of subsystems that we will shut down when we
1768 hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1769 hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1771 pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1772 hdw->subsys_stream_mask);
1774 hdw->usb_intf = intf;
1775 hdw->usb_dev = interface_to_usbdev(intf);
1777 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1778 usb_set_interface(hdw->usb_dev,ifnum,0);
1780 mutex_init(&hdw->ctl_lock_mutex);
1781 mutex_init(&hdw->big_lock_mutex);
1786 if (hdw->ctl_read_urb) usb_free_urb(hdw->ctl_read_urb);
1787 if (hdw->ctl_write_urb) usb_free_urb(hdw->ctl_write_urb);
1788 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1789 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1790 if (hdw->controls) kfree(hdw->controls);
1797 /* Remove _all_ associations between this driver and the underlying USB
1799 void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1801 if (hdw->flag_disconnected) return;
1802 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1803 if (hdw->ctl_read_urb) {
1804 usb_kill_urb(hdw->ctl_read_urb);
1805 usb_free_urb(hdw->ctl_read_urb);
1806 hdw->ctl_read_urb = 0;
1808 if (hdw->ctl_write_urb) {
1809 usb_kill_urb(hdw->ctl_write_urb);
1810 usb_free_urb(hdw->ctl_write_urb);
1811 hdw->ctl_write_urb = 0;
1813 if (hdw->ctl_read_buffer) {
1814 kfree(hdw->ctl_read_buffer);
1815 hdw->ctl_read_buffer = 0;
1817 if (hdw->ctl_write_buffer) {
1818 kfree(hdw->ctl_write_buffer);
1819 hdw->ctl_write_buffer = 0;
1821 pvr2_hdw_render_useless_unlocked(hdw);
1822 hdw->flag_disconnected = !0;
1828 /* Destroy hardware interaction structure */
1829 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
1831 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
1832 if (hdw->fw_buffer) {
1833 kfree(hdw->fw_buffer);
1836 if (hdw->vid_stream) {
1837 pvr2_stream_destroy(hdw->vid_stream);
1838 hdw->vid_stream = 0;
1840 if (hdw->audio_stat) {
1841 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
1843 if (hdw->decoder_ctrl) {
1844 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
1846 pvr2_i2c_core_done(hdw);
1847 pvr2_hdw_remove_usb_stuff(hdw);
1848 down(&pvr2_unit_sem); do {
1849 if ((hdw->unit_number >= 0) &&
1850 (hdw->unit_number < PVR_NUM) &&
1851 (unit_pointers[hdw->unit_number] == hdw)) {
1852 unit_pointers[hdw->unit_number] = 0;
1854 } while (0); up(&pvr2_unit_sem);
1855 if (hdw->controls) kfree(hdw->controls);
1856 if (hdw->std_defs) kfree(hdw->std_defs);
1857 if (hdw->std_enum_names) kfree(hdw->std_enum_names);
1862 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
1864 return hdw->flag_init_ok;
1868 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
1870 return (hdw && hdw->flag_ok);
1874 /* Called when hardware has been unplugged */
1875 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
1877 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
1878 LOCK_TAKE(hdw->big_lock);
1879 LOCK_TAKE(hdw->ctl_lock);
1880 pvr2_hdw_remove_usb_stuff(hdw);
1881 LOCK_GIVE(hdw->ctl_lock);
1882 LOCK_GIVE(hdw->big_lock);
1886 // Attempt to autoselect an appropriate value for std_enum_cur given
1887 // whatever is currently in std_mask_cur
1888 void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
1891 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
1892 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
1893 hdw->std_enum_cur = idx;
1897 hdw->std_enum_cur = 0;
1901 // Calculate correct set of enumerated standards based on currently known
1902 // set of available standards bits.
1903 void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
1905 struct v4l2_standard *newstd;
1906 unsigned int std_cnt;
1909 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
1911 if (hdw->std_defs) {
1912 kfree(hdw->std_defs);
1915 hdw->std_enum_cnt = 0;
1916 if (hdw->std_enum_names) {
1917 kfree(hdw->std_enum_names);
1918 hdw->std_enum_names = 0;
1923 PVR2_TRACE_ERROR_LEGS,
1924 "WARNING: Failed to identify any viable standards");
1926 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
1927 hdw->std_enum_names[0] = "none";
1928 for (idx = 0; idx < std_cnt; idx++) {
1929 hdw->std_enum_names[idx+1] =
1932 // Set up the dynamic control for this standard
1933 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
1934 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
1935 hdw->std_defs = newstd;
1936 hdw->std_enum_cnt = std_cnt+1;
1937 hdw->std_enum_cur = 0;
1938 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1942 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
1943 struct v4l2_standard *std,
1947 if (!idx) return ret;
1948 LOCK_TAKE(hdw->big_lock); do {
1949 if (idx >= hdw->std_enum_cnt) break;
1951 memcpy(std,hdw->std_defs+idx,sizeof(*std));
1953 } while (0); LOCK_GIVE(hdw->big_lock);
1958 /* Get the number of defined controls */
1959 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
1961 return hdw->control_cnt;
1965 /* Retrieve a control handle given its index (0..count-1) */
1966 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
1969 if (idx >= hdw->control_cnt) return 0;
1970 return hdw->controls + idx;
1974 /* Retrieve a control handle given its index (0..count-1) */
1975 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
1976 unsigned int ctl_id)
1978 struct pvr2_ctrl *cptr;
1982 /* This could be made a lot more efficient, but for now... */
1983 for (idx = 0; idx < hdw->control_cnt; idx++) {
1984 cptr = hdw->controls + idx;
1985 i = cptr->info->internal_id;
1986 if (i && (i == ctl_id)) return cptr;
1992 /* Given a V4L ID, retrieve the control structure associated with it. */
1993 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
1995 struct pvr2_ctrl *cptr;
1999 /* This could be made a lot more efficient, but for now... */
2000 for (idx = 0; idx < hdw->control_cnt; idx++) {
2001 cptr = hdw->controls + idx;
2002 i = cptr->info->v4l_id;
2003 if (i && (i == ctl_id)) return cptr;
2009 /* Given a V4L ID for its immediate predecessor, retrieve the control
2010 structure associated with it. */
2011 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2012 unsigned int ctl_id)
2014 struct pvr2_ctrl *cptr,*cp2;
2018 /* This could be made a lot more efficient, but for now... */
2020 for (idx = 0; idx < hdw->control_cnt; idx++) {
2021 cptr = hdw->controls + idx;
2022 i = cptr->info->v4l_id;
2024 if (i <= ctl_id) continue;
2025 if (cp2 && (cp2->info->v4l_id < i)) continue;
2033 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2036 case pvr2_ctl_int: return "integer";
2037 case pvr2_ctl_enum: return "enum";
2038 case pvr2_ctl_bool: return "boolean";
2039 case pvr2_ctl_bitmask: return "bitmask";
2045 /* Commit all control changes made up to this point. Subsystems can be
2046 indirectly affected by these changes. For a given set of things being
2047 committed, we'll clear the affected subsystem bits and then once we're
2048 done committing everything we'll make a request to restore the subsystem
2049 state(s) back to their previous value before this function was called.
2050 Thus we can automatically reconfigure affected pieces of the driver as
2051 controls are changed. */
2052 int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2054 unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2055 unsigned long stale_subsys_mask = 0;
2057 struct pvr2_ctrl *cptr;
2059 int commit_flag = 0;
2061 unsigned int bcnt,ccnt;
2063 for (idx = 0; idx < hdw->control_cnt; idx++) {
2064 cptr = hdw->controls + idx;
2065 if (cptr->info->is_dirty == 0) continue;
2066 if (!cptr->info->is_dirty(cptr)) continue;
2071 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2074 cptr->info->get_value(cptr,&value);
2075 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2077 sizeof(buf)-bcnt,&ccnt);
2079 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2080 get_ctrl_typename(cptr->info->type));
2081 pvr2_trace(PVR2_TRACE_CTL,
2082 "/*--TRACE_COMMIT--*/ %.*s",
2087 /* Nothing has changed */
2091 /* When video standard changes, reset the hres and vres values -
2092 but if the user has pending changes there, then let the changes
2094 if (hdw->std_dirty) {
2095 /* Rewrite the vertical resolution to be appropriate to the
2096 video standard that has been selected. */
2098 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2103 if (nvres != hdw->res_ver_val) {
2104 hdw->res_ver_val = nvres;
2105 hdw->res_ver_dirty = !0;
2107 if (!hdw->interlace_val) {
2108 hdw->interlace_val = 0;
2109 hdw->interlace_dirty = !0;
2113 if (hdw->std_dirty ||
2115 /* If any of this changes, then the encoder needs to be
2116 reconfigured, and we need to reset the stream. */
2117 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2118 stale_subsys_mask |= hdw->subsys_stream_mask;
2122 /* Scan i2c core at this point - before we clear all the dirty
2123 bits. Various parts of the i2c core will notice dirty bits as
2124 appropriate and arrange to broadcast or directly send updates to
2125 the client drivers in order to keep everything in sync */
2126 pvr2_i2c_core_check_stale(hdw);
2128 for (idx = 0; idx < hdw->control_cnt; idx++) {
2129 cptr = hdw->controls + idx;
2130 if (!cptr->info->clear_dirty) continue;
2131 cptr->info->clear_dirty(cptr);
2134 /* Now execute i2c core update */
2135 pvr2_i2c_core_sync(hdw);
2137 pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2138 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2144 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2146 LOCK_TAKE(hdw->big_lock); do {
2147 pvr2_hdw_commit_ctl_internal(hdw);
2148 } while (0); LOCK_GIVE(hdw->big_lock);
2153 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2155 LOCK_TAKE(hdw->big_lock); do {
2156 pvr2_i2c_core_sync(hdw);
2157 } while (0); LOCK_GIVE(hdw->big_lock);
2161 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2162 void (*func)(void *),
2165 LOCK_TAKE(hdw->big_lock); do {
2166 hdw->poll_trigger_func = func;
2167 hdw->poll_trigger_data = data;
2168 } while (0); LOCK_GIVE(hdw->big_lock);
2172 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2174 if (hdw->poll_trigger_func) {
2175 hdw->poll_trigger_func(hdw->poll_trigger_data);
2180 void pvr2_hdw_poll_trigger(struct pvr2_hdw *hdw)
2182 LOCK_TAKE(hdw->big_lock); do {
2183 pvr2_hdw_poll_trigger_unlocked(hdw);
2184 } while (0); LOCK_GIVE(hdw->big_lock);
2188 /* Return name for this driver instance */
2189 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2195 /* Return bit mask indicating signal status */
2196 unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2198 unsigned int msk = 0;
2199 switch (hdw->input_val) {
2200 case PVR2_CVAL_INPUT_TV:
2201 case PVR2_CVAL_INPUT_RADIO:
2202 if (hdw->decoder_ctrl &&
2203 hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2204 msk |= PVR2_SIGNAL_OK;
2205 if (hdw->audio_stat &&
2206 hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2207 if (hdw->flag_stereo) {
2208 msk |= PVR2_SIGNAL_STEREO;
2210 if (hdw->flag_bilingual) {
2211 msk |= PVR2_SIGNAL_SAP;
2217 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2223 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2226 LOCK_TAKE(hdw->ctl_lock); do {
2227 hdw->cmd_buffer[0] = 0x0b;
2228 result = pvr2_send_request(hdw,
2231 if (result < 0) break;
2232 result = (hdw->cmd_buffer[0] != 0);
2233 } while(0); LOCK_GIVE(hdw->ctl_lock);
2238 /* Return bit mask indicating signal status */
2239 unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2241 unsigned int msk = 0;
2242 LOCK_TAKE(hdw->big_lock); do {
2243 msk = pvr2_hdw_get_signal_status_internal(hdw);
2244 } while (0); LOCK_GIVE(hdw->big_lock);
2249 /* Get handle to video output stream */
2250 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2252 return hp->vid_stream;
2256 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2258 int nr = pvr2_hdw_get_unit_number(hdw);
2259 LOCK_TAKE(hdw->big_lock); do {
2260 hdw->log_requested = !0;
2261 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
2262 pvr2_i2c_core_check_stale(hdw);
2263 hdw->log_requested = 0;
2264 pvr2_i2c_core_sync(hdw);
2265 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
2266 } while (0); LOCK_GIVE(hdw->big_lock);
2269 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2274 LOCK_TAKE(hdw->big_lock); do {
2275 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2278 pvr2_trace(PVR2_TRACE_FIRMWARE,
2279 "Cleaning up after CPU firmware fetch");
2280 kfree(hdw->fw_buffer);
2283 /* Now release the CPU. It will disconnect and
2285 pvr2_hdw_cpureset_assert(hdw,0);
2289 pvr2_trace(PVR2_TRACE_FIRMWARE,
2290 "Preparing to suck out CPU firmware");
2291 hdw->fw_size = 0x2000;
2292 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2293 if (!hdw->fw_buffer) {
2298 memset(hdw->fw_buffer,0,hdw->fw_size);
2300 /* We have to hold the CPU during firmware upload. */
2301 pvr2_hdw_cpureset_assert(hdw,1);
2303 /* download the firmware from address 0000-1fff in 2048
2304 (=0x800) bytes chunk. */
2306 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2307 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2308 for(address = 0; address < hdw->fw_size; address += 0x800) {
2309 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2311 hdw->fw_buffer+address,0x800,HZ);
2315 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2317 } while (0); LOCK_GIVE(hdw->big_lock);
2321 /* Return true if we're in a mode for retrieval CPU firmware */
2322 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2324 return hdw->fw_buffer != 0;
2328 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2329 char *buf,unsigned int cnt)
2332 LOCK_TAKE(hdw->big_lock); do {
2336 if (!hdw->fw_buffer) {
2341 if (offs >= hdw->fw_size) {
2342 pvr2_trace(PVR2_TRACE_FIRMWARE,
2343 "Read firmware data offs=%d EOF",
2349 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2351 memcpy(buf,hdw->fw_buffer+offs,cnt);
2353 pvr2_trace(PVR2_TRACE_FIRMWARE,
2354 "Read firmware data offs=%d cnt=%d",
2357 } while (0); LOCK_GIVE(hdw->big_lock);
2363 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2365 return hdw->v4l_minor_number;
2369 /* Store the v4l minor device number */
2370 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2372 hdw->v4l_minor_number = v;
2376 void pvr2_reset_ctl_endpoints(struct pvr2_hdw *hdw)
2378 if (!hdw->usb_dev) return;
2379 usb_settoggle(hdw->usb_dev, PVR2_CTL_WRITE_ENDPOINT & 0xf,
2380 !(PVR2_CTL_WRITE_ENDPOINT & USB_DIR_IN), 0);
2381 usb_settoggle(hdw->usb_dev, PVR2_CTL_READ_ENDPOINT & 0xf,
2382 !(PVR2_CTL_READ_ENDPOINT & USB_DIR_IN), 0);
2383 usb_clear_halt(hdw->usb_dev,
2384 usb_rcvbulkpipe(hdw->usb_dev,
2385 PVR2_CTL_READ_ENDPOINT & 0x7f));
2386 usb_clear_halt(hdw->usb_dev,
2387 usb_sndbulkpipe(hdw->usb_dev,
2388 PVR2_CTL_WRITE_ENDPOINT & 0x7f));
2392 static void pvr2_ctl_write_complete(struct urb *urb, struct pt_regs *regs)
2394 struct pvr2_hdw *hdw = urb->context;
2395 hdw->ctl_write_pend_flag = 0;
2396 if (hdw->ctl_read_pend_flag) return;
2397 complete(&hdw->ctl_done);
2401 static void pvr2_ctl_read_complete(struct urb *urb, struct pt_regs *regs)
2403 struct pvr2_hdw *hdw = urb->context;
2404 hdw->ctl_read_pend_flag = 0;
2405 if (hdw->ctl_write_pend_flag) return;
2406 complete(&hdw->ctl_done);
2410 static void pvr2_ctl_timeout(unsigned long data)
2412 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2413 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2414 hdw->ctl_timeout_flag = !0;
2415 if (hdw->ctl_write_pend_flag && hdw->ctl_write_urb) {
2416 usb_unlink_urb(hdw->ctl_write_urb);
2418 if (hdw->ctl_read_pend_flag && hdw->ctl_read_urb) {
2419 usb_unlink_urb(hdw->ctl_read_urb);
2425 int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2426 unsigned int timeout,int probe_fl,
2427 void *write_data,unsigned int write_len,
2428 void *read_data,unsigned int read_len)
2432 struct timer_list timer;
2433 if (!hdw->ctl_lock_held) {
2434 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2435 "Attempted to execute control transfer"
2439 if ((!hdw->flag_ok) && !probe_fl) {
2440 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2441 "Attempted to execute control transfer"
2442 " when device not ok");
2445 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2447 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2448 "Attempted to execute control transfer"
2449 " when USB is disconnected");
2454 /* Ensure that we have sane parameters */
2455 if (!write_data) write_len = 0;
2456 if (!read_data) read_len = 0;
2457 if (write_len > PVR2_CTL_BUFFSIZE) {
2459 PVR2_TRACE_ERROR_LEGS,
2460 "Attempted to execute %d byte"
2461 " control-write transfer (limit=%d)",
2462 write_len,PVR2_CTL_BUFFSIZE);
2465 if (read_len > PVR2_CTL_BUFFSIZE) {
2467 PVR2_TRACE_ERROR_LEGS,
2468 "Attempted to execute %d byte"
2469 " control-read transfer (limit=%d)",
2470 write_len,PVR2_CTL_BUFFSIZE);
2473 if ((!write_len) && (!read_len)) {
2475 PVR2_TRACE_ERROR_LEGS,
2476 "Attempted to execute null control transfer?");
2481 hdw->cmd_debug_state = 1;
2483 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2485 hdw->cmd_debug_code = 0;
2487 hdw->cmd_debug_write_len = write_len;
2488 hdw->cmd_debug_read_len = read_len;
2490 /* Initialize common stuff */
2491 init_completion(&hdw->ctl_done);
2492 hdw->ctl_timeout_flag = 0;
2493 hdw->ctl_write_pend_flag = 0;
2494 hdw->ctl_read_pend_flag = 0;
2496 timer.expires = jiffies + timeout;
2497 timer.data = (unsigned long)hdw;
2498 timer.function = pvr2_ctl_timeout;
2501 hdw->cmd_debug_state = 2;
2502 /* Transfer write data to internal buffer */
2503 for (idx = 0; idx < write_len; idx++) {
2504 hdw->ctl_write_buffer[idx] =
2505 ((unsigned char *)write_data)[idx];
2507 /* Initiate a write request */
2508 usb_fill_bulk_urb(hdw->ctl_write_urb,
2510 usb_sndbulkpipe(hdw->usb_dev,
2511 PVR2_CTL_WRITE_ENDPOINT),
2512 hdw->ctl_write_buffer,
2514 pvr2_ctl_write_complete,
2516 hdw->ctl_write_urb->actual_length = 0;
2517 hdw->ctl_write_pend_flag = !0;
2518 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2520 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2521 "Failed to submit write-control"
2522 " URB status=%d",status);
2523 hdw->ctl_write_pend_flag = 0;
2529 hdw->cmd_debug_state = 3;
2530 memset(hdw->ctl_read_buffer,0x43,read_len);
2531 /* Initiate a read request */
2532 usb_fill_bulk_urb(hdw->ctl_read_urb,
2534 usb_rcvbulkpipe(hdw->usb_dev,
2535 PVR2_CTL_READ_ENDPOINT),
2536 hdw->ctl_read_buffer,
2538 pvr2_ctl_read_complete,
2540 hdw->ctl_read_urb->actual_length = 0;
2541 hdw->ctl_read_pend_flag = !0;
2542 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2544 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2545 "Failed to submit read-control"
2546 " URB status=%d",status);
2547 hdw->ctl_read_pend_flag = 0;
2555 /* Now wait for all I/O to complete */
2556 hdw->cmd_debug_state = 4;
2557 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2558 wait_for_completion(&hdw->ctl_done);
2560 hdw->cmd_debug_state = 5;
2563 del_timer_sync(&timer);
2565 hdw->cmd_debug_state = 6;
2568 if (hdw->ctl_timeout_flag) {
2569 status = -ETIMEDOUT;
2571 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2572 "Timed out control-write");
2578 /* Validate results of write request */
2579 if ((hdw->ctl_write_urb->status != 0) &&
2580 (hdw->ctl_write_urb->status != -ENOENT) &&
2581 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2582 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2583 /* USB subsystem is reporting some kind of failure
2585 status = hdw->ctl_write_urb->status;
2587 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2588 "control-write URB failure,"
2594 if (hdw->ctl_write_urb->actual_length < write_len) {
2595 /* Failed to write enough data */
2598 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2599 "control-write URB short,"
2600 " expected=%d got=%d",
2602 hdw->ctl_write_urb->actual_length);
2608 /* Validate results of read request */
2609 if ((hdw->ctl_read_urb->status != 0) &&
2610 (hdw->ctl_read_urb->status != -ENOENT) &&
2611 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2612 (hdw->ctl_read_urb->status != -ECONNRESET)) {
2613 /* USB subsystem is reporting some kind of failure
2615 status = hdw->ctl_read_urb->status;
2617 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2618 "control-read URB failure,"
2624 if (hdw->ctl_read_urb->actual_length < read_len) {
2625 /* Failed to read enough data */
2628 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2629 "control-read URB short,"
2630 " expected=%d got=%d",
2632 hdw->ctl_read_urb->actual_length);
2636 /* Transfer retrieved data out from internal buffer */
2637 for (idx = 0; idx < read_len; idx++) {
2638 ((unsigned char *)read_data)[idx] =
2639 hdw->ctl_read_buffer[idx];
2645 hdw->cmd_debug_state = 0;
2646 if ((status < 0) && (!probe_fl)) {
2647 pvr2_hdw_render_useless_unlocked(hdw);
2653 int pvr2_send_request(struct pvr2_hdw *hdw,
2654 void *write_data,unsigned int write_len,
2655 void *read_data,unsigned int read_len)
2657 return pvr2_send_request_ex(hdw,HZ*4,0,
2658 write_data,write_len,
2659 read_data,read_len);
2662 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2666 LOCK_TAKE(hdw->ctl_lock);
2668 hdw->cmd_buffer[0] = 0x04; /* write register prefix */
2669 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2670 hdw->cmd_buffer[5] = 0;
2671 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2672 hdw->cmd_buffer[7] = reg & 0xff;
2675 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2677 LOCK_GIVE(hdw->ctl_lock);
2683 int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2687 LOCK_TAKE(hdw->ctl_lock);
2689 hdw->cmd_buffer[0] = 0x05; /* read register prefix */
2690 hdw->cmd_buffer[1] = 0;
2691 hdw->cmd_buffer[2] = 0;
2692 hdw->cmd_buffer[3] = 0;
2693 hdw->cmd_buffer[4] = 0;
2694 hdw->cmd_buffer[5] = 0;
2695 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2696 hdw->cmd_buffer[7] = reg & 0xff;
2698 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2699 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2701 LOCK_GIVE(hdw->ctl_lock);
2707 int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2711 LOCK_TAKE(hdw->ctl_lock);
2713 hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2714 hdw->cmd_buffer[1] = data & 0xff;
2716 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2718 LOCK_GIVE(hdw->ctl_lock);
2724 int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2728 LOCK_TAKE(hdw->ctl_lock);
2730 hdw->cmd_buffer[0] = data;
2732 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2734 LOCK_GIVE(hdw->ctl_lock);
2740 void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2742 if (!hdw->flag_ok) return;
2743 pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2745 if (hdw->vid_stream) {
2746 pvr2_stream_setup(hdw->vid_stream,0,0,0);
2748 hdw->flag_streaming_enabled = 0;
2749 hdw->subsys_enabled_mask = 0;
2753 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2755 LOCK_TAKE(hdw->ctl_lock);
2756 pvr2_hdw_render_useless_unlocked(hdw);
2757 LOCK_GIVE(hdw->ctl_lock);
2761 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2764 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2765 ret = usb_lock_device_for_reset(hdw->usb_dev,0);
2767 ret = usb_reset_device(hdw->usb_dev);
2768 usb_unlock_device(hdw->usb_dev);
2770 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2771 "Failed to lock USB device ret=%d",ret);
2773 if (init_pause_msec) {
2774 pvr2_trace(PVR2_TRACE_INFO,
2775 "Waiting %u msec for hardware to settle",
2777 msleep(init_pause_msec);
2783 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2789 if (!hdw->usb_dev) return;
2791 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2793 da[0] = val ? 0x01 : 0x00;
2795 /* Write the CPUCS register on the 8051. The lsb of the register
2796 is the reset bit; a 1 asserts reset while a 0 clears it. */
2797 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2798 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2800 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2801 "cpureset_assert(%d) error=%d",val,ret);
2802 pvr2_hdw_render_useless(hdw);
2807 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2810 LOCK_TAKE(hdw->ctl_lock); do {
2811 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2813 hdw->cmd_buffer[0] = 0xdd;
2814 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2815 } while (0); LOCK_GIVE(hdw->ctl_lock);
2820 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2823 LOCK_TAKE(hdw->ctl_lock); do {
2824 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2825 hdw->cmd_buffer[0] = 0xde;
2826 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2827 } while (0); LOCK_GIVE(hdw->ctl_lock);
2832 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
2834 if (!hdw->decoder_ctrl) {
2835 pvr2_trace(PVR2_TRACE_INIT,
2836 "Unable to reset decoder: nothing attached");
2840 if (!hdw->decoder_ctrl->force_reset) {
2841 pvr2_trace(PVR2_TRACE_INIT,
2842 "Unable to reset decoder: not implemented");
2846 pvr2_trace(PVR2_TRACE_INIT,
2847 "Requesting decoder reset");
2848 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
2853 int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
2856 LOCK_TAKE(hdw->ctl_lock); do {
2857 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
2858 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2859 } while (0); LOCK_GIVE(hdw->ctl_lock);
2861 hdw->subsys_enabled_mask =
2862 ((hdw->subsys_enabled_mask &
2863 ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
2864 (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
2870 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
2871 struct pvr2_hdw_debug_info *ptr)
2873 ptr->big_lock_held = hdw->big_lock_held;
2874 ptr->ctl_lock_held = hdw->ctl_lock_held;
2875 ptr->flag_ok = hdw->flag_ok;
2876 ptr->flag_disconnected = hdw->flag_disconnected;
2877 ptr->flag_init_ok = hdw->flag_init_ok;
2878 ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
2879 ptr->subsys_flags = hdw->subsys_enabled_mask;
2880 ptr->cmd_debug_state = hdw->cmd_debug_state;
2881 ptr->cmd_code = hdw->cmd_debug_code;
2882 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
2883 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
2884 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
2885 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
2886 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
2887 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
2888 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
2892 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
2894 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
2898 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
2900 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
2904 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
2906 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
2910 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
2915 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
2916 if (ret) return ret;
2917 nval = (cval & ~msk) | (val & msk);
2918 pvr2_trace(PVR2_TRACE_GPIO,
2919 "GPIO direction changing 0x%x:0x%x"
2920 " from 0x%x to 0x%x",
2924 pvr2_trace(PVR2_TRACE_GPIO,
2925 "GPIO direction changing to 0x%x",nval);
2927 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
2931 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
2936 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
2937 if (ret) return ret;
2938 nval = (cval & ~msk) | (val & msk);
2939 pvr2_trace(PVR2_TRACE_GPIO,
2940 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
2944 pvr2_trace(PVR2_TRACE_GPIO,
2945 "GPIO output changing to 0x%x",nval);
2947 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
2951 int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
2954 LOCK_TAKE(hdw->ctl_lock); do {
2955 hdw->cmd_buffer[0] = 0xeb;
2956 result = pvr2_send_request(hdw,
2959 if (result < 0) break;
2960 result = hdw->cmd_buffer[0];
2961 } while(0); LOCK_GIVE(hdw->ctl_lock);
2967 Stuff for Emacs to see, in order to encourage consistent editing style:
2968 *** Local Variables: ***
2970 *** fill-column: 75 ***
2971 *** tab-width: 8 ***
2972 *** c-basic-offset: 8 ***