5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/errno.h>
23 #include <linux/string.h>
24 #include <linux/slab.h>
25 #include <linux/firmware.h>
26 #include <linux/videodev2.h>
27 #include <asm/semaphore.h>
29 #include "pvrusb2-std.h"
30 #include "pvrusb2-util.h"
31 #include "pvrusb2-hdw.h"
32 #include "pvrusb2-i2c-core.h"
33 #include "pvrusb2-tuner.h"
34 #include "pvrusb2-eeprom.h"
35 #include "pvrusb2-hdw-internal.h"
36 #include "pvrusb2-encoder.h"
37 #include "pvrusb2-debug.h"
39 struct usb_device_id pvr2_device_table[] = {
40 [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
41 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
42 [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
47 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
49 static const char *pvr2_device_names[] = {
50 [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
51 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
52 [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
56 struct pvr2_string_table {
61 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
62 // Names of other client modules to request for 24xxx model hardware
63 static const char *pvr2_client_24xxx[] = {
71 // Names of other client modules to request for 29xxx model hardware
72 static const char *pvr2_client_29xxx[] = {
79 static struct pvr2_string_table pvr2_client_lists[] = {
80 [PVR2_HDW_TYPE_29XXX] = {
82 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
84 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
85 [PVR2_HDW_TYPE_24XXX] = {
87 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
92 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = 0};
93 DECLARE_MUTEX(pvr2_unit_sem);
95 static int ctlchg = 0;
96 static int initusbreset = 1;
97 static int procreload = 0;
98 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
99 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
100 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
101 static int init_pause_msec = 0;
103 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
104 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
105 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
106 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
107 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
108 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
109 module_param(procreload, int, S_IRUGO|S_IWUSR);
110 MODULE_PARM_DESC(procreload,
111 "Attempt init failure recovery with firmware reload");
112 module_param_array(tuner, int, NULL, 0444);
113 MODULE_PARM_DESC(tuner,"specify installed tuner type");
114 module_param_array(video_std, int, NULL, 0444);
115 MODULE_PARM_DESC(video_std,"specify initial video standard");
116 module_param_array(tolerance, int, NULL, 0444);
117 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
119 #define PVR2_CTL_WRITE_ENDPOINT 0x01
120 #define PVR2_CTL_READ_ENDPOINT 0x81
122 #define PVR2_GPIO_IN 0x9008
123 #define PVR2_GPIO_OUT 0x900c
124 #define PVR2_GPIO_DIR 0x9020
126 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
128 #define PVR2_FIRMWARE_ENDPOINT 0x02
130 /* size of a firmware chunk */
131 #define FIRMWARE_CHUNK_SIZE 0x2000
134 static const char *control_values_srate[] = {
135 [PVR2_CVAL_SRATE_48] = "48KHz",
136 [PVR2_CVAL_SRATE_44_1] = "44.1KHz",
140 static const char *control_values_audiobitrate[] = {
141 [PVR2_CVAL_AUDIOBITRATE_384] = "384kb/s",
142 [PVR2_CVAL_AUDIOBITRATE_320] = "320kb/s",
143 [PVR2_CVAL_AUDIOBITRATE_256] = "256kb/s",
144 [PVR2_CVAL_AUDIOBITRATE_224] = "224kb/s",
145 [PVR2_CVAL_AUDIOBITRATE_192] = "192kb/s",
146 [PVR2_CVAL_AUDIOBITRATE_160] = "160kb/s",
147 [PVR2_CVAL_AUDIOBITRATE_128] = "128kb/s",
148 [PVR2_CVAL_AUDIOBITRATE_112] = "112kb/s",
149 [PVR2_CVAL_AUDIOBITRATE_96] = "96kb/s",
150 [PVR2_CVAL_AUDIOBITRATE_80] = "80kb/s",
151 [PVR2_CVAL_AUDIOBITRATE_64] = "64kb/s",
152 [PVR2_CVAL_AUDIOBITRATE_56] = "56kb/s",
153 [PVR2_CVAL_AUDIOBITRATE_48] = "48kb/s",
154 [PVR2_CVAL_AUDIOBITRATE_32] = "32kb/s",
155 [PVR2_CVAL_AUDIOBITRATE_VBR] = "VBR",
159 static const char *control_values_audioemphasis[] = {
160 [PVR2_CVAL_AUDIOEMPHASIS_NONE] = "None",
161 [PVR2_CVAL_AUDIOEMPHASIS_50_15] = "50/15us",
162 [PVR2_CVAL_AUDIOEMPHASIS_CCITT] = "CCITT J.17",
166 static const char *control_values_input[] = {
167 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
168 [PVR2_CVAL_INPUT_RADIO] = "radio",
169 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
170 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
174 static const char *control_values_audiomode[] = {
175 [V4L2_TUNER_MODE_MONO] = "Mono",
176 [V4L2_TUNER_MODE_STEREO] = "Stereo",
177 [V4L2_TUNER_MODE_LANG1] = "Lang1",
178 [V4L2_TUNER_MODE_LANG2] = "Lang2",
179 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
183 static const char *control_values_hsm[] = {
184 [PVR2_CVAL_HSM_FAIL] = "Fail",
185 [PVR2_CVAL_HSM_HIGH] = "High",
186 [PVR2_CVAL_HSM_FULL] = "Full",
190 static const char *control_values_subsystem[] = {
191 [PVR2_SUBSYS_B_ENC_FIRMWARE] = "enc_firmware",
192 [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
193 [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
194 [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
195 [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
199 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
201 struct pvr2_hdw *hdw = cptr->hdw;
202 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
203 *vp = hdw->freqTable[hdw->freqProgSlot-1];
210 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
212 struct pvr2_hdw *hdw = cptr->hdw;
213 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
214 hdw->freqTable[hdw->freqProgSlot-1] = v;
219 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
221 *vp = cptr->hdw->freqProgSlot;
225 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
227 struct pvr2_hdw *hdw = cptr->hdw;
228 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
229 hdw->freqProgSlot = v;
234 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
236 *vp = cptr->hdw->freqSlot;
240 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
243 struct pvr2_hdw *hdw = cptr->hdw;
245 if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
246 freq = hdw->freqTable[hdw->freqSlot-1];
248 if (freq && (freq != hdw->freqVal)) {
255 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
257 *vp = cptr->hdw->freqVal;
261 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
263 return cptr->hdw->freqDirty != 0;
266 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
268 cptr->hdw->freqDirty = 0;
271 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
273 struct pvr2_hdw *hdw = cptr->hdw;
280 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
282 *vp = cptr->hdw->flag_streaming_enabled;
286 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
288 int result = pvr2_hdw_is_hsm(cptr->hdw);
289 *vp = PVR2_CVAL_HSM_FULL;
290 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
291 if (result) *vp = PVR2_CVAL_HSM_HIGH;
295 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
297 *vp = cptr->hdw->std_mask_avail;
301 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
303 struct pvr2_hdw *hdw = cptr->hdw;
305 ns = hdw->std_mask_avail;
306 ns = (ns & ~m) | (v & m);
307 if (ns == hdw->std_mask_avail) return 0;
308 hdw->std_mask_avail = ns;
309 pvr2_hdw_internal_set_std_avail(hdw);
310 pvr2_hdw_internal_find_stdenum(hdw);
314 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
315 char *bufPtr,unsigned int bufSize,
318 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
322 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
323 const char *bufPtr,unsigned int bufSize,
328 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
329 if (ret < 0) return ret;
330 if (mskp) *mskp = id;
331 if (valp) *valp = id;
335 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
337 *vp = cptr->hdw->std_mask_cur;
341 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
343 struct pvr2_hdw *hdw = cptr->hdw;
345 ns = hdw->std_mask_cur;
346 ns = (ns & ~m) | (v & m);
347 if (ns == hdw->std_mask_cur) return 0;
348 hdw->std_mask_cur = ns;
350 pvr2_hdw_internal_find_stdenum(hdw);
354 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
356 return cptr->hdw->std_dirty != 0;
359 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
361 cptr->hdw->std_dirty = 0;
364 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
366 *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
367 PVR2_SIGNAL_OK) ? 1 : 0);
371 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
373 *vp = cptr->hdw->subsys_enabled_mask;
377 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
379 pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
383 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
385 *vp = cptr->hdw->subsys_stream_mask;
389 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
391 pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
395 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
397 struct pvr2_hdw *hdw = cptr->hdw;
398 if (v < 0) return -EINVAL;
399 if (v > hdw->std_enum_cnt) return -EINVAL;
400 hdw->std_enum_cur = v;
403 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
404 hdw->std_mask_cur = hdw->std_defs[v].id;
410 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
412 *vp = cptr->hdw->std_enum_cur;
417 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
419 return cptr->hdw->std_dirty != 0;
423 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
425 cptr->hdw->std_dirty = 0;
429 #define DEFINT(vmin,vmax) \
430 .type = pvr2_ctl_int, \
431 .def.type_int.min_value = vmin, \
432 .def.type_int.max_value = vmax
434 #define DEFENUM(tab) \
435 .type = pvr2_ctl_enum, \
436 .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
437 .def.type_enum.value_names = tab
439 #define DEFMASK(msk,tab) \
440 .type = pvr2_ctl_bitmask, \
441 .def.type_bitmask.valid_bits = msk, \
442 .def.type_bitmask.bit_names = tab
444 #define DEFREF(vname) \
445 .set_value = ctrl_set_##vname, \
446 .get_value = ctrl_get_##vname, \
447 .is_dirty = ctrl_isdirty_##vname, \
448 .clear_dirty = ctrl_cleardirty_##vname
451 #define VCREATE_FUNCS(vname) \
452 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
453 {*vp = cptr->hdw->vname##_val; return 0;} \
454 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
455 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
456 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
457 {return cptr->hdw->vname##_dirty != 0;} \
458 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
459 {cptr->hdw->vname##_dirty = 0;}
461 VCREATE_FUNCS(brightness)
462 VCREATE_FUNCS(contrast)
463 VCREATE_FUNCS(saturation)
465 VCREATE_FUNCS(volume)
466 VCREATE_FUNCS(balance)
468 VCREATE_FUNCS(treble)
471 VCREATE_FUNCS(audiomode)
472 VCREATE_FUNCS(res_hor)
473 VCREATE_FUNCS(res_ver)
475 VCREATE_FUNCS(audiobitrate)
476 VCREATE_FUNCS(audiocrc)
477 VCREATE_FUNCS(audioemphasis)
479 VCREATE_FUNCS(videobitrate)
480 VCREATE_FUNCS(videopeak)
481 VCREATE_FUNCS(interlace)
482 VCREATE_FUNCS(audiolayer)
484 #define MIN_FREQ 55250000L
485 #define MAX_FREQ 850000000L
487 /* Table definition of all controls which can be manipulated */
488 static const struct pvr2_ctl_info control_defs[] = {
490 .v4l_id = V4L2_CID_BRIGHTNESS,
491 .desc = "Brightness",
492 .name = "brightness",
493 .default_value = 128,
497 .v4l_id = V4L2_CID_CONTRAST,
504 .v4l_id = V4L2_CID_SATURATION,
505 .desc = "Saturation",
506 .name = "saturation",
511 .v4l_id = V4L2_CID_HUE,
518 .v4l_id = V4L2_CID_AUDIO_VOLUME,
521 .default_value = 65535,
525 .v4l_id = V4L2_CID_AUDIO_BALANCE,
530 DEFINT(-32768,32767),
532 .v4l_id = V4L2_CID_AUDIO_BASS,
537 DEFINT(-32768,32767),
539 .v4l_id = V4L2_CID_AUDIO_TREBLE,
544 DEFINT(-32768,32767),
546 .v4l_id = V4L2_CID_AUDIO_MUTE,
553 .desc = "Video Source",
555 .internal_id = PVR2_CID_INPUT,
556 .default_value = PVR2_CVAL_INPUT_TV,
558 DEFENUM(control_values_input),
560 .desc = "Audio Mode",
561 .name = "audio_mode",
562 .internal_id = PVR2_CID_AUDIOMODE,
563 .default_value = V4L2_TUNER_MODE_STEREO,
565 DEFENUM(control_values_audiomode),
567 .desc = "Horizontal capture resolution",
568 .name = "resolution_hor",
569 .internal_id = PVR2_CID_HRES,
570 .default_value = 720,
574 .desc = "Vertical capture resolution",
575 .name = "resolution_ver",
576 .internal_id = PVR2_CID_VRES,
577 .default_value = 480,
581 .v4l_id = V4L2_CID_PVR_SRATE,
582 .desc = "Sample rate",
584 .default_value = PVR2_CVAL_SRATE_48,
586 DEFENUM(control_values_srate),
588 .v4l_id = V4L2_CID_PVR_AUDIOBITRATE,
589 .desc = "Audio Bitrate",
590 .name = "audio_bitrate",
591 .default_value = PVR2_CVAL_AUDIOBITRATE_224,
592 DEFREF(audiobitrate),
593 DEFENUM(control_values_audiobitrate),
595 .v4l_id = V4L2_CID_PVR_AUDIOCRC,
602 .v4l_id = V4L2_CID_PVR_AUDIOEMPHASIS,
603 .desc = "Audio Emphasis",
604 .name = "audio_emphasis",
605 .default_value = PVR2_CVAL_AUDIOEMPHASIS_NONE,
606 DEFREF(audioemphasis),
607 DEFENUM(control_values_audioemphasis),
609 .v4l_id = V4L2_CID_PVR_VBR,
610 .desc = "Variable video bitrate",
616 .v4l_id = V4L2_CID_PVR_VIDEOBITRATE,
617 .desc = "Average video bitrate",
618 .name = "video_average_bitrate",
619 .default_value = 6000000,
620 DEFREF(videobitrate),
621 DEFINT(500000,20000000),
623 .v4l_id = V4L2_CID_PVR_VIDEOPEAK,
624 .desc = "Peak video bitrate",
625 .name = "video_peak_bitrate",
626 .default_value = 6000000,
628 DEFINT(500000,20000000),
630 .desc = "Interlace mode",
632 .internal_id = PVR2_CID_INTERLACE,
637 .desc = "Audio Layer",
638 .name = "audio_layer",
643 .desc = "Tuner Frequency (Hz)",
645 .internal_id = PVR2_CID_FREQUENCY,
646 .default_value = 175250000L,
647 .set_value = ctrl_freq_set,
648 .get_value = ctrl_freq_get,
649 .is_dirty = ctrl_freq_is_dirty,
650 .clear_dirty = ctrl_freq_clear_dirty,
651 DEFINT(MIN_FREQ,MAX_FREQ),
655 .set_value = ctrl_channel_set,
656 .get_value = ctrl_channel_get,
657 DEFINT(0,FREQTABLE_SIZE),
659 .desc = "Channel Program Frequency",
660 .name = "freq_table_value",
661 .set_value = ctrl_channelfreq_set,
662 .get_value = ctrl_channelfreq_get,
663 DEFINT(MIN_FREQ,MAX_FREQ),
665 .desc = "Channel Program ID",
666 .name = "freq_table_channel",
667 .set_value = ctrl_channelprog_set,
668 .get_value = ctrl_channelprog_get,
669 DEFINT(0,FREQTABLE_SIZE),
671 .desc = "Streaming Enabled",
672 .name = "streaming_enabled",
673 .get_value = ctrl_streamingenabled_get,
678 .get_value = ctrl_hsm_get,
679 DEFENUM(control_values_hsm),
681 .desc = "Signal Present",
682 .name = "signal_present",
683 .get_value = ctrl_signal_get,
686 .desc = "Video Standards Available Mask",
687 .name = "video_standard_mask_available",
688 .internal_id = PVR2_CID_STDAVAIL,
690 .get_value = ctrl_stdavail_get,
691 .set_value = ctrl_stdavail_set,
692 .val_to_sym = ctrl_std_val_to_sym,
693 .sym_to_val = ctrl_std_sym_to_val,
694 .type = pvr2_ctl_bitmask,
696 .desc = "Video Standards In Use Mask",
697 .name = "video_standard_mask_active",
698 .internal_id = PVR2_CID_STDCUR,
700 .get_value = ctrl_stdcur_get,
701 .set_value = ctrl_stdcur_set,
702 .is_dirty = ctrl_stdcur_is_dirty,
703 .clear_dirty = ctrl_stdcur_clear_dirty,
704 .val_to_sym = ctrl_std_val_to_sym,
705 .sym_to_val = ctrl_std_sym_to_val,
706 .type = pvr2_ctl_bitmask,
708 .desc = "Subsystem enabled mask",
709 .name = "debug_subsys_mask",
711 .get_value = ctrl_subsys_get,
712 .set_value = ctrl_subsys_set,
713 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
715 .desc = "Subsystem stream mask",
716 .name = "debug_subsys_stream_mask",
718 .get_value = ctrl_subsys_stream_get,
719 .set_value = ctrl_subsys_stream_set,
720 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
722 .desc = "Video Standard Name",
723 .name = "video_standard",
724 .internal_id = PVR2_CID_STDENUM,
726 .get_value = ctrl_stdenumcur_get,
727 .set_value = ctrl_stdenumcur_set,
728 .is_dirty = ctrl_stdenumcur_is_dirty,
729 .clear_dirty = ctrl_stdenumcur_clear_dirty,
730 .type = pvr2_ctl_enum,
734 #define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
737 const char *pvr2_config_get_name(enum pvr2_config cfg)
740 case pvr2_config_empty: return "empty";
741 case pvr2_config_mpeg: return "mpeg";
742 case pvr2_config_vbi: return "vbi";
743 case pvr2_config_radio: return "radio";
749 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
755 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
757 return hdw->serial_number;
761 struct pvr2_hdw *pvr2_hdw_find(int unit_number)
763 if (unit_number < 0) return 0;
764 if (unit_number >= PVR_NUM) return 0;
765 return unit_pointers[unit_number];
769 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
771 return hdw->unit_number;
775 /* Attempt to locate one of the given set of files. Messages are logged
776 appropriate to what has been found. The return value will be 0 or
777 greater on success (it will be the index of the file name found) and
778 fw_entry will be filled in. Otherwise a negative error is returned on
779 failure. If the return value is -ENOENT then no viable firmware file
781 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
782 const struct firmware **fw_entry,
783 const char *fwtypename,
784 unsigned int fwcount,
785 const char *fwnames[])
789 for (idx = 0; idx < fwcount; idx++) {
790 ret = request_firmware(fw_entry,
794 trace_firmware("Located %s firmware: %s;"
800 if (ret == -ENOENT) continue;
801 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
802 "request_firmware fatal error with code=%d",ret);
805 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
807 " Device %s firmware"
808 " seems to be missing.",
810 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
811 "Did you install the pvrusb2 firmware files"
812 " in their proper location?");
814 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
815 "request_firmware unable to locate %s file %s",
816 fwtypename,fwnames[0]);
818 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
819 "request_firmware unable to locate"
820 " one of the following %s files:",
822 for (idx = 0; idx < fwcount; idx++) {
823 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
824 "request_firmware: Failed to find %s",
833 * pvr2_upload_firmware1().
835 * Send the 8051 firmware to the device. After the upload, arrange for
836 * device to re-enumerate.
838 * NOTE : the pointer to the firmware data given by request_firmware()
839 * is not suitable for an usb transaction.
842 int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
844 const struct firmware *fw_entry = 0;
849 static const char *fw_files_29xxx[] = {
850 "v4l-pvrusb2-29xxx-01.fw",
852 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
853 static const char *fw_files_24xxx[] = {
854 "v4l-pvrusb2-24xxx-01.fw",
857 static const struct pvr2_string_table fw_file_defs[] = {
858 [PVR2_HDW_TYPE_29XXX] = {
860 sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
862 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
863 [PVR2_HDW_TYPE_24XXX] = {
865 sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
869 hdw->fw1_state = FW1_STATE_FAILED; // default result
871 trace_firmware("pvr2_upload_firmware1");
873 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
874 fw_file_defs[hdw->hdw_type].cnt,
875 fw_file_defs[hdw->hdw_type].lst);
877 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
881 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
882 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
884 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
886 if (fw_entry->size != 0x2000){
887 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
888 release_firmware(fw_entry);
892 fw_ptr = kmalloc(0x800, GFP_KERNEL);
894 release_firmware(fw_entry);
898 /* We have to hold the CPU during firmware upload. */
899 pvr2_hdw_cpureset_assert(hdw,1);
901 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
905 for(address = 0; address < fw_entry->size; address += 0x800) {
906 memcpy(fw_ptr, fw_entry->data + address, 0x800);
907 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
908 0, fw_ptr, 0x800, HZ);
911 trace_firmware("Upload done, releasing device's CPU");
913 /* Now release the CPU. It will disconnect and reconnect later. */
914 pvr2_hdw_cpureset_assert(hdw,0);
917 release_firmware(fw_entry);
919 trace_firmware("Upload done (%d bytes sent)",ret);
921 /* We should have written 8192 bytes */
923 hdw->fw1_state = FW1_STATE_RELOAD;
932 * pvr2_upload_firmware2()
934 * This uploads encoder firmware on endpoint 2.
938 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
940 const struct firmware *fw_entry = 0;
942 unsigned int pipe, fw_len, fw_done;
946 static const char *fw_files[] = {
947 CX2341X_FIRM_ENC_FILENAME,
950 trace_firmware("pvr2_upload_firmware2");
952 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
953 sizeof(fw_files)/sizeof(fw_files[0]),
955 if (ret < 0) return ret;
959 /* First prepare firmware loading */
960 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
961 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
962 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
963 ret |= pvr2_hdw_cmd_deep_reset(hdw);
964 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
965 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
966 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
967 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
968 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
969 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
970 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
971 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
972 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
973 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
974 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
975 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
976 ret |= pvr2_write_u8(hdw, 0x52, 0);
977 ret |= pvr2_write_u16(hdw, 0x0600, 0);
980 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
981 "firmware2 upload prep failed, ret=%d",ret);
982 release_firmware(fw_entry);
986 /* Now send firmware */
988 fw_len = fw_entry->size;
990 if (fw_len % FIRMWARE_CHUNK_SIZE) {
991 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
992 "size of %s firmware"
993 " must be a multiple of 8192B",
995 release_firmware(fw_entry);
999 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1000 if (fw_ptr == NULL){
1001 release_firmware(fw_entry);
1002 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1003 "failed to allocate memory for firmware2 upload");
1007 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1009 for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1010 fw_done += FIRMWARE_CHUNK_SIZE ) {
1012 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1013 /* Usbsnoop log shows that we must swap bytes... */
1014 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1015 ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1017 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1018 FIRMWARE_CHUNK_SIZE,
1019 &actual_length, HZ);
1020 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1023 trace_firmware("upload of %s : %i / %i ",
1024 fw_files[fwidx],fw_done,fw_len);
1027 release_firmware(fw_entry);
1030 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1031 "firmware2 upload transfer failure");
1037 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1038 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1039 ret |= pvr2_write_u16(hdw, 0x0600, 0);
1042 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1043 "firmware2 upload post-proc failure");
1045 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1051 #define FIRMWARE_RECOVERY_BITS \
1052 ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1053 (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1054 (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1055 (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1059 This single function is key to pretty much everything. The pvrusb2
1060 device can logically be viewed as a series of subsystems which can be
1061 stopped / started or unconfigured / configured. To get things streaming,
1062 one must configure everything and start everything, but there may be
1063 various reasons over time to deconfigure something or stop something.
1064 This function handles all of this activity. Everything EVERYWHERE that
1065 must affect a subsystem eventually comes here to do the work.
1067 The current state of all subsystems is represented by a single bit mask,
1068 known as subsys_enabled_mask. The bit positions are defined by the
1069 PVR2_SUBSYS_xxxx macros, with one subsystem per bit position. At any
1070 time the set of configured or active subsystems can be queried just by
1071 looking at that mask. To change bits in that mask, this function here
1072 must be called. The "msk" argument indicates which bit positions to
1073 change, and the "val" argument defines the new values for the positions
1076 There is a priority ordering of starting / stopping things, and for
1077 multiple requested changes, this function implements that ordering.
1078 (Thus we will act on a request to load encoder firmware before we
1079 configure the encoder.) In addition to priority ordering, there is a
1080 recovery strategy implemented here. If a particular step fails and we
1081 detect that failure, this function will clear the affected subsystem bits
1082 and restart. Thus we have a means for recovering from a dead encoder:
1083 Clear all bits that correspond to subsystems that we need to restart /
1084 reconfigure and start over.
1087 void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1088 unsigned long msk,unsigned long val)
1093 unsigned int tryCount = 0;
1095 if (!hdw->flag_ok) return;
1097 msk &= PVR2_SUBSYS_ALL;
1101 vmsk = hdw->subsys_enabled_mask & PVR2_SUBSYS_ALL;
1102 nmsk = (vmsk & ~msk) | (val & msk);
1103 if (!(nmsk ^ vmsk)) break;
1105 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1106 "Too many retries when configuring device;"
1108 pvr2_hdw_render_useless(hdw);
1112 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1113 "Retrying device reconfiguration");
1115 pvr2_trace(PVR2_TRACE_INIT,
1116 "subsys mask changing 0x%lx:0x%lx"
1117 " from 0x%lx to 0x%lx",
1118 msk,val,hdw->subsys_enabled_mask,nmsk);
1120 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1121 hdw->subsys_enabled_mask;
1123 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1124 pvr2_trace(PVR2_TRACE_CTL,
1125 "/*---TRACE_CTL----*/"
1126 " pvr2_encoder_stop");
1127 ret = pvr2_encoder_stop(hdw);
1129 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1130 "Error recovery initiated");
1131 hdw->subsys_enabled_mask &=
1132 ~FIRMWARE_RECOVERY_BITS;
1136 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1137 pvr2_trace(PVR2_TRACE_CTL,
1138 "/*---TRACE_CTL----*/"
1139 " pvr2_hdw_cmd_usbstream(0)");
1140 pvr2_hdw_cmd_usbstream(hdw,0);
1142 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1143 pvr2_trace(PVR2_TRACE_CTL,
1144 "/*---TRACE_CTL----*/"
1145 " decoder disable");
1146 if (hdw->decoder_ctrl) {
1147 hdw->decoder_ctrl->enable(
1148 hdw->decoder_ctrl->ctxt,0);
1150 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1152 " No decoder present");
1154 hdw->subsys_enabled_mask &=
1155 ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1157 if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1158 hdw->subsys_enabled_mask &=
1159 ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1162 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1164 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1165 pvr2_trace(PVR2_TRACE_CTL,
1166 "/*---TRACE_CTL----*/"
1167 " pvr2_upload_firmware2");
1168 ret = pvr2_upload_firmware2(hdw);
1170 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1171 "Failure uploading encoder"
1173 pvr2_hdw_render_useless(hdw);
1177 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1178 pvr2_trace(PVR2_TRACE_CTL,
1179 "/*---TRACE_CTL----*/"
1180 " pvr2_encoder_configure");
1181 ret = pvr2_encoder_configure(hdw);
1183 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1184 "Error recovery initiated");
1185 hdw->subsys_enabled_mask &=
1186 ~FIRMWARE_RECOVERY_BITS;
1190 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1191 pvr2_trace(PVR2_TRACE_CTL,
1192 "/*---TRACE_CTL----*/"
1194 if (hdw->decoder_ctrl) {
1195 hdw->decoder_ctrl->enable(
1196 hdw->decoder_ctrl->ctxt,!0);
1198 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1200 " No decoder present");
1202 hdw->subsys_enabled_mask |=
1203 (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1205 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1206 pvr2_trace(PVR2_TRACE_CTL,
1207 "/*---TRACE_CTL----*/"
1208 " pvr2_hdw_cmd_usbstream(1)");
1209 pvr2_hdw_cmd_usbstream(hdw,!0);
1211 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1212 pvr2_trace(PVR2_TRACE_CTL,
1213 "/*---TRACE_CTL----*/"
1214 " pvr2_encoder_start");
1215 ret = pvr2_encoder_start(hdw);
1217 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1218 "Error recovery initiated");
1219 hdw->subsys_enabled_mask &=
1220 ~FIRMWARE_RECOVERY_BITS;
1229 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1230 unsigned long msk,unsigned long val)
1232 LOCK_TAKE(hdw->big_lock); do {
1233 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1234 } while (0); LOCK_GIVE(hdw->big_lock);
1238 void pvr2_hdw_subsys_bit_set(struct pvr2_hdw *hdw,unsigned long msk)
1240 pvr2_hdw_subsys_bit_chg(hdw,msk,msk);
1244 void pvr2_hdw_subsys_bit_clr(struct pvr2_hdw *hdw,unsigned long msk)
1246 pvr2_hdw_subsys_bit_chg(hdw,msk,0);
1250 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1252 return hdw->subsys_enabled_mask;
1256 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1258 return hdw->subsys_stream_mask;
1262 void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1267 msk &= PVR2_SUBSYS_ALL;
1268 val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1269 pvr2_trace(PVR2_TRACE_INIT,
1270 "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1271 msk,val,hdw->subsys_stream_mask,val2);
1272 hdw->subsys_stream_mask = val2;
1276 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1280 LOCK_TAKE(hdw->big_lock); do {
1281 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1282 } while (0); LOCK_GIVE(hdw->big_lock);
1286 int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1288 if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1290 pvr2_trace(PVR2_TRACE_START_STOP,
1291 "/*--TRACE_STREAM--*/ enable");
1292 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1294 pvr2_trace(PVR2_TRACE_START_STOP,
1295 "/*--TRACE_STREAM--*/ disable");
1296 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1298 if (!hdw->flag_ok) return -EIO;
1299 hdw->flag_streaming_enabled = enableFl != 0;
1304 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1306 return hdw->flag_streaming_enabled != 0;
1310 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1313 LOCK_TAKE(hdw->big_lock); do {
1314 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1315 } while (0); LOCK_GIVE(hdw->big_lock);
1320 int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1321 enum pvr2_config config)
1323 unsigned long sm = hdw->subsys_enabled_mask;
1324 if (!hdw->flag_ok) return -EIO;
1325 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1326 hdw->config = config;
1327 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1332 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1335 if (!hdw->flag_ok) return -EIO;
1336 LOCK_TAKE(hdw->big_lock);
1337 ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1338 LOCK_GIVE(hdw->big_lock);
1343 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1345 int unit_number = hdw->unit_number;
1347 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1348 tp = tuner[unit_number];
1350 if (tp < 0) return -EINVAL;
1351 hdw->tuner_type = tp;
1356 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1358 int unit_number = hdw->unit_number;
1360 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1361 tp = video_std[unit_number];
1367 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1369 int unit_number = hdw->unit_number;
1371 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1372 tp = tolerance[unit_number];
1378 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1380 /* Try a harmless request to fetch the eeprom's address over
1381 endpoint 1. See what happens. Only the full FX2 image can
1382 respond to this. If this probe fails then likely the FX2
1383 firmware needs be loaded. */
1385 LOCK_TAKE(hdw->ctl_lock); do {
1386 hdw->cmd_buffer[0] = 0xeb;
1387 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1390 if (result < 0) break;
1391 } while(0); LOCK_GIVE(hdw->ctl_lock);
1393 pvr2_trace(PVR2_TRACE_INIT,
1394 "Probe of device endpoint 1 result status %d",
1397 pvr2_trace(PVR2_TRACE_INIT,
1398 "Probe of device endpoint 1 succeeded");
1403 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1407 v4l2_std_id std1,std2;
1409 std1 = get_default_standard(hdw);
1411 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1412 pvr2_trace(PVR2_TRACE_INIT,
1413 "Supported video standard(s) reported by eeprom: %.*s",
1416 hdw->std_mask_avail = hdw->std_mask_eeprom;
1418 std2 = std1 & ~hdw->std_mask_avail;
1420 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1421 pvr2_trace(PVR2_TRACE_INIT,
1422 "Expanding supported video standards"
1423 " to include: %.*s",
1425 hdw->std_mask_avail |= std2;
1428 pvr2_hdw_internal_set_std_avail(hdw);
1431 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1432 pvr2_trace(PVR2_TRACE_INIT,
1433 "Initial video standard forced to %.*s",
1435 hdw->std_mask_cur = std1;
1436 hdw->std_dirty = !0;
1437 pvr2_hdw_internal_find_stdenum(hdw);
1441 if (hdw->std_enum_cnt > 1) {
1442 // Autoselect the first listed standard
1443 hdw->std_enum_cur = 1;
1444 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1445 hdw->std_dirty = !0;
1446 pvr2_trace(PVR2_TRACE_INIT,
1447 "Initial video standard auto-selected to %s",
1448 hdw->std_defs[hdw->std_enum_cur-1].name);
1452 pvr2_trace(PVR2_TRACE_EEPROM,
1453 "Unable to select a viable initial video standard");
1457 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1461 struct pvr2_ctrl *cptr;
1464 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1467 pvr2_trace(PVR2_TRACE_INIT,
1468 "USB endpoint config looks strange"
1469 "; possibly firmware needs to be loaded");
1473 reloadFl = !pvr2_hdw_check_firmware(hdw);
1475 pvr2_trace(PVR2_TRACE_INIT,
1476 "Check for FX2 firmware failed"
1477 "; possibly firmware needs to be loaded");
1481 if (pvr2_upload_firmware1(hdw) != 0) {
1482 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1483 "Failure uploading firmware1");
1487 hdw->fw1_state = FW1_STATE_OK;
1490 pvr2_hdw_device_reset(hdw);
1492 if (!pvr2_hdw_dev_ok(hdw)) return;
1494 for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1495 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1498 pvr2_hdw_cmd_powerup(hdw);
1499 if (!pvr2_hdw_dev_ok(hdw)) return;
1501 if (pvr2_upload_firmware2(hdw)){
1502 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1503 pvr2_hdw_render_useless(hdw);
1507 // This step MUST happen after the earlier powerup step.
1508 pvr2_i2c_core_init(hdw);
1509 if (!pvr2_hdw_dev_ok(hdw)) return;
1511 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1512 cptr = hdw->controls + idx;
1513 if (cptr->info->skip_init) continue;
1514 if (!cptr->info->set_value) continue;
1515 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1518 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1519 // thread-safe against the normal pvr2_send_request() mechanism.
1520 // (We should make it thread safe).
1522 ret = pvr2_hdw_get_eeprom_addr(hdw);
1523 if (!pvr2_hdw_dev_ok(hdw)) return;
1525 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1526 "Unable to determine location of eeprom, skipping");
1528 hdw->eeprom_addr = ret;
1529 pvr2_eeprom_analyze(hdw);
1530 if (!pvr2_hdw_dev_ok(hdw)) return;
1533 pvr2_hdw_setup_std(hdw);
1535 if (!get_default_tuner_type(hdw)) {
1536 pvr2_trace(PVR2_TRACE_INIT,
1537 "pvr2_hdw_setup: Tuner type overridden to %d",
1541 hdw->tuner_updated = !0;
1542 pvr2_i2c_core_check_stale(hdw);
1543 hdw->tuner_updated = 0;
1545 if (!pvr2_hdw_dev_ok(hdw)) return;
1547 pvr2_hdw_commit_ctl_internal(hdw);
1548 if (!pvr2_hdw_dev_ok(hdw)) return;
1550 hdw->vid_stream = pvr2_stream_create();
1551 if (!pvr2_hdw_dev_ok(hdw)) return;
1552 pvr2_trace(PVR2_TRACE_INIT,
1553 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1554 if (hdw->vid_stream) {
1555 idx = get_default_error_tolerance(hdw);
1557 pvr2_trace(PVR2_TRACE_INIT,
1558 "pvr2_hdw_setup: video stream %p"
1559 " setting tolerance %u",
1560 hdw->vid_stream,idx);
1562 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1563 PVR2_VID_ENDPOINT,idx);
1566 if (!pvr2_hdw_dev_ok(hdw)) return;
1568 /* Make sure everything is up to date */
1569 pvr2_i2c_core_sync(hdw);
1571 if (!pvr2_hdw_dev_ok(hdw)) return;
1573 hdw->flag_init_ok = !0;
1577 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1579 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1580 LOCK_TAKE(hdw->big_lock); do {
1581 pvr2_hdw_setup_low(hdw);
1582 pvr2_trace(PVR2_TRACE_INIT,
1583 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1584 hdw,hdw->flag_ok,hdw->flag_init_ok);
1585 if (pvr2_hdw_dev_ok(hdw)) {
1586 if (pvr2_hdw_init_ok(hdw)) {
1589 "Device initialization"
1590 " completed successfully.");
1593 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1596 "Device microcontroller firmware"
1597 " (re)loaded; it should now reset"
1602 PVR2_TRACE_ERROR_LEGS,
1603 "Device initialization was not successful.");
1604 if (hdw->fw1_state == FW1_STATE_MISSING) {
1606 PVR2_TRACE_ERROR_LEGS,
1607 "Giving up since device"
1608 " microcontroller firmware"
1609 " appears to be missing.");
1615 PVR2_TRACE_ERROR_LEGS,
1616 "Attempting pvrusb2 recovery by reloading"
1617 " primary firmware.");
1619 PVR2_TRACE_ERROR_LEGS,
1620 "If this works, device should disconnect"
1621 " and reconnect in a sane state.");
1622 hdw->fw1_state = FW1_STATE_UNKNOWN;
1623 pvr2_upload_firmware1(hdw);
1626 PVR2_TRACE_ERROR_LEGS,
1627 "***WARNING*** pvrusb2 device hardware"
1628 " appears to be jammed"
1629 " and I can't clear it.");
1631 PVR2_TRACE_ERROR_LEGS,
1632 "You might need to power cycle"
1633 " the pvrusb2 device"
1634 " in order to recover.");
1636 } while (0); LOCK_GIVE(hdw->big_lock);
1637 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1638 return hdw->flag_init_ok;
1642 /* Create and return a structure for interacting with the underlying
1644 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1645 const struct usb_device_id *devid)
1647 unsigned int idx,cnt1,cnt2;
1648 struct pvr2_hdw *hdw;
1649 unsigned int hdw_type;
1651 struct pvr2_ctrl *cptr;
1654 hdw_type = devid - pvr2_device_table;
1656 sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1657 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1658 "Bogus device type of %u reported",hdw_type);
1662 hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1663 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1664 hdw,pvr2_device_names[hdw_type]);
1665 if (!hdw) goto fail;
1666 memset(hdw,0,sizeof(*hdw));
1668 hdw->control_cnt = CTRLDEF_COUNT;
1669 hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1671 if (!hdw->controls) goto fail;
1672 memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
1673 hdw->hdw_type = hdw_type;
1674 for (idx = 0; idx < hdw->control_cnt; idx++) {
1675 cptr = hdw->controls + idx;
1678 for (idx = 0; idx < 32; idx++) {
1679 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1681 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1682 cptr = hdw->controls + idx;
1683 cptr->info = control_defs+idx;
1686 // Initialize video standard enum dynamic control
1687 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1689 memcpy(&hdw->std_info_enum,cptr->info,
1690 sizeof(hdw->std_info_enum));
1691 cptr->info = &hdw->std_info_enum;
1694 // Initialize control data regarding video standard masks
1695 valid_std_mask = pvr2_std_get_usable();
1696 for (idx = 0; idx < 32; idx++) {
1697 if (!(valid_std_mask & (1 << idx))) continue;
1698 cnt1 = pvr2_std_id_to_str(
1699 hdw->std_mask_names[idx],
1700 sizeof(hdw->std_mask_names[idx])-1,
1702 hdw->std_mask_names[idx][cnt1] = 0;
1704 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1706 memcpy(&hdw->std_info_avail,cptr->info,
1707 sizeof(hdw->std_info_avail));
1708 cptr->info = &hdw->std_info_avail;
1709 hdw->std_info_avail.def.type_bitmask.bit_names =
1711 hdw->std_info_avail.def.type_bitmask.valid_bits =
1714 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1716 memcpy(&hdw->std_info_cur,cptr->info,
1717 sizeof(hdw->std_info_cur));
1718 cptr->info = &hdw->std_info_cur;
1719 hdw->std_info_cur.def.type_bitmask.bit_names =
1721 hdw->std_info_avail.def.type_bitmask.valid_bits =
1725 hdw->eeprom_addr = -1;
1726 hdw->unit_number = -1;
1727 hdw->v4l_minor_number = -1;
1728 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1729 if (!hdw->ctl_write_buffer) goto fail;
1730 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1731 if (!hdw->ctl_read_buffer) goto fail;
1732 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1733 if (!hdw->ctl_write_urb) goto fail;
1734 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1735 if (!hdw->ctl_read_urb) goto fail;
1737 down(&pvr2_unit_sem); do {
1738 for (idx = 0; idx < PVR_NUM; idx++) {
1739 if (unit_pointers[idx]) continue;
1740 hdw->unit_number = idx;
1741 unit_pointers[idx] = hdw;
1744 } while (0); up(&pvr2_unit_sem);
1747 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1749 if (hdw->unit_number >= 0) {
1750 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1751 ('a' + hdw->unit_number));
1754 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1755 hdw->name[cnt1] = 0;
1757 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1758 hdw->unit_number,hdw->name);
1760 hdw->tuner_type = -1;
1762 /* Initialize the mask of subsystems that we will shut down when we
1764 hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1765 hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1767 pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1768 hdw->subsys_stream_mask);
1770 hdw->usb_intf = intf;
1771 hdw->usb_dev = interface_to_usbdev(intf);
1773 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1774 usb_set_interface(hdw->usb_dev,ifnum,0);
1776 mutex_init(&hdw->ctl_lock_mutex);
1777 mutex_init(&hdw->big_lock_mutex);
1782 if (hdw->ctl_read_urb) usb_free_urb(hdw->ctl_read_urb);
1783 if (hdw->ctl_write_urb) usb_free_urb(hdw->ctl_write_urb);
1784 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1785 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1786 if (hdw->controls) kfree(hdw->controls);
1793 /* Remove _all_ associations between this driver and the underlying USB
1795 void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1797 if (hdw->flag_disconnected) return;
1798 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1799 if (hdw->ctl_read_urb) {
1800 usb_kill_urb(hdw->ctl_read_urb);
1801 usb_free_urb(hdw->ctl_read_urb);
1802 hdw->ctl_read_urb = 0;
1804 if (hdw->ctl_write_urb) {
1805 usb_kill_urb(hdw->ctl_write_urb);
1806 usb_free_urb(hdw->ctl_write_urb);
1807 hdw->ctl_write_urb = 0;
1809 if (hdw->ctl_read_buffer) {
1810 kfree(hdw->ctl_read_buffer);
1811 hdw->ctl_read_buffer = 0;
1813 if (hdw->ctl_write_buffer) {
1814 kfree(hdw->ctl_write_buffer);
1815 hdw->ctl_write_buffer = 0;
1817 pvr2_hdw_render_useless_unlocked(hdw);
1818 hdw->flag_disconnected = !0;
1824 /* Destroy hardware interaction structure */
1825 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
1827 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
1828 if (hdw->fw_buffer) {
1829 kfree(hdw->fw_buffer);
1832 if (hdw->vid_stream) {
1833 pvr2_stream_destroy(hdw->vid_stream);
1834 hdw->vid_stream = 0;
1836 if (hdw->audio_stat) {
1837 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
1839 if (hdw->decoder_ctrl) {
1840 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
1842 pvr2_i2c_core_done(hdw);
1843 pvr2_hdw_remove_usb_stuff(hdw);
1844 down(&pvr2_unit_sem); do {
1845 if ((hdw->unit_number >= 0) &&
1846 (hdw->unit_number < PVR_NUM) &&
1847 (unit_pointers[hdw->unit_number] == hdw)) {
1848 unit_pointers[hdw->unit_number] = 0;
1850 } while (0); up(&pvr2_unit_sem);
1851 if (hdw->controls) kfree(hdw->controls);
1852 if (hdw->std_defs) kfree(hdw->std_defs);
1853 if (hdw->std_enum_names) kfree(hdw->std_enum_names);
1858 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
1860 return hdw->flag_init_ok;
1864 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
1866 return (hdw && hdw->flag_ok);
1870 /* Called when hardware has been unplugged */
1871 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
1873 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
1874 LOCK_TAKE(hdw->big_lock);
1875 LOCK_TAKE(hdw->ctl_lock);
1876 pvr2_hdw_remove_usb_stuff(hdw);
1877 LOCK_GIVE(hdw->ctl_lock);
1878 LOCK_GIVE(hdw->big_lock);
1882 // Attempt to autoselect an appropriate value for std_enum_cur given
1883 // whatever is currently in std_mask_cur
1884 void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
1887 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
1888 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
1889 hdw->std_enum_cur = idx;
1893 hdw->std_enum_cur = 0;
1897 // Calculate correct set of enumerated standards based on currently known
1898 // set of available standards bits.
1899 void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
1901 struct v4l2_standard *newstd;
1902 unsigned int std_cnt;
1905 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
1907 if (hdw->std_defs) {
1908 kfree(hdw->std_defs);
1911 hdw->std_enum_cnt = 0;
1912 if (hdw->std_enum_names) {
1913 kfree(hdw->std_enum_names);
1914 hdw->std_enum_names = 0;
1919 PVR2_TRACE_ERROR_LEGS,
1920 "WARNING: Failed to identify any viable standards");
1922 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
1923 hdw->std_enum_names[0] = "none";
1924 for (idx = 0; idx < std_cnt; idx++) {
1925 hdw->std_enum_names[idx+1] =
1928 // Set up the dynamic control for this standard
1929 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
1930 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
1931 hdw->std_defs = newstd;
1932 hdw->std_enum_cnt = std_cnt+1;
1933 hdw->std_enum_cur = 0;
1934 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1938 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
1939 struct v4l2_standard *std,
1943 if (!idx) return ret;
1944 LOCK_TAKE(hdw->big_lock); do {
1945 if (idx >= hdw->std_enum_cnt) break;
1947 memcpy(std,hdw->std_defs+idx,sizeof(*std));
1949 } while (0); LOCK_GIVE(hdw->big_lock);
1954 /* Get the number of defined controls */
1955 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
1957 return hdw->control_cnt;
1961 /* Retrieve a control handle given its index (0..count-1) */
1962 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
1965 if (idx >= hdw->control_cnt) return 0;
1966 return hdw->controls + idx;
1970 /* Retrieve a control handle given its index (0..count-1) */
1971 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
1972 unsigned int ctl_id)
1974 struct pvr2_ctrl *cptr;
1978 /* This could be made a lot more efficient, but for now... */
1979 for (idx = 0; idx < hdw->control_cnt; idx++) {
1980 cptr = hdw->controls + idx;
1981 i = cptr->info->internal_id;
1982 if (i && (i == ctl_id)) return cptr;
1988 /* Given an ID, retrieve the control structure associated with it. */
1989 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
1991 struct pvr2_ctrl *cptr;
1995 /* This could be made a lot more efficient, but for now... */
1996 for (idx = 0; idx < hdw->control_cnt; idx++) {
1997 cptr = hdw->controls + idx;
1998 i = cptr->info->v4l_id;
1999 if (i && (i == ctl_id)) return cptr;
2005 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2008 case pvr2_ctl_int: return "integer";
2009 case pvr2_ctl_enum: return "enum";
2010 case pvr2_ctl_bitmask: return "bitmask";
2016 /* Commit all control changes made up to this point. Subsystems can be
2017 indirectly affected by these changes. For a given set of things being
2018 committed, we'll clear the affected subsystem bits and then once we're
2019 done committing everything we'll make a request to restore the subsystem
2020 state(s) back to their previous value before this function was called.
2021 Thus we can automatically reconfigure affected pieces of the driver as
2022 controls are changed. */
2023 int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2025 unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2026 unsigned long stale_subsys_mask = 0;
2028 struct pvr2_ctrl *cptr;
2030 int commit_flag = 0;
2032 unsigned int bcnt,ccnt;
2034 for (idx = 0; idx < hdw->control_cnt; idx++) {
2035 cptr = hdw->controls + idx;
2036 if (cptr->info->is_dirty == 0) continue;
2037 if (!cptr->info->is_dirty(cptr)) continue;
2042 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2045 cptr->info->get_value(cptr,&value);
2046 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2048 sizeof(buf)-bcnt,&ccnt);
2050 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2051 get_ctrl_typename(cptr->info->type));
2052 pvr2_trace(PVR2_TRACE_CTL,
2053 "/*--TRACE_COMMIT--*/ %.*s",
2058 /* Nothing has changed */
2062 /* When video standard changes, reset the hres and vres values -
2063 but if the user has pending changes there, then let the changes
2065 if (hdw->std_dirty) {
2066 /* Rewrite the vertical resolution to be appropriate to the
2067 video standard that has been selected. */
2069 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2074 if (nvres != hdw->res_ver_val) {
2075 hdw->res_ver_val = nvres;
2076 hdw->res_ver_dirty = !0;
2078 if (!hdw->interlace_val) {
2079 hdw->interlace_val = 0;
2080 hdw->interlace_dirty = !0;
2084 if (hdw->std_dirty ||
2085 hdw->interlace_dirty ||
2087 hdw->videobitrate_dirty ||
2088 hdw->videopeak_dirty ||
2089 hdw->audiobitrate_dirty ||
2090 hdw->audiolayer_dirty ||
2091 hdw->audiocrc_dirty ||
2092 hdw->audioemphasis_dirty ||
2094 hdw->res_ver_dirty ||
2095 hdw->res_hor_dirty) {
2096 /* If any of this changes, then the encoder needs to be
2097 reconfigured, and we need to reset the stream. */
2098 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2099 stale_subsys_mask |= hdw->subsys_stream_mask;
2103 /* Scan i2c core at this point - before we clear all the dirty
2104 bits. Various parts of the i2c core will notice dirty bits as
2105 appropriate and arrange to broadcast or directly send updates to
2106 the client drivers in order to keep everything in sync */
2107 pvr2_i2c_core_check_stale(hdw);
2109 for (idx = 0; idx < hdw->control_cnt; idx++) {
2110 cptr = hdw->controls + idx;
2111 if (!cptr->info->clear_dirty) continue;
2112 cptr->info->clear_dirty(cptr);
2115 /* Now execute i2c core update */
2116 pvr2_i2c_core_sync(hdw);
2118 pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2119 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2125 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2127 LOCK_TAKE(hdw->big_lock); do {
2128 pvr2_hdw_commit_ctl_internal(hdw);
2129 } while (0); LOCK_GIVE(hdw->big_lock);
2134 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2136 LOCK_TAKE(hdw->big_lock); do {
2137 pvr2_i2c_core_sync(hdw);
2138 } while (0); LOCK_GIVE(hdw->big_lock);
2142 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2143 void (*func)(void *),
2146 LOCK_TAKE(hdw->big_lock); do {
2147 hdw->poll_trigger_func = func;
2148 hdw->poll_trigger_data = data;
2149 } while (0); LOCK_GIVE(hdw->big_lock);
2153 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2155 if (hdw->poll_trigger_func) {
2156 hdw->poll_trigger_func(hdw->poll_trigger_data);
2161 void pvr2_hdw_poll_trigger(struct pvr2_hdw *hdw)
2163 LOCK_TAKE(hdw->big_lock); do {
2164 pvr2_hdw_poll_trigger_unlocked(hdw);
2165 } while (0); LOCK_GIVE(hdw->big_lock);
2169 /* Return name for this driver instance */
2170 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2176 /* Return bit mask indicating signal status */
2177 unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2179 unsigned int msk = 0;
2180 switch (hdw->input_val) {
2181 case PVR2_CVAL_INPUT_TV:
2182 case PVR2_CVAL_INPUT_RADIO:
2183 if (hdw->decoder_ctrl &&
2184 hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2185 msk |= PVR2_SIGNAL_OK;
2186 if (hdw->audio_stat &&
2187 hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2188 if (hdw->flag_stereo) {
2189 msk |= PVR2_SIGNAL_STEREO;
2191 if (hdw->flag_bilingual) {
2192 msk |= PVR2_SIGNAL_SAP;
2198 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2204 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2207 LOCK_TAKE(hdw->ctl_lock); do {
2208 hdw->cmd_buffer[0] = 0x0b;
2209 result = pvr2_send_request(hdw,
2212 if (result < 0) break;
2213 result = (hdw->cmd_buffer[0] != 0);
2214 } while(0); LOCK_GIVE(hdw->ctl_lock);
2219 /* Return bit mask indicating signal status */
2220 unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2222 unsigned int msk = 0;
2223 LOCK_TAKE(hdw->big_lock); do {
2224 msk = pvr2_hdw_get_signal_status_internal(hdw);
2225 } while (0); LOCK_GIVE(hdw->big_lock);
2230 /* Get handle to video output stream */
2231 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2233 return hp->vid_stream;
2237 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2239 LOCK_TAKE(hdw->big_lock); do {
2240 hdw->log_requested = !0;
2241 pvr2_i2c_core_check_stale(hdw);
2242 hdw->log_requested = 0;
2243 pvr2_i2c_core_sync(hdw);
2244 } while (0); LOCK_GIVE(hdw->big_lock);
2247 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2252 LOCK_TAKE(hdw->big_lock); do {
2253 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2256 pvr2_trace(PVR2_TRACE_FIRMWARE,
2257 "Cleaning up after CPU firmware fetch");
2258 kfree(hdw->fw_buffer);
2261 /* Now release the CPU. It will disconnect and
2263 pvr2_hdw_cpureset_assert(hdw,0);
2267 pvr2_trace(PVR2_TRACE_FIRMWARE,
2268 "Preparing to suck out CPU firmware");
2269 hdw->fw_size = 0x2000;
2270 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2271 if (!hdw->fw_buffer) {
2276 memset(hdw->fw_buffer,0,hdw->fw_size);
2278 /* We have to hold the CPU during firmware upload. */
2279 pvr2_hdw_cpureset_assert(hdw,1);
2281 /* download the firmware from address 0000-1fff in 2048
2282 (=0x800) bytes chunk. */
2284 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2285 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2286 for(address = 0; address < hdw->fw_size; address += 0x800) {
2287 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2289 hdw->fw_buffer+address,0x800,HZ);
2293 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2295 } while (0); LOCK_GIVE(hdw->big_lock);
2299 /* Return true if we're in a mode for retrieval CPU firmware */
2300 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2302 return hdw->fw_buffer != 0;
2306 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2307 char *buf,unsigned int cnt)
2310 LOCK_TAKE(hdw->big_lock); do {
2314 if (!hdw->fw_buffer) {
2319 if (offs >= hdw->fw_size) {
2320 pvr2_trace(PVR2_TRACE_FIRMWARE,
2321 "Read firmware data offs=%d EOF",
2327 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2329 memcpy(buf,hdw->fw_buffer+offs,cnt);
2331 pvr2_trace(PVR2_TRACE_FIRMWARE,
2332 "Read firmware data offs=%d cnt=%d",
2335 } while (0); LOCK_GIVE(hdw->big_lock);
2341 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2343 return hdw->v4l_minor_number;
2347 /* Store the v4l minor device number */
2348 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2350 hdw->v4l_minor_number = v;
2354 void pvr2_reset_ctl_endpoints(struct pvr2_hdw *hdw)
2356 if (!hdw->usb_dev) return;
2357 usb_settoggle(hdw->usb_dev, PVR2_CTL_WRITE_ENDPOINT & 0xf,
2358 !(PVR2_CTL_WRITE_ENDPOINT & USB_DIR_IN), 0);
2359 usb_settoggle(hdw->usb_dev, PVR2_CTL_READ_ENDPOINT & 0xf,
2360 !(PVR2_CTL_READ_ENDPOINT & USB_DIR_IN), 0);
2361 usb_clear_halt(hdw->usb_dev,
2362 usb_rcvbulkpipe(hdw->usb_dev,
2363 PVR2_CTL_READ_ENDPOINT & 0x7f));
2364 usb_clear_halt(hdw->usb_dev,
2365 usb_sndbulkpipe(hdw->usb_dev,
2366 PVR2_CTL_WRITE_ENDPOINT & 0x7f));
2370 static void pvr2_ctl_write_complete(struct urb *urb, struct pt_regs *regs)
2372 struct pvr2_hdw *hdw = urb->context;
2373 hdw->ctl_write_pend_flag = 0;
2374 if (hdw->ctl_read_pend_flag) return;
2375 complete(&hdw->ctl_done);
2379 static void pvr2_ctl_read_complete(struct urb *urb, struct pt_regs *regs)
2381 struct pvr2_hdw *hdw = urb->context;
2382 hdw->ctl_read_pend_flag = 0;
2383 if (hdw->ctl_write_pend_flag) return;
2384 complete(&hdw->ctl_done);
2388 static void pvr2_ctl_timeout(unsigned long data)
2390 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2391 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2392 hdw->ctl_timeout_flag = !0;
2393 if (hdw->ctl_write_pend_flag && hdw->ctl_write_urb) {
2394 usb_unlink_urb(hdw->ctl_write_urb);
2396 if (hdw->ctl_read_pend_flag && hdw->ctl_read_urb) {
2397 usb_unlink_urb(hdw->ctl_read_urb);
2403 int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2404 unsigned int timeout,int probe_fl,
2405 void *write_data,unsigned int write_len,
2406 void *read_data,unsigned int read_len)
2410 struct timer_list timer;
2411 if (!hdw->ctl_lock_held) {
2412 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2413 "Attempted to execute control transfer"
2417 if ((!hdw->flag_ok) && !probe_fl) {
2418 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2419 "Attempted to execute control transfer"
2420 " when device not ok");
2423 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2425 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2426 "Attempted to execute control transfer"
2427 " when USB is disconnected");
2432 /* Ensure that we have sane parameters */
2433 if (!write_data) write_len = 0;
2434 if (!read_data) read_len = 0;
2435 if (write_len > PVR2_CTL_BUFFSIZE) {
2437 PVR2_TRACE_ERROR_LEGS,
2438 "Attempted to execute %d byte"
2439 " control-write transfer (limit=%d)",
2440 write_len,PVR2_CTL_BUFFSIZE);
2443 if (read_len > PVR2_CTL_BUFFSIZE) {
2445 PVR2_TRACE_ERROR_LEGS,
2446 "Attempted to execute %d byte"
2447 " control-read transfer (limit=%d)",
2448 write_len,PVR2_CTL_BUFFSIZE);
2451 if ((!write_len) && (!read_len)) {
2453 PVR2_TRACE_ERROR_LEGS,
2454 "Attempted to execute null control transfer?");
2459 hdw->cmd_debug_state = 1;
2461 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2463 hdw->cmd_debug_code = 0;
2465 hdw->cmd_debug_write_len = write_len;
2466 hdw->cmd_debug_read_len = read_len;
2468 /* Initialize common stuff */
2469 init_completion(&hdw->ctl_done);
2470 hdw->ctl_timeout_flag = 0;
2471 hdw->ctl_write_pend_flag = 0;
2472 hdw->ctl_read_pend_flag = 0;
2474 timer.expires = jiffies + timeout;
2475 timer.data = (unsigned long)hdw;
2476 timer.function = pvr2_ctl_timeout;
2479 hdw->cmd_debug_state = 2;
2480 /* Transfer write data to internal buffer */
2481 for (idx = 0; idx < write_len; idx++) {
2482 hdw->ctl_write_buffer[idx] =
2483 ((unsigned char *)write_data)[idx];
2485 /* Initiate a write request */
2486 usb_fill_bulk_urb(hdw->ctl_write_urb,
2488 usb_sndbulkpipe(hdw->usb_dev,
2489 PVR2_CTL_WRITE_ENDPOINT),
2490 hdw->ctl_write_buffer,
2492 pvr2_ctl_write_complete,
2494 hdw->ctl_write_urb->actual_length = 0;
2495 hdw->ctl_write_pend_flag = !0;
2496 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2498 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2499 "Failed to submit write-control"
2500 " URB status=%d",status);
2501 hdw->ctl_write_pend_flag = 0;
2507 hdw->cmd_debug_state = 3;
2508 memset(hdw->ctl_read_buffer,0x43,read_len);
2509 /* Initiate a read request */
2510 usb_fill_bulk_urb(hdw->ctl_read_urb,
2512 usb_rcvbulkpipe(hdw->usb_dev,
2513 PVR2_CTL_READ_ENDPOINT),
2514 hdw->ctl_read_buffer,
2516 pvr2_ctl_read_complete,
2518 hdw->ctl_read_urb->actual_length = 0;
2519 hdw->ctl_read_pend_flag = !0;
2520 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2522 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2523 "Failed to submit read-control"
2524 " URB status=%d",status);
2525 hdw->ctl_read_pend_flag = 0;
2533 /* Now wait for all I/O to complete */
2534 hdw->cmd_debug_state = 4;
2535 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2536 wait_for_completion(&hdw->ctl_done);
2538 hdw->cmd_debug_state = 5;
2541 del_timer_sync(&timer);
2543 hdw->cmd_debug_state = 6;
2546 if (hdw->ctl_timeout_flag) {
2547 status = -ETIMEDOUT;
2549 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2550 "Timed out control-write");
2556 /* Validate results of write request */
2557 if ((hdw->ctl_write_urb->status != 0) &&
2558 (hdw->ctl_write_urb->status != -ENOENT) &&
2559 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2560 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2561 /* USB subsystem is reporting some kind of failure
2563 status = hdw->ctl_write_urb->status;
2565 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2566 "control-write URB failure,"
2572 if (hdw->ctl_write_urb->actual_length < write_len) {
2573 /* Failed to write enough data */
2576 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2577 "control-write URB short,"
2578 " expected=%d got=%d",
2580 hdw->ctl_write_urb->actual_length);
2586 /* Validate results of read request */
2587 if ((hdw->ctl_read_urb->status != 0) &&
2588 (hdw->ctl_read_urb->status != -ENOENT) &&
2589 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2590 (hdw->ctl_read_urb->status != -ECONNRESET)) {
2591 /* USB subsystem is reporting some kind of failure
2593 status = hdw->ctl_read_urb->status;
2595 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2596 "control-read URB failure,"
2602 if (hdw->ctl_read_urb->actual_length < read_len) {
2603 /* Failed to read enough data */
2606 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2607 "control-read URB short,"
2608 " expected=%d got=%d",
2610 hdw->ctl_read_urb->actual_length);
2614 /* Transfer retrieved data out from internal buffer */
2615 for (idx = 0; idx < read_len; idx++) {
2616 ((unsigned char *)read_data)[idx] =
2617 hdw->ctl_read_buffer[idx];
2623 hdw->cmd_debug_state = 0;
2624 if ((status < 0) && (!probe_fl)) {
2625 pvr2_hdw_render_useless_unlocked(hdw);
2631 int pvr2_send_request(struct pvr2_hdw *hdw,
2632 void *write_data,unsigned int write_len,
2633 void *read_data,unsigned int read_len)
2635 return pvr2_send_request_ex(hdw,HZ*4,0,
2636 write_data,write_len,
2637 read_data,read_len);
2640 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2644 LOCK_TAKE(hdw->ctl_lock);
2646 hdw->cmd_buffer[0] = 0x04; /* write register prefix */
2647 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2648 hdw->cmd_buffer[5] = 0;
2649 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2650 hdw->cmd_buffer[7] = reg & 0xff;
2653 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2655 LOCK_GIVE(hdw->ctl_lock);
2661 int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2665 LOCK_TAKE(hdw->ctl_lock);
2667 hdw->cmd_buffer[0] = 0x05; /* read register prefix */
2668 hdw->cmd_buffer[1] = 0;
2669 hdw->cmd_buffer[2] = 0;
2670 hdw->cmd_buffer[3] = 0;
2671 hdw->cmd_buffer[4] = 0;
2672 hdw->cmd_buffer[5] = 0;
2673 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2674 hdw->cmd_buffer[7] = reg & 0xff;
2676 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2677 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2679 LOCK_GIVE(hdw->ctl_lock);
2685 int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2689 LOCK_TAKE(hdw->ctl_lock);
2691 hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2692 hdw->cmd_buffer[1] = data & 0xff;
2694 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2696 LOCK_GIVE(hdw->ctl_lock);
2702 int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2706 LOCK_TAKE(hdw->ctl_lock);
2708 hdw->cmd_buffer[0] = data;
2710 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2712 LOCK_GIVE(hdw->ctl_lock);
2718 void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2720 if (!hdw->flag_ok) return;
2721 pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2723 if (hdw->vid_stream) {
2724 pvr2_stream_setup(hdw->vid_stream,0,0,0);
2726 hdw->flag_streaming_enabled = 0;
2727 hdw->subsys_enabled_mask = 0;
2731 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2733 LOCK_TAKE(hdw->ctl_lock);
2734 pvr2_hdw_render_useless_unlocked(hdw);
2735 LOCK_GIVE(hdw->ctl_lock);
2739 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2742 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2743 ret = usb_lock_device_for_reset(hdw->usb_dev,0);
2745 ret = usb_reset_device(hdw->usb_dev);
2746 usb_unlock_device(hdw->usb_dev);
2748 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2749 "Failed to lock USB device ret=%d",ret);
2751 if (init_pause_msec) {
2752 pvr2_trace(PVR2_TRACE_INFO,
2753 "Waiting %u msec for hardware to settle",
2755 msleep(init_pause_msec);
2761 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2767 if (!hdw->usb_dev) return;
2769 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2771 da[0] = val ? 0x01 : 0x00;
2773 /* Write the CPUCS register on the 8051. The lsb of the register
2774 is the reset bit; a 1 asserts reset while a 0 clears it. */
2775 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2776 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2778 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2779 "cpureset_assert(%d) error=%d",val,ret);
2780 pvr2_hdw_render_useless(hdw);
2785 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2788 LOCK_TAKE(hdw->ctl_lock); do {
2789 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2791 hdw->cmd_buffer[0] = 0xdd;
2792 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2793 } while (0); LOCK_GIVE(hdw->ctl_lock);
2798 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2801 LOCK_TAKE(hdw->ctl_lock); do {
2802 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2803 hdw->cmd_buffer[0] = 0xde;
2804 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2805 } while (0); LOCK_GIVE(hdw->ctl_lock);
2810 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
2812 if (!hdw->decoder_ctrl) {
2813 pvr2_trace(PVR2_TRACE_INIT,
2814 "Unable to reset decoder: nothing attached");
2818 if (!hdw->decoder_ctrl->force_reset) {
2819 pvr2_trace(PVR2_TRACE_INIT,
2820 "Unable to reset decoder: not implemented");
2824 pvr2_trace(PVR2_TRACE_INIT,
2825 "Requesting decoder reset");
2826 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
2831 int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
2834 LOCK_TAKE(hdw->ctl_lock); do {
2835 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
2836 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2837 } while (0); LOCK_GIVE(hdw->ctl_lock);
2839 hdw->subsys_enabled_mask =
2840 ((hdw->subsys_enabled_mask &
2841 ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
2842 (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
2848 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
2849 struct pvr2_hdw_debug_info *ptr)
2851 ptr->big_lock_held = hdw->big_lock_held;
2852 ptr->ctl_lock_held = hdw->ctl_lock_held;
2853 ptr->flag_ok = hdw->flag_ok;
2854 ptr->flag_disconnected = hdw->flag_disconnected;
2855 ptr->flag_init_ok = hdw->flag_init_ok;
2856 ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
2857 ptr->subsys_flags = hdw->subsys_enabled_mask;
2858 ptr->cmd_debug_state = hdw->cmd_debug_state;
2859 ptr->cmd_code = hdw->cmd_debug_code;
2860 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
2861 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
2862 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
2863 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
2864 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
2865 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
2866 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
2870 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
2872 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
2876 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
2878 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
2882 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
2884 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
2888 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
2893 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
2894 if (ret) return ret;
2895 nval = (cval & ~msk) | (val & msk);
2896 pvr2_trace(PVR2_TRACE_GPIO,
2897 "GPIO direction changing 0x%x:0x%x"
2898 " from 0x%x to 0x%x",
2902 pvr2_trace(PVR2_TRACE_GPIO,
2903 "GPIO direction changing to 0x%x",nval);
2905 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
2909 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
2914 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
2915 if (ret) return ret;
2916 nval = (cval & ~msk) | (val & msk);
2917 pvr2_trace(PVR2_TRACE_GPIO,
2918 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
2922 pvr2_trace(PVR2_TRACE_GPIO,
2923 "GPIO output changing to 0x%x",nval);
2925 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
2929 int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
2932 LOCK_TAKE(hdw->ctl_lock); do {
2933 hdw->cmd_buffer[0] = 0xeb;
2934 result = pvr2_send_request(hdw,
2937 if (result < 0) break;
2938 result = hdw->cmd_buffer[0];
2939 } while(0); LOCK_GIVE(hdw->ctl_lock);
2945 Stuff for Emacs to see, in order to encourage consistent editing style:
2946 *** Local Variables: ***
2948 *** fill-column: 75 ***
2949 *** tab-width: 8 ***
2950 *** c-basic-offset: 8 ***