drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <asm/semaphore.h>
  27 #include <linux/videodev2.h>
  28 #include <media/cx2341x.h>
  29 #include "pvrusb2.h"
  30 #include "pvrusb2-std.h"
  31 #include "pvrusb2-util.h"
  32 #include "pvrusb2-hdw.h"
  33 #include "pvrusb2-i2c-core.h"
  34 #include "pvrusb2-tuner.h"
  35 #include "pvrusb2-eeprom.h"
  36 #include "pvrusb2-hdw-internal.h"
  37 #include "pvrusb2-encoder.h"
  38 #include "pvrusb2-debug.h"
  39
  40 struct usb_device_id pvr2_device_table[] = {
  41         [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
  42 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  43         [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
  44 #endif
  45         { }
  46 };
  47
  48 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
  49
  50 static const char *pvr2_device_names[] = {
  51         [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
  52 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  53         [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
  54 #endif
  55 };
  56
  57 struct pvr2_string_table {
  58         const char **lst;
  59         unsigned int cnt;
  60 };
  61
  62 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  63 // Names of other client modules to request for 24xxx model hardware
  64 static const char *pvr2_client_24xxx[] = {
  65         "cx25840",
  66         "tuner",
  67         "tda9887",
  68         "wm8775",
  69 };
  70 #endif
  71
  72 // Names of other client modules to request for 29xxx model hardware
  73 static const char *pvr2_client_29xxx[] = {
  74         "msp3400",
  75         "saa7115",
  76         "tuner",
  77         "tda9887",
  78 };
  79
  80 static struct pvr2_string_table pvr2_client_lists[] = {
  81         [PVR2_HDW_TYPE_29XXX] = {
  82                 pvr2_client_29xxx,
  83                 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
  84         },
  85 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  86         [PVR2_HDW_TYPE_24XXX] = {
  87                 pvr2_client_24xxx,
  88                 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
  89         },
  90 #endif
  91 };
  92
  93 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = 0};
  94 DECLARE_MUTEX(pvr2_unit_sem);
  95
  96 static int ctlchg = 0;
  97 static int initusbreset = 1;
  98 static int procreload = 0;
  99 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
 100 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
 101 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
 102 static int init_pause_msec = 0;
 103
 104 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
 105 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
 106 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
 107 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
 108 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
 109 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
 110 module_param(procreload, int, S_IRUGO|S_IWUSR);
 111 MODULE_PARM_DESC(procreload,
 112                  "Attempt init failure recovery with firmware reload");
 113 module_param_array(tuner,    int, NULL, 0444);
 114 MODULE_PARM_DESC(tuner,"specify installed tuner type");
 115 module_param_array(video_std,    int, NULL, 0444);
 116 MODULE_PARM_DESC(video_std,"specify initial video standard");
 117 module_param_array(tolerance,    int, NULL, 0444);
 118 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
 119
 120 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 121 #define PVR2_CTL_READ_ENDPOINT   0x81
 122
 123 #define PVR2_GPIO_IN 0x9008
 124 #define PVR2_GPIO_OUT 0x900c
 125 #define PVR2_GPIO_DIR 0x9020
 126
 127 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 128
 129 #define PVR2_FIRMWARE_ENDPOINT   0x02
 130
 131 /* size of a firmware chunk */
 132 #define FIRMWARE_CHUNK_SIZE 0x2000
 133
 134 static const char *control_values_srate[] = {
 135         [PVR2_CVAL_SRATE_48]   = "48KHz",
 136         [PVR2_CVAL_SRATE_44_1] = "44.1KHz",
 137 };
 138
 139
 140 static const char *control_values_audiobitrate[] = {
 141         [PVR2_CVAL_AUDIOBITRATE_384] = "384kb/s",
 142         [PVR2_CVAL_AUDIOBITRATE_320] = "320kb/s",
 143         [PVR2_CVAL_AUDIOBITRATE_256] = "256kb/s",
 144         [PVR2_CVAL_AUDIOBITRATE_224] = "224kb/s",
 145         [PVR2_CVAL_AUDIOBITRATE_192] = "192kb/s",
 146         [PVR2_CVAL_AUDIOBITRATE_160] = "160kb/s",
 147         [PVR2_CVAL_AUDIOBITRATE_128] = "128kb/s",
 148         [PVR2_CVAL_AUDIOBITRATE_112] = "112kb/s",
 149         [PVR2_CVAL_AUDIOBITRATE_96]  = "96kb/s",
 150         [PVR2_CVAL_AUDIOBITRATE_80]  = "80kb/s",
 151         [PVR2_CVAL_AUDIOBITRATE_64]  = "64kb/s",
 152         [PVR2_CVAL_AUDIOBITRATE_56]  = "56kb/s",
 153         [PVR2_CVAL_AUDIOBITRATE_48]  = "48kb/s",
 154         [PVR2_CVAL_AUDIOBITRATE_32]  = "32kb/s",
 155         [PVR2_CVAL_AUDIOBITRATE_VBR] = "VBR",
 156 };
 157
 158
 159 static const char *control_values_audioemphasis[] = {
 160         [PVR2_CVAL_AUDIOEMPHASIS_NONE]  = "None",
 161         [PVR2_CVAL_AUDIOEMPHASIS_50_15] = "50/15us",
 162         [PVR2_CVAL_AUDIOEMPHASIS_CCITT] = "CCITT J.17",
 163 };
 164
 165
 166 static const char *control_values_input[] = {
 167         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 168         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 169         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 170         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 171 };
 172
 173
 174 static const char *control_values_audiomode[] = {
 175         [V4L2_TUNER_MODE_MONO]   = "Mono",
 176         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 177         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 178         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 179         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 180 };
 181
 182
 183 static const char *control_values_hsm[] = {
 184         [PVR2_CVAL_HSM_FAIL] = "Fail",
 185         [PVR2_CVAL_HSM_HIGH] = "High",
 186         [PVR2_CVAL_HSM_FULL] = "Full",
 187 };
 188
 189
 190 static const char *control_values_subsystem[] = {
 191         [PVR2_SUBSYS_B_ENC_FIRMWARE]  = "enc_firmware",
 192         [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
 193         [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
 194         [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
 195         [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
 196 };
 197
 198
 199 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 200 {
 201         struct pvr2_hdw *hdw = cptr->hdw;
 202         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 203                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 204         } else {
 205                 *vp = 0;
 206         }
 207         return 0;
 208 }
 209
 210 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 211 {
 212         struct pvr2_hdw *hdw = cptr->hdw;
 213         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 214                 hdw->freqTable[hdw->freqProgSlot-1] = v;
 215         }
 216         return 0;
 217 }
 218
 219 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 220 {
 221         *vp = cptr->hdw->freqProgSlot;
 222         return 0;
 223 }
 224
 225 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 226 {
 227         struct pvr2_hdw *hdw = cptr->hdw;
 228         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 229                 hdw->freqProgSlot = v;
 230         }
 231         return 0;
 232 }
 233
 234 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 235 {
 236         *vp = cptr->hdw->freqSlot;
 237         return 0;
 238 }
 239
 240 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
 241 {
 242         unsigned freq = 0;
 243         struct pvr2_hdw *hdw = cptr->hdw;
 244         hdw->freqSlot = v;
 245         if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
 246                 freq = hdw->freqTable[hdw->freqSlot-1];
 247         }
 248         if (freq && (freq != hdw->freqVal)) {
 249                 hdw->freqVal = freq;
 250                 hdw->freqDirty = !0;
 251         }
 252         return 0;
 253 }
 254
 255 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 256 {
 257         *vp = cptr->hdw->freqVal;
 258         return 0;
 259 }
 260
 261 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 262 {
 263         return cptr->hdw->freqDirty != 0;
 264 }
 265
 266 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 267 {
 268         cptr->hdw->freqDirty = 0;
 269 }
 270
 271 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 272 {
 273         struct pvr2_hdw *hdw = cptr->hdw;
 274         hdw->freqVal = v;
 275         hdw->freqDirty = !0;
 276         hdw->freqSlot = 0;
 277         return 0;
 278 }
 279
 280 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 281 {
 282         *vp = cptr->hdw->flag_streaming_enabled;
 283         return 0;
 284 }
 285
 286 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 287 {
 288         int result = pvr2_hdw_is_hsm(cptr->hdw);
 289         *vp = PVR2_CVAL_HSM_FULL;
 290         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 291         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 292         return 0;
 293 }
 294
 295 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 296 {
 297         *vp = cptr->hdw->std_mask_avail;
 298         return 0;
 299 }
 300
 301 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 302 {
 303         struct pvr2_hdw *hdw = cptr->hdw;
 304         v4l2_std_id ns;
 305         ns = hdw->std_mask_avail;
 306         ns = (ns & ~m) | (v & m);
 307         if (ns == hdw->std_mask_avail) return 0;
 308         hdw->std_mask_avail = ns;
 309         pvr2_hdw_internal_set_std_avail(hdw);
 310         pvr2_hdw_internal_find_stdenum(hdw);
 311         return 0;
 312 }
 313
 314 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 315                                char *bufPtr,unsigned int bufSize,
 316                                unsigned int *len)
 317 {
 318         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 319         return 0;
 320 }
 321
 322 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 323                                const char *bufPtr,unsigned int bufSize,
 324                                int *mskp,int *valp)
 325 {
 326         int ret;
 327         v4l2_std_id id;
 328         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 329         if (ret < 0) return ret;
 330         if (mskp) *mskp = id;
 331         if (valp) *valp = id;
 332         return 0;
 333 }
 334
 335 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 336 {
 337         *vp = cptr->hdw->std_mask_cur;
 338         return 0;
 339 }
 340
 341 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 342 {
 343         struct pvr2_hdw *hdw = cptr->hdw;
 344         v4l2_std_id ns;
 345         ns = hdw->std_mask_cur;
 346         ns = (ns & ~m) | (v & m);
 347         if (ns == hdw->std_mask_cur) return 0;
 348         hdw->std_mask_cur = ns;
 349         hdw->std_dirty = !0;
 350         pvr2_hdw_internal_find_stdenum(hdw);
 351         return 0;
 352 }
 353
 354 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 355 {
 356         return cptr->hdw->std_dirty != 0;
 357 }
 358
 359 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 360 {
 361         cptr->hdw->std_dirty = 0;
 362 }
 363
 364 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 365 {
 366         *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
 367                 PVR2_SIGNAL_OK) ? 1 : 0);
 368         return 0;
 369 }
 370
 371 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
 372 {
 373         *vp = cptr->hdw->subsys_enabled_mask;
 374         return 0;
 375 }
 376
 377 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
 378 {
 379         pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
 380         return 0;
 381 }
 382
 383 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
 384 {
 385         *vp = cptr->hdw->subsys_stream_mask;
 386         return 0;
 387 }
 388
 389 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
 390 {
 391         pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
 392         return 0;
 393 }
 394
 395 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 396 {
 397         struct pvr2_hdw *hdw = cptr->hdw;
 398         if (v < 0) return -EINVAL;
 399         if (v > hdw->std_enum_cnt) return -EINVAL;
 400         hdw->std_enum_cur = v;
 401         if (!v) return 0;
 402         v--;
 403         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 404         hdw->std_mask_cur = hdw->std_defs[v].id;
 405         hdw->std_dirty = !0;
 406         return 0;
 407 }
 408
 409
 410 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 411 {
 412         *vp = cptr->hdw->std_enum_cur;
 413         return 0;
 414 }
 415
 416
 417 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 418 {
 419         return cptr->hdw->std_dirty != 0;
 420 }
 421
 422
 423 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 424 {
 425         cptr->hdw->std_dirty = 0;
 426 }
 427
 428
 429 #define DEFINT(vmin,vmax) \
 430         .type = pvr2_ctl_int, \
 431         .def.type_int.min_value = vmin, \
 432         .def.type_int.max_value = vmax
 433
 434 #define DEFENUM(tab) \
 435         .type = pvr2_ctl_enum, \
 436         .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
 437         .def.type_enum.value_names = tab
 438
 439 #define DEFMASK(msk,tab) \
 440         .type = pvr2_ctl_bitmask, \
 441         .def.type_bitmask.valid_bits = msk, \
 442         .def.type_bitmask.bit_names = tab
 443
 444 #define DEFREF(vname) \
 445         .set_value = ctrl_set_##vname, \
 446         .get_value = ctrl_get_##vname, \
 447         .is_dirty = ctrl_isdirty_##vname, \
 448         .clear_dirty = ctrl_cleardirty_##vname
 449
 450
 451 #define VCREATE_FUNCS(vname) \
 452 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 453 {*vp = cptr->hdw->vname##_val; return 0;} \
 454 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 455 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 456 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 457 {return cptr->hdw->vname##_dirty != 0;} \
 458 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 459 {cptr->hdw->vname##_dirty = 0;}
 460
 461 VCREATE_FUNCS(brightness)
 462 VCREATE_FUNCS(contrast)
 463 VCREATE_FUNCS(saturation)
 464 VCREATE_FUNCS(hue)
 465 VCREATE_FUNCS(volume)
 466 VCREATE_FUNCS(balance)
 467 VCREATE_FUNCS(bass)
 468 VCREATE_FUNCS(treble)
 469 VCREATE_FUNCS(mute)
 470 VCREATE_FUNCS(srate)
 471 VCREATE_FUNCS(audiobitrate)
 472 VCREATE_FUNCS(audiocrc)
 473 VCREATE_FUNCS(audioemphasis)
 474 VCREATE_FUNCS(vbr)
 475 VCREATE_FUNCS(videobitrate)
 476 VCREATE_FUNCS(videopeak)
 477 VCREATE_FUNCS(input)
 478 VCREATE_FUNCS(audiomode)
 479 VCREATE_FUNCS(res_hor)
 480 VCREATE_FUNCS(res_ver)
 481 VCREATE_FUNCS(interlace)
 482 VCREATE_FUNCS(audiolayer)
 483
 484 #define MIN_FREQ 55250000L
 485 #define MAX_FREQ 850000000L
 486
 487 /* Table definition of all controls which can be manipulated */
 488 static const struct pvr2_ctl_info control_defs[] = {
 489         {
 490                 .v4l_id = V4L2_CID_BRIGHTNESS,
 491                 .desc = "Brightness",
 492                 .name = "brightness",
 493                 .default_value = 128,
 494                 DEFREF(brightness),
 495                 DEFINT(0,255),
 496         },{
 497                 .v4l_id = V4L2_CID_CONTRAST,
 498                 .desc = "Contrast",
 499                 .name = "contrast",
 500                 .default_value = 68,
 501                 DEFREF(contrast),
 502                 DEFINT(0,127),
 503         },{
 504                 .v4l_id = V4L2_CID_SATURATION,
 505                 .desc = "Saturation",
 506                 .name = "saturation",
 507                 .default_value = 64,
 508                 DEFREF(saturation),
 509                 DEFINT(0,127),
 510         },{
 511                 .v4l_id = V4L2_CID_HUE,
 512                 .desc = "Hue",
 513                 .name = "hue",
 514                 .default_value = 0,
 515                 DEFREF(hue),
 516                 DEFINT(-128,127),
 517         },{
 518                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 519                 .desc = "Volume",
 520                 .name = "volume",
 521                 .default_value = 65535,
 522                 DEFREF(volume),
 523                 DEFINT(0,65535),
 524         },{
 525                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 526                 .desc = "Balance",
 527                 .name = "balance",
 528                 .default_value = 0,
 529                 DEFREF(balance),
 530                 DEFINT(-32768,32767),
 531         },{
 532                 .v4l_id = V4L2_CID_AUDIO_BASS,
 533                 .desc = "Bass",
 534                 .name = "bass",
 535                 .default_value = 0,
 536                 DEFREF(bass),
 537                 DEFINT(-32768,32767),
 538         },{
 539                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 540                 .desc = "Treble",
 541                 .name = "treble",
 542                 .default_value = 0,
 543                 DEFREF(treble),
 544                 DEFINT(-32768,32767),
 545         },{
 546                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 547                 .desc = "Mute",
 548                 .name = "mute",
 549                 .default_value = 0,
 550                 DEFREF(mute),
 551                 DEFINT(0,1),
 552         },{
 553                 .v4l_id = V4L2_CID_PVR_SRATE,
 554                 .desc = "Sample rate",
 555                 .name = "srate",
 556                 .default_value = PVR2_CVAL_SRATE_48,
 557                 DEFREF(srate),
 558                 DEFENUM(control_values_srate),
 559         },{
 560                 .v4l_id = V4L2_CID_PVR_AUDIOBITRATE,
 561                 .desc = "Audio Bitrate",
 562                 .name = "audio_bitrate",
 563                 .default_value = PVR2_CVAL_AUDIOBITRATE_224,
 564                 DEFREF(audiobitrate),
 565                 DEFENUM(control_values_audiobitrate),
 566         },{
 567                 .v4l_id = V4L2_CID_PVR_AUDIOCRC,
 568                 .desc = "Audio CRC",
 569                 .name = "audio_crc",
 570                 .default_value = 1,
 571                 DEFREF(audiocrc),
 572                 DEFINT(0,1),
 573         },{
 574                 .desc = "Audio Layer",
 575                 .name = "audio_layer",
 576                 .default_value = 2,
 577                 DEFREF(audiolayer),
 578                 DEFINT(0,3),
 579         },{
 580                 .v4l_id = V4L2_CID_PVR_AUDIOEMPHASIS,
 581                 .desc = "Audio Emphasis",
 582                 .name = "audio_emphasis",
 583                 .default_value = PVR2_CVAL_AUDIOEMPHASIS_NONE,
 584                 DEFREF(audioemphasis),
 585                 DEFENUM(control_values_audioemphasis),
 586         },{
 587                 .desc = "Interlace mode",
 588                 .name = "interlace",
 589                 .internal_id = PVR2_CID_INTERLACE,
 590                 .default_value = 0,
 591                 DEFREF(interlace),
 592                 DEFINT(0,1),
 593         },{
 594                 .v4l_id = V4L2_CID_PVR_VBR,
 595                 .desc = "Variable video bitrate",
 596                 .name = "vbr",
 597                 .default_value = 0,
 598                 DEFREF(vbr),
 599                 DEFINT(0,1),
 600         },{
 601                 .v4l_id = V4L2_CID_PVR_VIDEOBITRATE,
 602                 .desc = "Average video bitrate",
 603                 .name = "video_average_bitrate",
 604                 .default_value = 6000000,
 605                 DEFREF(videobitrate),
 606                 DEFINT(500000,20000000),
 607         },{
 608                 .v4l_id = V4L2_CID_PVR_VIDEOPEAK,
 609                 .desc = "Peak video bitrate",
 610                 .name = "video_peak_bitrate",
 611                 .default_value = 6000000,
 612                 DEFREF(videopeak),
 613                 DEFINT(500000,20000000),
 614         },{
 615                 .desc = "Video Source",
 616                 .name = "input",
 617                 .internal_id = PVR2_CID_INPUT,
 618                 .default_value = PVR2_CVAL_INPUT_TV,
 619                 DEFREF(input),
 620                 DEFENUM(control_values_input),
 621         },{
 622                 .desc = "Audio Mode",
 623                 .name = "audio_mode",
 624                 .internal_id = PVR2_CID_AUDIOMODE,
 625                 .default_value = V4L2_TUNER_MODE_STEREO,
 626                 DEFREF(audiomode),
 627                 DEFENUM(control_values_audiomode),
 628         },{
 629                 .desc = "Tuner Frequency (Hz)",
 630                 .name = "frequency",
 631                 .internal_id = PVR2_CID_FREQUENCY,
 632                 .default_value = 175250000L,
 633                 .set_value = ctrl_freq_set,
 634                 .get_value = ctrl_freq_get,
 635                 .is_dirty = ctrl_freq_is_dirty,
 636                 .clear_dirty = ctrl_freq_clear_dirty,
 637                 DEFINT(MIN_FREQ,MAX_FREQ),
 638         },{
 639                 .desc = "Channel",
 640                 .name = "channel",
 641                 .set_value = ctrl_channel_set,
 642                 .get_value = ctrl_channel_get,
 643                 DEFINT(0,FREQTABLE_SIZE),
 644         },{
 645                 .desc = "Channel Program Frequency",
 646                 .name = "freq_table_value",
 647                 .set_value = ctrl_channelfreq_set,
 648                 .get_value = ctrl_channelfreq_get,
 649                 DEFINT(MIN_FREQ,MAX_FREQ),
 650         },{
 651                 .desc = "Channel Program ID",
 652                 .name = "freq_table_channel",
 653                 .set_value = ctrl_channelprog_set,
 654                 .get_value = ctrl_channelprog_get,
 655                 DEFINT(0,FREQTABLE_SIZE),
 656         },{
 657                 .desc = "Horizontal capture resolution",
 658                 .name = "resolution_hor",
 659                 .internal_id = PVR2_CID_HRES,
 660                 .default_value = 720,
 661                 DEFREF(res_hor),
 662                 DEFINT(320,720),
 663         },{
 664                 .desc = "Vertical capture resolution",
 665                 .name = "resolution_ver",
 666                 .internal_id = PVR2_CID_VRES,
 667                 .default_value = 480,
 668                 DEFREF(res_ver),
 669                 DEFINT(200,625),
 670         },{
 671                 .desc = "Streaming Enabled",
 672                 .name = "streaming_enabled",
 673                 .get_value = ctrl_streamingenabled_get,
 674                 DEFINT(0,1),
 675         },{
 676                 .desc = "USB Speed",
 677                 .name = "usb_speed",
 678                 .get_value = ctrl_hsm_get,
 679                 DEFENUM(control_values_hsm),
 680         },{
 681                 .desc = "Signal Present",
 682                 .name = "signal_present",
 683                 .get_value = ctrl_signal_get,
 684                 DEFINT(0,1),
 685         },{
 686                 .desc = "Video Standards Available Mask",
 687                 .name = "video_standard_mask_available",
 688                 .internal_id = PVR2_CID_STDAVAIL,
 689                 .skip_init = !0,
 690                 .get_value = ctrl_stdavail_get,
 691                 .set_value = ctrl_stdavail_set,
 692                 .val_to_sym = ctrl_std_val_to_sym,
 693                 .sym_to_val = ctrl_std_sym_to_val,
 694                 .type = pvr2_ctl_bitmask,
 695         },{
 696                 .desc = "Video Standards In Use Mask",
 697                 .name = "video_standard_mask_active",
 698                 .internal_id = PVR2_CID_STDCUR,
 699                 .skip_init = !0,
 700                 .get_value = ctrl_stdcur_get,
 701                 .set_value = ctrl_stdcur_set,
 702                 .is_dirty = ctrl_stdcur_is_dirty,
 703                 .clear_dirty = ctrl_stdcur_clear_dirty,
 704                 .val_to_sym = ctrl_std_val_to_sym,
 705                 .sym_to_val = ctrl_std_sym_to_val,
 706                 .type = pvr2_ctl_bitmask,
 707         },{
 708                 .desc = "Subsystem enabled mask",
 709                 .name = "debug_subsys_mask",
 710                 .skip_init = !0,
 711                 .get_value = ctrl_subsys_get,
 712                 .set_value = ctrl_subsys_set,
 713                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 714         },{
 715                 .desc = "Subsystem stream mask",
 716                 .name = "debug_subsys_stream_mask",
 717                 .skip_init = !0,
 718                 .get_value = ctrl_subsys_stream_get,
 719                 .set_value = ctrl_subsys_stream_set,
 720                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 721         },{
 722                 .desc = "Video Standard Name",
 723                 .name = "video_standard",
 724                 .internal_id = PVR2_CID_STDENUM,
 725                 .skip_init = !0,
 726                 .get_value = ctrl_stdenumcur_get,
 727                 .set_value = ctrl_stdenumcur_set,
 728                 .is_dirty = ctrl_stdenumcur_is_dirty,
 729                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 730                 .type = pvr2_ctl_enum,
 731         }
 732 };
 733
 734 #define CTRL_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
 735
 736
 737 const char *pvr2_config_get_name(enum pvr2_config cfg)
 738 {
 739         switch (cfg) {
 740         case pvr2_config_empty: return "empty";
 741         case pvr2_config_mpeg: return "mpeg";
 742         case pvr2_config_vbi: return "vbi";
 743         case pvr2_config_radio: return "radio";
 744         }
 745         return "<unknown>";
 746 }
 747
 748
 749 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
 750 {
 751         return hdw->usb_dev;
 752 }
 753
 754
 755 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
 756 {
 757         return hdw->serial_number;
 758 }
 759
 760
 761 struct pvr2_hdw *pvr2_hdw_find(int unit_number)
 762 {
 763         if (unit_number < 0) return 0;
 764         if (unit_number >= PVR_NUM) return 0;
 765         return unit_pointers[unit_number];
 766 }
 767
 768
 769 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
 770 {
 771         return hdw->unit_number;
 772 }
 773
 774
 775 /* Attempt to locate one of the given set of files.  Messages are logged
 776    appropriate to what has been found.  The return value will be 0 or
 777    greater on success (it will be the index of the file name found) and
 778    fw_entry will be filled in.  Otherwise a negative error is returned on
 779    failure.  If the return value is -ENOENT then no viable firmware file
 780    could be located. */
 781 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
 782                                 const struct firmware **fw_entry,
 783                                 const char *fwtypename,
 784                                 unsigned int fwcount,
 785                                 const char *fwnames[])
 786 {
 787         unsigned int idx;
 788         int ret = -EINVAL;
 789         for (idx = 0; idx < fwcount; idx++) {
 790                 ret = request_firmware(fw_entry,
 791                                        fwnames[idx],
 792                                        &hdw->usb_dev->dev);
 793                 if (!ret) {
 794                         trace_firmware("Located %s firmware: %s;"
 795                                        " uploading...",
 796                                        fwtypename,
 797                                        fwnames[idx]);
 798                         return idx;
 799                 }
 800                 if (ret == -ENOENT) continue;
 801                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 802                            "request_firmware fatal error with code=%d",ret);
 803                 return ret;
 804         }
 805         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 806                    "***WARNING***"
 807                    " Device %s firmware"
 808                    " seems to be missing.",
 809                    fwtypename);
 810         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 811                    "Did you install the pvrusb2 firmware files"
 812                    " in their proper location?");
 813         if (fwcount == 1) {
 814                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 815                            "request_firmware unable to locate %s file %s",
 816                            fwtypename,fwnames[0]);
 817         } else {
 818                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 819                            "request_firmware unable to locate"
 820                            " one of the following %s files:",
 821                            fwtypename);
 822                 for (idx = 0; idx < fwcount; idx++) {
 823                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 824                                    "request_firmware: Failed to find %s",
 825                                    fwnames[idx]);
 826                 }
 827         }
 828         return ret;
 829 }
 830
 831
 832 /*
 833  * pvr2_upload_firmware1().
 834  *
 835  * Send the 8051 firmware to the device.  After the upload, arrange for
 836  * device to re-enumerate.
 837  *
 838  * NOTE : the pointer to the firmware data given by request_firmware()
 839  * is not suitable for an usb transaction.
 840  *
 841  */
 842 int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
 843 {
 844         const struct firmware *fw_entry = 0;
 845         void  *fw_ptr;
 846         unsigned int pipe;
 847         int ret;
 848         u16 address;
 849         static const char *fw_files_29xxx[] = {
 850                 "v4l-pvrusb2-29xxx-01.fw",
 851         };
 852 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 853         static const char *fw_files_24xxx[] = {
 854                 "v4l-pvrusb2-24xxx-01.fw",
 855         };
 856 #endif
 857         static const struct pvr2_string_table fw_file_defs[] = {
 858                 [PVR2_HDW_TYPE_29XXX] = {
 859                         fw_files_29xxx,
 860                         sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
 861                 },
 862 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 863                 [PVR2_HDW_TYPE_24XXX] = {
 864                         fw_files_24xxx,
 865                         sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
 866                 },
 867 #endif
 868         };
 869         hdw->fw1_state = FW1_STATE_FAILED; // default result
 870
 871         trace_firmware("pvr2_upload_firmware1");
 872
 873         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
 874                                    fw_file_defs[hdw->hdw_type].cnt,
 875                                    fw_file_defs[hdw->hdw_type].lst);
 876         if (ret < 0) {
 877                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
 878                 return ret;
 879         }
 880
 881         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
 882         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
 883
 884         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
 885
 886         if (fw_entry->size != 0x2000){
 887                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
 888                 release_firmware(fw_entry);
 889                 return -ENOMEM;
 890         }
 891
 892         fw_ptr = kmalloc(0x800, GFP_KERNEL);
 893         if (fw_ptr == NULL){
 894                 release_firmware(fw_entry);
 895                 return -ENOMEM;
 896         }
 897
 898         /* We have to hold the CPU during firmware upload. */
 899         pvr2_hdw_cpureset_assert(hdw,1);
 900
 901         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
 902            chunk. */
 903
 904         ret = 0;
 905         for(address = 0; address < fw_entry->size; address += 0x800) {
 906                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
 907                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
 908                                        0, fw_ptr, 0x800, HZ);
 909         }
 910
 911         trace_firmware("Upload done, releasing device's CPU");
 912
 913         /* Now release the CPU.  It will disconnect and reconnect later. */
 914         pvr2_hdw_cpureset_assert(hdw,0);
 915
 916         kfree(fw_ptr);
 917         release_firmware(fw_entry);
 918
 919         trace_firmware("Upload done (%d bytes sent)",ret);
 920
 921         /* We should have written 8192 bytes */
 922         if (ret == 8192) {
 923                 hdw->fw1_state = FW1_STATE_RELOAD;
 924                 return 0;
 925         }
 926
 927         return -EIO;
 928 }
 929
 930
 931 /*
 932  * pvr2_upload_firmware2()
 933  *
 934  * This uploads encoder firmware on endpoint 2.
 935  *
 936  */
 937
 938 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
 939 {
 940         const struct firmware *fw_entry = 0;
 941         void  *fw_ptr;
 942         unsigned int pipe, fw_len, fw_done;
 943         int actual_length;
 944         int ret = 0;
 945         int fwidx;
 946         static const char *fw_files[] = {
 947                 CX2341X_FIRM_ENC_FILENAME,
 948         };
 949
 950         trace_firmware("pvr2_upload_firmware2");
 951
 952         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
 953                                    sizeof(fw_files)/sizeof(fw_files[0]),
 954                                    fw_files);
 955         if (ret < 0) return ret;
 956         fwidx = ret;
 957         ret = 0;
 958
 959         /* First prepare firmware loading */
 960         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
 961         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
 962         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
 963         ret |= pvr2_hdw_cmd_deep_reset(hdw);
 964         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
 965         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
 966         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
 967         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
 968         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
 969         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
 970         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
 971         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
 972         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
 973         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
 974         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
 975         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
 976         ret |= pvr2_write_u8(hdw, 0x52, 0);
 977         ret |= pvr2_write_u16(hdw, 0x0600, 0);
 978
 979         if (ret) {
 980                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 981                            "firmware2 upload prep failed, ret=%d",ret);
 982                 release_firmware(fw_entry);
 983                 return ret;
 984         }
 985
 986         /* Now send firmware */
 987
 988         fw_len = fw_entry->size;
 989
 990         if (fw_len % FIRMWARE_CHUNK_SIZE) {
 991                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 992                            "size of %s firmware"
 993                            " must be a multiple of 8192B",
 994                            fw_files[fwidx]);
 995                 release_firmware(fw_entry);
 996                 return -1;
 997         }
 998
 999         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1000         if (fw_ptr == NULL){
1001                 release_firmware(fw_entry);
1002                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1003                            "failed to allocate memory for firmware2 upload");
1004                 return -ENOMEM;
1005         }
1006
1007         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1008
1009         for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1010              fw_done += FIRMWARE_CHUNK_SIZE ) {
1011                 int i;
1012                 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1013                 /* Usbsnoop log  shows that we must swap bytes... */
1014                 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1015                         ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1016
1017                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1018                                     FIRMWARE_CHUNK_SIZE,
1019                                     &actual_length, HZ);
1020                 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1021         }
1022
1023         trace_firmware("upload of %s : %i / %i ",
1024                        fw_files[fwidx],fw_done,fw_len);
1025
1026         kfree(fw_ptr);
1027         release_firmware(fw_entry);
1028
1029         if (ret) {
1030                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1031                            "firmware2 upload transfer failure");
1032                 return ret;
1033         }
1034
1035         /* Finish upload */
1036
1037         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1038         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1039         ret |= pvr2_write_u16(hdw, 0x0600, 0);
1040
1041         if (ret) {
1042                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1043                            "firmware2 upload post-proc failure");
1044         } else {
1045                 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1046         }
1047         return ret;
1048 }
1049
1050
1051 #define FIRMWARE_RECOVERY_BITS \
1052         ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1053          (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1054          (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1055          (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1056
1057 /*
1058
1059   This single function is key to pretty much everything.  The pvrusb2
1060   device can logically be viewed as a series of subsystems which can be
1061   stopped / started or unconfigured / configured.  To get things streaming,
1062   one must configure everything and start everything, but there may be
1063   various reasons over time to deconfigure something or stop something.
1064   This function handles all of this activity.  Everything EVERYWHERE that
1065   must affect a subsystem eventually comes here to do the work.
1066
1067   The current state of all subsystems is represented by a single bit mask,
1068   known as subsys_enabled_mask.  The bit positions are defined by the
1069   PVR2_SUBSYS_xxxx macros, with one subsystem per bit position.  At any
1070   time the set of configured or active subsystems can be queried just by
1071   looking at that mask.  To change bits in that mask, this function here
1072   must be called.  The "msk" argument indicates which bit positions to
1073   change, and the "val" argument defines the new values for the positions
1074   defined by "msk".
1075
1076   There is a priority ordering of starting / stopping things, and for
1077   multiple requested changes, this function implements that ordering.
1078   (Thus we will act on a request to load encoder firmware before we
1079   configure the encoder.)  In addition to priority ordering, there is a
1080   recovery strategy implemented here.  If a particular step fails and we
1081   detect that failure, this function will clear the affected subsystem bits
1082   and restart.  Thus we have a means for recovering from a dead encoder:
1083   Clear all bits that correspond to subsystems that we need to restart /
1084   reconfigure and start over.
1085
1086 */
1087 void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1088                                      unsigned long msk,unsigned long val)
1089 {
1090         unsigned long nmsk;
1091         unsigned long vmsk;
1092         int ret;
1093         unsigned int tryCount = 0;
1094
1095         if (!hdw->flag_ok) return;
1096
1097         msk &= PVR2_SUBSYS_ALL;
1098
1099         for (;;) {
1100                 tryCount++;
1101                 vmsk = hdw->subsys_enabled_mask & PVR2_SUBSYS_ALL;
1102                 nmsk = (vmsk & ~msk) | (val & msk);
1103                 if (!(nmsk ^ vmsk)) break;
1104                 if (tryCount > 4) {
1105                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1106                                    "Too many retries when configuring device;"
1107                                    " giving up");
1108                         pvr2_hdw_render_useless(hdw);
1109                         break;
1110                 }
1111                 if (tryCount > 1) {
1112                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1113                                    "Retrying device reconfiguration");
1114                 }
1115                 pvr2_trace(PVR2_TRACE_INIT,
1116                            "subsys mask changing 0x%lx:0x%lx"
1117                            " from 0x%lx to 0x%lx",
1118                            msk,val,hdw->subsys_enabled_mask,nmsk);
1119
1120                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1121                         hdw->subsys_enabled_mask;
1122                 if (vmsk) {
1123                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1124                                 pvr2_trace(PVR2_TRACE_CTL,
1125                                            "/*---TRACE_CTL----*/"
1126                                            " pvr2_encoder_stop");
1127                                 ret = pvr2_encoder_stop(hdw);
1128                                 if (ret) {
1129                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1130                                                    "Error recovery initiated");
1131                                         hdw->subsys_enabled_mask &=
1132                                                 ~FIRMWARE_RECOVERY_BITS;
1133                                         continue;
1134                                 }
1135                         }
1136                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1137                                 pvr2_trace(PVR2_TRACE_CTL,
1138                                            "/*---TRACE_CTL----*/"
1139                                            " pvr2_hdw_cmd_usbstream(0)");
1140                                 pvr2_hdw_cmd_usbstream(hdw,0);
1141                         }
1142                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1143                                 pvr2_trace(PVR2_TRACE_CTL,
1144                                            "/*---TRACE_CTL----*/"
1145                                            " decoder disable");
1146                                 if (hdw->decoder_ctrl) {
1147                                         hdw->decoder_ctrl->enable(
1148                                                 hdw->decoder_ctrl->ctxt,0);
1149                                 } else {
1150                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1151                                                    "WARNING:"
1152                                                    " No decoder present");
1153                                 }
1154                                 hdw->subsys_enabled_mask &=
1155                                         ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1156                         }
1157                         if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1158                                 hdw->subsys_enabled_mask &=
1159                                         ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1160                         }
1161                 }
1162                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1163                 if (vmsk) {
1164                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1165                                 pvr2_trace(PVR2_TRACE_CTL,
1166                                            "/*---TRACE_CTL----*/"
1167                                            " pvr2_upload_firmware2");
1168                                 ret = pvr2_upload_firmware2(hdw);
1169                                 if (ret) {
1170                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1171                                                    "Failure uploading encoder"
1172                                                    " firmware");
1173                                         pvr2_hdw_render_useless(hdw);
1174                                         break;
1175                                 }
1176                         }
1177                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1178                                 pvr2_trace(PVR2_TRACE_CTL,
1179                                            "/*---TRACE_CTL----*/"
1180                                            " pvr2_encoder_configure");
1181                                 ret = pvr2_encoder_configure(hdw);
1182                                 if (ret) {
1183                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1184                                                    "Error recovery initiated");
1185                                         hdw->subsys_enabled_mask &=
1186                                                 ~FIRMWARE_RECOVERY_BITS;
1187                                         continue;
1188                                 }
1189                         }
1190                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1191                                 pvr2_trace(PVR2_TRACE_CTL,
1192                                            "/*---TRACE_CTL----*/"
1193                                            " decoder enable");
1194                                 if (hdw->decoder_ctrl) {
1195                                         hdw->decoder_ctrl->enable(
1196                                                 hdw->decoder_ctrl->ctxt,!0);
1197                                 } else {
1198                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1199                                                    "WARNING:"
1200                                                    " No decoder present");
1201                                 }
1202                                 hdw->subsys_enabled_mask |=
1203                                         (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1204                         }
1205                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1206                                 pvr2_trace(PVR2_TRACE_CTL,
1207                                            "/*---TRACE_CTL----*/"
1208                                            " pvr2_hdw_cmd_usbstream(1)");
1209                                 pvr2_hdw_cmd_usbstream(hdw,!0);
1210                         }
1211                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1212                                 pvr2_trace(PVR2_TRACE_CTL,
1213                                            "/*---TRACE_CTL----*/"
1214                                            " pvr2_encoder_start");
1215                                 ret = pvr2_encoder_start(hdw);
1216                                 if (ret) {
1217                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1218                                                    "Error recovery initiated");
1219                                         hdw->subsys_enabled_mask &=
1220                                                 ~FIRMWARE_RECOVERY_BITS;
1221                                         continue;
1222                                 }
1223                         }
1224                 }
1225         }
1226 }
1227
1228
1229 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1230                              unsigned long msk,unsigned long val)
1231 {
1232         LOCK_TAKE(hdw->big_lock); do {
1233                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1234         } while (0); LOCK_GIVE(hdw->big_lock);
1235 }
1236
1237
1238 void pvr2_hdw_subsys_bit_set(struct pvr2_hdw *hdw,unsigned long msk)
1239 {
1240         pvr2_hdw_subsys_bit_chg(hdw,msk,msk);
1241 }
1242
1243
1244 void pvr2_hdw_subsys_bit_clr(struct pvr2_hdw *hdw,unsigned long msk)
1245 {
1246         pvr2_hdw_subsys_bit_chg(hdw,msk,0);
1247 }
1248
1249
1250 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1251 {
1252         return hdw->subsys_enabled_mask;
1253 }
1254
1255
1256 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1257 {
1258         return hdw->subsys_stream_mask;
1259 }
1260
1261
1262 void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1263                                             unsigned long msk,
1264                                             unsigned long val)
1265 {
1266         unsigned long val2;
1267         msk &= PVR2_SUBSYS_ALL;
1268         val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1269         pvr2_trace(PVR2_TRACE_INIT,
1270                    "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1271                    msk,val,hdw->subsys_stream_mask,val2);
1272         hdw->subsys_stream_mask = val2;
1273 }
1274
1275
1276 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1277                                     unsigned long msk,
1278                                     unsigned long val)
1279 {
1280         LOCK_TAKE(hdw->big_lock); do {
1281                 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1282         } while (0); LOCK_GIVE(hdw->big_lock);
1283 }
1284
1285
1286 int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1287 {
1288         if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1289         if (enableFl) {
1290                 pvr2_trace(PVR2_TRACE_START_STOP,
1291                            "/*--TRACE_STREAM--*/ enable");
1292                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1293         } else {
1294                 pvr2_trace(PVR2_TRACE_START_STOP,
1295                            "/*--TRACE_STREAM--*/ disable");
1296                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1297         }
1298         if (!hdw->flag_ok) return -EIO;
1299         hdw->flag_streaming_enabled = enableFl != 0;
1300         return 0;
1301 }
1302
1303
1304 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1305 {
1306         return hdw->flag_streaming_enabled != 0;
1307 }
1308
1309
1310 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1311 {
1312         int ret;
1313         LOCK_TAKE(hdw->big_lock); do {
1314                 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1315         } while (0); LOCK_GIVE(hdw->big_lock);
1316         return ret;
1317 }
1318
1319
1320 int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1321                                      enum pvr2_config config)
1322 {
1323         unsigned long sm = hdw->subsys_enabled_mask;
1324         if (!hdw->flag_ok) return -EIO;
1325         pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1326         hdw->config = config;
1327         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1328         return 0;
1329 }
1330
1331
1332 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1333 {
1334         int ret;
1335         if (!hdw->flag_ok) return -EIO;
1336         LOCK_TAKE(hdw->big_lock);
1337         ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1338         LOCK_GIVE(hdw->big_lock);
1339         return ret;
1340 }
1341
1342
1343 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1344 {
1345         int unit_number = hdw->unit_number;
1346         int tp = -1;
1347         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1348                 tp = tuner[unit_number];
1349         }
1350         if (tp < 0) return -EINVAL;
1351         hdw->tuner_type = tp;
1352         return 0;
1353 }
1354
1355
1356 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1357 {
1358         int unit_number = hdw->unit_number;
1359         int tp = 0;
1360         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1361                 tp = video_std[unit_number];
1362         }
1363         return tp;
1364 }
1365
1366
1367 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1368 {
1369         int unit_number = hdw->unit_number;
1370         int tp = 0;
1371         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1372                 tp = tolerance[unit_number];
1373         }
1374         return tp;
1375 }
1376
1377
1378 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1379 {
1380         /* Try a harmless request to fetch the eeprom's address over
1381            endpoint 1.  See what happens.  Only the full FX2 image can
1382            respond to this.  If this probe fails then likely the FX2
1383            firmware needs be loaded. */
1384         int result;
1385         LOCK_TAKE(hdw->ctl_lock); do {
1386                 hdw->cmd_buffer[0] = 0xeb;
1387                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1388                                            hdw->cmd_buffer,1,
1389                                            hdw->cmd_buffer,1);
1390                 if (result < 0) break;
1391         } while(0); LOCK_GIVE(hdw->ctl_lock);
1392         if (result) {
1393                 pvr2_trace(PVR2_TRACE_INIT,
1394                            "Probe of device endpoint 1 result status %d",
1395                            result);
1396         } else {
1397                 pvr2_trace(PVR2_TRACE_INIT,
1398                            "Probe of device endpoint 1 succeeded");
1399         }
1400         return result == 0;
1401 }
1402
1403 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1404 {
1405         char buf[40];
1406         unsigned int bcnt;
1407         v4l2_std_id std1,std2;
1408
1409         std1 = get_default_standard(hdw);
1410
1411         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1412         pvr2_trace(PVR2_TRACE_INIT,
1413                    "Supported video standard(s) reported by eeprom: %.*s",
1414                    bcnt,buf);
1415
1416         hdw->std_mask_avail = hdw->std_mask_eeprom;
1417
1418         std2 = std1 & ~hdw->std_mask_avail;
1419         if (std2) {
1420                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1421                 pvr2_trace(PVR2_TRACE_INIT,
1422                            "Expanding supported video standards"
1423                            " to include: %.*s",
1424                            bcnt,buf);
1425                 hdw->std_mask_avail |= std2;
1426         }
1427
1428         pvr2_hdw_internal_set_std_avail(hdw);
1429
1430         if (std1) {
1431                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1432                 pvr2_trace(PVR2_TRACE_INIT,
1433                            "Initial video standard forced to %.*s",
1434                            bcnt,buf);
1435                 hdw->std_mask_cur = std1;
1436                 hdw->std_dirty = !0;
1437                 pvr2_hdw_internal_find_stdenum(hdw);
1438                 return;
1439         }
1440
1441         if (hdw->std_enum_cnt > 1) {
1442                 // Autoselect the first listed standard
1443                 hdw->std_enum_cur = 1;
1444                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1445                 hdw->std_dirty = !0;
1446                 pvr2_trace(PVR2_TRACE_INIT,
1447                            "Initial video standard auto-selected to %s",
1448                            hdw->std_defs[hdw->std_enum_cur-1].name);
1449                 return;
1450         }
1451
1452         pvr2_trace(PVR2_TRACE_EEPROM,
1453                    "Unable to select a viable initial video standard");
1454 }
1455
1456
1457 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1458 {
1459         int ret;
1460         unsigned int idx;
1461         struct pvr2_ctrl *cptr;
1462         int reloadFl = 0;
1463         if (!reloadFl) {
1464                 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1465                             == 0);
1466                 if (reloadFl) {
1467                         pvr2_trace(PVR2_TRACE_INIT,
1468                                    "USB endpoint config looks strange"
1469                                    "; possibly firmware needs to be loaded");
1470                 }
1471         }
1472         if (!reloadFl) {
1473                 reloadFl = !pvr2_hdw_check_firmware(hdw);
1474                 if (reloadFl) {
1475                         pvr2_trace(PVR2_TRACE_INIT,
1476                                    "Check for FX2 firmware failed"
1477                                    "; possibly firmware needs to be loaded");
1478                 }
1479         }
1480         if (reloadFl) {
1481                 if (pvr2_upload_firmware1(hdw) != 0) {
1482                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1483                                    "Failure uploading firmware1");
1484                 }
1485                 return;
1486         }
1487         hdw->fw1_state = FW1_STATE_OK;
1488
1489         if (initusbreset) {
1490                 pvr2_hdw_device_reset(hdw);
1491         }
1492         if (!pvr2_hdw_dev_ok(hdw)) return;
1493
1494         for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1495                 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1496         }
1497
1498         pvr2_hdw_cmd_powerup(hdw);
1499         if (!pvr2_hdw_dev_ok(hdw)) return;
1500
1501         if (pvr2_upload_firmware2(hdw)){
1502                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1503                 pvr2_hdw_render_useless(hdw);
1504                 return;
1505         }
1506
1507         // This step MUST happen after the earlier powerup step.
1508         pvr2_i2c_core_init(hdw);
1509         if (!pvr2_hdw_dev_ok(hdw)) return;
1510
1511         for (idx = 0; idx < CTRL_COUNT; idx++) {
1512                 cptr = hdw->controls + idx;
1513                 if (cptr->info->skip_init) continue;
1514                 if (!cptr->info->set_value) continue;
1515                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1516         }
1517
1518         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1519         // thread-safe against the normal pvr2_send_request() mechanism.
1520         // (We should make it thread safe).
1521
1522         ret = pvr2_hdw_get_eeprom_addr(hdw);
1523         if (!pvr2_hdw_dev_ok(hdw)) return;
1524         if (ret < 0) {
1525                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1526                            "Unable to determine location of eeprom, skipping");
1527         } else {
1528                 hdw->eeprom_addr = ret;
1529                 pvr2_eeprom_analyze(hdw);
1530                 if (!pvr2_hdw_dev_ok(hdw)) return;
1531         }
1532
1533         pvr2_hdw_setup_std(hdw);
1534
1535         if (!get_default_tuner_type(hdw)) {
1536                 pvr2_trace(PVR2_TRACE_INIT,
1537                            "pvr2_hdw_setup: Tuner type overridden to %d",
1538                            hdw->tuner_type);
1539         }
1540
1541         hdw->tuner_updated = !0;
1542         pvr2_i2c_core_check_stale(hdw);
1543         hdw->tuner_updated = 0;
1544
1545         if (!pvr2_hdw_dev_ok(hdw)) return;
1546
1547         pvr2_hdw_commit_ctl_internal(hdw);
1548         if (!pvr2_hdw_dev_ok(hdw)) return;
1549
1550         hdw->vid_stream = pvr2_stream_create();
1551         if (!pvr2_hdw_dev_ok(hdw)) return;
1552         pvr2_trace(PVR2_TRACE_INIT,
1553                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1554         if (hdw->vid_stream) {
1555                 idx = get_default_error_tolerance(hdw);
1556                 if (idx) {
1557                         pvr2_trace(PVR2_TRACE_INIT,
1558                                    "pvr2_hdw_setup: video stream %p"
1559                                    " setting tolerance %u",
1560                                    hdw->vid_stream,idx);
1561                 }
1562                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1563                                   PVR2_VID_ENDPOINT,idx);
1564         }
1565
1566         if (!pvr2_hdw_dev_ok(hdw)) return;
1567
1568         /* Make sure everything is up to date */
1569         pvr2_i2c_core_sync(hdw);
1570
1571         if (!pvr2_hdw_dev_ok(hdw)) return;
1572
1573         hdw->flag_init_ok = !0;
1574 }
1575
1576
1577 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1578 {
1579         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1580         LOCK_TAKE(hdw->big_lock); do {
1581                 pvr2_hdw_setup_low(hdw);
1582                 pvr2_trace(PVR2_TRACE_INIT,
1583                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1584                            hdw,hdw->flag_ok,hdw->flag_init_ok);
1585                 if (pvr2_hdw_dev_ok(hdw)) {
1586                         if (pvr2_hdw_init_ok(hdw)) {
1587                                 pvr2_trace(
1588                                         PVR2_TRACE_INFO,
1589                                         "Device initialization"
1590                                         " completed successfully.");
1591                                 break;
1592                         }
1593                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1594                                 pvr2_trace(
1595                                         PVR2_TRACE_INFO,
1596                                         "Device microcontroller firmware"
1597                                         " (re)loaded; it should now reset"
1598                                         " and reconnect.");
1599                                 break;
1600                         }
1601                         pvr2_trace(
1602                                 PVR2_TRACE_ERROR_LEGS,
1603                                 "Device initialization was not successful.");
1604                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1605                                 pvr2_trace(
1606                                         PVR2_TRACE_ERROR_LEGS,
1607                                         "Giving up since device"
1608                                         " microcontroller firmware"
1609                                         " appears to be missing.");
1610                                 break;
1611                         }
1612                 }
1613                 if (procreload) {
1614                         pvr2_trace(
1615                                 PVR2_TRACE_ERROR_LEGS,
1616                                 "Attempting pvrusb2 recovery by reloading"
1617                                 " primary firmware.");
1618                         pvr2_trace(
1619                                 PVR2_TRACE_ERROR_LEGS,
1620                                 "If this works, device should disconnect"
1621                                 " and reconnect in a sane state.");
1622                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1623                         pvr2_upload_firmware1(hdw);
1624                 } else {
1625                         pvr2_trace(
1626                                 PVR2_TRACE_ERROR_LEGS,
1627                                 "***WARNING*** pvrusb2 device hardware"
1628                                 " appears to be jammed"
1629                                 " and I can't clear it.");
1630                         pvr2_trace(
1631                                 PVR2_TRACE_ERROR_LEGS,
1632                                 "You might need to power cycle"
1633                                 " the pvrusb2 device"
1634                                 " in order to recover.");
1635                 }
1636         } while (0); LOCK_GIVE(hdw->big_lock);
1637         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1638         return hdw->flag_init_ok;
1639 }
1640
1641
1642 /* Create and return a structure for interacting with the underlying
1643    hardware */
1644 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1645                                  const struct usb_device_id *devid)
1646 {
1647         unsigned int idx,cnt1,cnt2;
1648         struct pvr2_hdw *hdw;
1649         unsigned int hdw_type;
1650         int valid_std_mask;
1651         struct pvr2_ctrl *cptr;
1652         __u8 ifnum;
1653
1654         hdw_type = devid - pvr2_device_table;
1655         if (hdw_type >=
1656             sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1657                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1658                            "Bogus device type of %u reported",hdw_type);
1659                 return 0;
1660         }
1661
1662         hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1663         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1664                    hdw,pvr2_device_names[hdw_type]);
1665         if (!hdw) goto fail;
1666         memset(hdw,0,sizeof(*hdw));
1667
1668         hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * CTRL_COUNT,
1669                                 GFP_KERNEL);
1670         if (!hdw->controls) goto fail;
1671         memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * CTRL_COUNT);
1672         hdw->hdw_type = hdw_type;
1673
1674         for (idx = 0; idx < 32; idx++) {
1675                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1676         }
1677
1678         for (idx = 0; idx < CTRL_COUNT; idx++) {
1679                 cptr = hdw->controls + idx;
1680                 cptr->hdw = hdw;
1681                 cptr->info = control_defs+idx;
1682         }
1683
1684         // Initialize video standard enum dynamic control
1685         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1686         if (cptr) {
1687                 memcpy(&hdw->std_info_enum,cptr->info,
1688                        sizeof(hdw->std_info_enum));
1689                 cptr->info = &hdw->std_info_enum;
1690
1691         }
1692         // Initialize control data regarding video standard masks
1693         valid_std_mask = pvr2_std_get_usable();
1694         for (idx = 0; idx < 32; idx++) {
1695                 if (!(valid_std_mask & (1 << idx))) continue;
1696                 cnt1 = pvr2_std_id_to_str(
1697                         hdw->std_mask_names[idx],
1698                         sizeof(hdw->std_mask_names[idx])-1,
1699                         1 << idx);
1700                 hdw->std_mask_names[idx][cnt1] = 0;
1701         }
1702         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1703         if (cptr) {
1704                 memcpy(&hdw->std_info_avail,cptr->info,
1705                        sizeof(hdw->std_info_avail));
1706                 cptr->info = &hdw->std_info_avail;
1707                 hdw->std_info_avail.def.type_bitmask.bit_names =
1708                         hdw->std_mask_ptrs;
1709                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1710                         valid_std_mask;
1711         }
1712         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1713         if (cptr) {
1714                 memcpy(&hdw->std_info_cur,cptr->info,
1715                        sizeof(hdw->std_info_cur));
1716                 cptr->info = &hdw->std_info_cur;
1717                 hdw->std_info_cur.def.type_bitmask.bit_names =
1718                         hdw->std_mask_ptrs;
1719                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1720                         valid_std_mask;
1721         }
1722
1723         hdw->eeprom_addr = -1;
1724         hdw->unit_number = -1;
1725         hdw->v4l_minor_number = -1;
1726         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1727         if (!hdw->ctl_write_buffer) goto fail;
1728         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1729         if (!hdw->ctl_read_buffer) goto fail;
1730         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1731         if (!hdw->ctl_write_urb) goto fail;
1732         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1733         if (!hdw->ctl_read_urb) goto fail;
1734
1735         down(&pvr2_unit_sem); do {
1736                 for (idx = 0; idx < PVR_NUM; idx++) {
1737                         if (unit_pointers[idx]) continue;
1738                         hdw->unit_number = idx;
1739                         unit_pointers[idx] = hdw;
1740                         break;
1741                 }
1742         } while (0); up(&pvr2_unit_sem);
1743
1744         cnt1 = 0;
1745         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1746         cnt1 += cnt2;
1747         if (hdw->unit_number >= 0) {
1748                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1749                                  ('a' + hdw->unit_number));
1750                 cnt1 += cnt2;
1751         }
1752         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1753         hdw->name[cnt1] = 0;
1754
1755         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1756                    hdw->unit_number,hdw->name);
1757
1758         hdw->tuner_type = -1;
1759         hdw->flag_ok = !0;
1760         /* Initialize the mask of subsystems that we will shut down when we
1761            stop streaming. */
1762         hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1763         hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1764
1765         pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1766                    hdw->subsys_stream_mask);
1767
1768         hdw->usb_intf = intf;
1769         hdw->usb_dev = interface_to_usbdev(intf);
1770
1771         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1772         usb_set_interface(hdw->usb_dev,ifnum,0);
1773
1774         mutex_init(&hdw->ctl_lock_mutex);
1775         mutex_init(&hdw->big_lock_mutex);
1776
1777         return hdw;
1778  fail:
1779         if (hdw) {
1780                 if (hdw->ctl_read_urb) usb_free_urb(hdw->ctl_read_urb);
1781                 if (hdw->ctl_write_urb) usb_free_urb(hdw->ctl_write_urb);
1782                 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1783                 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1784                 if (hdw->controls) kfree(hdw->controls);
1785                 kfree(hdw);
1786         }
1787         return 0;
1788 }
1789
1790
1791 /* Remove _all_ associations between this driver and the underlying USB
1792    layer. */
1793 void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1794 {
1795         if (hdw->flag_disconnected) return;
1796         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1797         if (hdw->ctl_read_urb) {
1798                 usb_kill_urb(hdw->ctl_read_urb);
1799                 usb_free_urb(hdw->ctl_read_urb);
1800                 hdw->ctl_read_urb = 0;
1801         }
1802         if (hdw->ctl_write_urb) {
1803                 usb_kill_urb(hdw->ctl_write_urb);
1804                 usb_free_urb(hdw->ctl_write_urb);
1805                 hdw->ctl_write_urb = 0;
1806         }
1807         if (hdw->ctl_read_buffer) {
1808                 kfree(hdw->ctl_read_buffer);
1809                 hdw->ctl_read_buffer = 0;
1810         }
1811         if (hdw->ctl_write_buffer) {
1812                 kfree(hdw->ctl_write_buffer);
1813                 hdw->ctl_write_buffer = 0;
1814         }
1815         pvr2_hdw_render_useless_unlocked(hdw);
1816         hdw->flag_disconnected = !0;
1817         hdw->usb_dev = 0;
1818         hdw->usb_intf = 0;
1819 }
1820
1821
1822 /* Destroy hardware interaction structure */
1823 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
1824 {
1825         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
1826         if (hdw->fw_buffer) {
1827                 kfree(hdw->fw_buffer);
1828                 hdw->fw_buffer = 0;
1829         }
1830         if (hdw->vid_stream) {
1831                 pvr2_stream_destroy(hdw->vid_stream);
1832                 hdw->vid_stream = 0;
1833         }
1834         if (hdw->audio_stat) {
1835                 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
1836         }
1837         if (hdw->decoder_ctrl) {
1838                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
1839         }
1840         pvr2_i2c_core_done(hdw);
1841         pvr2_hdw_remove_usb_stuff(hdw);
1842         down(&pvr2_unit_sem); do {
1843                 if ((hdw->unit_number >= 0) &&
1844                     (hdw->unit_number < PVR_NUM) &&
1845                     (unit_pointers[hdw->unit_number] == hdw)) {
1846                         unit_pointers[hdw->unit_number] = 0;
1847                 }
1848         } while (0); up(&pvr2_unit_sem);
1849         kfree(hdw->controls);
1850         if (hdw->std_defs) kfree(hdw->std_defs);
1851         if (hdw->std_enum_names) kfree(hdw->std_enum_names);
1852         kfree(hdw);
1853 }
1854
1855
1856 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
1857 {
1858         return hdw->flag_init_ok;
1859 }
1860
1861
1862 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
1863 {
1864         return (hdw && hdw->flag_ok);
1865 }
1866
1867
1868 /* Called when hardware has been unplugged */
1869 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
1870 {
1871         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
1872         LOCK_TAKE(hdw->big_lock);
1873         LOCK_TAKE(hdw->ctl_lock);
1874         pvr2_hdw_remove_usb_stuff(hdw);
1875         LOCK_GIVE(hdw->ctl_lock);
1876         LOCK_GIVE(hdw->big_lock);
1877 }
1878
1879
1880 // Attempt to autoselect an appropriate value for std_enum_cur given
1881 // whatever is currently in std_mask_cur
1882 void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
1883 {
1884         unsigned int idx;
1885         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
1886                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
1887                         hdw->std_enum_cur = idx;
1888                         return;
1889                 }
1890         }
1891         hdw->std_enum_cur = 0;
1892 }
1893
1894
1895 // Calculate correct set of enumerated standards based on currently known
1896 // set of available standards bits.
1897 void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
1898 {
1899         struct v4l2_standard *newstd;
1900         unsigned int std_cnt;
1901         unsigned int idx;
1902
1903         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
1904
1905         if (hdw->std_defs) {
1906                 kfree(hdw->std_defs);
1907                 hdw->std_defs = 0;
1908         }
1909         hdw->std_enum_cnt = 0;
1910         if (hdw->std_enum_names) {
1911                 kfree(hdw->std_enum_names);
1912                 hdw->std_enum_names = 0;
1913         }
1914
1915         if (!std_cnt) {
1916                 pvr2_trace(
1917                         PVR2_TRACE_ERROR_LEGS,
1918                         "WARNING: Failed to identify any viable standards");
1919         }
1920         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
1921         hdw->std_enum_names[0] = "none";
1922         for (idx = 0; idx < std_cnt; idx++) {
1923                 hdw->std_enum_names[idx+1] =
1924                         newstd[idx].name;
1925         }
1926         // Set up the dynamic control for this standard
1927         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
1928         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
1929         hdw->std_defs = newstd;
1930         hdw->std_enum_cnt = std_cnt+1;
1931         hdw->std_enum_cur = 0;
1932         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1933 }
1934
1935
1936 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
1937                                struct v4l2_standard *std,
1938                                unsigned int idx)
1939 {
1940         int ret = -EINVAL;
1941         if (!idx) return ret;
1942         LOCK_TAKE(hdw->big_lock); do {
1943                 if (idx >= hdw->std_enum_cnt) break;
1944                 idx--;
1945                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
1946                 ret = 0;
1947         } while (0); LOCK_GIVE(hdw->big_lock);
1948         return ret;
1949 }
1950
1951
1952 /* Get the number of defined controls */
1953 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
1954 {
1955         return CTRL_COUNT;
1956 }
1957
1958
1959 /* Retrieve a control handle given its index (0..count-1) */
1960 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
1961                                              unsigned int idx)
1962 {
1963         if (idx >= CTRL_COUNT) return 0;
1964         return hdw->controls + idx;
1965 }
1966
1967
1968 /* Retrieve a control handle given its index (0..count-1) */
1969 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
1970                                           unsigned int ctl_id)
1971 {
1972         struct pvr2_ctrl *cptr;
1973         unsigned int idx;
1974         int i;
1975
1976         /* This could be made a lot more efficient, but for now... */
1977         for (idx = 0; idx < CTRL_COUNT; idx++) {
1978                 cptr = hdw->controls + idx;
1979                 i = cptr->info->internal_id;
1980                 if (i && (i == ctl_id)) return cptr;
1981         }
1982         return 0;
1983 }
1984
1985
1986 /* Given an ID, retrieve the control structure associated with it. */
1987 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
1988 {
1989         struct pvr2_ctrl *cptr;
1990         unsigned int idx;
1991         int i;
1992
1993         /* This could be made a lot more efficient, but for now... */
1994         for (idx = 0; idx < CTRL_COUNT; idx++) {
1995                 cptr = hdw->controls + idx;
1996                 i = cptr->info->v4l_id;
1997                 if (i && (i == ctl_id)) return cptr;
1998         }
1999         return 0;
2000 }
2001
2002
2003 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2004 {
2005         switch (tp) {
2006         case pvr2_ctl_int: return "integer";
2007         case pvr2_ctl_enum: return "enum";
2008         case pvr2_ctl_bitmask: return "bitmask";
2009         }
2010         return "";
2011 }
2012
2013
2014 /* Commit all control changes made up to this point.  Subsystems can be
2015    indirectly affected by these changes.  For a given set of things being
2016    committed, we'll clear the affected subsystem bits and then once we're
2017    done committing everything we'll make a request to restore the subsystem
2018    state(s) back to their previous value before this function was called.
2019    Thus we can automatically reconfigure affected pieces of the driver as
2020    controls are changed. */
2021 int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2022 {
2023         unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2024         unsigned long stale_subsys_mask = 0;
2025         unsigned int idx;
2026         struct pvr2_ctrl *cptr;
2027         int value;
2028         int commit_flag = 0;
2029         char buf[100];
2030         unsigned int bcnt,ccnt;
2031
2032         for (idx = 0; idx < CTRL_COUNT; idx++) {
2033                 cptr = hdw->controls + idx;
2034                 if (cptr->info->is_dirty == 0) continue;
2035                 if (!cptr->info->is_dirty(cptr)) continue;
2036                 if (!commit_flag) {
2037                         commit_flag = !0;
2038                 }
2039
2040                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2041                                  cptr->info->name);
2042                 value = 0;
2043                 cptr->info->get_value(cptr,&value);
2044                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2045                                                 buf+bcnt,
2046                                                 sizeof(buf)-bcnt,&ccnt);
2047                 bcnt += ccnt;
2048                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2049                                   get_ctrl_typename(cptr->info->type));
2050                 pvr2_trace(PVR2_TRACE_CTL,
2051                            "/*--TRACE_COMMIT--*/ %.*s",
2052                            bcnt,buf);
2053         }
2054
2055         if (!commit_flag) {
2056                 /* Nothing has changed */
2057                 return 0;
2058         }
2059
2060         /* When video standard changes, reset the hres and vres values -
2061            but if the user has pending changes there, then let the changes
2062            take priority. */
2063         if (hdw->std_dirty) {
2064                 /* Rewrite the vertical resolution to be appropriate to the
2065                    video standard that has been selected. */
2066                 int nvres;
2067                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2068                         nvres = 480;
2069                 } else {
2070                         nvres = 576;
2071                 }
2072                 if (nvres != hdw->res_ver_val) {
2073                         hdw->res_ver_val = nvres;
2074                         hdw->res_ver_dirty = !0;
2075                 }
2076                 if (!hdw->interlace_val) {
2077                         hdw->interlace_val = 0;
2078                         hdw->interlace_dirty = !0;
2079                 }
2080         }
2081
2082         if (hdw->std_dirty ||
2083             hdw->res_ver_dirty ||
2084             hdw->res_hor_dirty ||
2085             hdw->interlace_dirty ||
2086             hdw->vbr_dirty ||
2087             hdw->videobitrate_dirty ||
2088             hdw->videopeak_dirty ||
2089             hdw->audiobitrate_dirty ||
2090             hdw->srate_dirty ||
2091             hdw->audiolayer_dirty ||
2092             hdw->audiocrc_dirty ||
2093             hdw->audioemphasis_dirty) {
2094                 /* If any of this changes, then the encoder needs to be
2095                    reconfigured, and we need to reset the stream. */
2096                 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2097                 stale_subsys_mask |= hdw->subsys_stream_mask;
2098         }
2099
2100         /* Scan i2c core at this point - before we clear all the dirty
2101            bits.  Various parts of the i2c core will notice dirty bits as
2102            appropriate and arrange to broadcast or directly send updates to
2103            the client drivers in order to keep everything in sync */
2104         pvr2_i2c_core_check_stale(hdw);
2105
2106         for (idx = 0; idx < CTRL_COUNT; idx++) {
2107                 cptr = hdw->controls + idx;
2108                 if (!cptr->info->clear_dirty) continue;
2109                 cptr->info->clear_dirty(cptr);
2110         }
2111
2112         /* Now execute i2c core update */
2113         pvr2_i2c_core_sync(hdw);
2114
2115         pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2116         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2117
2118         return 0;
2119 }
2120
2121
2122 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2123 {
2124         LOCK_TAKE(hdw->big_lock); do {
2125                 pvr2_hdw_commit_ctl_internal(hdw);
2126         } while (0); LOCK_GIVE(hdw->big_lock);
2127         return 0;
2128 }
2129
2130
2131 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2132 {
2133         LOCK_TAKE(hdw->big_lock); do {
2134                 pvr2_i2c_core_sync(hdw);
2135         } while (0); LOCK_GIVE(hdw->big_lock);
2136 }
2137
2138
2139 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2140                                  void (*func)(void *),
2141                                  void *data)
2142 {
2143         LOCK_TAKE(hdw->big_lock); do {
2144                 hdw->poll_trigger_func = func;
2145                 hdw->poll_trigger_data = data;
2146         } while (0); LOCK_GIVE(hdw->big_lock);
2147 }
2148
2149
2150 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2151 {
2152         if (hdw->poll_trigger_func) {
2153                 hdw->poll_trigger_func(hdw->poll_trigger_data);
2154         }
2155 }
2156
2157
2158 void pvr2_hdw_poll_trigger(struct pvr2_hdw *hdw)
2159 {
2160         LOCK_TAKE(hdw->big_lock); do {
2161                 pvr2_hdw_poll_trigger_unlocked(hdw);
2162         } while (0); LOCK_GIVE(hdw->big_lock);
2163 }
2164
2165
2166 /* Return name for this driver instance */
2167 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2168 {
2169         return hdw->name;
2170 }
2171
2172
2173 /* Return bit mask indicating signal status */
2174 unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2175 {
2176         unsigned int msk = 0;
2177         switch (hdw->input_val) {
2178         case PVR2_CVAL_INPUT_TV:
2179         case PVR2_CVAL_INPUT_RADIO:
2180                 if (hdw->decoder_ctrl &&
2181                     hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2182                         msk |= PVR2_SIGNAL_OK;
2183                         if (hdw->audio_stat &&
2184                             hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2185                                 if (hdw->flag_stereo) {
2186                                         msk |= PVR2_SIGNAL_STEREO;
2187                                 }
2188                                 if (hdw->flag_bilingual) {
2189                                         msk |= PVR2_SIGNAL_SAP;
2190                                 }
2191                         }
2192                 }
2193                 break;
2194         default:
2195                 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2196         }
2197         return msk;
2198 }
2199
2200
2201 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2202 {
2203         int result;
2204         LOCK_TAKE(hdw->ctl_lock); do {
2205                 hdw->cmd_buffer[0] = 0x0b;
2206                 result = pvr2_send_request(hdw,
2207                                            hdw->cmd_buffer,1,
2208                                            hdw->cmd_buffer,1);
2209                 if (result < 0) break;
2210                 result = (hdw->cmd_buffer[0] != 0);
2211         } while(0); LOCK_GIVE(hdw->ctl_lock);
2212         return result;
2213 }
2214
2215
2216 /* Return bit mask indicating signal status */
2217 unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2218 {
2219         unsigned int msk = 0;
2220         LOCK_TAKE(hdw->big_lock); do {
2221                 msk = pvr2_hdw_get_signal_status_internal(hdw);
2222         } while (0); LOCK_GIVE(hdw->big_lock);
2223         return msk;
2224 }
2225
2226
2227 /* Get handle to video output stream */
2228 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2229 {
2230         return hp->vid_stream;
2231 }
2232
2233
2234 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2235 {
2236         LOCK_TAKE(hdw->big_lock); do {
2237                 hdw->log_requested = !0;
2238                 pvr2_i2c_core_check_stale(hdw);
2239                 hdw->log_requested = 0;
2240                 pvr2_i2c_core_sync(hdw);
2241         } while (0); LOCK_GIVE(hdw->big_lock);
2242 }
2243
2244 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2245 {
2246         int ret;
2247         u16 address;
2248         unsigned int pipe;
2249         LOCK_TAKE(hdw->big_lock); do {
2250                 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2251
2252                 if (!enable_flag) {
2253                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2254                                    "Cleaning up after CPU firmware fetch");
2255                         kfree(hdw->fw_buffer);
2256                         hdw->fw_buffer = 0;
2257                         hdw->fw_size = 0;
2258                         /* Now release the CPU.  It will disconnect and
2259                            reconnect later. */
2260                         pvr2_hdw_cpureset_assert(hdw,0);
2261                         break;
2262                 }
2263
2264                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2265                            "Preparing to suck out CPU firmware");
2266                 hdw->fw_size = 0x2000;
2267                 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2268                 if (!hdw->fw_buffer) {
2269                         hdw->fw_size = 0;
2270                         break;
2271                 }
2272
2273                 memset(hdw->fw_buffer,0,hdw->fw_size);
2274
2275                 /* We have to hold the CPU during firmware upload. */
2276                 pvr2_hdw_cpureset_assert(hdw,1);
2277
2278                 /* download the firmware from address 0000-1fff in 2048
2279                    (=0x800) bytes chunk. */
2280
2281                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2282                 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2283                 for(address = 0; address < hdw->fw_size; address += 0x800) {
2284                         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2285                                               address,0,
2286                                               hdw->fw_buffer+address,0x800,HZ);
2287                         if (ret < 0) break;
2288                 }
2289
2290                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2291
2292         } while (0); LOCK_GIVE(hdw->big_lock);
2293 }
2294
2295
2296 /* Return true if we're in a mode for retrieval CPU firmware */
2297 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2298 {
2299         return hdw->fw_buffer != 0;
2300 }
2301
2302
2303 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2304                        char *buf,unsigned int cnt)
2305 {
2306         int ret = -EINVAL;
2307         LOCK_TAKE(hdw->big_lock); do {
2308                 if (!buf) break;
2309                 if (!cnt) break;
2310
2311                 if (!hdw->fw_buffer) {
2312                         ret = -EIO;
2313                         break;
2314                 }
2315
2316                 if (offs >= hdw->fw_size) {
2317                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2318                                    "Read firmware data offs=%d EOF",
2319                                    offs);
2320                         ret = 0;
2321                         break;
2322                 }
2323
2324                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2325
2326                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2327
2328                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2329                            "Read firmware data offs=%d cnt=%d",
2330                            offs,cnt);
2331                 ret = cnt;
2332         } while (0); LOCK_GIVE(hdw->big_lock);
2333
2334         return ret;
2335 }
2336
2337
2338 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2339 {
2340         return hdw->v4l_minor_number;
2341 }
2342
2343
2344 /* Store the v4l minor device number */
2345 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2346 {
2347         hdw->v4l_minor_number = v;
2348 }
2349
2350
2351 void pvr2_reset_ctl_endpoints(struct pvr2_hdw *hdw)
2352 {
2353         if (!hdw->usb_dev) return;
2354         usb_settoggle(hdw->usb_dev, PVR2_CTL_WRITE_ENDPOINT & 0xf,
2355                       !(PVR2_CTL_WRITE_ENDPOINT & USB_DIR_IN), 0);
2356         usb_settoggle(hdw->usb_dev, PVR2_CTL_READ_ENDPOINT & 0xf,
2357                       !(PVR2_CTL_READ_ENDPOINT & USB_DIR_IN), 0);
2358         usb_clear_halt(hdw->usb_dev,
2359                        usb_rcvbulkpipe(hdw->usb_dev,
2360                                        PVR2_CTL_READ_ENDPOINT & 0x7f));
2361         usb_clear_halt(hdw->usb_dev,
2362                        usb_sndbulkpipe(hdw->usb_dev,
2363                                        PVR2_CTL_WRITE_ENDPOINT & 0x7f));
2364 }
2365
2366
2367 static void pvr2_ctl_write_complete(struct urb *urb, struct pt_regs *regs)
2368 {
2369         struct pvr2_hdw *hdw = urb->context;
2370         hdw->ctl_write_pend_flag = 0;
2371         if (hdw->ctl_read_pend_flag) return;
2372         complete(&hdw->ctl_done);
2373 }
2374
2375
2376 static void pvr2_ctl_read_complete(struct urb *urb, struct pt_regs *regs)
2377 {
2378         struct pvr2_hdw *hdw = urb->context;
2379         hdw->ctl_read_pend_flag = 0;
2380         if (hdw->ctl_write_pend_flag) return;
2381         complete(&hdw->ctl_done);
2382 }
2383
2384
2385 static void pvr2_ctl_timeout(unsigned long data)
2386 {
2387         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2388         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2389                 hdw->ctl_timeout_flag = !0;
2390                 if (hdw->ctl_write_pend_flag && hdw->ctl_write_urb) {
2391                         usb_unlink_urb(hdw->ctl_write_urb);
2392                 }
2393                 if (hdw->ctl_read_pend_flag && hdw->ctl_read_urb) {
2394                         usb_unlink_urb(hdw->ctl_read_urb);
2395                 }
2396         }
2397 }
2398
2399
2400 int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2401                          unsigned int timeout,int probe_fl,
2402                          void *write_data,unsigned int write_len,
2403                          void *read_data,unsigned int read_len)
2404 {
2405         unsigned int idx;
2406         int status = 0;
2407         struct timer_list timer;
2408         if (!hdw->ctl_lock_held) {
2409                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2410                            "Attempted to execute control transfer"
2411                            " without lock!!");
2412                 return -EDEADLK;
2413         }
2414         if ((!hdw->flag_ok) && !probe_fl) {
2415                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2416                            "Attempted to execute control transfer"
2417                            " when device not ok");
2418                 return -EIO;
2419         }
2420         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2421                 if (!probe_fl) {
2422                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2423                                    "Attempted to execute control transfer"
2424                                    " when USB is disconnected");
2425                 }
2426                 return -ENOTTY;
2427         }
2428
2429         /* Ensure that we have sane parameters */
2430         if (!write_data) write_len = 0;
2431         if (!read_data) read_len = 0;
2432         if (write_len > PVR2_CTL_BUFFSIZE) {
2433                 pvr2_trace(
2434                         PVR2_TRACE_ERROR_LEGS,
2435                         "Attempted to execute %d byte"
2436                         " control-write transfer (limit=%d)",
2437                         write_len,PVR2_CTL_BUFFSIZE);
2438                 return -EINVAL;
2439         }
2440         if (read_len > PVR2_CTL_BUFFSIZE) {
2441                 pvr2_trace(
2442                         PVR2_TRACE_ERROR_LEGS,
2443                         "Attempted to execute %d byte"
2444                         " control-read transfer (limit=%d)",
2445                         write_len,PVR2_CTL_BUFFSIZE);
2446                 return -EINVAL;
2447         }
2448         if ((!write_len) && (!read_len)) {
2449                 pvr2_trace(
2450                         PVR2_TRACE_ERROR_LEGS,
2451                         "Attempted to execute null control transfer?");
2452                 return -EINVAL;
2453         }
2454
2455
2456         hdw->cmd_debug_state = 1;
2457         if (write_len) {
2458                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2459         } else {
2460                 hdw->cmd_debug_code = 0;
2461         }
2462         hdw->cmd_debug_write_len = write_len;
2463         hdw->cmd_debug_read_len = read_len;
2464
2465         /* Initialize common stuff */
2466         init_completion(&hdw->ctl_done);
2467         hdw->ctl_timeout_flag = 0;
2468         hdw->ctl_write_pend_flag = 0;
2469         hdw->ctl_read_pend_flag = 0;
2470         init_timer(&timer);
2471         timer.expires = jiffies + timeout;
2472         timer.data = (unsigned long)hdw;
2473         timer.function = pvr2_ctl_timeout;
2474
2475         if (write_len) {
2476                 hdw->cmd_debug_state = 2;
2477                 /* Transfer write data to internal buffer */
2478                 for (idx = 0; idx < write_len; idx++) {
2479                         hdw->ctl_write_buffer[idx] =
2480                                 ((unsigned char *)write_data)[idx];
2481                 }
2482                 /* Initiate a write request */
2483                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2484                                   hdw->usb_dev,
2485                                   usb_sndbulkpipe(hdw->usb_dev,
2486                                                   PVR2_CTL_WRITE_ENDPOINT),
2487                                   hdw->ctl_write_buffer,
2488                                   write_len,
2489                                   pvr2_ctl_write_complete,
2490                                   hdw);
2491                 hdw->ctl_write_urb->actual_length = 0;
2492                 hdw->ctl_write_pend_flag = !0;
2493                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2494                 if (status < 0) {
2495                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2496                                    "Failed to submit write-control"
2497                                    " URB status=%d",status);
2498                         hdw->ctl_write_pend_flag = 0;
2499                         goto done;
2500                 }
2501         }
2502
2503         if (read_len) {
2504                 hdw->cmd_debug_state = 3;
2505                 memset(hdw->ctl_read_buffer,0x43,read_len);
2506                 /* Initiate a read request */
2507                 usb_fill_bulk_urb(hdw->ctl_read_urb,
2508                                   hdw->usb_dev,
2509                                   usb_rcvbulkpipe(hdw->usb_dev,
2510                                                   PVR2_CTL_READ_ENDPOINT),
2511                                   hdw->ctl_read_buffer,
2512                                   read_len,
2513                                   pvr2_ctl_read_complete,
2514                                   hdw);
2515                 hdw->ctl_read_urb->actual_length = 0;
2516                 hdw->ctl_read_pend_flag = !0;
2517                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2518                 if (status < 0) {
2519                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2520                                    "Failed to submit read-control"
2521                                    " URB status=%d",status);
2522                         hdw->ctl_read_pend_flag = 0;
2523                         goto done;
2524                 }
2525         }
2526
2527         /* Start timer */
2528         add_timer(&timer);
2529
2530         /* Now wait for all I/O to complete */
2531         hdw->cmd_debug_state = 4;
2532         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2533                 wait_for_completion(&hdw->ctl_done);
2534         }
2535         hdw->cmd_debug_state = 5;
2536
2537         /* Stop timer */
2538         del_timer_sync(&timer);
2539
2540         hdw->cmd_debug_state = 6;
2541         status = 0;
2542
2543         if (hdw->ctl_timeout_flag) {
2544                 status = -ETIMEDOUT;
2545                 if (!probe_fl) {
2546                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2547                                    "Timed out control-write");
2548                 }
2549                 goto done;
2550         }
2551
2552         if (write_len) {
2553                 /* Validate results of write request */
2554                 if ((hdw->ctl_write_urb->status != 0) &&
2555                     (hdw->ctl_write_urb->status != -ENOENT) &&
2556                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2557                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
2558                         /* USB subsystem is reporting some kind of failure
2559                            on the write */
2560                         status = hdw->ctl_write_urb->status;
2561                         if (!probe_fl) {
2562                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2563                                            "control-write URB failure,"
2564                                            " status=%d",
2565                                            status);
2566                         }
2567                         goto done;
2568                 }
2569                 if (hdw->ctl_write_urb->actual_length < write_len) {
2570                         /* Failed to write enough data */
2571                         status = -EIO;
2572                         if (!probe_fl) {
2573                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2574                                            "control-write URB short,"
2575                                            " expected=%d got=%d",
2576                                            write_len,
2577                                            hdw->ctl_write_urb->actual_length);
2578                         }
2579                         goto done;
2580                 }
2581         }
2582         if (read_len) {
2583                 /* Validate results of read request */
2584                 if ((hdw->ctl_read_urb->status != 0) &&
2585                     (hdw->ctl_read_urb->status != -ENOENT) &&
2586                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2587                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
2588                         /* USB subsystem is reporting some kind of failure
2589                            on the read */
2590                         status = hdw->ctl_read_urb->status;
2591                         if (!probe_fl) {
2592                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2593                                            "control-read URB failure,"
2594                                            " status=%d",
2595                                            status);
2596                         }
2597                         goto done;
2598                 }
2599                 if (hdw->ctl_read_urb->actual_length < read_len) {
2600                         /* Failed to read enough data */
2601                         status = -EIO;
2602                         if (!probe_fl) {
2603                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2604                                            "control-read URB short,"
2605                                            " expected=%d got=%d",
2606                                            read_len,
2607                                            hdw->ctl_read_urb->actual_length);
2608                         }
2609                         goto done;
2610                 }
2611                 /* Transfer retrieved data out from internal buffer */
2612                 for (idx = 0; idx < read_len; idx++) {
2613                         ((unsigned char *)read_data)[idx] =
2614                                 hdw->ctl_read_buffer[idx];
2615                 }
2616         }
2617
2618  done:
2619
2620         hdw->cmd_debug_state = 0;
2621         if ((status < 0) && (!probe_fl)) {
2622                 pvr2_hdw_render_useless_unlocked(hdw);
2623         }
2624         return status;
2625 }
2626
2627
2628 int pvr2_send_request(struct pvr2_hdw *hdw,
2629                       void *write_data,unsigned int write_len,
2630                       void *read_data,unsigned int read_len)
2631 {
2632         return pvr2_send_request_ex(hdw,HZ*4,0,
2633                                     write_data,write_len,
2634                                     read_data,read_len);
2635 }
2636
2637 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2638 {
2639         int ret;
2640
2641         LOCK_TAKE(hdw->ctl_lock);
2642
2643         hdw->cmd_buffer[0] = 0x04;  /* write register prefix */
2644         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2645         hdw->cmd_buffer[5] = 0;
2646         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2647         hdw->cmd_buffer[7] = reg & 0xff;
2648
2649
2650         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2651
2652         LOCK_GIVE(hdw->ctl_lock);
2653
2654         return ret;
2655 }
2656
2657
2658 int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2659 {
2660         int ret = 0;
2661
2662         LOCK_TAKE(hdw->ctl_lock);
2663
2664         hdw->cmd_buffer[0] = 0x05;  /* read register prefix */
2665         hdw->cmd_buffer[1] = 0;
2666         hdw->cmd_buffer[2] = 0;
2667         hdw->cmd_buffer[3] = 0;
2668         hdw->cmd_buffer[4] = 0;
2669         hdw->cmd_buffer[5] = 0;
2670         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2671         hdw->cmd_buffer[7] = reg & 0xff;
2672
2673         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2674         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2675
2676         LOCK_GIVE(hdw->ctl_lock);
2677
2678         return ret;
2679 }
2680
2681
2682 int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2683 {
2684         int ret;
2685
2686         LOCK_TAKE(hdw->ctl_lock);
2687
2688         hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2689         hdw->cmd_buffer[1] = data & 0xff;
2690
2691         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2692
2693         LOCK_GIVE(hdw->ctl_lock);
2694
2695         return ret;
2696 }
2697
2698
2699 int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2700 {
2701         int ret;
2702
2703         LOCK_TAKE(hdw->ctl_lock);
2704
2705         hdw->cmd_buffer[0] = data;
2706
2707         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2708
2709         LOCK_GIVE(hdw->ctl_lock);
2710
2711         return ret;
2712 }
2713
2714
2715 void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2716 {
2717         if (!hdw->flag_ok) return;
2718         pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2719         hdw->flag_ok = 0;
2720         if (hdw->vid_stream) {
2721                 pvr2_stream_setup(hdw->vid_stream,0,0,0);
2722         }
2723         hdw->flag_streaming_enabled = 0;
2724         hdw->subsys_enabled_mask = 0;
2725 }
2726
2727
2728 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2729 {
2730         LOCK_TAKE(hdw->ctl_lock);
2731         pvr2_hdw_render_useless_unlocked(hdw);
2732         LOCK_GIVE(hdw->ctl_lock);
2733 }
2734
2735
2736 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2737 {
2738         int ret;
2739         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2740         ret = usb_lock_device_for_reset(hdw->usb_dev,0);
2741         if (ret == 1) {
2742                 ret = usb_reset_device(hdw->usb_dev);
2743                 usb_unlock_device(hdw->usb_dev);
2744         } else {
2745                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2746                            "Failed to lock USB device ret=%d",ret);
2747         }
2748         if (init_pause_msec) {
2749                 pvr2_trace(PVR2_TRACE_INFO,
2750                            "Waiting %u msec for hardware to settle",
2751                            init_pause_msec);
2752                 msleep(init_pause_msec);
2753         }
2754
2755 }
2756
2757
2758 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2759 {
2760         char da[1];
2761         unsigned int pipe;
2762         int ret;
2763
2764         if (!hdw->usb_dev) return;
2765
2766         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2767
2768         da[0] = val ? 0x01 : 0x00;
2769
2770         /* Write the CPUCS register on the 8051.  The lsb of the register
2771            is the reset bit; a 1 asserts reset while a 0 clears it. */
2772         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2773         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2774         if (ret < 0) {
2775                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2776                            "cpureset_assert(%d) error=%d",val,ret);
2777                 pvr2_hdw_render_useless(hdw);
2778         }
2779 }
2780
2781
2782 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2783 {
2784         int status;
2785         LOCK_TAKE(hdw->ctl_lock); do {
2786                 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2787                 hdw->flag_ok = !0;
2788                 hdw->cmd_buffer[0] = 0xdd;
2789                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2790         } while (0); LOCK_GIVE(hdw->ctl_lock);
2791         return status;
2792 }
2793
2794
2795 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2796 {
2797         int status;
2798         LOCK_TAKE(hdw->ctl_lock); do {
2799                 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2800                 hdw->cmd_buffer[0] = 0xde;
2801                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2802         } while (0); LOCK_GIVE(hdw->ctl_lock);
2803         return status;
2804 }
2805
2806
2807 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
2808 {
2809         if (!hdw->decoder_ctrl) {
2810                 pvr2_trace(PVR2_TRACE_INIT,
2811                            "Unable to reset decoder: nothing attached");
2812                 return -ENOTTY;
2813         }
2814
2815         if (!hdw->decoder_ctrl->force_reset) {
2816                 pvr2_trace(PVR2_TRACE_INIT,
2817                            "Unable to reset decoder: not implemented");
2818                 return -ENOTTY;
2819         }
2820
2821         pvr2_trace(PVR2_TRACE_INIT,
2822                    "Requesting decoder reset");
2823         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
2824         return 0;
2825 }
2826
2827
2828 int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
2829 {
2830         int status;
2831         LOCK_TAKE(hdw->ctl_lock); do {
2832                 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
2833                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2834         } while (0); LOCK_GIVE(hdw->ctl_lock);
2835         if (!status) {
2836                 hdw->subsys_enabled_mask =
2837                         ((hdw->subsys_enabled_mask &
2838                           ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
2839                          (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
2840         }
2841         return status;
2842 }
2843
2844
2845 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
2846                              struct pvr2_hdw_debug_info *ptr)
2847 {
2848         ptr->big_lock_held = hdw->big_lock_held;
2849         ptr->ctl_lock_held = hdw->ctl_lock_held;
2850         ptr->flag_ok = hdw->flag_ok;
2851         ptr->flag_disconnected = hdw->flag_disconnected;
2852         ptr->flag_init_ok = hdw->flag_init_ok;
2853         ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
2854         ptr->subsys_flags = hdw->subsys_enabled_mask;
2855         ptr->cmd_debug_state = hdw->cmd_debug_state;
2856         ptr->cmd_code = hdw->cmd_debug_code;
2857         ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
2858         ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
2859         ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
2860         ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
2861         ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
2862         ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
2863         ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
2864 }
2865
2866
2867 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
2868 {
2869         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
2870 }
2871
2872
2873 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
2874 {
2875         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
2876 }
2877
2878
2879 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
2880 {
2881         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
2882 }
2883
2884
2885 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
2886 {
2887         u32 cval,nval;
2888         int ret;
2889         if (~msk) {
2890                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
2891                 if (ret) return ret;
2892                 nval = (cval & ~msk) | (val & msk);
2893                 pvr2_trace(PVR2_TRACE_GPIO,
2894                            "GPIO direction changing 0x%x:0x%x"
2895                            " from 0x%x to 0x%x",
2896                            msk,val,cval,nval);
2897         } else {
2898                 nval = val;
2899                 pvr2_trace(PVR2_TRACE_GPIO,
2900                            "GPIO direction changing to 0x%x",nval);
2901         }
2902         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
2903 }
2904
2905
2906 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
2907 {
2908         u32 cval,nval;
2909         int ret;
2910         if (~msk) {
2911                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
2912                 if (ret) return ret;
2913                 nval = (cval & ~msk) | (val & msk);
2914                 pvr2_trace(PVR2_TRACE_GPIO,
2915                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
2916                            msk,val,cval,nval);
2917         } else {
2918                 nval = val;
2919                 pvr2_trace(PVR2_TRACE_GPIO,
2920                            "GPIO output changing to 0x%x",nval);
2921         }
2922         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
2923 }
2924
2925
2926 int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
2927 {
2928         int result;
2929         LOCK_TAKE(hdw->ctl_lock); do {
2930                 hdw->cmd_buffer[0] = 0xeb;
2931                 result = pvr2_send_request(hdw,
2932                                            hdw->cmd_buffer,1,
2933                                            hdw->cmd_buffer,1);
2934                 if (result < 0) break;
2935                 result = hdw->cmd_buffer[0];
2936         } while(0); LOCK_GIVE(hdw->ctl_lock);
2937         return result;
2938 }
2939
2940
2941 /*
2942   Stuff for Emacs to see, in order to encourage consistent editing style:
2943   *** Local Variables: ***
2944   *** mode: c ***
2945   *** fill-column: 75 ***
2946   *** tab-width: 8 ***
2947   *** c-basic-offset: 8 ***
2948   *** End: ***
2949   */