drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <asm/semaphore.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38
  39 struct usb_device_id pvr2_device_table[] = {
  40         [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
  41 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  42         [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
  43 #endif
  44         { }
  45 };
  46
  47 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
  48
  49 static const char *pvr2_device_names[] = {
  50         [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
  51 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  52         [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
  53 #endif
  54 };
  55
  56 struct pvr2_string_table {
  57         const char **lst;
  58         unsigned int cnt;
  59 };
  60
  61 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  62 // Names of other client modules to request for 24xxx model hardware
  63 static const char *pvr2_client_24xxx[] = {
  64         "cx25840",
  65         "tuner",
  66         "tda9887",
  67         "wm8775",
  68 };
  69 #endif
  70
  71 // Names of other client modules to request for 29xxx model hardware
  72 static const char *pvr2_client_29xxx[] = {
  73         "msp3400",
  74         "saa7115",
  75         "tuner",
  76         "tda9887",
  77 };
  78
  79 static struct pvr2_string_table pvr2_client_lists[] = {
  80         [PVR2_HDW_TYPE_29XXX] = {
  81                 pvr2_client_29xxx,
  82                 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
  83         },
  84 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
  85         [PVR2_HDW_TYPE_24XXX] = {
  86                 pvr2_client_24xxx,
  87                 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
  88         },
  89 #endif
  90 };
  91
  92 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = 0};
  93 DECLARE_MUTEX(pvr2_unit_sem);
  94
  95 static int ctlchg = 0;
  96 static int initusbreset = 1;
  97 static int procreload = 0;
  98 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  99 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
 100 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
 101 static int init_pause_msec = 0;
 102
 103 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
 104 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
 105 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
 106 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
 107 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
 108 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
 109 module_param(procreload, int, S_IRUGO|S_IWUSR);
 110 MODULE_PARM_DESC(procreload,
 111                  "Attempt init failure recovery with firmware reload");
 112 module_param_array(tuner,    int, NULL, 0444);
 113 MODULE_PARM_DESC(tuner,"specify installed tuner type");
 114 module_param_array(video_std,    int, NULL, 0444);
 115 MODULE_PARM_DESC(video_std,"specify initial video standard");
 116 module_param_array(tolerance,    int, NULL, 0444);
 117 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
 118
 119 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 120 #define PVR2_CTL_READ_ENDPOINT   0x81
 121
 122 #define PVR2_GPIO_IN 0x9008
 123 #define PVR2_GPIO_OUT 0x900c
 124 #define PVR2_GPIO_DIR 0x9020
 125
 126 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 127
 128 #define PVR2_FIRMWARE_ENDPOINT   0x02
 129
 130 /* size of a firmware chunk */
 131 #define FIRMWARE_CHUNK_SIZE 0x2000
 132
 133
 134 static const char *control_values_srate[] = {
 135         [PVR2_CVAL_SRATE_48]   = "48KHz",
 136         [PVR2_CVAL_SRATE_44_1] = "44.1KHz",
 137 };
 138
 139
 140 static const char *control_values_audiobitrate[] = {
 141         [PVR2_CVAL_AUDIOBITRATE_384] = "384kb/s",
 142         [PVR2_CVAL_AUDIOBITRATE_320] = "320kb/s",
 143         [PVR2_CVAL_AUDIOBITRATE_256] = "256kb/s",
 144         [PVR2_CVAL_AUDIOBITRATE_224] = "224kb/s",
 145         [PVR2_CVAL_AUDIOBITRATE_192] = "192kb/s",
 146         [PVR2_CVAL_AUDIOBITRATE_160] = "160kb/s",
 147         [PVR2_CVAL_AUDIOBITRATE_128] = "128kb/s",
 148         [PVR2_CVAL_AUDIOBITRATE_112] = "112kb/s",
 149         [PVR2_CVAL_AUDIOBITRATE_96]  = "96kb/s",
 150         [PVR2_CVAL_AUDIOBITRATE_80]  = "80kb/s",
 151         [PVR2_CVAL_AUDIOBITRATE_64]  = "64kb/s",
 152         [PVR2_CVAL_AUDIOBITRATE_56]  = "56kb/s",
 153         [PVR2_CVAL_AUDIOBITRATE_48]  = "48kb/s",
 154         [PVR2_CVAL_AUDIOBITRATE_32]  = "32kb/s",
 155         [PVR2_CVAL_AUDIOBITRATE_VBR] = "VBR",
 156 };
 157
 158
 159 static const char *control_values_audioemphasis[] = {
 160         [PVR2_CVAL_AUDIOEMPHASIS_NONE]  = "None",
 161         [PVR2_CVAL_AUDIOEMPHASIS_50_15] = "50/15us",
 162         [PVR2_CVAL_AUDIOEMPHASIS_CCITT] = "CCITT J.17",
 163 };
 164
 165
 166 static const char *control_values_input[] = {
 167         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 168         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 169         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 170         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 171 };
 172
 173
 174 static const char *control_values_audiomode[] = {
 175         [V4L2_TUNER_MODE_MONO]   = "Mono",
 176         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 177         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 178         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 179         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 180 };
 181
 182
 183 static const char *control_values_hsm[] = {
 184         [PVR2_CVAL_HSM_FAIL] = "Fail",
 185         [PVR2_CVAL_HSM_HIGH] = "High",
 186         [PVR2_CVAL_HSM_FULL] = "Full",
 187 };
 188
 189
 190 static const char *control_values_subsystem[] = {
 191         [PVR2_SUBSYS_B_ENC_FIRMWARE]  = "enc_firmware",
 192         [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
 193         [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
 194         [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
 195         [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
 196 };
 197
 198
 199 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 200 {
 201         struct pvr2_hdw *hdw = cptr->hdw;
 202         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 203                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 204         } else {
 205                 *vp = 0;
 206         }
 207         return 0;
 208 }
 209
 210 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 211 {
 212         struct pvr2_hdw *hdw = cptr->hdw;
 213         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 214                 hdw->freqTable[hdw->freqProgSlot-1] = v;
 215         }
 216         return 0;
 217 }
 218
 219 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 220 {
 221         *vp = cptr->hdw->freqProgSlot;
 222         return 0;
 223 }
 224
 225 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 226 {
 227         struct pvr2_hdw *hdw = cptr->hdw;
 228         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 229                 hdw->freqProgSlot = v;
 230         }
 231         return 0;
 232 }
 233
 234 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 235 {
 236         *vp = cptr->hdw->freqSlot;
 237         return 0;
 238 }
 239
 240 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
 241 {
 242         unsigned freq = 0;
 243         struct pvr2_hdw *hdw = cptr->hdw;
 244         hdw->freqSlot = v;
 245         if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
 246                 freq = hdw->freqTable[hdw->freqSlot-1];
 247         }
 248         if (freq && (freq != hdw->freqVal)) {
 249                 hdw->freqVal = freq;
 250                 hdw->freqDirty = !0;
 251         }
 252         return 0;
 253 }
 254
 255 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 256 {
 257         *vp = cptr->hdw->freqVal;
 258         return 0;
 259 }
 260
 261 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 262 {
 263         return cptr->hdw->freqDirty != 0;
 264 }
 265
 266 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 267 {
 268         cptr->hdw->freqDirty = 0;
 269 }
 270
 271 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 272 {
 273         struct pvr2_hdw *hdw = cptr->hdw;
 274         hdw->freqVal = v;
 275         hdw->freqDirty = !0;
 276         hdw->freqSlot = 0;
 277         return 0;
 278 }
 279
 280 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 281 {
 282         *vp = cptr->hdw->flag_streaming_enabled;
 283         return 0;
 284 }
 285
 286 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 287 {
 288         int result = pvr2_hdw_is_hsm(cptr->hdw);
 289         *vp = PVR2_CVAL_HSM_FULL;
 290         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 291         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 292         return 0;
 293 }
 294
 295 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 296 {
 297         *vp = cptr->hdw->std_mask_avail;
 298         return 0;
 299 }
 300
 301 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 302 {
 303         struct pvr2_hdw *hdw = cptr->hdw;
 304         v4l2_std_id ns;
 305         ns = hdw->std_mask_avail;
 306         ns = (ns & ~m) | (v & m);
 307         if (ns == hdw->std_mask_avail) return 0;
 308         hdw->std_mask_avail = ns;
 309         pvr2_hdw_internal_set_std_avail(hdw);
 310         pvr2_hdw_internal_find_stdenum(hdw);
 311         return 0;
 312 }
 313
 314 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 315                                char *bufPtr,unsigned int bufSize,
 316                                unsigned int *len)
 317 {
 318         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 319         return 0;
 320 }
 321
 322 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 323                                const char *bufPtr,unsigned int bufSize,
 324                                int *mskp,int *valp)
 325 {
 326         int ret;
 327         v4l2_std_id id;
 328         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 329         if (ret < 0) return ret;
 330         if (mskp) *mskp = id;
 331         if (valp) *valp = id;
 332         return 0;
 333 }
 334
 335 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 336 {
 337         *vp = cptr->hdw->std_mask_cur;
 338         return 0;
 339 }
 340
 341 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 342 {
 343         struct pvr2_hdw *hdw = cptr->hdw;
 344         v4l2_std_id ns;
 345         ns = hdw->std_mask_cur;
 346         ns = (ns & ~m) | (v & m);
 347         if (ns == hdw->std_mask_cur) return 0;
 348         hdw->std_mask_cur = ns;
 349         hdw->std_dirty = !0;
 350         pvr2_hdw_internal_find_stdenum(hdw);
 351         return 0;
 352 }
 353
 354 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 355 {
 356         return cptr->hdw->std_dirty != 0;
 357 }
 358
 359 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 360 {
 361         cptr->hdw->std_dirty = 0;
 362 }
 363
 364 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 365 {
 366         *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
 367                 PVR2_SIGNAL_OK) ? 1 : 0);
 368         return 0;
 369 }
 370
 371 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
 372 {
 373         *vp = cptr->hdw->subsys_enabled_mask;
 374         return 0;
 375 }
 376
 377 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
 378 {
 379         pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
 380         return 0;
 381 }
 382
 383 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
 384 {
 385         *vp = cptr->hdw->subsys_stream_mask;
 386         return 0;
 387 }
 388
 389 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
 390 {
 391         pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
 392         return 0;
 393 }
 394
 395 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 396 {
 397         struct pvr2_hdw *hdw = cptr->hdw;
 398         if (v < 0) return -EINVAL;
 399         if (v > hdw->std_enum_cnt) return -EINVAL;
 400         hdw->std_enum_cur = v;
 401         if (!v) return 0;
 402         v--;
 403         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 404         hdw->std_mask_cur = hdw->std_defs[v].id;
 405         hdw->std_dirty = !0;
 406         return 0;
 407 }
 408
 409
 410 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 411 {
 412         *vp = cptr->hdw->std_enum_cur;
 413         return 0;
 414 }
 415
 416
 417 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 418 {
 419         return cptr->hdw->std_dirty != 0;
 420 }
 421
 422
 423 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 424 {
 425         cptr->hdw->std_dirty = 0;
 426 }
 427
 428
 429 #define DEFINT(vmin,vmax) \
 430         .type = pvr2_ctl_int, \
 431         .def.type_int.min_value = vmin, \
 432         .def.type_int.max_value = vmax
 433
 434 #define DEFENUM(tab) \
 435         .type = pvr2_ctl_enum, \
 436         .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
 437         .def.type_enum.value_names = tab
 438
 439 #define DEFBOOL \
 440         .type = pvr2_ctl_bool
 441
 442 #define DEFMASK(msk,tab) \
 443         .type = pvr2_ctl_bitmask, \
 444         .def.type_bitmask.valid_bits = msk, \
 445         .def.type_bitmask.bit_names = tab
 446
 447 #define DEFREF(vname) \
 448         .set_value = ctrl_set_##vname, \
 449         .get_value = ctrl_get_##vname, \
 450         .is_dirty = ctrl_isdirty_##vname, \
 451         .clear_dirty = ctrl_cleardirty_##vname
 452
 453
 454 #define VCREATE_FUNCS(vname) \
 455 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 456 {*vp = cptr->hdw->vname##_val; return 0;} \
 457 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 458 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 459 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 460 {return cptr->hdw->vname##_dirty != 0;} \
 461 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 462 {cptr->hdw->vname##_dirty = 0;}
 463
 464 VCREATE_FUNCS(brightness)
 465 VCREATE_FUNCS(contrast)
 466 VCREATE_FUNCS(saturation)
 467 VCREATE_FUNCS(hue)
 468 VCREATE_FUNCS(volume)
 469 VCREATE_FUNCS(balance)
 470 VCREATE_FUNCS(bass)
 471 VCREATE_FUNCS(treble)
 472 VCREATE_FUNCS(mute)
 473 VCREATE_FUNCS(input)
 474 VCREATE_FUNCS(audiomode)
 475 VCREATE_FUNCS(res_hor)
 476 VCREATE_FUNCS(res_ver)
 477 VCREATE_FUNCS(srate)
 478 VCREATE_FUNCS(audiobitrate)
 479 VCREATE_FUNCS(audiocrc)
 480 VCREATE_FUNCS(audioemphasis)
 481 VCREATE_FUNCS(vbr)
 482 VCREATE_FUNCS(videobitrate)
 483 VCREATE_FUNCS(videopeak)
 484 VCREATE_FUNCS(interlace)
 485 VCREATE_FUNCS(audiolayer)
 486
 487 #define MIN_FREQ 55250000L
 488 #define MAX_FREQ 850000000L
 489
 490 /* Table definition of all controls which can be manipulated */
 491 static const struct pvr2_ctl_info control_defs[] = {
 492         {
 493                 .v4l_id = V4L2_CID_BRIGHTNESS,
 494                 .desc = "Brightness",
 495                 .name = "brightness",
 496                 .default_value = 128,
 497                 DEFREF(brightness),
 498                 DEFINT(0,255),
 499         },{
 500                 .v4l_id = V4L2_CID_CONTRAST,
 501                 .desc = "Contrast",
 502                 .name = "contrast",
 503                 .default_value = 68,
 504                 DEFREF(contrast),
 505                 DEFINT(0,127),
 506         },{
 507                 .v4l_id = V4L2_CID_SATURATION,
 508                 .desc = "Saturation",
 509                 .name = "saturation",
 510                 .default_value = 64,
 511                 DEFREF(saturation),
 512                 DEFINT(0,127),
 513         },{
 514                 .v4l_id = V4L2_CID_HUE,
 515                 .desc = "Hue",
 516                 .name = "hue",
 517                 .default_value = 0,
 518                 DEFREF(hue),
 519                 DEFINT(-128,127),
 520         },{
 521                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 522                 .desc = "Volume",
 523                 .name = "volume",
 524                 .default_value = 65535,
 525                 DEFREF(volume),
 526                 DEFINT(0,65535),
 527         },{
 528                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 529                 .desc = "Balance",
 530                 .name = "balance",
 531                 .default_value = 0,
 532                 DEFREF(balance),
 533                 DEFINT(-32768,32767),
 534         },{
 535                 .v4l_id = V4L2_CID_AUDIO_BASS,
 536                 .desc = "Bass",
 537                 .name = "bass",
 538                 .default_value = 0,
 539                 DEFREF(bass),
 540                 DEFINT(-32768,32767),
 541         },{
 542                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 543                 .desc = "Treble",
 544                 .name = "treble",
 545                 .default_value = 0,
 546                 DEFREF(treble),
 547                 DEFINT(-32768,32767),
 548         },{
 549                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 550                 .desc = "Mute",
 551                 .name = "mute",
 552                 .default_value = 0,
 553                 DEFREF(mute),
 554                 DEFBOOL,
 555         },{
 556                 .desc = "Video Source",
 557                 .name = "input",
 558                 .internal_id = PVR2_CID_INPUT,
 559                 .default_value = PVR2_CVAL_INPUT_TV,
 560                 DEFREF(input),
 561                 DEFENUM(control_values_input),
 562         },{
 563                 .desc = "Audio Mode",
 564                 .name = "audio_mode",
 565                 .internal_id = PVR2_CID_AUDIOMODE,
 566                 .default_value = V4L2_TUNER_MODE_STEREO,
 567                 DEFREF(audiomode),
 568                 DEFENUM(control_values_audiomode),
 569         },{
 570                 .desc = "Horizontal capture resolution",
 571                 .name = "resolution_hor",
 572                 .internal_id = PVR2_CID_HRES,
 573                 .default_value = 720,
 574                 DEFREF(res_hor),
 575                 DEFINT(320,720),
 576         },{
 577                 .desc = "Vertical capture resolution",
 578                 .name = "resolution_ver",
 579                 .internal_id = PVR2_CID_VRES,
 580                 .default_value = 480,
 581                 DEFREF(res_ver),
 582                 DEFINT(200,625),
 583         },{
 584                 .v4l_id = V4L2_CID_PVR_SRATE,
 585                 .desc = "Sample rate",
 586                 .name = "srate",
 587                 .default_value = PVR2_CVAL_SRATE_48,
 588                 DEFREF(srate),
 589                 DEFENUM(control_values_srate),
 590         },{
 591                 .v4l_id = V4L2_CID_PVR_AUDIOBITRATE,
 592                 .desc = "Audio Bitrate",
 593                 .name = "audio_bitrate",
 594                 .default_value = PVR2_CVAL_AUDIOBITRATE_224,
 595                 DEFREF(audiobitrate),
 596                 DEFENUM(control_values_audiobitrate),
 597         },{
 598                 .v4l_id = V4L2_CID_PVR_AUDIOCRC,
 599                 .desc = "Audio CRC",
 600                 .name = "audio_crc",
 601                 .default_value = 1,
 602                 DEFREF(audiocrc),
 603                 DEFBOOL,
 604         },{
 605                 .v4l_id = V4L2_CID_PVR_AUDIOEMPHASIS,
 606                 .desc = "Audio Emphasis",
 607                 .name = "audio_emphasis",
 608                 .default_value = PVR2_CVAL_AUDIOEMPHASIS_NONE,
 609                 DEFREF(audioemphasis),
 610                 DEFENUM(control_values_audioemphasis),
 611         },{
 612                 .v4l_id = V4L2_CID_PVR_VBR,
 613                 .desc = "Variable video bitrate",
 614                 .name = "vbr",
 615                 .default_value = 0,
 616                 DEFREF(vbr),
 617                 DEFBOOL,
 618         },{
 619                 .v4l_id = V4L2_CID_PVR_VIDEOBITRATE,
 620                 .desc = "Average video bitrate",
 621                 .name = "video_average_bitrate",
 622                 .default_value = 6000000,
 623                 DEFREF(videobitrate),
 624                 DEFINT(500000,20000000),
 625         },{
 626                 .v4l_id = V4L2_CID_PVR_VIDEOPEAK,
 627                 .desc = "Peak video bitrate",
 628                 .name = "video_peak_bitrate",
 629                 .default_value = 6000000,
 630                 DEFREF(videopeak),
 631                 DEFINT(500000,20000000),
 632         },{
 633                 .desc = "Interlace mode",
 634                 .name = "interlace",
 635                 .internal_id = PVR2_CID_INTERLACE,
 636                 .default_value = 0,
 637                 DEFREF(interlace),
 638                 DEFBOOL,
 639         },{
 640                 .desc = "Audio Layer",
 641                 .name = "audio_layer",
 642                 .default_value = 2,
 643                 DEFREF(audiolayer),
 644                 DEFINT(0,3),
 645         },{
 646                 .desc = "Tuner Frequency (Hz)",
 647                 .name = "frequency",
 648                 .internal_id = PVR2_CID_FREQUENCY,
 649                 .default_value = 175250000L,
 650                 .set_value = ctrl_freq_set,
 651                 .get_value = ctrl_freq_get,
 652                 .is_dirty = ctrl_freq_is_dirty,
 653                 .clear_dirty = ctrl_freq_clear_dirty,
 654                 DEFINT(MIN_FREQ,MAX_FREQ),
 655         },{
 656                 .desc = "Channel",
 657                 .name = "channel",
 658                 .set_value = ctrl_channel_set,
 659                 .get_value = ctrl_channel_get,
 660                 DEFINT(0,FREQTABLE_SIZE),
 661         },{
 662                 .desc = "Channel Program Frequency",
 663                 .name = "freq_table_value",
 664                 .set_value = ctrl_channelfreq_set,
 665                 .get_value = ctrl_channelfreq_get,
 666                 DEFINT(MIN_FREQ,MAX_FREQ),
 667         },{
 668                 .desc = "Channel Program ID",
 669                 .name = "freq_table_channel",
 670                 .set_value = ctrl_channelprog_set,
 671                 .get_value = ctrl_channelprog_get,
 672                 DEFINT(0,FREQTABLE_SIZE),
 673         },{
 674                 .desc = "Streaming Enabled",
 675                 .name = "streaming_enabled",
 676                 .get_value = ctrl_streamingenabled_get,
 677                 DEFBOOL,
 678         },{
 679                 .desc = "USB Speed",
 680                 .name = "usb_speed",
 681                 .get_value = ctrl_hsm_get,
 682                 DEFENUM(control_values_hsm),
 683         },{
 684                 .desc = "Signal Present",
 685                 .name = "signal_present",
 686                 .get_value = ctrl_signal_get,
 687                 DEFBOOL,
 688         },{
 689                 .desc = "Video Standards Available Mask",
 690                 .name = "video_standard_mask_available",
 691                 .internal_id = PVR2_CID_STDAVAIL,
 692                 .skip_init = !0,
 693                 .get_value = ctrl_stdavail_get,
 694                 .set_value = ctrl_stdavail_set,
 695                 .val_to_sym = ctrl_std_val_to_sym,
 696                 .sym_to_val = ctrl_std_sym_to_val,
 697                 .type = pvr2_ctl_bitmask,
 698         },{
 699                 .desc = "Video Standards In Use Mask",
 700                 .name = "video_standard_mask_active",
 701                 .internal_id = PVR2_CID_STDCUR,
 702                 .skip_init = !0,
 703                 .get_value = ctrl_stdcur_get,
 704                 .set_value = ctrl_stdcur_set,
 705                 .is_dirty = ctrl_stdcur_is_dirty,
 706                 .clear_dirty = ctrl_stdcur_clear_dirty,
 707                 .val_to_sym = ctrl_std_val_to_sym,
 708                 .sym_to_val = ctrl_std_sym_to_val,
 709                 .type = pvr2_ctl_bitmask,
 710         },{
 711                 .desc = "Subsystem enabled mask",
 712                 .name = "debug_subsys_mask",
 713                 .skip_init = !0,
 714                 .get_value = ctrl_subsys_get,
 715                 .set_value = ctrl_subsys_set,
 716                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 717         },{
 718                 .desc = "Subsystem stream mask",
 719                 .name = "debug_subsys_stream_mask",
 720                 .skip_init = !0,
 721                 .get_value = ctrl_subsys_stream_get,
 722                 .set_value = ctrl_subsys_stream_set,
 723                 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
 724         },{
 725                 .desc = "Video Standard Name",
 726                 .name = "video_standard",
 727                 .internal_id = PVR2_CID_STDENUM,
 728                 .skip_init = !0,
 729                 .get_value = ctrl_stdenumcur_get,
 730                 .set_value = ctrl_stdenumcur_set,
 731                 .is_dirty = ctrl_stdenumcur_is_dirty,
 732                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 733                 .type = pvr2_ctl_enum,
 734         }
 735 };
 736
 737 #define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
 738
 739
 740 const char *pvr2_config_get_name(enum pvr2_config cfg)
 741 {
 742         switch (cfg) {
 743         case pvr2_config_empty: return "empty";
 744         case pvr2_config_mpeg: return "mpeg";
 745         case pvr2_config_vbi: return "vbi";
 746         case pvr2_config_radio: return "radio";
 747         }
 748         return "<unknown>";
 749 }
 750
 751
 752 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
 753 {
 754         return hdw->usb_dev;
 755 }
 756
 757
 758 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
 759 {
 760         return hdw->serial_number;
 761 }
 762
 763
 764 struct pvr2_hdw *pvr2_hdw_find(int unit_number)
 765 {
 766         if (unit_number < 0) return 0;
 767         if (unit_number >= PVR_NUM) return 0;
 768         return unit_pointers[unit_number];
 769 }
 770
 771
 772 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
 773 {
 774         return hdw->unit_number;
 775 }
 776
 777
 778 /* Attempt to locate one of the given set of files.  Messages are logged
 779    appropriate to what has been found.  The return value will be 0 or
 780    greater on success (it will be the index of the file name found) and
 781    fw_entry will be filled in.  Otherwise a negative error is returned on
 782    failure.  If the return value is -ENOENT then no viable firmware file
 783    could be located. */
 784 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
 785                                 const struct firmware **fw_entry,
 786                                 const char *fwtypename,
 787                                 unsigned int fwcount,
 788                                 const char *fwnames[])
 789 {
 790         unsigned int idx;
 791         int ret = -EINVAL;
 792         for (idx = 0; idx < fwcount; idx++) {
 793                 ret = request_firmware(fw_entry,
 794                                        fwnames[idx],
 795                                        &hdw->usb_dev->dev);
 796                 if (!ret) {
 797                         trace_firmware("Located %s firmware: %s;"
 798                                        " uploading...",
 799                                        fwtypename,
 800                                        fwnames[idx]);
 801                         return idx;
 802                 }
 803                 if (ret == -ENOENT) continue;
 804                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 805                            "request_firmware fatal error with code=%d",ret);
 806                 return ret;
 807         }
 808         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 809                    "***WARNING***"
 810                    " Device %s firmware"
 811                    " seems to be missing.",
 812                    fwtypename);
 813         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 814                    "Did you install the pvrusb2 firmware files"
 815                    " in their proper location?");
 816         if (fwcount == 1) {
 817                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 818                            "request_firmware unable to locate %s file %s",
 819                            fwtypename,fwnames[0]);
 820         } else {
 821                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 822                            "request_firmware unable to locate"
 823                            " one of the following %s files:",
 824                            fwtypename);
 825                 for (idx = 0; idx < fwcount; idx++) {
 826                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 827                                    "request_firmware: Failed to find %s",
 828                                    fwnames[idx]);
 829                 }
 830         }
 831         return ret;
 832 }
 833
 834
 835 /*
 836  * pvr2_upload_firmware1().
 837  *
 838  * Send the 8051 firmware to the device.  After the upload, arrange for
 839  * device to re-enumerate.
 840  *
 841  * NOTE : the pointer to the firmware data given by request_firmware()
 842  * is not suitable for an usb transaction.
 843  *
 844  */
 845 int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
 846 {
 847         const struct firmware *fw_entry = 0;
 848         void  *fw_ptr;
 849         unsigned int pipe;
 850         int ret;
 851         u16 address;
 852         static const char *fw_files_29xxx[] = {
 853                 "v4l-pvrusb2-29xxx-01.fw",
 854         };
 855 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 856         static const char *fw_files_24xxx[] = {
 857                 "v4l-pvrusb2-24xxx-01.fw",
 858         };
 859 #endif
 860         static const struct pvr2_string_table fw_file_defs[] = {
 861                 [PVR2_HDW_TYPE_29XXX] = {
 862                         fw_files_29xxx,
 863                         sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
 864                 },
 865 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
 866                 [PVR2_HDW_TYPE_24XXX] = {
 867                         fw_files_24xxx,
 868                         sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
 869                 },
 870 #endif
 871         };
 872         hdw->fw1_state = FW1_STATE_FAILED; // default result
 873
 874         trace_firmware("pvr2_upload_firmware1");
 875
 876         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
 877                                    fw_file_defs[hdw->hdw_type].cnt,
 878                                    fw_file_defs[hdw->hdw_type].lst);
 879         if (ret < 0) {
 880                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
 881                 return ret;
 882         }
 883
 884         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
 885         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
 886
 887         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
 888
 889         if (fw_entry->size != 0x2000){
 890                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
 891                 release_firmware(fw_entry);
 892                 return -ENOMEM;
 893         }
 894
 895         fw_ptr = kmalloc(0x800, GFP_KERNEL);
 896         if (fw_ptr == NULL){
 897                 release_firmware(fw_entry);
 898                 return -ENOMEM;
 899         }
 900
 901         /* We have to hold the CPU during firmware upload. */
 902         pvr2_hdw_cpureset_assert(hdw,1);
 903
 904         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
 905            chunk. */
 906
 907         ret = 0;
 908         for(address = 0; address < fw_entry->size; address += 0x800) {
 909                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
 910                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
 911                                        0, fw_ptr, 0x800, HZ);
 912         }
 913
 914         trace_firmware("Upload done, releasing device's CPU");
 915
 916         /* Now release the CPU.  It will disconnect and reconnect later. */
 917         pvr2_hdw_cpureset_assert(hdw,0);
 918
 919         kfree(fw_ptr);
 920         release_firmware(fw_entry);
 921
 922         trace_firmware("Upload done (%d bytes sent)",ret);
 923
 924         /* We should have written 8192 bytes */
 925         if (ret == 8192) {
 926                 hdw->fw1_state = FW1_STATE_RELOAD;
 927                 return 0;
 928         }
 929
 930         return -EIO;
 931 }
 932
 933
 934 /*
 935  * pvr2_upload_firmware2()
 936  *
 937  * This uploads encoder firmware on endpoint 2.
 938  *
 939  */
 940
 941 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
 942 {
 943         const struct firmware *fw_entry = 0;
 944         void  *fw_ptr;
 945         unsigned int pipe, fw_len, fw_done;
 946         int actual_length;
 947         int ret = 0;
 948         int fwidx;
 949         static const char *fw_files[] = {
 950                 CX2341X_FIRM_ENC_FILENAME,
 951         };
 952
 953         trace_firmware("pvr2_upload_firmware2");
 954
 955         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
 956                                    sizeof(fw_files)/sizeof(fw_files[0]),
 957                                    fw_files);
 958         if (ret < 0) return ret;
 959         fwidx = ret;
 960         ret = 0;
 961
 962         /* First prepare firmware loading */
 963         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
 964         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
 965         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
 966         ret |= pvr2_hdw_cmd_deep_reset(hdw);
 967         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
 968         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
 969         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
 970         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
 971         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
 972         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
 973         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
 974         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
 975         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
 976         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
 977         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
 978         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
 979         ret |= pvr2_write_u8(hdw, 0x52, 0);
 980         ret |= pvr2_write_u16(hdw, 0x0600, 0);
 981
 982         if (ret) {
 983                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 984                            "firmware2 upload prep failed, ret=%d",ret);
 985                 release_firmware(fw_entry);
 986                 return ret;
 987         }
 988
 989         /* Now send firmware */
 990
 991         fw_len = fw_entry->size;
 992
 993         if (fw_len % FIRMWARE_CHUNK_SIZE) {
 994                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 995                            "size of %s firmware"
 996                            " must be a multiple of 8192B",
 997                            fw_files[fwidx]);
 998                 release_firmware(fw_entry);
 999                 return -1;
1000         }
1001
1002         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1003         if (fw_ptr == NULL){
1004                 release_firmware(fw_entry);
1005                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1006                            "failed to allocate memory for firmware2 upload");
1007                 return -ENOMEM;
1008         }
1009
1010         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1011
1012         for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1013              fw_done += FIRMWARE_CHUNK_SIZE ) {
1014                 int i;
1015                 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1016                 /* Usbsnoop log  shows that we must swap bytes... */
1017                 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1018                         ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1019
1020                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1021                                     FIRMWARE_CHUNK_SIZE,
1022                                     &actual_length, HZ);
1023                 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1024         }
1025
1026         trace_firmware("upload of %s : %i / %i ",
1027                        fw_files[fwidx],fw_done,fw_len);
1028
1029         kfree(fw_ptr);
1030         release_firmware(fw_entry);
1031
1032         if (ret) {
1033                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1034                            "firmware2 upload transfer failure");
1035                 return ret;
1036         }
1037
1038         /* Finish upload */
1039
1040         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1041         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1042         ret |= pvr2_write_u16(hdw, 0x0600, 0);
1043
1044         if (ret) {
1045                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1046                            "firmware2 upload post-proc failure");
1047         } else {
1048                 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1049         }
1050         return ret;
1051 }
1052
1053
1054 #define FIRMWARE_RECOVERY_BITS \
1055         ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1056          (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1057          (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1058          (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1059
1060 /*
1061
1062   This single function is key to pretty much everything.  The pvrusb2
1063   device can logically be viewed as a series of subsystems which can be
1064   stopped / started or unconfigured / configured.  To get things streaming,
1065   one must configure everything and start everything, but there may be
1066   various reasons over time to deconfigure something or stop something.
1067   This function handles all of this activity.  Everything EVERYWHERE that
1068   must affect a subsystem eventually comes here to do the work.
1069
1070   The current state of all subsystems is represented by a single bit mask,
1071   known as subsys_enabled_mask.  The bit positions are defined by the
1072   PVR2_SUBSYS_xxxx macros, with one subsystem per bit position.  At any
1073   time the set of configured or active subsystems can be queried just by
1074   looking at that mask.  To change bits in that mask, this function here
1075   must be called.  The "msk" argument indicates which bit positions to
1076   change, and the "val" argument defines the new values for the positions
1077   defined by "msk".
1078
1079   There is a priority ordering of starting / stopping things, and for
1080   multiple requested changes, this function implements that ordering.
1081   (Thus we will act on a request to load encoder firmware before we
1082   configure the encoder.)  In addition to priority ordering, there is a
1083   recovery strategy implemented here.  If a particular step fails and we
1084   detect that failure, this function will clear the affected subsystem bits
1085   and restart.  Thus we have a means for recovering from a dead encoder:
1086   Clear all bits that correspond to subsystems that we need to restart /
1087   reconfigure and start over.
1088
1089 */
1090 void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1091                                      unsigned long msk,unsigned long val)
1092 {
1093         unsigned long nmsk;
1094         unsigned long vmsk;
1095         int ret;
1096         unsigned int tryCount = 0;
1097
1098         if (!hdw->flag_ok) return;
1099
1100         msk &= PVR2_SUBSYS_ALL;
1101         nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1102         nmsk &= PVR2_SUBSYS_ALL;
1103
1104         for (;;) {
1105                 tryCount++;
1106                 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1107                       PVR2_SUBSYS_ALL)) break;
1108                 if (tryCount > 4) {
1109                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1110                                    "Too many retries when configuring device;"
1111                                    " giving up");
1112                         pvr2_hdw_render_useless(hdw);
1113                         break;
1114                 }
1115                 if (tryCount > 1) {
1116                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1117                                    "Retrying device reconfiguration");
1118                 }
1119                 pvr2_trace(PVR2_TRACE_INIT,
1120                            "subsys mask changing 0x%lx:0x%lx"
1121                            " from 0x%lx to 0x%lx",
1122                            msk,val,hdw->subsys_enabled_mask,nmsk);
1123
1124                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1125                         hdw->subsys_enabled_mask;
1126                 if (vmsk) {
1127                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1128                                 pvr2_trace(PVR2_TRACE_CTL,
1129                                            "/*---TRACE_CTL----*/"
1130                                            " pvr2_encoder_stop");
1131                                 ret = pvr2_encoder_stop(hdw);
1132                                 if (ret) {
1133                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1134                                                    "Error recovery initiated");
1135                                         hdw->subsys_enabled_mask &=
1136                                                 ~FIRMWARE_RECOVERY_BITS;
1137                                         continue;
1138                                 }
1139                         }
1140                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1141                                 pvr2_trace(PVR2_TRACE_CTL,
1142                                            "/*---TRACE_CTL----*/"
1143                                            " pvr2_hdw_cmd_usbstream(0)");
1144                                 pvr2_hdw_cmd_usbstream(hdw,0);
1145                         }
1146                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1147                                 pvr2_trace(PVR2_TRACE_CTL,
1148                                            "/*---TRACE_CTL----*/"
1149                                            " decoder disable");
1150                                 if (hdw->decoder_ctrl) {
1151                                         hdw->decoder_ctrl->enable(
1152                                                 hdw->decoder_ctrl->ctxt,0);
1153                                 } else {
1154                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1155                                                    "WARNING:"
1156                                                    " No decoder present");
1157                                 }
1158                                 hdw->subsys_enabled_mask &=
1159                                         ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1160                         }
1161                         if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1162                                 hdw->subsys_enabled_mask &=
1163                                         ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1164                         }
1165                 }
1166                 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1167                 if (vmsk) {
1168                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1169                                 pvr2_trace(PVR2_TRACE_CTL,
1170                                            "/*---TRACE_CTL----*/"
1171                                            " pvr2_upload_firmware2");
1172                                 ret = pvr2_upload_firmware2(hdw);
1173                                 if (ret) {
1174                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1175                                                    "Failure uploading encoder"
1176                                                    " firmware");
1177                                         pvr2_hdw_render_useless(hdw);
1178                                         break;
1179                                 }
1180                         }
1181                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1182                                 pvr2_trace(PVR2_TRACE_CTL,
1183                                            "/*---TRACE_CTL----*/"
1184                                            " pvr2_encoder_configure");
1185                                 ret = pvr2_encoder_configure(hdw);
1186                                 if (ret) {
1187                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1188                                                    "Error recovery initiated");
1189                                         hdw->subsys_enabled_mask &=
1190                                                 ~FIRMWARE_RECOVERY_BITS;
1191                                         continue;
1192                                 }
1193                         }
1194                         if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1195                                 pvr2_trace(PVR2_TRACE_CTL,
1196                                            "/*---TRACE_CTL----*/"
1197                                            " decoder enable");
1198                                 if (hdw->decoder_ctrl) {
1199                                         hdw->decoder_ctrl->enable(
1200                                                 hdw->decoder_ctrl->ctxt,!0);
1201                                 } else {
1202                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1203                                                    "WARNING:"
1204                                                    " No decoder present");
1205                                 }
1206                                 hdw->subsys_enabled_mask |=
1207                                         (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1208                         }
1209                         if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1210                                 pvr2_trace(PVR2_TRACE_CTL,
1211                                            "/*---TRACE_CTL----*/"
1212                                            " pvr2_hdw_cmd_usbstream(1)");
1213                                 pvr2_hdw_cmd_usbstream(hdw,!0);
1214                         }
1215                         if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1216                                 pvr2_trace(PVR2_TRACE_CTL,
1217                                            "/*---TRACE_CTL----*/"
1218                                            " pvr2_encoder_start");
1219                                 ret = pvr2_encoder_start(hdw);
1220                                 if (ret) {
1221                                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1222                                                    "Error recovery initiated");
1223                                         hdw->subsys_enabled_mask &=
1224                                                 ~FIRMWARE_RECOVERY_BITS;
1225                                         continue;
1226                                 }
1227                         }
1228                 }
1229         }
1230 }
1231
1232
1233 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1234                              unsigned long msk,unsigned long val)
1235 {
1236         LOCK_TAKE(hdw->big_lock); do {
1237                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1238         } while (0); LOCK_GIVE(hdw->big_lock);
1239 }
1240
1241
1242 void pvr2_hdw_subsys_bit_set(struct pvr2_hdw *hdw,unsigned long msk)
1243 {
1244         pvr2_hdw_subsys_bit_chg(hdw,msk,msk);
1245 }
1246
1247
1248 void pvr2_hdw_subsys_bit_clr(struct pvr2_hdw *hdw,unsigned long msk)
1249 {
1250         pvr2_hdw_subsys_bit_chg(hdw,msk,0);
1251 }
1252
1253
1254 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1255 {
1256         return hdw->subsys_enabled_mask;
1257 }
1258
1259
1260 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1261 {
1262         return hdw->subsys_stream_mask;
1263 }
1264
1265
1266 void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1267                                             unsigned long msk,
1268                                             unsigned long val)
1269 {
1270         unsigned long val2;
1271         msk &= PVR2_SUBSYS_ALL;
1272         val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1273         pvr2_trace(PVR2_TRACE_INIT,
1274                    "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1275                    msk,val,hdw->subsys_stream_mask,val2);
1276         hdw->subsys_stream_mask = val2;
1277 }
1278
1279
1280 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1281                                     unsigned long msk,
1282                                     unsigned long val)
1283 {
1284         LOCK_TAKE(hdw->big_lock); do {
1285                 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1286         } while (0); LOCK_GIVE(hdw->big_lock);
1287 }
1288
1289
1290 int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1291 {
1292         if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1293         if (enableFl) {
1294                 pvr2_trace(PVR2_TRACE_START_STOP,
1295                            "/*--TRACE_STREAM--*/ enable");
1296                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1297         } else {
1298                 pvr2_trace(PVR2_TRACE_START_STOP,
1299                            "/*--TRACE_STREAM--*/ disable");
1300                 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1301         }
1302         if (!hdw->flag_ok) return -EIO;
1303         hdw->flag_streaming_enabled = enableFl != 0;
1304         return 0;
1305 }
1306
1307
1308 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1309 {
1310         return hdw->flag_streaming_enabled != 0;
1311 }
1312
1313
1314 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1315 {
1316         int ret;
1317         LOCK_TAKE(hdw->big_lock); do {
1318                 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1319         } while (0); LOCK_GIVE(hdw->big_lock);
1320         return ret;
1321 }
1322
1323
1324 int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1325                                      enum pvr2_config config)
1326 {
1327         unsigned long sm = hdw->subsys_enabled_mask;
1328         if (!hdw->flag_ok) return -EIO;
1329         pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1330         hdw->config = config;
1331         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1332         return 0;
1333 }
1334
1335
1336 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1337 {
1338         int ret;
1339         if (!hdw->flag_ok) return -EIO;
1340         LOCK_TAKE(hdw->big_lock);
1341         ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1342         LOCK_GIVE(hdw->big_lock);
1343         return ret;
1344 }
1345
1346
1347 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1348 {
1349         int unit_number = hdw->unit_number;
1350         int tp = -1;
1351         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1352                 tp = tuner[unit_number];
1353         }
1354         if (tp < 0) return -EINVAL;
1355         hdw->tuner_type = tp;
1356         return 0;
1357 }
1358
1359
1360 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1361 {
1362         int unit_number = hdw->unit_number;
1363         int tp = 0;
1364         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1365                 tp = video_std[unit_number];
1366         }
1367         return tp;
1368 }
1369
1370
1371 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1372 {
1373         int unit_number = hdw->unit_number;
1374         int tp = 0;
1375         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1376                 tp = tolerance[unit_number];
1377         }
1378         return tp;
1379 }
1380
1381
1382 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1383 {
1384         /* Try a harmless request to fetch the eeprom's address over
1385            endpoint 1.  See what happens.  Only the full FX2 image can
1386            respond to this.  If this probe fails then likely the FX2
1387            firmware needs be loaded. */
1388         int result;
1389         LOCK_TAKE(hdw->ctl_lock); do {
1390                 hdw->cmd_buffer[0] = 0xeb;
1391                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1392                                            hdw->cmd_buffer,1,
1393                                            hdw->cmd_buffer,1);
1394                 if (result < 0) break;
1395         } while(0); LOCK_GIVE(hdw->ctl_lock);
1396         if (result) {
1397                 pvr2_trace(PVR2_TRACE_INIT,
1398                            "Probe of device endpoint 1 result status %d",
1399                            result);
1400         } else {
1401                 pvr2_trace(PVR2_TRACE_INIT,
1402                            "Probe of device endpoint 1 succeeded");
1403         }
1404         return result == 0;
1405 }
1406
1407 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1408 {
1409         char buf[40];
1410         unsigned int bcnt;
1411         v4l2_std_id std1,std2;
1412
1413         std1 = get_default_standard(hdw);
1414
1415         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1416         pvr2_trace(PVR2_TRACE_INIT,
1417                    "Supported video standard(s) reported by eeprom: %.*s",
1418                    bcnt,buf);
1419
1420         hdw->std_mask_avail = hdw->std_mask_eeprom;
1421
1422         std2 = std1 & ~hdw->std_mask_avail;
1423         if (std2) {
1424                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1425                 pvr2_trace(PVR2_TRACE_INIT,
1426                            "Expanding supported video standards"
1427                            " to include: %.*s",
1428                            bcnt,buf);
1429                 hdw->std_mask_avail |= std2;
1430         }
1431
1432         pvr2_hdw_internal_set_std_avail(hdw);
1433
1434         if (std1) {
1435                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1436                 pvr2_trace(PVR2_TRACE_INIT,
1437                            "Initial video standard forced to %.*s",
1438                            bcnt,buf);
1439                 hdw->std_mask_cur = std1;
1440                 hdw->std_dirty = !0;
1441                 pvr2_hdw_internal_find_stdenum(hdw);
1442                 return;
1443         }
1444
1445         if (hdw->std_enum_cnt > 1) {
1446                 // Autoselect the first listed standard
1447                 hdw->std_enum_cur = 1;
1448                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1449                 hdw->std_dirty = !0;
1450                 pvr2_trace(PVR2_TRACE_INIT,
1451                            "Initial video standard auto-selected to %s",
1452                            hdw->std_defs[hdw->std_enum_cur-1].name);
1453                 return;
1454         }
1455
1456         pvr2_trace(PVR2_TRACE_EEPROM,
1457                    "Unable to select a viable initial video standard");
1458 }
1459
1460
1461 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1462 {
1463         int ret;
1464         unsigned int idx;
1465         struct pvr2_ctrl *cptr;
1466         int reloadFl = 0;
1467         if (!reloadFl) {
1468                 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1469                             == 0);
1470                 if (reloadFl) {
1471                         pvr2_trace(PVR2_TRACE_INIT,
1472                                    "USB endpoint config looks strange"
1473                                    "; possibly firmware needs to be loaded");
1474                 }
1475         }
1476         if (!reloadFl) {
1477                 reloadFl = !pvr2_hdw_check_firmware(hdw);
1478                 if (reloadFl) {
1479                         pvr2_trace(PVR2_TRACE_INIT,
1480                                    "Check for FX2 firmware failed"
1481                                    "; possibly firmware needs to be loaded");
1482                 }
1483         }
1484         if (reloadFl) {
1485                 if (pvr2_upload_firmware1(hdw) != 0) {
1486                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1487                                    "Failure uploading firmware1");
1488                 }
1489                 return;
1490         }
1491         hdw->fw1_state = FW1_STATE_OK;
1492
1493         if (initusbreset) {
1494                 pvr2_hdw_device_reset(hdw);
1495         }
1496         if (!pvr2_hdw_dev_ok(hdw)) return;
1497
1498         for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1499                 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1500         }
1501
1502         pvr2_hdw_cmd_powerup(hdw);
1503         if (!pvr2_hdw_dev_ok(hdw)) return;
1504
1505         if (pvr2_upload_firmware2(hdw)){
1506                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1507                 pvr2_hdw_render_useless(hdw);
1508                 return;
1509         }
1510
1511         // This step MUST happen after the earlier powerup step.
1512         pvr2_i2c_core_init(hdw);
1513         if (!pvr2_hdw_dev_ok(hdw)) return;
1514
1515         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1516                 cptr = hdw->controls + idx;
1517                 if (cptr->info->skip_init) continue;
1518                 if (!cptr->info->set_value) continue;
1519                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1520         }
1521
1522         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1523         // thread-safe against the normal pvr2_send_request() mechanism.
1524         // (We should make it thread safe).
1525
1526         ret = pvr2_hdw_get_eeprom_addr(hdw);
1527         if (!pvr2_hdw_dev_ok(hdw)) return;
1528         if (ret < 0) {
1529                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1530                            "Unable to determine location of eeprom, skipping");
1531         } else {
1532                 hdw->eeprom_addr = ret;
1533                 pvr2_eeprom_analyze(hdw);
1534                 if (!pvr2_hdw_dev_ok(hdw)) return;
1535         }
1536
1537         pvr2_hdw_setup_std(hdw);
1538
1539         if (!get_default_tuner_type(hdw)) {
1540                 pvr2_trace(PVR2_TRACE_INIT,
1541                            "pvr2_hdw_setup: Tuner type overridden to %d",
1542                            hdw->tuner_type);
1543         }
1544
1545         hdw->tuner_updated = !0;
1546         pvr2_i2c_core_check_stale(hdw);
1547         hdw->tuner_updated = 0;
1548
1549         if (!pvr2_hdw_dev_ok(hdw)) return;
1550
1551         pvr2_hdw_commit_ctl_internal(hdw);
1552         if (!pvr2_hdw_dev_ok(hdw)) return;
1553
1554         hdw->vid_stream = pvr2_stream_create();
1555         if (!pvr2_hdw_dev_ok(hdw)) return;
1556         pvr2_trace(PVR2_TRACE_INIT,
1557                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1558         if (hdw->vid_stream) {
1559                 idx = get_default_error_tolerance(hdw);
1560                 if (idx) {
1561                         pvr2_trace(PVR2_TRACE_INIT,
1562                                    "pvr2_hdw_setup: video stream %p"
1563                                    " setting tolerance %u",
1564                                    hdw->vid_stream,idx);
1565                 }
1566                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1567                                   PVR2_VID_ENDPOINT,idx);
1568         }
1569
1570         if (!pvr2_hdw_dev_ok(hdw)) return;
1571
1572         /* Make sure everything is up to date */
1573         pvr2_i2c_core_sync(hdw);
1574
1575         if (!pvr2_hdw_dev_ok(hdw)) return;
1576
1577         hdw->flag_init_ok = !0;
1578 }
1579
1580
1581 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1582 {
1583         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1584         LOCK_TAKE(hdw->big_lock); do {
1585                 pvr2_hdw_setup_low(hdw);
1586                 pvr2_trace(PVR2_TRACE_INIT,
1587                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1588                            hdw,hdw->flag_ok,hdw->flag_init_ok);
1589                 if (pvr2_hdw_dev_ok(hdw)) {
1590                         if (pvr2_hdw_init_ok(hdw)) {
1591                                 pvr2_trace(
1592                                         PVR2_TRACE_INFO,
1593                                         "Device initialization"
1594                                         " completed successfully.");
1595                                 break;
1596                         }
1597                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1598                                 pvr2_trace(
1599                                         PVR2_TRACE_INFO,
1600                                         "Device microcontroller firmware"
1601                                         " (re)loaded; it should now reset"
1602                                         " and reconnect.");
1603                                 break;
1604                         }
1605                         pvr2_trace(
1606                                 PVR2_TRACE_ERROR_LEGS,
1607                                 "Device initialization was not successful.");
1608                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1609                                 pvr2_trace(
1610                                         PVR2_TRACE_ERROR_LEGS,
1611                                         "Giving up since device"
1612                                         " microcontroller firmware"
1613                                         " appears to be missing.");
1614                                 break;
1615                         }
1616                 }
1617                 if (procreload) {
1618                         pvr2_trace(
1619                                 PVR2_TRACE_ERROR_LEGS,
1620                                 "Attempting pvrusb2 recovery by reloading"
1621                                 " primary firmware.");
1622                         pvr2_trace(
1623                                 PVR2_TRACE_ERROR_LEGS,
1624                                 "If this works, device should disconnect"
1625                                 " and reconnect in a sane state.");
1626                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1627                         pvr2_upload_firmware1(hdw);
1628                 } else {
1629                         pvr2_trace(
1630                                 PVR2_TRACE_ERROR_LEGS,
1631                                 "***WARNING*** pvrusb2 device hardware"
1632                                 " appears to be jammed"
1633                                 " and I can't clear it.");
1634                         pvr2_trace(
1635                                 PVR2_TRACE_ERROR_LEGS,
1636                                 "You might need to power cycle"
1637                                 " the pvrusb2 device"
1638                                 " in order to recover.");
1639                 }
1640         } while (0); LOCK_GIVE(hdw->big_lock);
1641         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1642         return hdw->flag_init_ok;
1643 }
1644
1645
1646 /* Create and return a structure for interacting with the underlying
1647    hardware */
1648 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1649                                  const struct usb_device_id *devid)
1650 {
1651         unsigned int idx,cnt1,cnt2;
1652         struct pvr2_hdw *hdw;
1653         unsigned int hdw_type;
1654         int valid_std_mask;
1655         struct pvr2_ctrl *cptr;
1656         __u8 ifnum;
1657
1658         hdw_type = devid - pvr2_device_table;
1659         if (hdw_type >=
1660             sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1661                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1662                            "Bogus device type of %u reported",hdw_type);
1663                 return 0;
1664         }
1665
1666         hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1667         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1668                    hdw,pvr2_device_names[hdw_type]);
1669         if (!hdw) goto fail;
1670         memset(hdw,0,sizeof(*hdw));
1671
1672         hdw->control_cnt = CTRLDEF_COUNT;
1673         hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1674                                 GFP_KERNEL);
1675         if (!hdw->controls) goto fail;
1676         memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
1677         hdw->hdw_type = hdw_type;
1678         for (idx = 0; idx < hdw->control_cnt; idx++) {
1679                 cptr = hdw->controls + idx;
1680                 cptr->hdw = hdw;
1681         }
1682         for (idx = 0; idx < 32; idx++) {
1683                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1684         }
1685         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1686                 cptr = hdw->controls + idx;
1687                 cptr->info = control_defs+idx;
1688         }
1689
1690         // Initialize video standard enum dynamic control
1691         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1692         if (cptr) {
1693                 memcpy(&hdw->std_info_enum,cptr->info,
1694                        sizeof(hdw->std_info_enum));
1695                 cptr->info = &hdw->std_info_enum;
1696
1697         }
1698         // Initialize control data regarding video standard masks
1699         valid_std_mask = pvr2_std_get_usable();
1700         for (idx = 0; idx < 32; idx++) {
1701                 if (!(valid_std_mask & (1 << idx))) continue;
1702                 cnt1 = pvr2_std_id_to_str(
1703                         hdw->std_mask_names[idx],
1704                         sizeof(hdw->std_mask_names[idx])-1,
1705                         1 << idx);
1706                 hdw->std_mask_names[idx][cnt1] = 0;
1707         }
1708         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1709         if (cptr) {
1710                 memcpy(&hdw->std_info_avail,cptr->info,
1711                        sizeof(hdw->std_info_avail));
1712                 cptr->info = &hdw->std_info_avail;
1713                 hdw->std_info_avail.def.type_bitmask.bit_names =
1714                         hdw->std_mask_ptrs;
1715                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1716                         valid_std_mask;
1717         }
1718         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1719         if (cptr) {
1720                 memcpy(&hdw->std_info_cur,cptr->info,
1721                        sizeof(hdw->std_info_cur));
1722                 cptr->info = &hdw->std_info_cur;
1723                 hdw->std_info_cur.def.type_bitmask.bit_names =
1724                         hdw->std_mask_ptrs;
1725                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1726                         valid_std_mask;
1727         }
1728
1729         hdw->eeprom_addr = -1;
1730         hdw->unit_number = -1;
1731         hdw->v4l_minor_number = -1;
1732         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1733         if (!hdw->ctl_write_buffer) goto fail;
1734         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1735         if (!hdw->ctl_read_buffer) goto fail;
1736         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1737         if (!hdw->ctl_write_urb) goto fail;
1738         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1739         if (!hdw->ctl_read_urb) goto fail;
1740
1741         down(&pvr2_unit_sem); do {
1742                 for (idx = 0; idx < PVR_NUM; idx++) {
1743                         if (unit_pointers[idx]) continue;
1744                         hdw->unit_number = idx;
1745                         unit_pointers[idx] = hdw;
1746                         break;
1747                 }
1748         } while (0); up(&pvr2_unit_sem);
1749
1750         cnt1 = 0;
1751         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1752         cnt1 += cnt2;
1753         if (hdw->unit_number >= 0) {
1754                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1755                                  ('a' + hdw->unit_number));
1756                 cnt1 += cnt2;
1757         }
1758         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1759         hdw->name[cnt1] = 0;
1760
1761         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1762                    hdw->unit_number,hdw->name);
1763
1764         hdw->tuner_type = -1;
1765         hdw->flag_ok = !0;
1766         /* Initialize the mask of subsystems that we will shut down when we
1767            stop streaming. */
1768         hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1769         hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1770
1771         pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1772                    hdw->subsys_stream_mask);
1773
1774         hdw->usb_intf = intf;
1775         hdw->usb_dev = interface_to_usbdev(intf);
1776
1777         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1778         usb_set_interface(hdw->usb_dev,ifnum,0);
1779
1780         mutex_init(&hdw->ctl_lock_mutex);
1781         mutex_init(&hdw->big_lock_mutex);
1782
1783         return hdw;
1784  fail:
1785         if (hdw) {
1786                 if (hdw->ctl_read_urb) usb_free_urb(hdw->ctl_read_urb);
1787                 if (hdw->ctl_write_urb) usb_free_urb(hdw->ctl_write_urb);
1788                 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1789                 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1790                 if (hdw->controls) kfree(hdw->controls);
1791                 kfree(hdw);
1792         }
1793         return 0;
1794 }
1795
1796
1797 /* Remove _all_ associations between this driver and the underlying USB
1798    layer. */
1799 void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1800 {
1801         if (hdw->flag_disconnected) return;
1802         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1803         if (hdw->ctl_read_urb) {
1804                 usb_kill_urb(hdw->ctl_read_urb);
1805                 usb_free_urb(hdw->ctl_read_urb);
1806                 hdw->ctl_read_urb = 0;
1807         }
1808         if (hdw->ctl_write_urb) {
1809                 usb_kill_urb(hdw->ctl_write_urb);
1810                 usb_free_urb(hdw->ctl_write_urb);
1811                 hdw->ctl_write_urb = 0;
1812         }
1813         if (hdw->ctl_read_buffer) {
1814                 kfree(hdw->ctl_read_buffer);
1815                 hdw->ctl_read_buffer = 0;
1816         }
1817         if (hdw->ctl_write_buffer) {
1818                 kfree(hdw->ctl_write_buffer);
1819                 hdw->ctl_write_buffer = 0;
1820         }
1821         pvr2_hdw_render_useless_unlocked(hdw);
1822         hdw->flag_disconnected = !0;
1823         hdw->usb_dev = 0;
1824         hdw->usb_intf = 0;
1825 }
1826
1827
1828 /* Destroy hardware interaction structure */
1829 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
1830 {
1831         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
1832         if (hdw->fw_buffer) {
1833                 kfree(hdw->fw_buffer);
1834                 hdw->fw_buffer = 0;
1835         }
1836         if (hdw->vid_stream) {
1837                 pvr2_stream_destroy(hdw->vid_stream);
1838                 hdw->vid_stream = 0;
1839         }
1840         if (hdw->audio_stat) {
1841                 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
1842         }
1843         if (hdw->decoder_ctrl) {
1844                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
1845         }
1846         pvr2_i2c_core_done(hdw);
1847         pvr2_hdw_remove_usb_stuff(hdw);
1848         down(&pvr2_unit_sem); do {
1849                 if ((hdw->unit_number >= 0) &&
1850                     (hdw->unit_number < PVR_NUM) &&
1851                     (unit_pointers[hdw->unit_number] == hdw)) {
1852                         unit_pointers[hdw->unit_number] = 0;
1853                 }
1854         } while (0); up(&pvr2_unit_sem);
1855         if (hdw->controls) kfree(hdw->controls);
1856         if (hdw->std_defs) kfree(hdw->std_defs);
1857         if (hdw->std_enum_names) kfree(hdw->std_enum_names);
1858         kfree(hdw);
1859 }
1860
1861
1862 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
1863 {
1864         return hdw->flag_init_ok;
1865 }
1866
1867
1868 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
1869 {
1870         return (hdw && hdw->flag_ok);
1871 }
1872
1873
1874 /* Called when hardware has been unplugged */
1875 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
1876 {
1877         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
1878         LOCK_TAKE(hdw->big_lock);
1879         LOCK_TAKE(hdw->ctl_lock);
1880         pvr2_hdw_remove_usb_stuff(hdw);
1881         LOCK_GIVE(hdw->ctl_lock);
1882         LOCK_GIVE(hdw->big_lock);
1883 }
1884
1885
1886 // Attempt to autoselect an appropriate value for std_enum_cur given
1887 // whatever is currently in std_mask_cur
1888 void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
1889 {
1890         unsigned int idx;
1891         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
1892                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
1893                         hdw->std_enum_cur = idx;
1894                         return;
1895                 }
1896         }
1897         hdw->std_enum_cur = 0;
1898 }
1899
1900
1901 // Calculate correct set of enumerated standards based on currently known
1902 // set of available standards bits.
1903 void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
1904 {
1905         struct v4l2_standard *newstd;
1906         unsigned int std_cnt;
1907         unsigned int idx;
1908
1909         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
1910
1911         if (hdw->std_defs) {
1912                 kfree(hdw->std_defs);
1913                 hdw->std_defs = 0;
1914         }
1915         hdw->std_enum_cnt = 0;
1916         if (hdw->std_enum_names) {
1917                 kfree(hdw->std_enum_names);
1918                 hdw->std_enum_names = 0;
1919         }
1920
1921         if (!std_cnt) {
1922                 pvr2_trace(
1923                         PVR2_TRACE_ERROR_LEGS,
1924                         "WARNING: Failed to identify any viable standards");
1925         }
1926         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
1927         hdw->std_enum_names[0] = "none";
1928         for (idx = 0; idx < std_cnt; idx++) {
1929                 hdw->std_enum_names[idx+1] =
1930                         newstd[idx].name;
1931         }
1932         // Set up the dynamic control for this standard
1933         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
1934         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
1935         hdw->std_defs = newstd;
1936         hdw->std_enum_cnt = std_cnt+1;
1937         hdw->std_enum_cur = 0;
1938         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1939 }
1940
1941
1942 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
1943                                struct v4l2_standard *std,
1944                                unsigned int idx)
1945 {
1946         int ret = -EINVAL;
1947         if (!idx) return ret;
1948         LOCK_TAKE(hdw->big_lock); do {
1949                 if (idx >= hdw->std_enum_cnt) break;
1950                 idx--;
1951                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
1952                 ret = 0;
1953         } while (0); LOCK_GIVE(hdw->big_lock);
1954         return ret;
1955 }
1956
1957
1958 /* Get the number of defined controls */
1959 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
1960 {
1961         return hdw->control_cnt;
1962 }
1963
1964
1965 /* Retrieve a control handle given its index (0..count-1) */
1966 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
1967                                              unsigned int idx)
1968 {
1969         if (idx >= hdw->control_cnt) return 0;
1970         return hdw->controls + idx;
1971 }
1972
1973
1974 /* Retrieve a control handle given its index (0..count-1) */
1975 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
1976                                           unsigned int ctl_id)
1977 {
1978         struct pvr2_ctrl *cptr;
1979         unsigned int idx;
1980         int i;
1981
1982         /* This could be made a lot more efficient, but for now... */
1983         for (idx = 0; idx < hdw->control_cnt; idx++) {
1984                 cptr = hdw->controls + idx;
1985                 i = cptr->info->internal_id;
1986                 if (i && (i == ctl_id)) return cptr;
1987         }
1988         return 0;
1989 }
1990
1991
1992 /* Given a V4L ID, retrieve the control structure associated with it. */
1993 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
1994 {
1995         struct pvr2_ctrl *cptr;
1996         unsigned int idx;
1997         int i;
1998
1999         /* This could be made a lot more efficient, but for now... */
2000         for (idx = 0; idx < hdw->control_cnt; idx++) {
2001                 cptr = hdw->controls + idx;
2002                 i = cptr->info->v4l_id;
2003                 if (i && (i == ctl_id)) return cptr;
2004         }
2005         return 0;
2006 }
2007
2008
2009 /* Given a V4L ID for its immediate predecessor, retrieve the control
2010    structure associated with it. */
2011 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2012                                             unsigned int ctl_id)
2013 {
2014         struct pvr2_ctrl *cptr,*cp2;
2015         unsigned int idx;
2016         int i;
2017
2018         /* This could be made a lot more efficient, but for now... */
2019         cp2 = 0;
2020         for (idx = 0; idx < hdw->control_cnt; idx++) {
2021                 cptr = hdw->controls + idx;
2022                 i = cptr->info->v4l_id;
2023                 if (!i) continue;
2024                 if (i <= ctl_id) continue;
2025                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2026                 cp2 = cptr;
2027         }
2028         return cp2;
2029         return 0;
2030 }
2031
2032
2033 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2034 {
2035         switch (tp) {
2036         case pvr2_ctl_int: return "integer";
2037         case pvr2_ctl_enum: return "enum";
2038         case pvr2_ctl_bool: return "boolean";
2039         case pvr2_ctl_bitmask: return "bitmask";
2040         }
2041         return "";
2042 }
2043
2044
2045 /* Commit all control changes made up to this point.  Subsystems can be
2046    indirectly affected by these changes.  For a given set of things being
2047    committed, we'll clear the affected subsystem bits and then once we're
2048    done committing everything we'll make a request to restore the subsystem
2049    state(s) back to their previous value before this function was called.
2050    Thus we can automatically reconfigure affected pieces of the driver as
2051    controls are changed. */
2052 int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2053 {
2054         unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2055         unsigned long stale_subsys_mask = 0;
2056         unsigned int idx;
2057         struct pvr2_ctrl *cptr;
2058         int value;
2059         int commit_flag = 0;
2060         char buf[100];
2061         unsigned int bcnt,ccnt;
2062
2063         for (idx = 0; idx < hdw->control_cnt; idx++) {
2064                 cptr = hdw->controls + idx;
2065                 if (cptr->info->is_dirty == 0) continue;
2066                 if (!cptr->info->is_dirty(cptr)) continue;
2067                 if (!commit_flag) {
2068                         commit_flag = !0;
2069                 }
2070
2071                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2072                                  cptr->info->name);
2073                 value = 0;
2074                 cptr->info->get_value(cptr,&value);
2075                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2076                                                 buf+bcnt,
2077                                                 sizeof(buf)-bcnt,&ccnt);
2078                 bcnt += ccnt;
2079                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2080                                   get_ctrl_typename(cptr->info->type));
2081                 pvr2_trace(PVR2_TRACE_CTL,
2082                            "/*--TRACE_COMMIT--*/ %.*s",
2083                            bcnt,buf);
2084         }
2085
2086         if (!commit_flag) {
2087                 /* Nothing has changed */
2088                 return 0;
2089         }
2090
2091         /* When video standard changes, reset the hres and vres values -
2092            but if the user has pending changes there, then let the changes
2093            take priority. */
2094         if (hdw->std_dirty) {
2095                 /* Rewrite the vertical resolution to be appropriate to the
2096                    video standard that has been selected. */
2097                 int nvres;
2098                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2099                         nvres = 480;
2100                 } else {
2101                         nvres = 576;
2102                 }
2103                 if (nvres != hdw->res_ver_val) {
2104                         hdw->res_ver_val = nvres;
2105                         hdw->res_ver_dirty = !0;
2106                 }
2107                 if (!hdw->interlace_val) {
2108                         hdw->interlace_val = 0;
2109                         hdw->interlace_dirty = !0;
2110                 }
2111         }
2112
2113         if (hdw->std_dirty ||
2114             hdw->interlace_dirty ||
2115             hdw->vbr_dirty ||
2116             hdw->videobitrate_dirty ||
2117             hdw->videopeak_dirty ||
2118             hdw->audiobitrate_dirty ||
2119             hdw->audiolayer_dirty ||
2120             hdw->audiocrc_dirty ||
2121             hdw->audioemphasis_dirty ||
2122             hdw->srate_dirty ||
2123             hdw->res_ver_dirty ||
2124             hdw->res_hor_dirty) {
2125                 /* If any of this changes, then the encoder needs to be
2126                    reconfigured, and we need to reset the stream. */
2127                 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2128                 stale_subsys_mask |= hdw->subsys_stream_mask;
2129         }
2130
2131
2132         /* Scan i2c core at this point - before we clear all the dirty
2133            bits.  Various parts of the i2c core will notice dirty bits as
2134            appropriate and arrange to broadcast or directly send updates to
2135            the client drivers in order to keep everything in sync */
2136         pvr2_i2c_core_check_stale(hdw);
2137
2138         for (idx = 0; idx < hdw->control_cnt; idx++) {
2139                 cptr = hdw->controls + idx;
2140                 if (!cptr->info->clear_dirty) continue;
2141                 cptr->info->clear_dirty(cptr);
2142         }
2143
2144         /* Now execute i2c core update */
2145         pvr2_i2c_core_sync(hdw);
2146
2147         pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2148         pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2149
2150         return 0;
2151 }
2152
2153
2154 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2155 {
2156         LOCK_TAKE(hdw->big_lock); do {
2157                 pvr2_hdw_commit_ctl_internal(hdw);
2158         } while (0); LOCK_GIVE(hdw->big_lock);
2159         return 0;
2160 }
2161
2162
2163 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2164 {
2165         LOCK_TAKE(hdw->big_lock); do {
2166                 pvr2_i2c_core_sync(hdw);
2167         } while (0); LOCK_GIVE(hdw->big_lock);
2168 }
2169
2170
2171 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2172                                  void (*func)(void *),
2173                                  void *data)
2174 {
2175         LOCK_TAKE(hdw->big_lock); do {
2176                 hdw->poll_trigger_func = func;
2177                 hdw->poll_trigger_data = data;
2178         } while (0); LOCK_GIVE(hdw->big_lock);
2179 }
2180
2181
2182 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2183 {
2184         if (hdw->poll_trigger_func) {
2185                 hdw->poll_trigger_func(hdw->poll_trigger_data);
2186         }
2187 }
2188
2189
2190 void pvr2_hdw_poll_trigger(struct pvr2_hdw *hdw)
2191 {
2192         LOCK_TAKE(hdw->big_lock); do {
2193                 pvr2_hdw_poll_trigger_unlocked(hdw);
2194         } while (0); LOCK_GIVE(hdw->big_lock);
2195 }
2196
2197
2198 /* Return name for this driver instance */
2199 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2200 {
2201         return hdw->name;
2202 }
2203
2204
2205 /* Return bit mask indicating signal status */
2206 unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2207 {
2208         unsigned int msk = 0;
2209         switch (hdw->input_val) {
2210         case PVR2_CVAL_INPUT_TV:
2211         case PVR2_CVAL_INPUT_RADIO:
2212                 if (hdw->decoder_ctrl &&
2213                     hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2214                         msk |= PVR2_SIGNAL_OK;
2215                         if (hdw->audio_stat &&
2216                             hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2217                                 if (hdw->flag_stereo) {
2218                                         msk |= PVR2_SIGNAL_STEREO;
2219                                 }
2220                                 if (hdw->flag_bilingual) {
2221                                         msk |= PVR2_SIGNAL_SAP;
2222                                 }
2223                         }
2224                 }
2225                 break;
2226         default:
2227                 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2228         }
2229         return msk;
2230 }
2231
2232
2233 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2234 {
2235         int result;
2236         LOCK_TAKE(hdw->ctl_lock); do {
2237                 hdw->cmd_buffer[0] = 0x0b;
2238                 result = pvr2_send_request(hdw,
2239                                            hdw->cmd_buffer,1,
2240                                            hdw->cmd_buffer,1);
2241                 if (result < 0) break;
2242                 result = (hdw->cmd_buffer[0] != 0);
2243         } while(0); LOCK_GIVE(hdw->ctl_lock);
2244         return result;
2245 }
2246
2247
2248 /* Return bit mask indicating signal status */
2249 unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2250 {
2251         unsigned int msk = 0;
2252         LOCK_TAKE(hdw->big_lock); do {
2253                 msk = pvr2_hdw_get_signal_status_internal(hdw);
2254         } while (0); LOCK_GIVE(hdw->big_lock);
2255         return msk;
2256 }
2257
2258
2259 /* Get handle to video output stream */
2260 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2261 {
2262         return hp->vid_stream;
2263 }
2264
2265
2266 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2267 {
2268         int nr = pvr2_hdw_get_unit_number(hdw);
2269         LOCK_TAKE(hdw->big_lock); do {
2270                 hdw->log_requested = !0;
2271                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2272                 pvr2_i2c_core_check_stale(hdw);
2273                 hdw->log_requested = 0;
2274                 pvr2_i2c_core_sync(hdw);
2275                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2276         } while (0); LOCK_GIVE(hdw->big_lock);
2277 }
2278
2279 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2280 {
2281         int ret;
2282         u16 address;
2283         unsigned int pipe;
2284         LOCK_TAKE(hdw->big_lock); do {
2285                 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2286
2287                 if (!enable_flag) {
2288                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2289                                    "Cleaning up after CPU firmware fetch");
2290                         kfree(hdw->fw_buffer);
2291                         hdw->fw_buffer = 0;
2292                         hdw->fw_size = 0;
2293                         /* Now release the CPU.  It will disconnect and
2294                            reconnect later. */
2295                         pvr2_hdw_cpureset_assert(hdw,0);
2296                         break;
2297                 }
2298
2299                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2300                            "Preparing to suck out CPU firmware");
2301                 hdw->fw_size = 0x2000;
2302                 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2303                 if (!hdw->fw_buffer) {
2304                         hdw->fw_size = 0;
2305                         break;
2306                 }
2307
2308                 memset(hdw->fw_buffer,0,hdw->fw_size);
2309
2310                 /* We have to hold the CPU during firmware upload. */
2311                 pvr2_hdw_cpureset_assert(hdw,1);
2312
2313                 /* download the firmware from address 0000-1fff in 2048
2314                    (=0x800) bytes chunk. */
2315
2316                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2317                 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2318                 for(address = 0; address < hdw->fw_size; address += 0x800) {
2319                         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2320                                               address,0,
2321                                               hdw->fw_buffer+address,0x800,HZ);
2322                         if (ret < 0) break;
2323                 }
2324
2325                 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2326
2327         } while (0); LOCK_GIVE(hdw->big_lock);
2328 }
2329
2330
2331 /* Return true if we're in a mode for retrieval CPU firmware */
2332 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2333 {
2334         return hdw->fw_buffer != 0;
2335 }
2336
2337
2338 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2339                        char *buf,unsigned int cnt)
2340 {
2341         int ret = -EINVAL;
2342         LOCK_TAKE(hdw->big_lock); do {
2343                 if (!buf) break;
2344                 if (!cnt) break;
2345
2346                 if (!hdw->fw_buffer) {
2347                         ret = -EIO;
2348                         break;
2349                 }
2350
2351                 if (offs >= hdw->fw_size) {
2352                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2353                                    "Read firmware data offs=%d EOF",
2354                                    offs);
2355                         ret = 0;
2356                         break;
2357                 }
2358
2359                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2360
2361                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2362
2363                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2364                            "Read firmware data offs=%d cnt=%d",
2365                            offs,cnt);
2366                 ret = cnt;
2367         } while (0); LOCK_GIVE(hdw->big_lock);
2368
2369         return ret;
2370 }
2371
2372
2373 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2374 {
2375         return hdw->v4l_minor_number;
2376 }
2377
2378
2379 /* Store the v4l minor device number */
2380 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2381 {
2382         hdw->v4l_minor_number = v;
2383 }
2384
2385
2386 void pvr2_reset_ctl_endpoints(struct pvr2_hdw *hdw)
2387 {
2388         if (!hdw->usb_dev) return;
2389         usb_settoggle(hdw->usb_dev, PVR2_CTL_WRITE_ENDPOINT & 0xf,
2390                       !(PVR2_CTL_WRITE_ENDPOINT & USB_DIR_IN), 0);
2391         usb_settoggle(hdw->usb_dev, PVR2_CTL_READ_ENDPOINT & 0xf,
2392                       !(PVR2_CTL_READ_ENDPOINT & USB_DIR_IN), 0);
2393         usb_clear_halt(hdw->usb_dev,
2394                        usb_rcvbulkpipe(hdw->usb_dev,
2395                                        PVR2_CTL_READ_ENDPOINT & 0x7f));
2396         usb_clear_halt(hdw->usb_dev,
2397                        usb_sndbulkpipe(hdw->usb_dev,
2398                                        PVR2_CTL_WRITE_ENDPOINT & 0x7f));
2399 }
2400
2401
2402 static void pvr2_ctl_write_complete(struct urb *urb, struct pt_regs *regs)
2403 {
2404         struct pvr2_hdw *hdw = urb->context;
2405         hdw->ctl_write_pend_flag = 0;
2406         if (hdw->ctl_read_pend_flag) return;
2407         complete(&hdw->ctl_done);
2408 }
2409
2410
2411 static void pvr2_ctl_read_complete(struct urb *urb, struct pt_regs *regs)
2412 {
2413         struct pvr2_hdw *hdw = urb->context;
2414         hdw->ctl_read_pend_flag = 0;
2415         if (hdw->ctl_write_pend_flag) return;
2416         complete(&hdw->ctl_done);
2417 }
2418
2419
2420 static void pvr2_ctl_timeout(unsigned long data)
2421 {
2422         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2423         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2424                 hdw->ctl_timeout_flag = !0;
2425                 if (hdw->ctl_write_pend_flag && hdw->ctl_write_urb) {
2426                         usb_unlink_urb(hdw->ctl_write_urb);
2427                 }
2428                 if (hdw->ctl_read_pend_flag && hdw->ctl_read_urb) {
2429                         usb_unlink_urb(hdw->ctl_read_urb);
2430                 }
2431         }
2432 }
2433
2434
2435 int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2436                          unsigned int timeout,int probe_fl,
2437                          void *write_data,unsigned int write_len,
2438                          void *read_data,unsigned int read_len)
2439 {
2440         unsigned int idx;
2441         int status = 0;
2442         struct timer_list timer;
2443         if (!hdw->ctl_lock_held) {
2444                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2445                            "Attempted to execute control transfer"
2446                            " without lock!!");
2447                 return -EDEADLK;
2448         }
2449         if ((!hdw->flag_ok) && !probe_fl) {
2450                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2451                            "Attempted to execute control transfer"
2452                            " when device not ok");
2453                 return -EIO;
2454         }
2455         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2456                 if (!probe_fl) {
2457                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2458                                    "Attempted to execute control transfer"
2459                                    " when USB is disconnected");
2460                 }
2461                 return -ENOTTY;
2462         }
2463
2464         /* Ensure that we have sane parameters */
2465         if (!write_data) write_len = 0;
2466         if (!read_data) read_len = 0;
2467         if (write_len > PVR2_CTL_BUFFSIZE) {
2468                 pvr2_trace(
2469                         PVR2_TRACE_ERROR_LEGS,
2470                         "Attempted to execute %d byte"
2471                         " control-write transfer (limit=%d)",
2472                         write_len,PVR2_CTL_BUFFSIZE);
2473                 return -EINVAL;
2474         }
2475         if (read_len > PVR2_CTL_BUFFSIZE) {
2476                 pvr2_trace(
2477                         PVR2_TRACE_ERROR_LEGS,
2478                         "Attempted to execute %d byte"
2479                         " control-read transfer (limit=%d)",
2480                         write_len,PVR2_CTL_BUFFSIZE);
2481                 return -EINVAL;
2482         }
2483         if ((!write_len) && (!read_len)) {
2484                 pvr2_trace(
2485                         PVR2_TRACE_ERROR_LEGS,
2486                         "Attempted to execute null control transfer?");
2487                 return -EINVAL;
2488         }
2489
2490
2491         hdw->cmd_debug_state = 1;
2492         if (write_len) {
2493                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2494         } else {
2495                 hdw->cmd_debug_code = 0;
2496         }
2497         hdw->cmd_debug_write_len = write_len;
2498         hdw->cmd_debug_read_len = read_len;
2499
2500         /* Initialize common stuff */
2501         init_completion(&hdw->ctl_done);
2502         hdw->ctl_timeout_flag = 0;
2503         hdw->ctl_write_pend_flag = 0;
2504         hdw->ctl_read_pend_flag = 0;
2505         init_timer(&timer);
2506         timer.expires = jiffies + timeout;
2507         timer.data = (unsigned long)hdw;
2508         timer.function = pvr2_ctl_timeout;
2509
2510         if (write_len) {
2511                 hdw->cmd_debug_state = 2;
2512                 /* Transfer write data to internal buffer */
2513                 for (idx = 0; idx < write_len; idx++) {
2514                         hdw->ctl_write_buffer[idx] =
2515                                 ((unsigned char *)write_data)[idx];
2516                 }
2517                 /* Initiate a write request */
2518                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2519                                   hdw->usb_dev,
2520                                   usb_sndbulkpipe(hdw->usb_dev,
2521                                                   PVR2_CTL_WRITE_ENDPOINT),
2522                                   hdw->ctl_write_buffer,
2523                                   write_len,
2524                                   pvr2_ctl_write_complete,
2525                                   hdw);
2526                 hdw->ctl_write_urb->actual_length = 0;
2527                 hdw->ctl_write_pend_flag = !0;
2528                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2529                 if (status < 0) {
2530                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2531                                    "Failed to submit write-control"
2532                                    " URB status=%d",status);
2533                         hdw->ctl_write_pend_flag = 0;
2534                         goto done;
2535                 }
2536         }
2537
2538         if (read_len) {
2539                 hdw->cmd_debug_state = 3;
2540                 memset(hdw->ctl_read_buffer,0x43,read_len);
2541                 /* Initiate a read request */
2542                 usb_fill_bulk_urb(hdw->ctl_read_urb,
2543                                   hdw->usb_dev,
2544                                   usb_rcvbulkpipe(hdw->usb_dev,
2545                                                   PVR2_CTL_READ_ENDPOINT),
2546                                   hdw->ctl_read_buffer,
2547                                   read_len,
2548                                   pvr2_ctl_read_complete,
2549                                   hdw);
2550                 hdw->ctl_read_urb->actual_length = 0;
2551                 hdw->ctl_read_pend_flag = !0;
2552                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2553                 if (status < 0) {
2554                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2555                                    "Failed to submit read-control"
2556                                    " URB status=%d",status);
2557                         hdw->ctl_read_pend_flag = 0;
2558                         goto done;
2559                 }
2560         }
2561
2562         /* Start timer */
2563         add_timer(&timer);
2564
2565         /* Now wait for all I/O to complete */
2566         hdw->cmd_debug_state = 4;
2567         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2568                 wait_for_completion(&hdw->ctl_done);
2569         }
2570         hdw->cmd_debug_state = 5;
2571
2572         /* Stop timer */
2573         del_timer_sync(&timer);
2574
2575         hdw->cmd_debug_state = 6;
2576         status = 0;
2577
2578         if (hdw->ctl_timeout_flag) {
2579                 status = -ETIMEDOUT;
2580                 if (!probe_fl) {
2581                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2582                                    "Timed out control-write");
2583                 }
2584                 goto done;
2585         }
2586
2587         if (write_len) {
2588                 /* Validate results of write request */
2589                 if ((hdw->ctl_write_urb->status != 0) &&
2590                     (hdw->ctl_write_urb->status != -ENOENT) &&
2591                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2592                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
2593                         /* USB subsystem is reporting some kind of failure
2594                            on the write */
2595                         status = hdw->ctl_write_urb->status;
2596                         if (!probe_fl) {
2597                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2598                                            "control-write URB failure,"
2599                                            " status=%d",
2600                                            status);
2601                         }
2602                         goto done;
2603                 }
2604                 if (hdw->ctl_write_urb->actual_length < write_len) {
2605                         /* Failed to write enough data */
2606                         status = -EIO;
2607                         if (!probe_fl) {
2608                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2609                                            "control-write URB short,"
2610                                            " expected=%d got=%d",
2611                                            write_len,
2612                                            hdw->ctl_write_urb->actual_length);
2613                         }
2614                         goto done;
2615                 }
2616         }
2617         if (read_len) {
2618                 /* Validate results of read request */
2619                 if ((hdw->ctl_read_urb->status != 0) &&
2620                     (hdw->ctl_read_urb->status != -ENOENT) &&
2621                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2622                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
2623                         /* USB subsystem is reporting some kind of failure
2624                            on the read */
2625                         status = hdw->ctl_read_urb->status;
2626                         if (!probe_fl) {
2627                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2628                                            "control-read URB failure,"
2629                                            " status=%d",
2630                                            status);
2631                         }
2632                         goto done;
2633                 }
2634                 if (hdw->ctl_read_urb->actual_length < read_len) {
2635                         /* Failed to read enough data */
2636                         status = -EIO;
2637                         if (!probe_fl) {
2638                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2639                                            "control-read URB short,"
2640                                            " expected=%d got=%d",
2641                                            read_len,
2642                                            hdw->ctl_read_urb->actual_length);
2643                         }
2644                         goto done;
2645                 }
2646                 /* Transfer retrieved data out from internal buffer */
2647                 for (idx = 0; idx < read_len; idx++) {
2648                         ((unsigned char *)read_data)[idx] =
2649                                 hdw->ctl_read_buffer[idx];
2650                 }
2651         }
2652
2653  done:
2654
2655         hdw->cmd_debug_state = 0;
2656         if ((status < 0) && (!probe_fl)) {
2657                 pvr2_hdw_render_useless_unlocked(hdw);
2658         }
2659         return status;
2660 }
2661
2662
2663 int pvr2_send_request(struct pvr2_hdw *hdw,
2664                       void *write_data,unsigned int write_len,
2665                       void *read_data,unsigned int read_len)
2666 {
2667         return pvr2_send_request_ex(hdw,HZ*4,0,
2668                                     write_data,write_len,
2669                                     read_data,read_len);
2670 }
2671
2672 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2673 {
2674         int ret;
2675
2676         LOCK_TAKE(hdw->ctl_lock);
2677
2678         hdw->cmd_buffer[0] = 0x04;  /* write register prefix */
2679         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2680         hdw->cmd_buffer[5] = 0;
2681         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2682         hdw->cmd_buffer[7] = reg & 0xff;
2683
2684
2685         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2686
2687         LOCK_GIVE(hdw->ctl_lock);
2688
2689         return ret;
2690 }
2691
2692
2693 int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2694 {
2695         int ret = 0;
2696
2697         LOCK_TAKE(hdw->ctl_lock);
2698
2699         hdw->cmd_buffer[0] = 0x05;  /* read register prefix */
2700         hdw->cmd_buffer[1] = 0;
2701         hdw->cmd_buffer[2] = 0;
2702         hdw->cmd_buffer[3] = 0;
2703         hdw->cmd_buffer[4] = 0;
2704         hdw->cmd_buffer[5] = 0;
2705         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2706         hdw->cmd_buffer[7] = reg & 0xff;
2707
2708         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2709         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2710
2711         LOCK_GIVE(hdw->ctl_lock);
2712
2713         return ret;
2714 }
2715
2716
2717 int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2718 {
2719         int ret;
2720
2721         LOCK_TAKE(hdw->ctl_lock);
2722
2723         hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2724         hdw->cmd_buffer[1] = data & 0xff;
2725
2726         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2727
2728         LOCK_GIVE(hdw->ctl_lock);
2729
2730         return ret;
2731 }
2732
2733
2734 int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2735 {
2736         int ret;
2737
2738         LOCK_TAKE(hdw->ctl_lock);
2739
2740         hdw->cmd_buffer[0] = data;
2741
2742         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2743
2744         LOCK_GIVE(hdw->ctl_lock);
2745
2746         return ret;
2747 }
2748
2749
2750 void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2751 {
2752         if (!hdw->flag_ok) return;
2753         pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2754         hdw->flag_ok = 0;
2755         if (hdw->vid_stream) {
2756                 pvr2_stream_setup(hdw->vid_stream,0,0,0);
2757         }
2758         hdw->flag_streaming_enabled = 0;
2759         hdw->subsys_enabled_mask = 0;
2760 }
2761
2762
2763 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2764 {
2765         LOCK_TAKE(hdw->ctl_lock);
2766         pvr2_hdw_render_useless_unlocked(hdw);
2767         LOCK_GIVE(hdw->ctl_lock);
2768 }
2769
2770
2771 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2772 {
2773         int ret;
2774         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2775         ret = usb_lock_device_for_reset(hdw->usb_dev,0);
2776         if (ret == 1) {
2777                 ret = usb_reset_device(hdw->usb_dev);
2778                 usb_unlock_device(hdw->usb_dev);
2779         } else {
2780                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2781                            "Failed to lock USB device ret=%d",ret);
2782         }
2783         if (init_pause_msec) {
2784                 pvr2_trace(PVR2_TRACE_INFO,
2785                            "Waiting %u msec for hardware to settle",
2786                            init_pause_msec);
2787                 msleep(init_pause_msec);
2788         }
2789
2790 }
2791
2792
2793 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2794 {
2795         char da[1];
2796         unsigned int pipe;
2797         int ret;
2798
2799         if (!hdw->usb_dev) return;
2800
2801         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2802
2803         da[0] = val ? 0x01 : 0x00;
2804
2805         /* Write the CPUCS register on the 8051.  The lsb of the register
2806            is the reset bit; a 1 asserts reset while a 0 clears it. */
2807         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2808         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2809         if (ret < 0) {
2810                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2811                            "cpureset_assert(%d) error=%d",val,ret);
2812                 pvr2_hdw_render_useless(hdw);
2813         }
2814 }
2815
2816
2817 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2818 {
2819         int status;
2820         LOCK_TAKE(hdw->ctl_lock); do {
2821                 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2822                 hdw->flag_ok = !0;
2823                 hdw->cmd_buffer[0] = 0xdd;
2824                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2825         } while (0); LOCK_GIVE(hdw->ctl_lock);
2826         return status;
2827 }
2828
2829
2830 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2831 {
2832         int status;
2833         LOCK_TAKE(hdw->ctl_lock); do {
2834                 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2835                 hdw->cmd_buffer[0] = 0xde;
2836                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2837         } while (0); LOCK_GIVE(hdw->ctl_lock);
2838         return status;
2839 }
2840
2841
2842 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
2843 {
2844         if (!hdw->decoder_ctrl) {
2845                 pvr2_trace(PVR2_TRACE_INIT,
2846                            "Unable to reset decoder: nothing attached");
2847                 return -ENOTTY;
2848         }
2849
2850         if (!hdw->decoder_ctrl->force_reset) {
2851                 pvr2_trace(PVR2_TRACE_INIT,
2852                            "Unable to reset decoder: not implemented");
2853                 return -ENOTTY;
2854         }
2855
2856         pvr2_trace(PVR2_TRACE_INIT,
2857                    "Requesting decoder reset");
2858         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
2859         return 0;
2860 }
2861
2862
2863 int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
2864 {
2865         int status;
2866         LOCK_TAKE(hdw->ctl_lock); do {
2867                 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
2868                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2869         } while (0); LOCK_GIVE(hdw->ctl_lock);
2870         if (!status) {
2871                 hdw->subsys_enabled_mask =
2872                         ((hdw->subsys_enabled_mask &
2873                           ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
2874                          (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
2875         }
2876         return status;
2877 }
2878
2879
2880 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
2881                              struct pvr2_hdw_debug_info *ptr)
2882 {
2883         ptr->big_lock_held = hdw->big_lock_held;
2884         ptr->ctl_lock_held = hdw->ctl_lock_held;
2885         ptr->flag_ok = hdw->flag_ok;
2886         ptr->flag_disconnected = hdw->flag_disconnected;
2887         ptr->flag_init_ok = hdw->flag_init_ok;
2888         ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
2889         ptr->subsys_flags = hdw->subsys_enabled_mask;
2890         ptr->cmd_debug_state = hdw->cmd_debug_state;
2891         ptr->cmd_code = hdw->cmd_debug_code;
2892         ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
2893         ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
2894         ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
2895         ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
2896         ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
2897         ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
2898         ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
2899 }
2900
2901
2902 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
2903 {
2904         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
2905 }
2906
2907
2908 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
2909 {
2910         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
2911 }
2912
2913
2914 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
2915 {
2916         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
2917 }
2918
2919
2920 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
2921 {
2922         u32 cval,nval;
2923         int ret;
2924         if (~msk) {
2925                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
2926                 if (ret) return ret;
2927                 nval = (cval & ~msk) | (val & msk);
2928                 pvr2_trace(PVR2_TRACE_GPIO,
2929                            "GPIO direction changing 0x%x:0x%x"
2930                            " from 0x%x to 0x%x",
2931                            msk,val,cval,nval);
2932         } else {
2933                 nval = val;
2934                 pvr2_trace(PVR2_TRACE_GPIO,
2935                            "GPIO direction changing to 0x%x",nval);
2936         }
2937         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
2938 }
2939
2940
2941 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
2942 {
2943         u32 cval,nval;
2944         int ret;
2945         if (~msk) {
2946                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
2947                 if (ret) return ret;
2948                 nval = (cval & ~msk) | (val & msk);
2949                 pvr2_trace(PVR2_TRACE_GPIO,
2950                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
2951                            msk,val,cval,nval);
2952         } else {
2953                 nval = val;
2954                 pvr2_trace(PVR2_TRACE_GPIO,
2955                            "GPIO output changing to 0x%x",nval);
2956         }
2957         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
2958 }
2959
2960
2961 int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
2962 {
2963         int result;
2964         LOCK_TAKE(hdw->ctl_lock); do {
2965                 hdw->cmd_buffer[0] = 0xeb;
2966                 result = pvr2_send_request(hdw,
2967                                            hdw->cmd_buffer,1,
2968                                            hdw->cmd_buffer,1);
2969                 if (result < 0) break;
2970                 result = hdw->cmd_buffer[0];
2971         } while(0); LOCK_GIVE(hdw->ctl_lock);
2972         return result;
2973 }
2974
2975
2976 /*
2977   Stuff for Emacs to see, in order to encourage consistent editing style:
2978   *** Local Variables: ***
2979   *** mode: c ***
2980   *** fill-column: 75 ***
2981   *** tab-width: 8 ***
2982   *** c-basic-offset: 8 ***
2983   *** End: ***
2984   */