2 * Register interface file for Samsung Camera Interface (FIMC) driver
4 * Copyright (c) 2010 Samsung Electronics
6 * Sylwester Nawrocki, s.nawrocki@samsung.com
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/delay.h>
17 #include "fimc-core.h"
20 void fimc_hw_reset(struct fimc_dev *dev)
24 cfg = readl(dev->regs + S5P_CISRCFMT);
25 cfg |= S5P_CISRCFMT_ITU601_8BIT;
26 writel(cfg, dev->regs + S5P_CISRCFMT);
29 cfg = readl(dev->regs + S5P_CIGCTRL);
30 cfg |= (S5P_CIGCTRL_SWRST | S5P_CIGCTRL_IRQ_LEVEL);
31 writel(cfg, dev->regs + S5P_CIGCTRL);
34 cfg = readl(dev->regs + S5P_CIGCTRL);
35 cfg &= ~S5P_CIGCTRL_SWRST;
36 writel(cfg, dev->regs + S5P_CIGCTRL);
40 void fimc_hw_set_rotation(struct fimc_ctx *ctx)
43 struct fimc_dev *dev = ctx->fimc_dev;
45 cfg = readl(dev->regs + S5P_CITRGFMT);
46 cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90);
48 flip = readl(dev->regs + S5P_MSCTRL);
49 flip &= ~S5P_MSCTRL_FLIP_MASK;
52 * The input and output rotator cannot work simultaneously.
53 * Use the output rotator in output DMA mode or the input rotator
54 * in direct fifo output mode.
56 if (ctx->rotation == 90 || ctx->rotation == 270) {
57 if (ctx->out_path == FIMC_LCDFIFO) {
58 cfg |= S5P_CITRGFMT_INROT90;
59 if (ctx->rotation == 270)
60 flip |= S5P_MSCTRL_FLIP_180;
62 cfg |= S5P_CITRGFMT_OUTROT90;
63 if (ctx->rotation == 270)
64 cfg |= S5P_CITRGFMT_FLIP_180;
66 } else if (ctx->rotation == 180) {
67 if (ctx->out_path == FIMC_LCDFIFO)
68 flip |= S5P_MSCTRL_FLIP_180;
70 cfg |= S5P_CITRGFMT_FLIP_180;
72 if (ctx->rotation == 180 || ctx->rotation == 270)
73 writel(flip, dev->regs + S5P_MSCTRL);
74 writel(cfg, dev->regs + S5P_CITRGFMT);
77 static u32 fimc_hw_get_in_flip(u32 ctx_flip)
79 u32 flip = S5P_MSCTRL_FLIP_NORMAL;
83 flip = S5P_MSCTRL_FLIP_X_MIRROR;
86 flip = S5P_MSCTRL_FLIP_Y_MIRROR;
89 flip = S5P_MSCTRL_FLIP_180;
96 static u32 fimc_hw_get_target_flip(u32 ctx_flip)
98 u32 flip = S5P_CITRGFMT_FLIP_NORMAL;
102 flip = S5P_CITRGFMT_FLIP_X_MIRROR;
105 flip = S5P_CITRGFMT_FLIP_Y_MIRROR;
108 flip = S5P_CITRGFMT_FLIP_180;
117 void fimc_hw_set_target_format(struct fimc_ctx *ctx)
120 struct fimc_dev *dev = ctx->fimc_dev;
121 struct fimc_frame *frame = &ctx->d_frame;
123 dbg("w= %d, h= %d color: %d", frame->width,
124 frame->height, frame->fmt->color);
126 cfg = readl(dev->regs + S5P_CITRGFMT);
127 cfg &= ~(S5P_CITRGFMT_FMT_MASK | S5P_CITRGFMT_HSIZE_MASK |
128 S5P_CITRGFMT_VSIZE_MASK);
130 switch (frame->fmt->color) {
131 case S5P_FIMC_RGB565:
132 case S5P_FIMC_RGB666:
133 case S5P_FIMC_RGB888:
134 cfg |= S5P_CITRGFMT_RGB;
136 case S5P_FIMC_YCBCR420:
137 cfg |= S5P_CITRGFMT_YCBCR420;
139 case S5P_FIMC_YCBYCR422:
140 case S5P_FIMC_YCRYCB422:
141 case S5P_FIMC_CBYCRY422:
142 case S5P_FIMC_CRYCBY422:
143 if (frame->fmt->planes_cnt == 1)
144 cfg |= S5P_CITRGFMT_YCBCR422_1P;
146 cfg |= S5P_CITRGFMT_YCBCR422;
152 cfg |= S5P_CITRGFMT_HSIZE(frame->width);
153 cfg |= S5P_CITRGFMT_VSIZE(frame->height);
155 if (ctx->rotation == 0) {
156 cfg &= ~S5P_CITRGFMT_FLIP_MASK;
157 cfg |= fimc_hw_get_target_flip(ctx->flip);
159 writel(cfg, dev->regs + S5P_CITRGFMT);
161 cfg = readl(dev->regs + S5P_CITAREA) & ~S5P_CITAREA_MASK;
162 cfg |= (frame->width * frame->height);
163 writel(cfg, dev->regs + S5P_CITAREA);
166 static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
168 struct fimc_dev *dev = ctx->fimc_dev;
169 struct fimc_frame *frame = &ctx->d_frame;
172 if (ctx->rotation == 90 || ctx->rotation == 270) {
173 cfg |= S5P_ORIG_SIZE_HOR(frame->f_height);
174 cfg |= S5P_ORIG_SIZE_VER(frame->f_width);
176 cfg |= S5P_ORIG_SIZE_HOR(frame->f_width);
177 cfg |= S5P_ORIG_SIZE_VER(frame->f_height);
179 writel(cfg, dev->regs + S5P_ORGOSIZE);
182 void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
185 struct fimc_dev *dev = ctx->fimc_dev;
186 struct fimc_frame *frame = &ctx->d_frame;
187 struct fimc_dma_offset *offset = &frame->dma_offset;
189 /* Set the input dma offsets. */
191 cfg |= S5P_CIO_OFFS_HOR(offset->y_h);
192 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
193 writel(cfg, dev->regs + S5P_CIOYOFF);
196 cfg |= S5P_CIO_OFFS_HOR(offset->cb_h);
197 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
198 writel(cfg, dev->regs + S5P_CIOCBOFF);
201 cfg |= S5P_CIO_OFFS_HOR(offset->cr_h);
202 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
203 writel(cfg, dev->regs + S5P_CIOCROFF);
205 fimc_hw_set_out_dma_size(ctx);
207 /* Configure chroma components order. */
208 cfg = readl(dev->regs + S5P_CIOCTRL);
210 cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK |
211 S5P_CIOCTRL_YCBCR_PLANE_MASK);
213 if (frame->fmt->planes_cnt == 1)
214 cfg |= ctx->out_order_1p;
215 else if (frame->fmt->planes_cnt == 2)
216 cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE;
217 else if (frame->fmt->planes_cnt == 3)
218 cfg |= S5P_CIOCTRL_YCBCR_3PLANE;
220 writel(cfg, dev->regs + S5P_CIOCTRL);
223 static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
225 u32 cfg = readl(dev->regs + S5P_ORGISIZE);
227 cfg |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
229 cfg &= ~S5P_CIREAL_ISIZE_AUTOLOAD_EN;
230 writel(cfg, dev->regs + S5P_ORGISIZE);
233 void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
238 spin_lock_irqsave(&dev->slock, flags);
240 cfg = readl(dev->regs + S5P_CIOCTRL);
242 cfg |= S5P_CIOCTRL_LASTIRQ_ENABLE;
244 cfg &= ~S5P_CIOCTRL_LASTIRQ_ENABLE;
245 writel(cfg, dev->regs + S5P_CIOCTRL);
247 spin_unlock_irqrestore(&dev->slock, flags);
250 void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
252 struct fimc_dev *dev = ctx->fimc_dev;
253 struct fimc_scaler *sc = &ctx->scaler;
254 u32 cfg = 0, shfactor;
256 shfactor = 10 - (sc->hfactor + sc->vfactor);
258 cfg |= S5P_CISCPRERATIO_SHFACTOR(shfactor);
259 cfg |= S5P_CISCPRERATIO_HOR(sc->pre_hratio);
260 cfg |= S5P_CISCPRERATIO_VER(sc->pre_vratio);
261 writel(cfg, dev->regs + S5P_CISCPRERATIO);
264 cfg |= S5P_CISCPREDST_WIDTH(sc->pre_dst_width);
265 cfg |= S5P_CISCPREDST_HEIGHT(sc->pre_dst_height);
266 writel(cfg, dev->regs + S5P_CISCPREDST);
269 void fimc_hw_set_scaler(struct fimc_ctx *ctx)
271 struct fimc_dev *dev = ctx->fimc_dev;
272 struct fimc_scaler *sc = &ctx->scaler;
273 struct fimc_frame *src_frame = &ctx->s_frame;
274 struct fimc_frame *dst_frame = &ctx->d_frame;
277 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
278 cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE);
281 cfg |= S5P_CISCCTRL_SCALERBYPASS;
284 cfg |= S5P_CISCCTRL_SCALEUP_H;
287 cfg |= S5P_CISCCTRL_SCALEUP_V;
290 cfg |= S5P_CISCCTRL_ONE2ONE;
293 if (ctx->in_path == FIMC_DMA) {
294 if (src_frame->fmt->color == S5P_FIMC_RGB565)
295 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB565;
296 else if (src_frame->fmt->color == S5P_FIMC_RGB666)
297 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB666;
298 else if (src_frame->fmt->color == S5P_FIMC_RGB888)
299 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB888;
302 if (ctx->out_path == FIMC_DMA) {
303 if (dst_frame->fmt->color == S5P_FIMC_RGB565)
304 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565;
305 else if (dst_frame->fmt->color == S5P_FIMC_RGB666)
306 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666;
307 else if (dst_frame->fmt->color == S5P_FIMC_RGB888)
308 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
310 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
312 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
313 cfg |= S5P_CISCCTRL_INTERLACE;
316 dbg("main_hratio= 0x%X main_vratio= 0x%X",
317 sc->main_hratio, sc->main_vratio);
319 cfg |= S5P_CISCCTRL_SC_HORRATIO(sc->main_hratio);
320 cfg |= S5P_CISCCTRL_SC_VERRATIO(sc->main_vratio);
322 writel(cfg, dev->regs + S5P_CISCCTRL);
325 void fimc_hw_en_capture(struct fimc_ctx *ctx)
327 struct fimc_dev *dev = ctx->fimc_dev;
330 cfg = readl(dev->regs + S5P_CIIMGCPT);
331 /* One shot mode for output DMA or freerun for FIFO. */
332 if (ctx->out_path == FIMC_DMA)
333 cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE;
335 cfg &= ~S5P_CIIMGCPT_CPT_FREN_ENABLE;
337 if (ctx->scaler.enabled)
338 cfg |= S5P_CIIMGCPT_IMGCPTEN_SC;
340 writel(cfg | S5P_CIIMGCPT_IMGCPTEN, dev->regs + S5P_CIIMGCPT);
343 void fimc_hw_set_effect(struct fimc_ctx *ctx)
345 struct fimc_dev *dev = ctx->fimc_dev;
346 struct fimc_effect *effect = &ctx->effect;
347 u32 cfg = (S5P_CIIMGEFF_IE_ENABLE | S5P_CIIMGEFF_IE_SC_AFTER);
351 if (effect->type == S5P_FIMC_EFFECT_ARBITRARY) {
352 cfg |= S5P_CIIMGEFF_PAT_CB(effect->pat_cb);
353 cfg |= S5P_CIIMGEFF_PAT_CR(effect->pat_cr);
356 writel(cfg, dev->regs + S5P_CIIMGEFF);
359 static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
361 struct fimc_dev *dev = ctx->fimc_dev;
362 struct fimc_frame *frame = &ctx->s_frame;
366 if (FIMC_LCDFIFO == ctx->out_path)
367 cfg_r |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
369 cfg_o |= S5P_ORIG_SIZE_HOR(frame->f_width);
370 cfg_o |= S5P_ORIG_SIZE_VER(frame->f_height);
371 cfg_r |= S5P_CIREAL_ISIZE_WIDTH(frame->width);
372 cfg_r |= S5P_CIREAL_ISIZE_HEIGHT(frame->height);
374 writel(cfg_o, dev->regs + S5P_ORGISIZE);
375 writel(cfg_r, dev->regs + S5P_CIREAL_ISIZE);
378 void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
380 struct fimc_dev *dev = ctx->fimc_dev;
381 struct fimc_frame *frame = &ctx->s_frame;
382 struct fimc_dma_offset *offset = &frame->dma_offset;
385 /* Set the pixel offsets. */
386 cfg |= S5P_CIO_OFFS_HOR(offset->y_h);
387 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
388 writel(cfg, dev->regs + S5P_CIIYOFF);
391 cfg |= S5P_CIO_OFFS_HOR(offset->cb_h);
392 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
393 writel(cfg, dev->regs + S5P_CIICBOFF);
396 cfg |= S5P_CIO_OFFS_HOR(offset->cr_h);
397 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
398 writel(cfg, dev->regs + S5P_CIICROFF);
400 /* Input original and real size. */
401 fimc_hw_set_in_dma_size(ctx);
403 /* Autoload is used currently only in FIFO mode. */
404 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO);
406 /* Set the input DMA to process single frame only. */
407 cfg = readl(dev->regs + S5P_MSCTRL);
408 cfg &= ~(S5P_MSCTRL_FLIP_MASK
409 | S5P_MSCTRL_INFORMAT_MASK
410 | S5P_MSCTRL_IN_BURST_COUNT_MASK
411 | S5P_MSCTRL_INPUT_MASK
412 | S5P_MSCTRL_C_INT_IN_MASK
413 | S5P_MSCTRL_2P_IN_ORDER_MASK);
415 cfg |= (S5P_MSCTRL_FRAME_COUNT(1) | S5P_MSCTRL_INPUT_MEMORY);
417 switch (frame->fmt->color) {
418 case S5P_FIMC_RGB565:
419 case S5P_FIMC_RGB666:
420 case S5P_FIMC_RGB888:
421 cfg |= S5P_MSCTRL_INFORMAT_RGB;
423 case S5P_FIMC_YCBCR420:
424 cfg |= S5P_MSCTRL_INFORMAT_YCBCR420;
426 if (frame->fmt->planes_cnt == 2)
427 cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE;
429 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
432 case S5P_FIMC_YCBYCR422:
433 case S5P_FIMC_YCRYCB422:
434 case S5P_FIMC_CBYCRY422:
435 case S5P_FIMC_CRYCBY422:
436 if (frame->fmt->planes_cnt == 1) {
437 cfg |= ctx->in_order_1p
438 | S5P_MSCTRL_INFORMAT_YCBCR422_1P;
440 cfg |= S5P_MSCTRL_INFORMAT_YCBCR422;
442 if (frame->fmt->planes_cnt == 2)
443 cfg |= ctx->in_order_2p
444 | S5P_MSCTRL_C_INT_IN_2PLANE;
446 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
454 * Input DMA flip mode (and rotation).
455 * Do not allow simultaneous rotation and flipping.
457 if (!ctx->rotation && ctx->out_path == FIMC_LCDFIFO)
458 cfg |= fimc_hw_get_in_flip(ctx->flip);
460 writel(cfg, dev->regs + S5P_MSCTRL);
462 /* Input/output DMA linear/tiled mode. */
463 cfg = readl(dev->regs + S5P_CIDMAPARAM);
464 cfg &= ~S5P_CIDMAPARAM_TILE_MASK;
466 if (tiled_fmt(ctx->s_frame.fmt))
467 cfg |= S5P_CIDMAPARAM_R_64X32;
469 if (tiled_fmt(ctx->d_frame.fmt))
470 cfg |= S5P_CIDMAPARAM_W_64X32;
472 writel(cfg, dev->regs + S5P_CIDMAPARAM);
476 void fimc_hw_set_input_path(struct fimc_ctx *ctx)
478 struct fimc_dev *dev = ctx->fimc_dev;
480 u32 cfg = readl(dev->regs + S5P_MSCTRL);
481 cfg &= ~S5P_MSCTRL_INPUT_MASK;
483 if (ctx->in_path == FIMC_DMA)
484 cfg |= S5P_MSCTRL_INPUT_MEMORY;
486 cfg |= S5P_MSCTRL_INPUT_EXTCAM;
488 writel(cfg, dev->regs + S5P_MSCTRL);
491 void fimc_hw_set_output_path(struct fimc_ctx *ctx)
493 struct fimc_dev *dev = ctx->fimc_dev;
495 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
496 cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO;
497 if (ctx->out_path == FIMC_LCDFIFO)
498 cfg |= S5P_CISCCTRL_LCDPATHEN_FIFO;
499 writel(cfg, dev->regs + S5P_CISCCTRL);
502 void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
506 cfg = readl(dev->regs + S5P_CIREAL_ISIZE);
507 cfg |= S5P_CIREAL_ISIZE_ADDR_CH_DIS;
508 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
510 writel(paddr->y, dev->regs + S5P_CIIYSA0);
511 writel(paddr->cb, dev->regs + S5P_CIICBSA0);
512 writel(paddr->cr, dev->regs + S5P_CIICRSA0);
514 cfg &= ~S5P_CIREAL_ISIZE_ADDR_CH_DIS;
515 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
518 void fimc_hw_set_output_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
521 /* Set all the output register sets to point to single video buffer. */
522 for (i = 0; i < FIMC_MAX_OUT_BUFS; i++) {
523 writel(paddr->y, dev->regs + S5P_CIOYSA(i));
524 writel(paddr->cb, dev->regs + S5P_CIOCBSA(i));
525 writel(paddr->cr, dev->regs + S5P_CIOCRSA(i));