drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/driver.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_device.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/omap-gpmc.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include <linux/platform_data/mtd-nand-omap2.h>
  35 #include <linux/platform_data/mtd-onenand-omap2.h>
  36
  37 #include <asm/mach-types.h>
  38
  39 #define DEVICE_NAME             "omap-gpmc"
  40
  41 /* GPMC register offsets */
  42 #define GPMC_REVISION           0x00
  43 #define GPMC_SYSCONFIG          0x10
  44 #define GPMC_SYSSTATUS          0x14
  45 #define GPMC_IRQSTATUS          0x18
  46 #define GPMC_IRQENABLE          0x1c
  47 #define GPMC_TIMEOUT_CONTROL    0x40
  48 #define GPMC_ERR_ADDRESS        0x44
  49 #define GPMC_ERR_TYPE           0x48
  50 #define GPMC_CONFIG             0x50
  51 #define GPMC_STATUS             0x54
  52 #define GPMC_PREFETCH_CONFIG1   0x1e0
  53 #define GPMC_PREFETCH_CONFIG2   0x1e4
  54 #define GPMC_PREFETCH_CONTROL   0x1ec
  55 #define GPMC_PREFETCH_STATUS    0x1f0
  56 #define GPMC_ECC_CONFIG         0x1f4
  57 #define GPMC_ECC_CONTROL        0x1f8
  58 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  59 #define GPMC_ECC1_RESULT        0x200
  60 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  61 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  67
  68 /* GPMC ECC control settings */
  69 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  70 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  71 #define GPMC_ECC_CTRL_ECCREG1           0x001
  72 #define GPMC_ECC_CTRL_ECCREG2           0x002
  73 #define GPMC_ECC_CTRL_ECCREG3           0x003
  74 #define GPMC_ECC_CTRL_ECCREG4           0x004
  75 #define GPMC_ECC_CTRL_ECCREG5           0x005
  76 #define GPMC_ECC_CTRL_ECCREG6           0x006
  77 #define GPMC_ECC_CTRL_ECCREG7           0x007
  78 #define GPMC_ECC_CTRL_ECCREG8           0x008
  79 #define GPMC_ECC_CTRL_ECCREG9           0x009
  80
  81 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  82
  83 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS      BIT(0)
  84
  85 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  86 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  87 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  88 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  89 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  90 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  91
  92 #define GPMC_CS0_OFFSET         0x60
  93 #define GPMC_CS_SIZE            0x30
  94 #define GPMC_BCH_SIZE           0x10
  95
  96 /*
  97  * The first 1MB of GPMC address space is typically mapped to
  98  * the internal ROM. Never allocate the first page, to
  99  * facilitate bug detection; even if we didn't boot from ROM.
 100  * As GPMC minimum partition size is 16MB we can only start from
 101  * there.
 102  */
 103 #define GPMC_MEM_START          0x1000000
 104 #define GPMC_MEM_END            0x3FFFFFFF
 105
 106 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 107 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 108
 109 #define CS_NUM_SHIFT            24
 110 #define ENABLE_PREFETCH         (0x1 << 7)
 111 #define DMA_MPU_MODE            2
 112
 113 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 114 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 115
 116 #define GPMC_HAS_WR_ACCESS              0x1
 117 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 118 #define GPMC_HAS_MUX_AAD                0x4
 119
 120 #define GPMC_NR_WAITPINS                4
 121
 122 #define GPMC_CS_CONFIG1         0x00
 123 #define GPMC_CS_CONFIG2         0x04
 124 #define GPMC_CS_CONFIG3         0x08
 125 #define GPMC_CS_CONFIG4         0x0c
 126 #define GPMC_CS_CONFIG5         0x10
 127 #define GPMC_CS_CONFIG6         0x14
 128 #define GPMC_CS_CONFIG7         0x18
 129 #define GPMC_CS_NAND_COMMAND    0x1c
 130 #define GPMC_CS_NAND_ADDRESS    0x20
 131 #define GPMC_CS_NAND_DATA       0x24
 132
 133 /* Control Commands */
 134 #define GPMC_CONFIG_RDY_BSY     0x00000001
 135 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 136 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 137
 138 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 139 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 140 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 141 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 142 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 143 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 144 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 145 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 146 /** CLKACTIVATIONTIME Max Ticks */
 147 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 148 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 149 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 150 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 151 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 152 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 153 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
 154 /** WAITMONITORINGTIME Max Ticks */
 155 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 156 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 157 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 158 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 159 /** DEVICESIZE Max Value */
 160 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 161 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 162 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 163 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 164 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 165 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 166 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 167 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 168 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 169 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 170
 171 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 172 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 173 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 174 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 175 /* All CONFIG7 bits except reserved bits */
 176 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 177                                          GPMC_CONFIG7_CSVALID_MASK |     \
 178                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 179
 180 #define GPMC_DEVICETYPE_NOR             0
 181 #define GPMC_DEVICETYPE_NAND            2
 182 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 183 #define WR_RD_PIN_MONITORING            0x00600000
 184
 185 /* ECC commands */
 186 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 187 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 188 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 189
 190 #define GPMC_NR_NAND_IRQS       2 /* number of NAND specific IRQs */
 191
 192 enum gpmc_clk_domain {
 193         GPMC_CD_FCLK,
 194         GPMC_CD_CLK
 195 };
 196
 197 struct gpmc_cs_data {
 198         const char *name;
 199
 200 #define GPMC_CS_RESERVED        (1 << 0)
 201         u32 flags;
 202
 203         struct resource mem;
 204 };
 205
 206 /* Structure to save gpmc cs context */
 207 struct gpmc_cs_config {
 208         u32 config1;
 209         u32 config2;
 210         u32 config3;
 211         u32 config4;
 212         u32 config5;
 213         u32 config6;
 214         u32 config7;
 215         int is_valid;
 216 };
 217
 218 /*
 219  * Structure to save/restore gpmc context
 220  * to support core off on OMAP3
 221  */
 222 struct omap3_gpmc_regs {
 223         u32 sysconfig;
 224         u32 irqenable;
 225         u32 timeout_ctrl;
 226         u32 config;
 227         u32 prefetch_config1;
 228         u32 prefetch_config2;
 229         u32 prefetch_control;
 230         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 231 };
 232
 233 struct gpmc_device {
 234         struct device *dev;
 235         int irq;
 236         struct irq_chip irq_chip;
 237         struct gpio_chip gpio_chip;
 238         int nirqs;
 239 };
 240
 241 static struct irq_domain *gpmc_irq_domain;
 242
 243 static struct resource  gpmc_mem_root;
 244 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 245 static DEFINE_SPINLOCK(gpmc_mem_lock);
 246 /* Define chip-selects as reserved by default until probe completes */
 247 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 248 static unsigned int gpmc_nr_waitpins;
 249 static resource_size_t phys_base, mem_size;
 250 static unsigned gpmc_capability;
 251 static void __iomem *gpmc_base;
 252
 253 static struct clk *gpmc_l3_clk;
 254
 255 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 256
 257 static void gpmc_write_reg(int idx, u32 val)
 258 {
 259         writel_relaxed(val, gpmc_base + idx);
 260 }
 261
 262 static u32 gpmc_read_reg(int idx)
 263 {
 264         return readl_relaxed(gpmc_base + idx);
 265 }
 266
 267 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 268 {
 269         void __iomem *reg_addr;
 270
 271         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 272         writel_relaxed(val, reg_addr);
 273 }
 274
 275 static u32 gpmc_cs_read_reg(int cs, int idx)
 276 {
 277         void __iomem *reg_addr;
 278
 279         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 280         return readl_relaxed(reg_addr);
 281 }
 282
 283 /* TODO: Add support for gpmc_fck to clock framework and use it */
 284 static unsigned long gpmc_get_fclk_period(void)
 285 {
 286         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 287
 288         rate /= 1000;
 289         rate = 1000000000 / rate;       /* In picoseconds */
 290
 291         return rate;
 292 }
 293
 294 /**
 295  * gpmc_get_clk_period - get period of selected clock domain in ps
 296  * @cs Chip Select Region.
 297  * @cd Clock Domain.
 298  *
 299  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 300  * prior to calling this function with GPMC_CD_CLK.
 301  */
 302 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 303 {
 304
 305         unsigned long tick_ps = gpmc_get_fclk_period();
 306         u32 l;
 307         int div;
 308
 309         switch (cd) {
 310         case GPMC_CD_CLK:
 311                 /* get current clk divider */
 312                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 313                 div = (l & 0x03) + 1;
 314                 /* get GPMC_CLK period */
 315                 tick_ps *= div;
 316                 break;
 317         case GPMC_CD_FCLK:
 318                 /* FALL-THROUGH */
 319         default:
 320                 break;
 321         }
 322
 323         return tick_ps;
 324
 325 }
 326
 327 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 328                                          enum gpmc_clk_domain cd)
 329 {
 330         unsigned long tick_ps;
 331
 332         /* Calculate in picosecs to yield more exact results */
 333         tick_ps = gpmc_get_clk_period(cs, cd);
 334
 335         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 336 }
 337
 338 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 339 {
 340         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 341 }
 342
 343 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 344 {
 345         unsigned long tick_ps;
 346
 347         /* Calculate in picosecs to yield more exact results */
 348         tick_ps = gpmc_get_fclk_period();
 349
 350         return (time_ps + tick_ps - 1) / tick_ps;
 351 }
 352
 353 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
 354                                   enum gpmc_clk_domain cd)
 355 {
 356         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 357 }
 358
 359 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 360 {
 361         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 362 }
 363
 364 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 365 {
 366         return ticks * gpmc_get_fclk_period();
 367 }
 368
 369 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 370 {
 371         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 372
 373         return ticks * gpmc_get_fclk_period();
 374 }
 375
 376 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 377 {
 378         u32 l;
 379
 380         l = gpmc_cs_read_reg(cs, reg);
 381         if (value)
 382                 l |= mask;
 383         else
 384                 l &= ~mask;
 385         gpmc_cs_write_reg(cs, reg, l);
 386 }
 387
 388 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 389 {
 390         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 391                            GPMC_CONFIG1_TIME_PARA_GRAN,
 392                            p->time_para_granularity);
 393         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 394                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 395         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 396                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 397         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 398                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 399         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 400                            GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
 401         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 402                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 403                            p->cycle2cyclesamecsen);
 404         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 405                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 406                            p->cycle2cyclediffcsen);
 407 }
 408
 409 #ifdef CONFIG_OMAP_GPMC_DEBUG
 410 /**
 411  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 412  * @cs:      Chip Select Region
 413  * @reg:     GPMC_CS_CONFIGn register offset.
 414  * @st_bit:  Start Bit
 415  * @end_bit: End Bit. Must be >= @st_bit.
 416  * @ma:x     Maximum parameter value (before optional @shift).
 417  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 418  * @name:    DTS node name, w/o "gpmc,"
 419  * @cd:      Clock Domain of timing parameter.
 420  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 421  * @raw:     Raw Format Option.
 422  *           raw format:  gpmc,name = <value>
 423  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 424  *           Where x ns -- y ns result in the same tick value.
 425  *           When @max is exceeded, "invalid" is printed inside comment.
 426  * @noval:   Parameter values equal to 0 are not printed.
 427  * @return:  Specified timing parameter (after optional @shift).
 428  *
 429  */
 430 static int get_gpmc_timing_reg(
 431         /* timing specifiers */
 432         int cs, int reg, int st_bit, int end_bit, int max,
 433         const char *name, const enum gpmc_clk_domain cd,
 434         /* value transform */
 435         int shift,
 436         /* format specifiers */
 437         bool raw, bool noval)
 438 {
 439         u32 l;
 440         int nr_bits;
 441         int mask;
 442         bool invalid;
 443
 444         l = gpmc_cs_read_reg(cs, reg);
 445         nr_bits = end_bit - st_bit + 1;
 446         mask = (1 << nr_bits) - 1;
 447         l = (l >> st_bit) & mask;
 448         if (!max)
 449                 max = mask;
 450         invalid = l > max;
 451         if (shift)
 452                 l = (shift << l);
 453         if (noval && (l == 0))
 454                 return 0;
 455         if (!raw) {
 456                 /* DTS tick format for timings in ns */
 457                 unsigned int time_ns;
 458                 unsigned int time_ns_min = 0;
 459
 460                 if (l)
 461                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 462                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 463                 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
 464                         name, time_ns, time_ns_min, time_ns, l,
 465                         invalid ? "; invalid " : " ");
 466         } else {
 467                 /* raw format */
 468                 pr_info("gpmc,%s = <%u>%s\n", name, l,
 469                         invalid ? " /* invalid */" : "");
 470         }
 471
 472         return l;
 473 }
 474
 475 #define GPMC_PRINT_CONFIG(cs, config) \
 476         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 477                 gpmc_cs_read_reg(cs, config))
 478 #define GPMC_GET_RAW(reg, st, end, field) \
 479         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 480 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 481         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 482 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 483         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 484 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 485         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 486 #define GPMC_GET_TICKS(reg, st, end, field) \
 487         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 488 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 489         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 490 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 491         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 492
 493 static void gpmc_show_regs(int cs, const char *desc)
 494 {
 495         pr_info("gpmc cs%i %s:\n", cs, desc);
 496         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 497         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 498         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 499         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 500         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 501         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 502 }
 503
 504 /*
 505  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 506  * see commit c9fb809.
 507  */
 508 static void gpmc_cs_show_timings(int cs, const char *desc)
 509 {
 510         gpmc_show_regs(cs, desc);
 511
 512         pr_info("gpmc cs%i access configuration:\n", cs);
 513         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 514         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 515         GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
 516                          GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 517         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 518         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 519         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 520         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 521                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 522                                "burst-length");
 523         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 524         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 525         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 527         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 528
 529         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 530
 531         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 532
 533         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 534         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 535
 536         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 537         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 538
 539         pr_info("gpmc cs%i timings configuration:\n", cs);
 540         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 541         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 542         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 543
 544         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 545         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 546         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 547         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 548                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 549                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 550                                 "adv-aad-mux-rd-off-ns");
 551                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 552                                 "adv-aad-mux-wr-off-ns");
 553         }
 554
 555         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 556         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 557         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 558                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 559                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 560         }
 561         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 562         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 563
 564         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 565         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 566         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 567
 568         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 569
 570         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 571         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 572
 573         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 574                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 575                               "wait-monitoring-ns", GPMC_CD_CLK);
 576         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 577                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 578                               "clk-activation-ns", GPMC_CD_FCLK);
 579
 580         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 581         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 582 }
 583 #else
 584 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 585 {
 586 }
 587 #endif
 588
 589 /**
 590  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 591  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 592  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 593  *
 594  * @cs:      Chip Select Region.
 595  * @reg:     GPMC_CS_CONFIGn register offset.
 596  * @st_bit:  Start Bit
 597  * @end_bit: End Bit. Must be >= @st_bit.
 598  * @max:     Maximum parameter value.
 599  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 600  * @time:    Timing parameter in ns.
 601  * @cd:      Timing parameter clock domain.
 602  * @name:    Timing parameter name.
 603  * @return:  0 on success, -1 on error.
 604  */
 605 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 606                                int time, enum gpmc_clk_domain cd, const char *name)
 607 {
 608         u32 l;
 609         int ticks, mask, nr_bits;
 610
 611         if (time == 0)
 612                 ticks = 0;
 613         else
 614                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 615         nr_bits = end_bit - st_bit + 1;
 616         mask = (1 << nr_bits) - 1;
 617
 618         if (!max)
 619                 max = mask;
 620
 621         if (ticks > max) {
 622                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 623                        __func__, cs, name, time, ticks, max);
 624
 625                 return -1;
 626         }
 627
 628         l = gpmc_cs_read_reg(cs, reg);
 629 #ifdef CONFIG_OMAP_GPMC_DEBUG
 630         pr_info(
 631                 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 632                cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 633                         (l >> st_bit) & mask, time);
 634 #endif
 635         l &= ~(mask << st_bit);
 636         l |= ticks << st_bit;
 637         gpmc_cs_write_reg(cs, reg, l);
 638
 639         return 0;
 640 }
 641
 642 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
 643         if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
 644             t->field, (cd), #field) < 0)                       \
 645                 return -1
 646
 647 #define GPMC_SET_ONE(reg, st, end, field) \
 648         GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
 649
 650 /**
 651  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 652  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 653  * read  --> don't sample bus too early
 654  * write --> data is longer on bus
 655  *
 656  * Formula:
 657  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 658  *                    / waitmonitoring_ticks)
 659  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 660  * div <= 0 check.
 661  *
 662  * @wait_monitoring: WAITMONITORINGTIME in ns.
 663  * @return:          -1 on failure to scale, else proper divider > 0.
 664  */
 665 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 666 {
 667
 668         int div = gpmc_ns_to_ticks(wait_monitoring);
 669
 670         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 671         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 672
 673         if (div > 4)
 674                 return -1;
 675         if (div <= 0)
 676                 div = 1;
 677
 678         return div;
 679
 680 }
 681
 682 /**
 683  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 684  * @sync_clk: GPMC_CLK period in ps.
 685  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 686  *            Else, returns -1.
 687  */
 688 int gpmc_calc_divider(unsigned int sync_clk)
 689 {
 690         int div = gpmc_ps_to_ticks(sync_clk);
 691
 692         if (div > 4)
 693                 return -1;
 694         if (div <= 0)
 695                 div = 1;
 696
 697         return div;
 698 }
 699
 700 /**
 701  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 702  * @cs:     Chip Select Region.
 703  * @t:      GPMC timing parameters.
 704  * @s:      GPMC timing settings.
 705  * @return: 0 on success, -1 on error.
 706  */
 707 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 708                         const struct gpmc_settings *s)
 709 {
 710         int div;
 711         u32 l;
 712
 713         div = gpmc_calc_divider(t->sync_clk);
 714         if (div < 0)
 715                 return div;
 716
 717         /*
 718          * See if we need to change the divider for waitmonitoringtime.
 719          *
 720          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 721          * pure asynchronous accesses, i.e. both read and write asynchronous.
 722          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 723          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 724          *
 725          * This statement must not change div to scale async WAITMONITORINGTIME
 726          * to protect mixed synchronous and asynchronous accesses.
 727          *
 728          * We raise an error later if WAITMONITORINGTIME does not fit.
 729          */
 730         if (!s->sync_read && !s->sync_write &&
 731             (s->wait_on_read || s->wait_on_write)
 732            ) {
 733
 734                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 735                 if (div < 0) {
 736                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 737                                __func__,
 738                                t->wait_monitoring
 739                                );
 740                         return -1;
 741                 }
 742         }
 743
 744         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 745         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 746         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 747
 748         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 749         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 750         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 751         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 752                 GPMC_SET_ONE(GPMC_CS_CONFIG3,  4,  6, adv_aad_mux_on);
 753                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
 754                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
 755         }
 756
 757         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 758         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 759         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 760                 GPMC_SET_ONE(GPMC_CS_CONFIG4,  4,  6, oe_aad_mux_on);
 761                 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
 762         }
 763         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 764         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 765
 766         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 767         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 768         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 769
 770         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 771
 772         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 773         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 774
 775         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 776                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 777         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 778                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 779
 780         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 781         l &= ~0x03;
 782         l |= (div - 1);
 783         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 784
 785         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 786                             GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 787                             wait_monitoring, GPMC_CD_CLK);
 788         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 789                             GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 790                             clk_activation, GPMC_CD_FCLK);
 791
 792 #ifdef CONFIG_OMAP_GPMC_DEBUG
 793         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 794                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 795 #endif
 796
 797         gpmc_cs_bool_timings(cs, &t->bool_timings);
 798         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 799
 800         return 0;
 801 }
 802
 803 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 804 {
 805         u32 l;
 806         u32 mask;
 807
 808         /*
 809          * Ensure that base address is aligned on a
 810          * boundary equal to or greater than size.
 811          */
 812         if (base & (size - 1))
 813                 return -EINVAL;
 814
 815         base >>= GPMC_CHUNK_SHIFT;
 816         mask = (1 << GPMC_SECTION_SHIFT) - size;
 817         mask >>= GPMC_CHUNK_SHIFT;
 818         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 819
 820         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 821         l &= ~GPMC_CONFIG7_MASK;
 822         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 823         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 824         l |= GPMC_CONFIG7_CSVALID;
 825         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 826
 827         return 0;
 828 }
 829
 830 static void gpmc_cs_enable_mem(int cs)
 831 {
 832         u32 l;
 833
 834         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 835         l |= GPMC_CONFIG7_CSVALID;
 836         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 837 }
 838
 839 static void gpmc_cs_disable_mem(int cs)
 840 {
 841         u32 l;
 842
 843         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 844         l &= ~GPMC_CONFIG7_CSVALID;
 845         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 846 }
 847
 848 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 849 {
 850         u32 l;
 851         u32 mask;
 852
 853         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 854         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 855         mask = (l >> 8) & 0x0f;
 856         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 857 }
 858
 859 static int gpmc_cs_mem_enabled(int cs)
 860 {
 861         u32 l;
 862
 863         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 864         return l & GPMC_CONFIG7_CSVALID;
 865 }
 866
 867 static void gpmc_cs_set_reserved(int cs, int reserved)
 868 {
 869         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 870
 871         gpmc->flags |= GPMC_CS_RESERVED;
 872 }
 873
 874 static bool gpmc_cs_reserved(int cs)
 875 {
 876         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 877
 878         return gpmc->flags & GPMC_CS_RESERVED;
 879 }
 880
 881 static void gpmc_cs_set_name(int cs, const char *name)
 882 {
 883         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 884
 885         gpmc->name = name;
 886 }
 887
 888 static const char *gpmc_cs_get_name(int cs)
 889 {
 890         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 891
 892         return gpmc->name;
 893 }
 894
 895 static unsigned long gpmc_mem_align(unsigned long size)
 896 {
 897         int order;
 898
 899         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 900         order = GPMC_CHUNK_SHIFT - 1;
 901         do {
 902                 size >>= 1;
 903                 order++;
 904         } while (size);
 905         size = 1 << order;
 906         return size;
 907 }
 908
 909 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 910 {
 911         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 912         struct resource *res = &gpmc->mem;
 913         int r;
 914
 915         size = gpmc_mem_align(size);
 916         spin_lock(&gpmc_mem_lock);
 917         res->start = base;
 918         res->end = base + size - 1;
 919         r = request_resource(&gpmc_mem_root, res);
 920         spin_unlock(&gpmc_mem_lock);
 921
 922         return r;
 923 }
 924
 925 static int gpmc_cs_delete_mem(int cs)
 926 {
 927         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 928         struct resource *res = &gpmc->mem;
 929         int r;
 930
 931         spin_lock(&gpmc_mem_lock);
 932         r = release_resource(res);
 933         res->start = 0;
 934         res->end = 0;
 935         spin_unlock(&gpmc_mem_lock);
 936
 937         return r;
 938 }
 939
 940 /**
 941  * gpmc_cs_remap - remaps a chip-select physical base address
 942  * @cs:         chip-select to remap
 943  * @base:       physical base address to re-map chip-select to
 944  *
 945  * Re-maps a chip-select to a new physical base address specified by
 946  * "base". Returns 0 on success and appropriate negative error code
 947  * on failure.
 948  */
 949 static int gpmc_cs_remap(int cs, u32 base)
 950 {
 951         int ret;
 952         u32 old_base, size;
 953
 954         if (cs > gpmc_cs_num) {
 955                 pr_err("%s: requested chip-select is disabled\n", __func__);
 956                 return -ENODEV;
 957         }
 958
 959         /*
 960          * Make sure we ignore any device offsets from the GPMC partition
 961          * allocated for the chip select and that the new base confirms
 962          * to the GPMC 16MB minimum granularity.
 963          */
 964         base &= ~(SZ_16M - 1);
 965
 966         gpmc_cs_get_memconf(cs, &old_base, &size);
 967         if (base == old_base)
 968                 return 0;
 969
 970         ret = gpmc_cs_delete_mem(cs);
 971         if (ret < 0)
 972                 return ret;
 973
 974         ret = gpmc_cs_insert_mem(cs, base, size);
 975         if (ret < 0)
 976                 return ret;
 977
 978         ret = gpmc_cs_set_memconf(cs, base, size);
 979
 980         return ret;
 981 }
 982
 983 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 984 {
 985         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 986         struct resource *res = &gpmc->mem;
 987         int r = -1;
 988
 989         if (cs > gpmc_cs_num) {
 990                 pr_err("%s: requested chip-select is disabled\n", __func__);
 991                 return -ENODEV;
 992         }
 993         size = gpmc_mem_align(size);
 994         if (size > (1 << GPMC_SECTION_SHIFT))
 995                 return -ENOMEM;
 996
 997         spin_lock(&gpmc_mem_lock);
 998         if (gpmc_cs_reserved(cs)) {
 999                 r = -EBUSY;
1000                 goto out;
1001         }
1002         if (gpmc_cs_mem_enabled(cs))
1003                 r = adjust_resource(res, res->start & ~(size - 1), size);
1004         if (r < 0)
1005                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1006                                       size, NULL, NULL);
1007         if (r < 0)
1008                 goto out;
1009
1010         /* Disable CS while changing base address and size mask */
1011         gpmc_cs_disable_mem(cs);
1012
1013         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1014         if (r < 0) {
1015                 release_resource(res);
1016                 goto out;
1017         }
1018
1019         /* Enable CS */
1020         gpmc_cs_enable_mem(cs);
1021         *base = res->start;
1022         gpmc_cs_set_reserved(cs, 1);
1023 out:
1024         spin_unlock(&gpmc_mem_lock);
1025         return r;
1026 }
1027 EXPORT_SYMBOL(gpmc_cs_request);
1028
1029 void gpmc_cs_free(int cs)
1030 {
1031         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1032         struct resource *res = &gpmc->mem;
1033
1034         spin_lock(&gpmc_mem_lock);
1035         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1036                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1037                 BUG();
1038                 spin_unlock(&gpmc_mem_lock);
1039                 return;
1040         }
1041         gpmc_cs_disable_mem(cs);
1042         if (res->flags)
1043                 release_resource(res);
1044         gpmc_cs_set_reserved(cs, 0);
1045         spin_unlock(&gpmc_mem_lock);
1046 }
1047 EXPORT_SYMBOL(gpmc_cs_free);
1048
1049 /**
1050  * gpmc_configure - write request to configure gpmc
1051  * @cmd: command type
1052  * @wval: value to write
1053  * @return status of the operation
1054  */
1055 int gpmc_configure(int cmd, int wval)
1056 {
1057         u32 regval;
1058
1059         switch (cmd) {
1060         case GPMC_CONFIG_WP:
1061                 regval = gpmc_read_reg(GPMC_CONFIG);
1062                 if (wval)
1063                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1064                 else
1065                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1066                 gpmc_write_reg(GPMC_CONFIG, regval);
1067                 break;
1068
1069         default:
1070                 pr_err("%s: command not supported\n", __func__);
1071                 return -EINVAL;
1072         }
1073
1074         return 0;
1075 }
1076 EXPORT_SYMBOL(gpmc_configure);
1077
1078 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
1079 {
1080         int i;
1081
1082         reg->gpmc_status = NULL;        /* deprecated */
1083         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1084                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1085         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1086                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1087         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1088                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1089         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1090         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1091         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1092         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1093         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1094         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1095         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1096         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1097
1098         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1099                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1100                                            GPMC_BCH_SIZE * i;
1101                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1102                                            GPMC_BCH_SIZE * i;
1103                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1104                                            GPMC_BCH_SIZE * i;
1105                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1106                                            GPMC_BCH_SIZE * i;
1107                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1108                                            i * GPMC_BCH_SIZE;
1109                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1110                                            i * GPMC_BCH_SIZE;
1111                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1112                                            i * GPMC_BCH_SIZE;
1113         }
1114 }
1115
1116 static bool gpmc_nand_writebuffer_empty(void)
1117 {
1118         if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1119                 return true;
1120
1121         return false;
1122 }
1123
1124 static struct gpmc_nand_ops nand_ops = {
1125         .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1126 };
1127
1128 /**
1129  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1130  * @regs: the GPMC NAND register map exclusive for NAND use.
1131  * @cs: GPMC chip select number on which the NAND sits. The
1132  *      register map returned will be specific to this chip select.
1133  *
1134  * Returns NULL on error e.g. invalid cs.
1135  */
1136 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1137 {
1138         if (cs >= gpmc_cs_num)
1139                 return NULL;
1140
1141         gpmc_update_nand_reg(reg, cs);
1142
1143         return &nand_ops;
1144 }
1145 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1146
1147 int gpmc_get_client_irq(unsigned irq_config)
1148 {
1149         if (!gpmc_irq_domain) {
1150                 pr_warn("%s called before GPMC IRQ domain available\n",
1151                         __func__);
1152                 return 0;
1153         }
1154
1155         /* we restrict this to NAND IRQs only */
1156         if (irq_config >= GPMC_NR_NAND_IRQS)
1157                 return 0;
1158
1159         return irq_create_mapping(gpmc_irq_domain, irq_config);
1160 }
1161
1162 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1163 {
1164         u32 regval;
1165
1166         /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1167         if (hwirq >= GPMC_NR_NAND_IRQS)
1168                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1169
1170         regval = gpmc_read_reg(GPMC_IRQENABLE);
1171         if (endis)
1172                 regval |= BIT(hwirq);
1173         else
1174                 regval &= ~BIT(hwirq);
1175         gpmc_write_reg(GPMC_IRQENABLE, regval);
1176
1177         return 0;
1178 }
1179
1180 static void gpmc_irq_disable(struct irq_data *p)
1181 {
1182         gpmc_irq_endis(p->hwirq, false);
1183 }
1184
1185 static void gpmc_irq_enable(struct irq_data *p)
1186 {
1187         gpmc_irq_endis(p->hwirq, true);
1188 }
1189
1190 static void gpmc_irq_mask(struct irq_data *d)
1191 {
1192         gpmc_irq_endis(d->hwirq, false);
1193 }
1194
1195 static void gpmc_irq_unmask(struct irq_data *d)
1196 {
1197         gpmc_irq_endis(d->hwirq, true);
1198 }
1199
1200 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1201 {
1202         u32 regval;
1203
1204         /* NAND IRQs polarity is not configurable */
1205         if (hwirq < GPMC_NR_NAND_IRQS)
1206                 return;
1207
1208         /* WAITPIN starts at BIT 8 */
1209         hwirq += 8 - GPMC_NR_NAND_IRQS;
1210
1211         regval = gpmc_read_reg(GPMC_CONFIG);
1212         if (rising_edge)
1213                 regval &= ~BIT(hwirq);
1214         else
1215                 regval |= BIT(hwirq);
1216
1217         gpmc_write_reg(GPMC_CONFIG, regval);
1218 }
1219
1220 static void gpmc_irq_ack(struct irq_data *d)
1221 {
1222         unsigned int hwirq = d->hwirq;
1223
1224         /* skip reserved bits */
1225         if (hwirq >= GPMC_NR_NAND_IRQS)
1226                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1227
1228         /* Setting bit to 1 clears (or Acks) the interrupt */
1229         gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1230 }
1231
1232 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1233 {
1234         /* can't set type for NAND IRQs */
1235         if (d->hwirq < GPMC_NR_NAND_IRQS)
1236                 return -EINVAL;
1237
1238         /* We can support either rising or falling edge at a time */
1239         if (trigger == IRQ_TYPE_EDGE_FALLING)
1240                 gpmc_irq_edge_config(d->hwirq, false);
1241         else if (trigger == IRQ_TYPE_EDGE_RISING)
1242                 gpmc_irq_edge_config(d->hwirq, true);
1243         else
1244                 return -EINVAL;
1245
1246         return 0;
1247 }
1248
1249 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1250                         irq_hw_number_t hw)
1251 {
1252         struct gpmc_device *gpmc = d->host_data;
1253
1254         irq_set_chip_data(virq, gpmc);
1255         if (hw < GPMC_NR_NAND_IRQS) {
1256                 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1257                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1258                                          handle_simple_irq);
1259         } else {
1260                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1261                                          handle_edge_irq);
1262         }
1263
1264         return 0;
1265 }
1266
1267 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1268         .map    = gpmc_irq_map,
1269         .xlate  = irq_domain_xlate_twocell,
1270 };
1271
1272 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1273 {
1274         int hwirq, virq;
1275         u32 regval, regvalx;
1276         struct gpmc_device *gpmc = data;
1277
1278         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1279         regvalx = regval;
1280
1281         if (!regval)
1282                 return IRQ_NONE;
1283
1284         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1285                 /* skip reserved status bits */
1286                 if (hwirq == GPMC_NR_NAND_IRQS)
1287                         regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1288
1289                 if (regvalx & BIT(hwirq)) {
1290                         virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1291                         if (!virq) {
1292                                 dev_warn(gpmc->dev,
1293                                          "spurious irq detected hwirq %d, virq %d\n",
1294                                          hwirq, virq);
1295                         }
1296
1297                         generic_handle_irq(virq);
1298                 }
1299         }
1300
1301         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1302
1303         return IRQ_HANDLED;
1304 }
1305
1306 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1307 {
1308         u32 regval;
1309         int rc;
1310
1311         /* Disable interrupts */
1312         gpmc_write_reg(GPMC_IRQENABLE, 0);
1313
1314         /* clear interrupts */
1315         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1316         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1317
1318         gpmc->irq_chip.name = "gpmc";
1319         gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1320         gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1321         gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1322         gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1323         gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1324         gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1325
1326         gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1327                                                 gpmc->nirqs,
1328                                                 &gpmc_irq_domain_ops,
1329                                                 gpmc);
1330         if (!gpmc_irq_domain) {
1331                 dev_err(gpmc->dev, "IRQ domain add failed\n");
1332                 return -ENODEV;
1333         }
1334
1335         rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1336         if (rc) {
1337                 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1338                         gpmc->irq, rc);
1339                 irq_domain_remove(gpmc_irq_domain);
1340                 gpmc_irq_domain = NULL;
1341         }
1342
1343         return rc;
1344 }
1345
1346 static int gpmc_free_irq(struct gpmc_device *gpmc)
1347 {
1348         int hwirq;
1349
1350         free_irq(gpmc->irq, gpmc);
1351
1352         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1353                 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1354
1355         irq_domain_remove(gpmc_irq_domain);
1356         gpmc_irq_domain = NULL;
1357
1358         return 0;
1359 }
1360
1361 static void gpmc_mem_exit(void)
1362 {
1363         int cs;
1364
1365         for (cs = 0; cs < gpmc_cs_num; cs++) {
1366                 if (!gpmc_cs_mem_enabled(cs))
1367                         continue;
1368                 gpmc_cs_delete_mem(cs);
1369         }
1370
1371 }
1372
1373 static void gpmc_mem_init(void)
1374 {
1375         int cs;
1376
1377         gpmc_mem_root.start = GPMC_MEM_START;
1378         gpmc_mem_root.end = GPMC_MEM_END;
1379
1380         /* Reserve all regions that has been set up by bootloader */
1381         for (cs = 0; cs < gpmc_cs_num; cs++) {
1382                 u32 base, size;
1383
1384                 if (!gpmc_cs_mem_enabled(cs))
1385                         continue;
1386                 gpmc_cs_get_memconf(cs, &base, &size);
1387                 if (gpmc_cs_insert_mem(cs, base, size)) {
1388                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1389                                 __func__, cs, base, base + size);
1390                         gpmc_cs_disable_mem(cs);
1391                 }
1392         }
1393 }
1394
1395 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1396 {
1397         u32 temp;
1398         int div;
1399
1400         div = gpmc_calc_divider(sync_clk);
1401         temp = gpmc_ps_to_ticks(time_ps);
1402         temp = (temp + div - 1) / div;
1403         return gpmc_ticks_to_ps(temp * div);
1404 }
1405
1406 /* XXX: can the cycles be avoided ? */
1407 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1408                                        struct gpmc_device_timings *dev_t,
1409                                        bool mux)
1410 {
1411         u32 temp;
1412
1413         /* adv_rd_off */
1414         temp = dev_t->t_avdp_r;
1415         /* XXX: mux check required ? */
1416         if (mux) {
1417                 /* XXX: t_avdp not to be required for sync, only added for tusb
1418                  * this indirectly necessitates requirement of t_avdp_r and
1419                  * t_avdp_w instead of having a single t_avdp
1420                  */
1421                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1422                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1423         }
1424         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1425
1426         /* oe_on */
1427         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1428         if (mux) {
1429                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1430                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1431                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1432         }
1433         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1434
1435         /* access */
1436         /* XXX: any scope for improvement ?, by combining oe_on
1437          * and clk_activation, need to check whether
1438          * access = clk_activation + round to sync clk ?
1439          */
1440         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1441         temp += gpmc_t->clk_activation;
1442         if (dev_t->cyc_oe)
1443                 temp = max_t(u32, temp, gpmc_t->oe_on +
1444                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1445         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1446
1447         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1448         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1449
1450         /* rd_cycle */
1451         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1452         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1453                                                         gpmc_t->access;
1454         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1455         if (dev_t->t_ce_rdyz)
1456                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1457         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1458
1459         return 0;
1460 }
1461
1462 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1463                                         struct gpmc_device_timings *dev_t,
1464                                         bool mux)
1465 {
1466         u32 temp;
1467
1468         /* adv_wr_off */
1469         temp = dev_t->t_avdp_w;
1470         if (mux) {
1471                 temp = max_t(u32, temp,
1472                         gpmc_t->clk_activation + dev_t->t_avdh);
1473                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1474         }
1475         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1476
1477         /* wr_data_mux_bus */
1478         temp = max_t(u32, dev_t->t_weasu,
1479                         gpmc_t->clk_activation + dev_t->t_rdyo);
1480         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1481          * and in that case remember to handle we_on properly
1482          */
1483         if (mux) {
1484                 temp = max_t(u32, temp,
1485                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1486                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1487                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1488         }
1489         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1490
1491         /* we_on */
1492         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1493                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1494         else
1495                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1496
1497         /* wr_access */
1498         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1499         gpmc_t->wr_access = gpmc_t->access;
1500
1501         /* we_off */
1502         temp = gpmc_t->we_on + dev_t->t_wpl;
1503         temp = max_t(u32, temp,
1504                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1505         temp = max_t(u32, temp,
1506                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1507         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1508
1509         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1510                                                         dev_t->t_wph);
1511
1512         /* wr_cycle */
1513         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1514         temp += gpmc_t->wr_access;
1515         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1516         if (dev_t->t_ce_rdyz)
1517                 temp = max_t(u32, temp,
1518                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1519         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1520
1521         return 0;
1522 }
1523
1524 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1525                                         struct gpmc_device_timings *dev_t,
1526                                         bool mux)
1527 {
1528         u32 temp;
1529
1530         /* adv_rd_off */
1531         temp = dev_t->t_avdp_r;
1532         if (mux)
1533                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1534         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1535
1536         /* oe_on */
1537         temp = dev_t->t_oeasu;
1538         if (mux)
1539                 temp = max_t(u32, temp,
1540                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1541         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1542
1543         /* access */
1544         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1545                                 gpmc_t->oe_on + dev_t->t_oe);
1546         temp = max_t(u32, temp,
1547                                 gpmc_t->cs_on + dev_t->t_ce);
1548         temp = max_t(u32, temp,
1549                                 gpmc_t->adv_on + dev_t->t_aa);
1550         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1551
1552         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1553         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1554
1555         /* rd_cycle */
1556         temp = max_t(u32, dev_t->t_rd_cycle,
1557                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1558         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1559         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1560
1561         return 0;
1562 }
1563
1564 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1565                                          struct gpmc_device_timings *dev_t,
1566                                          bool mux)
1567 {
1568         u32 temp;
1569
1570         /* adv_wr_off */
1571         temp = dev_t->t_avdp_w;
1572         if (mux)
1573                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1574         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1575
1576         /* wr_data_mux_bus */
1577         temp = dev_t->t_weasu;
1578         if (mux) {
1579                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1580                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1581                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1582         }
1583         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1584
1585         /* we_on */
1586         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1587                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1588         else
1589                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1590
1591         /* we_off */
1592         temp = gpmc_t->we_on + dev_t->t_wpl;
1593         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1594
1595         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1596                                                         dev_t->t_wph);
1597
1598         /* wr_cycle */
1599         temp = max_t(u32, dev_t->t_wr_cycle,
1600                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1601         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1602
1603         return 0;
1604 }
1605
1606 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1607                         struct gpmc_device_timings *dev_t)
1608 {
1609         u32 temp;
1610
1611         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1612                                                 gpmc_get_fclk_period();
1613
1614         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1615                                         dev_t->t_bacc,
1616                                         gpmc_t->sync_clk);
1617
1618         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1619         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1620
1621         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1622                 return 0;
1623
1624         if (dev_t->ce_xdelay)
1625                 gpmc_t->bool_timings.cs_extra_delay = true;
1626         if (dev_t->avd_xdelay)
1627                 gpmc_t->bool_timings.adv_extra_delay = true;
1628         if (dev_t->oe_xdelay)
1629                 gpmc_t->bool_timings.oe_extra_delay = true;
1630         if (dev_t->we_xdelay)
1631                 gpmc_t->bool_timings.we_extra_delay = true;
1632
1633         return 0;
1634 }
1635
1636 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1637                                     struct gpmc_device_timings *dev_t,
1638                                     bool sync)
1639 {
1640         u32 temp;
1641
1642         /* cs_on */
1643         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1644
1645         /* adv_on */
1646         temp = dev_t->t_avdasu;
1647         if (dev_t->t_ce_avd)
1648                 temp = max_t(u32, temp,
1649                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1650         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1651
1652         if (sync)
1653                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1654
1655         return 0;
1656 }
1657
1658 /* TODO: remove this function once all peripherals are confirmed to
1659  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1660  * has to be modified to handle timings in ps instead of ns
1661 */
1662 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1663 {
1664         t->cs_on /= 1000;
1665         t->cs_rd_off /= 1000;
1666         t->cs_wr_off /= 1000;
1667         t->adv_on /= 1000;
1668         t->adv_rd_off /= 1000;
1669         t->adv_wr_off /= 1000;
1670         t->we_on /= 1000;
1671         t->we_off /= 1000;
1672         t->oe_on /= 1000;
1673         t->oe_off /= 1000;
1674         t->page_burst_access /= 1000;
1675         t->access /= 1000;
1676         t->rd_cycle /= 1000;
1677         t->wr_cycle /= 1000;
1678         t->bus_turnaround /= 1000;
1679         t->cycle2cycle_delay /= 1000;
1680         t->wait_monitoring /= 1000;
1681         t->clk_activation /= 1000;
1682         t->wr_access /= 1000;
1683         t->wr_data_mux_bus /= 1000;
1684 }
1685
1686 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1687                       struct gpmc_settings *gpmc_s,
1688                       struct gpmc_device_timings *dev_t)
1689 {
1690         bool mux = false, sync = false;
1691
1692         if (gpmc_s) {
1693                 mux = gpmc_s->mux_add_data ? true : false;
1694                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1695         }
1696
1697         memset(gpmc_t, 0, sizeof(*gpmc_t));
1698
1699         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1700
1701         if (gpmc_s && gpmc_s->sync_read)
1702                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1703         else
1704                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1705
1706         if (gpmc_s && gpmc_s->sync_write)
1707                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1708         else
1709                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1710
1711         /* TODO: remove, see function definition */
1712         gpmc_convert_ps_to_ns(gpmc_t);
1713
1714         return 0;
1715 }
1716
1717 /**
1718  * gpmc_cs_program_settings - programs non-timing related settings
1719  * @cs:         GPMC chip-select to program
1720  * @p:          pointer to GPMC settings structure
1721  *
1722  * Programs non-timing related settings for a GPMC chip-select, such as
1723  * bus-width, burst configuration, etc. Function should be called once
1724  * for each chip-select that is being used and must be called before
1725  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1726  * register will be initialised to zero by this function. Returns 0 on
1727  * success and appropriate negative error code on failure.
1728  */
1729 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1730 {
1731         u32 config1;
1732
1733         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1734                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1735                 return -EINVAL;
1736         }
1737
1738         /* Address-data multiplexing not supported for NAND devices */
1739         if (p->device_nand && p->mux_add_data) {
1740                 pr_err("%s: invalid configuration!\n", __func__);
1741                 return -EINVAL;
1742         }
1743
1744         if ((p->mux_add_data > GPMC_MUX_AD) ||
1745             ((p->mux_add_data == GPMC_MUX_AAD) &&
1746              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1747                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1748                 return -EINVAL;
1749         }
1750
1751         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1752         if (p->burst_read || p->burst_write) {
1753                 switch (p->burst_len) {
1754                 case GPMC_BURST_4:
1755                 case GPMC_BURST_8:
1756                 case GPMC_BURST_16:
1757                         break;
1758                 default:
1759                         pr_err("%s: invalid page/burst-length (%d)\n",
1760                                __func__, p->burst_len);
1761                         return -EINVAL;
1762                 }
1763         }
1764
1765         if (p->wait_pin > gpmc_nr_waitpins) {
1766                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1767                 return -EINVAL;
1768         }
1769
1770         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1771
1772         if (p->sync_read)
1773                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1774         if (p->sync_write)
1775                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1776         if (p->wait_on_read)
1777                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1778         if (p->wait_on_write)
1779                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1780         if (p->wait_on_read || p->wait_on_write)
1781                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1782         if (p->device_nand)
1783                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1784         if (p->mux_add_data)
1785                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1786         if (p->burst_read)
1787                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1788         if (p->burst_write)
1789                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1790         if (p->burst_read || p->burst_write) {
1791                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1792                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1793         }
1794
1795         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1796
1797         return 0;
1798 }
1799
1800 #ifdef CONFIG_OF
1801 static const struct of_device_id gpmc_dt_ids[] = {
1802         { .compatible = "ti,omap2420-gpmc" },
1803         { .compatible = "ti,omap2430-gpmc" },
1804         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1805         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1806         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1807         { }
1808 };
1809
1810 /**
1811  * gpmc_read_settings_dt - read gpmc settings from device-tree
1812  * @np:         pointer to device-tree node for a gpmc child device
1813  * @p:          pointer to gpmc settings structure
1814  *
1815  * Reads the GPMC settings for a GPMC child device from device-tree and
1816  * stores them in the GPMC settings structure passed. The GPMC settings
1817  * structure is initialised to zero by this function and so any
1818  * previously stored settings will be cleared.
1819  */
1820 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1821 {
1822         memset(p, 0, sizeof(struct gpmc_settings));
1823
1824         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1825         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1826         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1827         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1828
1829         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1830                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1831                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1832                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1833                 if (!p->burst_read && !p->burst_write)
1834                         pr_warn("%s: page/burst-length set but not used!\n",
1835                                 __func__);
1836         }
1837
1838         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1839                 p->wait_on_read = of_property_read_bool(np,
1840                                                         "gpmc,wait-on-read");
1841                 p->wait_on_write = of_property_read_bool(np,
1842                                                          "gpmc,wait-on-write");
1843                 if (!p->wait_on_read && !p->wait_on_write)
1844                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1845                                  __func__);
1846         }
1847 }
1848
1849 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1850                                                 struct gpmc_timings *gpmc_t)
1851 {
1852         struct gpmc_bool_timings *p;
1853
1854         if (!np || !gpmc_t)
1855                 return;
1856
1857         memset(gpmc_t, 0, sizeof(*gpmc_t));
1858
1859         /* minimum clock period for syncronous mode */
1860         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1861
1862         /* chip select timtings */
1863         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1864         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1865         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1866
1867         /* ADV signal timings */
1868         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1869         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1870         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1871         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1872                              &gpmc_t->adv_aad_mux_on);
1873         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1874                              &gpmc_t->adv_aad_mux_rd_off);
1875         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1876                              &gpmc_t->adv_aad_mux_wr_off);
1877
1878         /* WE signal timings */
1879         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1880         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1881
1882         /* OE signal timings */
1883         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1884         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1885         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1886                              &gpmc_t->oe_aad_mux_on);
1887         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1888                              &gpmc_t->oe_aad_mux_off);
1889
1890         /* access and cycle timings */
1891         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1892                              &gpmc_t->page_burst_access);
1893         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1894         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1895         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1896         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1897                              &gpmc_t->bus_turnaround);
1898         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1899                              &gpmc_t->cycle2cycle_delay);
1900         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1901                              &gpmc_t->wait_monitoring);
1902         of_property_read_u32(np, "gpmc,clk-activation-ns",
1903                              &gpmc_t->clk_activation);
1904
1905         /* only applicable to OMAP3+ */
1906         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1907         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1908                              &gpmc_t->wr_data_mux_bus);
1909
1910         /* bool timing parameters */
1911         p = &gpmc_t->bool_timings;
1912
1913         p->cycle2cyclediffcsen =
1914                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1915         p->cycle2cyclesamecsen =
1916                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1917         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1918         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1919         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1920         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1921         p->time_para_granularity =
1922                 of_property_read_bool(np, "gpmc,time-para-granularity");
1923 }
1924
1925 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1926 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1927                                  struct device_node *child)
1928 {
1929         u32 val;
1930         struct omap_onenand_platform_data *gpmc_onenand_data;
1931
1932         if (of_property_read_u32(child, "reg", &val) < 0) {
1933                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1934                         child->full_name);
1935                 return -ENODEV;
1936         }
1937
1938         gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1939                                          GFP_KERNEL);
1940         if (!gpmc_onenand_data)
1941                 return -ENOMEM;
1942
1943         gpmc_onenand_data->cs = val;
1944         gpmc_onenand_data->of_node = child;
1945         gpmc_onenand_data->dma_channel = -1;
1946
1947         if (!of_property_read_u32(child, "dma-channel", &val))
1948                 gpmc_onenand_data->dma_channel = val;
1949
1950         gpmc_onenand_init(gpmc_onenand_data);
1951
1952         return 0;
1953 }
1954 #else
1955 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1956                                     struct device_node *child)
1957 {
1958         return 0;
1959 }
1960 #endif
1961
1962 /**
1963  * gpmc_probe_generic_child - configures the gpmc for a child device
1964  * @pdev:       pointer to gpmc platform device
1965  * @child:      pointer to device-tree node for child device
1966  *
1967  * Allocates and configures a GPMC chip-select for a child device.
1968  * Returns 0 on success and appropriate negative error code on failure.
1969  */
1970 static int gpmc_probe_generic_child(struct platform_device *pdev,
1971                                 struct device_node *child)
1972 {
1973         struct gpmc_settings gpmc_s;
1974         struct gpmc_timings gpmc_t;
1975         struct resource res;
1976         unsigned long base;
1977         const char *name;
1978         int ret, cs;
1979         u32 val;
1980         struct gpio_desc *waitpin_desc = NULL;
1981         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
1982
1983         if (of_property_read_u32(child, "reg", &cs) < 0) {
1984                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1985                         child->full_name);
1986                 return -ENODEV;
1987         }
1988
1989         if (of_address_to_resource(child, 0, &res) < 0) {
1990                 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1991                         child->full_name);
1992                 return -ENODEV;
1993         }
1994
1995         /*
1996          * Check if we have multiple instances of the same device
1997          * on a single chip select. If so, use the already initialized
1998          * timings.
1999          */
2000         name = gpmc_cs_get_name(cs);
2001         if (name && child->name && of_node_cmp(child->name, name) == 0)
2002                         goto no_timings;
2003
2004         ret = gpmc_cs_request(cs, resource_size(&res), &base);
2005         if (ret < 0) {
2006                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2007                 return ret;
2008         }
2009         gpmc_cs_set_name(cs, child->name);
2010
2011         gpmc_read_settings_dt(child, &gpmc_s);
2012         gpmc_read_timings_dt(child, &gpmc_t);
2013
2014         /*
2015          * For some GPMC devices we still need to rely on the bootloader
2016          * timings because the devices can be connected via FPGA.
2017          * REVISIT: Add timing support from slls644g.pdf.
2018          */
2019         if (!gpmc_t.cs_rd_off) {
2020                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2021                         cs);
2022                 gpmc_cs_show_timings(cs,
2023                                      "please add GPMC bootloader timings to .dts");
2024                 goto no_timings;
2025         }
2026
2027         /* CS must be disabled while making changes to gpmc configuration */
2028         gpmc_cs_disable_mem(cs);
2029
2030         /*
2031          * FIXME: gpmc_cs_request() will map the CS to an arbitary
2032          * location in the gpmc address space. When booting with
2033          * device-tree we want the NOR flash to be mapped to the
2034          * location specified in the device-tree blob. So remap the
2035          * CS to this location. Once DT migration is complete should
2036          * just make gpmc_cs_request() map a specific address.
2037          */
2038         ret = gpmc_cs_remap(cs, res.start);
2039         if (ret < 0) {
2040                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2041                         cs, &res.start);
2042                 if (res.start < GPMC_MEM_START) {
2043                         dev_info(&pdev->dev,
2044                                  "GPMC CS %d start cannot be lesser than 0x%x\n",
2045                                  cs, GPMC_MEM_START);
2046                 } else if (res.end > GPMC_MEM_END) {
2047                         dev_info(&pdev->dev,
2048                                  "GPMC CS %d end cannot be greater than 0x%x\n",
2049                                  cs, GPMC_MEM_END);
2050                 }
2051                 goto err;
2052         }
2053
2054         if (of_node_cmp(child->name, "nand") == 0) {
2055                 /* Warn about older DT blobs with no compatible property */
2056                 if (!of_property_read_bool(child, "compatible")) {
2057                         dev_warn(&pdev->dev,
2058                                  "Incompatible NAND node: missing compatible");
2059                         ret = -EINVAL;
2060                         goto err;
2061                 }
2062         }
2063
2064         if (of_device_is_compatible(child, "ti,omap2-nand")) {
2065                 /* NAND specific setup */
2066                 val = 8;
2067                 of_property_read_u32(child, "nand-bus-width", &val);
2068                 switch (val) {
2069                 case 8:
2070                         gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2071                         break;
2072                 case 16:
2073                         gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2074                         break;
2075                 default:
2076                         dev_err(&pdev->dev, "%s: invalid 'nand-bus-width'\n",
2077                                 child->name);
2078                         ret = -EINVAL;
2079                         goto err;
2080                 }
2081
2082                 /* disable write protect */
2083                 gpmc_configure(GPMC_CONFIG_WP, 0);
2084                 gpmc_s.device_nand = true;
2085         } else {
2086                 ret = of_property_read_u32(child, "bank-width",
2087                                            &gpmc_s.device_width);
2088                 if (ret < 0)
2089                         goto err;
2090         }
2091
2092         /* Reserve wait pin if it is required and valid */
2093         if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2094                 unsigned int wait_pin = gpmc_s.wait_pin;
2095
2096                 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2097                                                          wait_pin, "WAITPIN");
2098                 if (IS_ERR(waitpin_desc)) {
2099                         dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2100                         ret = PTR_ERR(waitpin_desc);
2101                         goto err;
2102                 }
2103         }
2104
2105         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2106
2107         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2108         if (ret < 0)
2109                 goto err_cs;
2110
2111         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2112         if (ret) {
2113                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2114                         child->name);
2115                 goto err_cs;
2116         }
2117
2118         /* Clear limited address i.e. enable A26-A11 */
2119         val = gpmc_read_reg(GPMC_CONFIG);
2120         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2121         gpmc_write_reg(GPMC_CONFIG, val);
2122
2123         /* Enable CS region */
2124         gpmc_cs_enable_mem(cs);
2125
2126 no_timings:
2127
2128         /* create platform device, NULL on error or when disabled */
2129         if (!of_platform_device_create(child, NULL, &pdev->dev))
2130                 goto err_child_fail;
2131
2132         /* is child a common bus? */
2133         if (of_match_node(of_default_bus_match_table, child))
2134                 /* create children and other common bus children */
2135                 if (of_platform_default_populate(child, NULL, &pdev->dev))
2136                         goto err_child_fail;
2137
2138         return 0;
2139
2140 err_child_fail:
2141
2142         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2143         ret = -ENODEV;
2144
2145 err_cs:
2146         if (waitpin_desc)
2147                 gpiochip_free_own_desc(waitpin_desc);
2148
2149 err:
2150         gpmc_cs_free(cs);
2151
2152         return ret;
2153 }
2154
2155 static int gpmc_probe_dt(struct platform_device *pdev)
2156 {
2157         int ret;
2158         const struct of_device_id *of_id =
2159                 of_match_device(gpmc_dt_ids, &pdev->dev);
2160
2161         if (!of_id)
2162                 return 0;
2163
2164         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2165                                    &gpmc_cs_num);
2166         if (ret < 0) {
2167                 pr_err("%s: number of chip-selects not defined\n", __func__);
2168                 return ret;
2169         } else if (gpmc_cs_num < 1) {
2170                 pr_err("%s: all chip-selects are disabled\n", __func__);
2171                 return -EINVAL;
2172         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2173                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2174                                          __func__, GPMC_CS_NUM);
2175                 return -EINVAL;
2176         }
2177
2178         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2179                                    &gpmc_nr_waitpins);
2180         if (ret < 0) {
2181                 pr_err("%s: number of wait pins not found!\n", __func__);
2182                 return ret;
2183         }
2184
2185         return 0;
2186 }
2187
2188 static void gpmc_probe_dt_children(struct platform_device *pdev)
2189 {
2190         int ret;
2191         struct device_node *child;
2192
2193         for_each_available_child_of_node(pdev->dev.of_node, child) {
2194
2195                 if (!child->name)
2196                         continue;
2197
2198                 if (of_node_cmp(child->name, "onenand") == 0)
2199                         ret = gpmc_probe_onenand_child(pdev, child);
2200                 else
2201                         ret = gpmc_probe_generic_child(pdev, child);
2202
2203                 if (ret) {
2204                         dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n",
2205                                 child->name, ret);
2206                 }
2207         }
2208 }
2209 #else
2210 static int gpmc_probe_dt(struct platform_device *pdev)
2211 {
2212         return 0;
2213 }
2214
2215 static void gpmc_probe_dt_children(struct platform_device *pdev)
2216 {
2217 }
2218 #endif /* CONFIG_OF */
2219
2220 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2221 {
2222         return 1;       /* we're input only */
2223 }
2224
2225 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2226                                      unsigned int offset)
2227 {
2228         return 0;       /* we're input only */
2229 }
2230
2231 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2232                                       unsigned int offset, int value)
2233 {
2234         return -EINVAL; /* we're input only */
2235 }
2236
2237 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2238                           int value)
2239 {
2240 }
2241
2242 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2243 {
2244         u32 reg;
2245
2246         offset += 8;
2247
2248         reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2249
2250         return !!reg;
2251 }
2252
2253 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2254 {
2255         int ret;
2256
2257         gpmc->gpio_chip.parent = gpmc->dev;
2258         gpmc->gpio_chip.owner = THIS_MODULE;
2259         gpmc->gpio_chip.label = DEVICE_NAME;
2260         gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2261         gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2262         gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2263         gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2264         gpmc->gpio_chip.set = gpmc_gpio_set;
2265         gpmc->gpio_chip.get = gpmc_gpio_get;
2266         gpmc->gpio_chip.base = -1;
2267
2268         ret = gpiochip_add(&gpmc->gpio_chip);
2269         if (ret < 0) {
2270                 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2271                 return ret;
2272         }
2273
2274         return 0;
2275 }
2276
2277 static void gpmc_gpio_exit(struct gpmc_device *gpmc)
2278 {
2279         gpiochip_remove(&gpmc->gpio_chip);
2280 }
2281
2282 static int gpmc_probe(struct platform_device *pdev)
2283 {
2284         int rc;
2285         u32 l;
2286         struct resource *res;
2287         struct gpmc_device *gpmc;
2288
2289         gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2290         if (!gpmc)
2291                 return -ENOMEM;
2292
2293         gpmc->dev = &pdev->dev;
2294         platform_set_drvdata(pdev, gpmc);
2295
2296         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2297         if (res == NULL)
2298                 return -ENOENT;
2299
2300         phys_base = res->start;
2301         mem_size = resource_size(res);
2302
2303         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2304         if (IS_ERR(gpmc_base))
2305                 return PTR_ERR(gpmc_base);
2306
2307         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2308         if (!res) {
2309                 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2310                 return -ENOENT;
2311         }
2312
2313         gpmc->irq = res->start;
2314
2315         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2316         if (IS_ERR(gpmc_l3_clk)) {
2317                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2318                 return PTR_ERR(gpmc_l3_clk);
2319         }
2320
2321         if (!clk_get_rate(gpmc_l3_clk)) {
2322                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2323                 return -EINVAL;
2324         }
2325
2326         if (pdev->dev.of_node) {
2327                 rc = gpmc_probe_dt(pdev);
2328                 if (rc)
2329                         return rc;
2330         } else {
2331                 gpmc_cs_num = GPMC_CS_NUM;
2332                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2333         }
2334
2335         pm_runtime_enable(&pdev->dev);
2336         pm_runtime_get_sync(&pdev->dev);
2337
2338         l = gpmc_read_reg(GPMC_REVISION);
2339
2340         /*
2341          * FIXME: Once device-tree migration is complete the below flags
2342          * should be populated based upon the device-tree compatible
2343          * string. For now just use the IP revision. OMAP3+ devices have
2344          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2345          * devices support the addr-addr-data multiplex protocol.
2346          *
2347          * GPMC IP revisions:
2348          * - OMAP24xx                   = 2.0
2349          * - OMAP3xxx                   = 5.0
2350          * - OMAP44xx/54xx/AM335x       = 6.0
2351          */
2352         if (GPMC_REVISION_MAJOR(l) > 0x4)
2353                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2354         if (GPMC_REVISION_MAJOR(l) > 0x5)
2355                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2356         dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2357                  GPMC_REVISION_MINOR(l));
2358
2359         gpmc_mem_init();
2360         rc = gpmc_gpio_init(gpmc);
2361         if (rc)
2362                 goto gpio_init_failed;
2363
2364         gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2365         rc = gpmc_setup_irq(gpmc);
2366         if (rc) {
2367                 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2368                 goto setup_irq_failed;
2369         }
2370
2371         gpmc_probe_dt_children(pdev);
2372
2373         return 0;
2374
2375 setup_irq_failed:
2376         gpmc_gpio_exit(gpmc);
2377 gpio_init_failed:
2378         gpmc_mem_exit();
2379         pm_runtime_put_sync(&pdev->dev);
2380         pm_runtime_disable(&pdev->dev);
2381
2382         return rc;
2383 }
2384
2385 static int gpmc_remove(struct platform_device *pdev)
2386 {
2387         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2388
2389         gpmc_free_irq(gpmc);
2390         gpmc_gpio_exit(gpmc);
2391         gpmc_mem_exit();
2392         pm_runtime_put_sync(&pdev->dev);
2393         pm_runtime_disable(&pdev->dev);
2394
2395         return 0;
2396 }
2397
2398 #ifdef CONFIG_PM_SLEEP
2399 static int gpmc_suspend(struct device *dev)
2400 {
2401         omap3_gpmc_save_context();
2402         pm_runtime_put_sync(dev);
2403         return 0;
2404 }
2405
2406 static int gpmc_resume(struct device *dev)
2407 {
2408         pm_runtime_get_sync(dev);
2409         omap3_gpmc_restore_context();
2410         return 0;
2411 }
2412 #endif
2413
2414 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2415
2416 static struct platform_driver gpmc_driver = {
2417         .probe          = gpmc_probe,
2418         .remove         = gpmc_remove,
2419         .driver         = {
2420                 .name   = DEVICE_NAME,
2421                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2422                 .pm     = &gpmc_pm_ops,
2423         },
2424 };
2425
2426 static __init int gpmc_init(void)
2427 {
2428         return platform_driver_register(&gpmc_driver);
2429 }
2430 postcore_initcall(gpmc_init);
2431
2432 static struct omap3_gpmc_regs gpmc_context;
2433
2434 void omap3_gpmc_save_context(void)
2435 {
2436         int i;
2437
2438         if (!gpmc_base)
2439                 return;
2440
2441         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2442         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2443         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2444         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2445         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2446         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2447         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2448         for (i = 0; i < gpmc_cs_num; i++) {
2449                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2450                 if (gpmc_context.cs_context[i].is_valid) {
2451                         gpmc_context.cs_context[i].config1 =
2452                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2453                         gpmc_context.cs_context[i].config2 =
2454                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2455                         gpmc_context.cs_context[i].config3 =
2456                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2457                         gpmc_context.cs_context[i].config4 =
2458                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2459                         gpmc_context.cs_context[i].config5 =
2460                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2461                         gpmc_context.cs_context[i].config6 =
2462                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2463                         gpmc_context.cs_context[i].config7 =
2464                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2465                 }
2466         }
2467 }
2468
2469 void omap3_gpmc_restore_context(void)
2470 {
2471         int i;
2472
2473         if (!gpmc_base)
2474                 return;
2475
2476         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2477         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2478         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2479         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2480         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2481         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2482         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2483         for (i = 0; i < gpmc_cs_num; i++) {
2484                 if (gpmc_context.cs_context[i].is_valid) {
2485                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2486                                 gpmc_context.cs_context[i].config1);
2487                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2488                                 gpmc_context.cs_context[i].config2);
2489                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2490                                 gpmc_context.cs_context[i].config3);
2491                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2492                                 gpmc_context.cs_context[i].config4);
2493                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2494                                 gpmc_context.cs_context[i].config5);
2495                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2496                                 gpmc_context.cs_context[i].config6);
2497                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2498                                 gpmc_context.cs_context[i].config7);
2499                 }
2500         }
2501 }