2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
12 #include <asm/cacheflush.h>
14 #include <dt-bindings/memory/tegra124-mc.h>
18 #define MC_EMEM_ARB_CFG 0x90
19 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
20 #define MC_EMEM_ARB_TIMING_RCD 0x98
21 #define MC_EMEM_ARB_TIMING_RP 0x9c
22 #define MC_EMEM_ARB_TIMING_RC 0xa0
23 #define MC_EMEM_ARB_TIMING_RAS 0xa4
24 #define MC_EMEM_ARB_TIMING_FAW 0xa8
25 #define MC_EMEM_ARB_TIMING_RRD 0xac
26 #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
27 #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
28 #define MC_EMEM_ARB_TIMING_R2R 0xb8
29 #define MC_EMEM_ARB_TIMING_W2W 0xbc
30 #define MC_EMEM_ARB_TIMING_R2W 0xc0
31 #define MC_EMEM_ARB_TIMING_W2R 0xc4
32 #define MC_EMEM_ARB_DA_TURNS 0xd0
33 #define MC_EMEM_ARB_DA_COVERS 0xd4
34 #define MC_EMEM_ARB_MISC0 0xd8
35 #define MC_EMEM_ARB_MISC1 0xdc
36 #define MC_EMEM_ARB_RING1_THROTTLE 0xe0
38 static const unsigned long tegra124_mc_emem_regs[] = {
40 MC_EMEM_ARB_OUTSTANDING_REQ,
41 MC_EMEM_ARB_TIMING_RCD,
42 MC_EMEM_ARB_TIMING_RP,
43 MC_EMEM_ARB_TIMING_RC,
44 MC_EMEM_ARB_TIMING_RAS,
45 MC_EMEM_ARB_TIMING_FAW,
46 MC_EMEM_ARB_TIMING_RRD,
47 MC_EMEM_ARB_TIMING_RAP2PRE,
48 MC_EMEM_ARB_TIMING_WAP2PRE,
49 MC_EMEM_ARB_TIMING_R2R,
50 MC_EMEM_ARB_TIMING_W2W,
51 MC_EMEM_ARB_TIMING_R2W,
52 MC_EMEM_ARB_TIMING_W2R,
54 MC_EMEM_ARB_DA_COVERS,
57 MC_EMEM_ARB_RING1_THROTTLE
60 static const struct tegra_mc_client tegra124_mc_clients[] = {
64 .swgroup = TEGRA_SWGROUP_PTC,
68 .swgroup = TEGRA_SWGROUP_DC,
82 .swgroup = TEGRA_SWGROUP_DCB,
96 .swgroup = TEGRA_SWGROUP_DC,
109 .name = "display0bb",
110 .swgroup = TEGRA_SWGROUP_DCB,
124 .swgroup = TEGRA_SWGROUP_DC,
137 .name = "display0cb",
138 .swgroup = TEGRA_SWGROUP_DCB,
152 .swgroup = TEGRA_SWGROUP_AFI,
166 .swgroup = TEGRA_SWGROUP_AVPC,
180 .swgroup = TEGRA_SWGROUP_DC,
193 .name = "displayhcb",
194 .swgroup = TEGRA_SWGROUP_DCB,
208 .swgroup = TEGRA_SWGROUP_HDA,
221 .name = "host1xdmar",
222 .swgroup = TEGRA_SWGROUP_HC,
236 .swgroup = TEGRA_SWGROUP_HC,
250 .swgroup = TEGRA_SWGROUP_MSENC,
263 .name = "ppcsahbdmar",
264 .swgroup = TEGRA_SWGROUP_PPCS,
277 .name = "ppcsahbslvr",
278 .swgroup = TEGRA_SWGROUP_PPCS,
292 .swgroup = TEGRA_SWGROUP_SATA,
306 .swgroup = TEGRA_SWGROUP_VDE,
320 .swgroup = TEGRA_SWGROUP_VDE,
334 .swgroup = TEGRA_SWGROUP_VDE,
348 .swgroup = TEGRA_SWGROUP_VDE,
362 .swgroup = TEGRA_SWGROUP_MPCORELP,
372 .swgroup = TEGRA_SWGROUP_MPCORE,
382 .swgroup = TEGRA_SWGROUP_MSENC,
396 .swgroup = TEGRA_SWGROUP_AFI,
410 .swgroup = TEGRA_SWGROUP_AVPC,
424 .swgroup = TEGRA_SWGROUP_HDA,
438 .swgroup = TEGRA_SWGROUP_HC,
452 .swgroup = TEGRA_SWGROUP_MPCORELP,
462 .swgroup = TEGRA_SWGROUP_MPCORE,
471 .name = "ppcsahbdmaw",
472 .swgroup = TEGRA_SWGROUP_PPCS,
485 .name = "ppcsahbslvw",
486 .swgroup = TEGRA_SWGROUP_PPCS,
500 .swgroup = TEGRA_SWGROUP_SATA,
514 .swgroup = TEGRA_SWGROUP_VDE,
528 .swgroup = TEGRA_SWGROUP_VDE,
542 .swgroup = TEGRA_SWGROUP_VDE,
556 .swgroup = TEGRA_SWGROUP_VDE,
570 .swgroup = TEGRA_SWGROUP_ISP2,
584 .swgroup = TEGRA_SWGROUP_ISP2,
598 .swgroup = TEGRA_SWGROUP_ISP2,
611 .name = "xusb_hostr",
612 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
625 .name = "xusb_hostw",
626 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
640 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
654 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
668 .swgroup = TEGRA_SWGROUP_ISP2B,
682 .swgroup = TEGRA_SWGROUP_ISP2B,
696 .swgroup = TEGRA_SWGROUP_ISP2B,
710 .swgroup = TEGRA_SWGROUP_TSEC,
724 .swgroup = TEGRA_SWGROUP_TSEC,
738 .swgroup = TEGRA_SWGROUP_A9AVP,
752 .swgroup = TEGRA_SWGROUP_A9AVP,
766 .swgroup = TEGRA_SWGROUP_GPU,
781 .swgroup = TEGRA_SWGROUP_GPU,
796 .swgroup = TEGRA_SWGROUP_DC,
810 .swgroup = TEGRA_SWGROUP_SDMMC1A,
824 .swgroup = TEGRA_SWGROUP_SDMMC2A,
838 .swgroup = TEGRA_SWGROUP_SDMMC3A,
851 .swgroup = TEGRA_SWGROUP_SDMMC4A,
866 .swgroup = TEGRA_SWGROUP_SDMMC1A,
880 .swgroup = TEGRA_SWGROUP_SDMMC2A,
894 .swgroup = TEGRA_SWGROUP_SDMMC3A,
908 .swgroup = TEGRA_SWGROUP_SDMMC4A,
922 .swgroup = TEGRA_SWGROUP_VIC,
936 .swgroup = TEGRA_SWGROUP_VIC,
950 .swgroup = TEGRA_SWGROUP_VI,
964 .swgroup = TEGRA_SWGROUP_DC,
978 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
979 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
980 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
981 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
982 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
983 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
984 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
985 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
986 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
987 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
988 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
989 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
990 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
991 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
992 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
993 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
994 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
995 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
996 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
997 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
998 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
999 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1000 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1001 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1004 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1005 static void tegra124_flush_dcache(struct page *page, unsigned long offset,
1008 phys_addr_t phys = page_to_phys(page) + offset;
1009 void *virt = page_address(page) + offset;
1011 __cpuc_flush_dcache_area(virt, size);
1012 outer_flush_range(phys, phys + size);
1015 static const struct tegra_smmu_ops tegra124_smmu_ops = {
1016 .flush_dcache = tegra124_flush_dcache,
1019 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1020 .clients = tegra124_mc_clients,
1021 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1022 .swgroups = tegra124_swgroups,
1023 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1024 .supports_round_robin_arbitration = true,
1025 .supports_request_limit = true,
1027 .ops = &tegra124_smmu_ops,
1030 const struct tegra_mc_soc tegra124_mc_soc = {
1031 .clients = tegra124_mc_clients,
1032 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1033 .num_address_bits = 34,
1035 .smmu = &tegra124_smmu_soc,
1036 .emem_regs = tegra124_mc_emem_regs,
1037 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1039 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1041 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1042 static void tegra132_flush_dcache(struct page *page, unsigned long offset,
1045 void *virt = page_address(page) + offset;
1047 __flush_dcache_area(virt, size);
1050 static const struct tegra_smmu_ops tegra132_smmu_ops = {
1051 .flush_dcache = tegra132_flush_dcache,
1054 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1055 .clients = tegra124_mc_clients,
1056 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1057 .swgroups = tegra124_swgroups,
1058 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1059 .supports_round_robin_arbitration = true,
1060 .supports_request_limit = true,
1062 .ops = &tegra132_smmu_ops,
1065 const struct tegra_mc_soc tegra132_mc_soc = {
1066 .clients = tegra124_mc_clients,
1067 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1068 .num_address_bits = 34,
1070 .smmu = &tegra132_smmu_soc,
1072 #endif /* CONFIG_ARCH_TEGRA_132_SOC */