2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
10 * U8500 PRCM Unit interface driver
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/spinlock.h>
20 #include <linux/slab.h>
21 #include <linux/mutex.h>
22 #include <linux/completion.h>
23 #include <linux/irq.h>
24 #include <linux/jiffies.h>
25 #include <linux/bitops.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/mfd/core.h>
30 #include <linux/mfd/dbx500-prcmu.h>
31 #include <linux/mfd/abx500/ab8500.h>
32 #include <linux/regulator/db8500-prcmu.h>
33 #include <linux/regulator/machine.h>
34 #include <linux/cpufreq.h>
35 #include <linux/platform_data/ux500_wdt.h>
36 #include <linux/platform_data/db8500_thermal.h>
37 #include "dbx500-prcmu-regs.h"
39 /* Index of different voltages to be used when accessing AVSData */
40 #define PRCM_AVS_BASE 0x2FC
41 #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
42 #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
43 #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
44 #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
45 #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
46 #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
47 #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
48 #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
49 #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
50 #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
51 #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
52 #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
53 #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
55 #define PRCM_AVS_VOLTAGE 0
56 #define PRCM_AVS_VOLTAGE_MASK 0x3f
57 #define PRCM_AVS_ISSLOWSTARTUP 6
58 #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
59 #define PRCM_AVS_ISMODEENABLE 7
60 #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
62 #define PRCM_BOOT_STATUS 0xFFF
63 #define PRCM_ROMCODE_A2P 0xFFE
64 #define PRCM_ROMCODE_P2A 0xFFD
65 #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
67 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
69 #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
70 #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
71 #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
72 #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
73 #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
74 #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
75 #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
76 #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
79 #define PRCM_REQ_MB0 0xFDC /* 12 bytes */
80 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
81 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
82 #define PRCM_REQ_MB3 0xE4C /* 372 bytes */
83 #define PRCM_REQ_MB4 0xE48 /* 4 bytes */
84 #define PRCM_REQ_MB5 0xE44 /* 4 bytes */
87 #define PRCM_ACK_MB0 0xE08 /* 52 bytes */
88 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
89 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
90 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
91 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
92 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
94 /* Mailbox 0 headers */
95 #define MB0H_POWER_STATE_TRANS 0
96 #define MB0H_CONFIG_WAKEUPS_EXE 1
97 #define MB0H_READ_WAKEUP_ACK 3
98 #define MB0H_CONFIG_WAKEUPS_SLEEP 4
100 #define MB0H_WAKEUP_EXE 2
101 #define MB0H_WAKEUP_SLEEP 5
104 #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
105 #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
106 #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
107 #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
108 #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
109 #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
112 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
113 #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
114 #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
115 #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
116 #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
117 #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
118 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
120 /* Mailbox 1 headers */
121 #define MB1H_ARM_APE_OPP 0x0
122 #define MB1H_RESET_MODEM 0x2
123 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
124 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
125 #define MB1H_RELEASE_USB_WAKEUP 0x5
126 #define MB1H_PLL_ON_OFF 0x6
128 /* Mailbox 1 Requests */
129 #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
130 #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
131 #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
132 #define PLL_SOC0_OFF 0x1
133 #define PLL_SOC0_ON 0x2
134 #define PLL_SOC1_OFF 0x4
135 #define PLL_SOC1_ON 0x8
138 #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
139 #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
140 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
141 #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
143 /* Mailbox 2 headers */
145 #define MB2H_AUTO_PWR 0x1
148 #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
149 #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
150 #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
151 #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
152 #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
153 #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
154 #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
155 #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
156 #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
157 #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
160 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
161 #define HWACC_PWR_ST_OK 0xFE
163 /* Mailbox 3 headers */
165 #define MB3H_SIDETONE 0x1
166 #define MB3H_SYSCLK 0xE
168 /* Mailbox 3 Requests */
169 #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
170 #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
171 #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
172 #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
173 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
174 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
175 #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
177 /* Mailbox 4 headers */
178 #define MB4H_DDR_INIT 0x0
179 #define MB4H_MEM_ST 0x1
180 #define MB4H_HOTDOG 0x12
181 #define MB4H_HOTMON 0x13
182 #define MB4H_HOT_PERIOD 0x14
183 #define MB4H_A9WDOG_CONF 0x16
184 #define MB4H_A9WDOG_EN 0x17
185 #define MB4H_A9WDOG_DIS 0x18
186 #define MB4H_A9WDOG_LOAD 0x19
187 #define MB4H_A9WDOG_KICK 0x20
189 /* Mailbox 4 Requests */
190 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
191 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
192 #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
193 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
194 #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
195 #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
196 #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
197 #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
198 #define HOTMON_CONFIG_LOW BIT(0)
199 #define HOTMON_CONFIG_HIGH BIT(1)
200 #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
201 #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
202 #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
203 #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
204 #define A9WDOG_AUTO_OFF_EN BIT(7)
205 #define A9WDOG_AUTO_OFF_DIS 0
206 #define A9WDOG_ID_MASK 0xf
208 /* Mailbox 5 Requests */
209 #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
210 #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
211 #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
212 #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
213 #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
214 #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
215 #define PRCMU_I2C_STOP_EN BIT(3)
218 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
219 #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
220 #define I2C_WR_OK 0x1
221 #define I2C_RD_OK 0x2
225 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
231 #define WAKEUP_BIT_RTC BIT(0)
232 #define WAKEUP_BIT_RTT0 BIT(1)
233 #define WAKEUP_BIT_RTT1 BIT(2)
234 #define WAKEUP_BIT_HSI0 BIT(3)
235 #define WAKEUP_BIT_HSI1 BIT(4)
236 #define WAKEUP_BIT_CA_WAKE BIT(5)
237 #define WAKEUP_BIT_USB BIT(6)
238 #define WAKEUP_BIT_ABB BIT(7)
239 #define WAKEUP_BIT_ABB_FIFO BIT(8)
240 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
241 #define WAKEUP_BIT_CA_SLEEP BIT(10)
242 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
243 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
244 #define WAKEUP_BIT_ANC_OK BIT(13)
245 #define WAKEUP_BIT_SW_ERROR BIT(14)
246 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
247 #define WAKEUP_BIT_ARM BIT(17)
248 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
249 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
250 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
251 #define WAKEUP_BIT_GPIO0 BIT(23)
252 #define WAKEUP_BIT_GPIO1 BIT(24)
253 #define WAKEUP_BIT_GPIO2 BIT(25)
254 #define WAKEUP_BIT_GPIO3 BIT(26)
255 #define WAKEUP_BIT_GPIO4 BIT(27)
256 #define WAKEUP_BIT_GPIO5 BIT(28)
257 #define WAKEUP_BIT_GPIO6 BIT(29)
258 #define WAKEUP_BIT_GPIO7 BIT(30)
259 #define WAKEUP_BIT_GPIO8 BIT(31)
263 struct prcmu_fw_version version;
266 static struct irq_domain *db8500_irq_domain;
269 * This vector maps irq numbers to the bits in the bit field used in
270 * communication with the PRCMU firmware.
272 * The reason for having this is to keep the irq numbers contiguous even though
273 * the bits in the bit field are not. (The bits also have a tendency to move
274 * around, to further complicate matters.)
276 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
277 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
279 #define IRQ_PRCMU_RTC 0
280 #define IRQ_PRCMU_RTT0 1
281 #define IRQ_PRCMU_RTT1 2
282 #define IRQ_PRCMU_HSI0 3
283 #define IRQ_PRCMU_HSI1 4
284 #define IRQ_PRCMU_CA_WAKE 5
285 #define IRQ_PRCMU_USB 6
286 #define IRQ_PRCMU_ABB 7
287 #define IRQ_PRCMU_ABB_FIFO 8
288 #define IRQ_PRCMU_ARM 9
289 #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
290 #define IRQ_PRCMU_GPIO0 11
291 #define IRQ_PRCMU_GPIO1 12
292 #define IRQ_PRCMU_GPIO2 13
293 #define IRQ_PRCMU_GPIO3 14
294 #define IRQ_PRCMU_GPIO4 15
295 #define IRQ_PRCMU_GPIO5 16
296 #define IRQ_PRCMU_GPIO6 17
297 #define IRQ_PRCMU_GPIO7 18
298 #define IRQ_PRCMU_GPIO8 19
299 #define IRQ_PRCMU_CA_SLEEP 20
300 #define IRQ_PRCMU_HOTMON_LOW 21
301 #define IRQ_PRCMU_HOTMON_HIGH 22
302 #define NUM_PRCMU_WAKEUPS 23
304 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
316 IRQ_ENTRY(HOTMON_LOW),
317 IRQ_ENTRY(HOTMON_HIGH),
318 IRQ_ENTRY(MODEM_SW_RESET_REQ),
330 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
331 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
332 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
340 WAKEUP_ENTRY(ABB_FIFO),
345 * mb0_transfer - state needed for mailbox 0 communication.
346 * @lock: The transaction lock.
347 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
349 * @mask_work: Work structure used for (un)masking wakeup interrupts.
350 * @req: Request data that need to persist between requests.
354 spinlock_t dbb_irqs_lock;
355 struct work_struct mask_work;
356 struct mutex ac_wake_lock;
357 struct completion ac_wake_work;
366 * mb1_transfer - state needed for mailbox 1 communication.
367 * @lock: The transaction lock.
368 * @work: The transaction completion structure.
369 * @ape_opp: The current APE OPP.
370 * @ack: Reply ("acknowledge") data.
374 struct completion work;
380 u8 ape_voltage_status;
385 * mb2_transfer - state needed for mailbox 2 communication.
386 * @lock: The transaction lock.
387 * @work: The transaction completion structure.
388 * @auto_pm_lock: The autonomous power management configuration lock.
389 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
390 * @req: Request data that need to persist between requests.
391 * @ack: Reply ("acknowledge") data.
395 struct completion work;
396 spinlock_t auto_pm_lock;
397 bool auto_pm_enabled;
404 * mb3_transfer - state needed for mailbox 3 communication.
405 * @lock: The request lock.
406 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
407 * @sysclk_work: Work structure used for sysclk requests.
411 struct mutex sysclk_lock;
412 struct completion sysclk_work;
416 * mb4_transfer - state needed for mailbox 4 communication.
417 * @lock: The transaction lock.
418 * @work: The transaction completion structure.
422 struct completion work;
426 * mb5_transfer - state needed for mailbox 5 communication.
427 * @lock: The transaction lock.
428 * @work: The transaction completion structure.
429 * @ack: Reply ("acknowledge") data.
433 struct completion work;
440 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
443 static DEFINE_SPINLOCK(prcmu_lock);
444 static DEFINE_SPINLOCK(clkout_lock);
446 /* Global var to runtime determine TCDM base for v2 or v1 */
447 static __iomem void *tcdm_base;
448 static __iomem void *prcmu_base;
463 static DEFINE_SPINLOCK(clk_mgt_lock);
465 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
466 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
467 struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
468 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
469 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
470 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
471 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
472 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
473 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
474 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
475 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
476 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
477 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
478 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
482 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
483 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
485 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
486 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
487 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
488 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
489 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
490 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
491 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
492 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
493 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
494 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
495 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
496 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
505 static struct dsiclk dsiclk[2] = {
507 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
508 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
509 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
512 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
513 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
514 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
524 static struct dsiescclk dsiescclk[3] = {
526 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
527 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
528 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
531 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
532 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
533 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
536 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
537 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
538 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
544 * Used by MCDE to setup all necessary PRCMU registers
546 #define PRCMU_RESET_DSIPLL 0x00004000
547 #define PRCMU_UNCLAMP_DSIPLL 0x00400800
549 #define PRCMU_CLK_PLL_DIV_SHIFT 0
550 #define PRCMU_CLK_PLL_SW_SHIFT 5
551 #define PRCMU_CLK_38 (1 << 9)
552 #define PRCMU_CLK_38_SRC (1 << 10)
553 #define PRCMU_CLK_38_DIV (1 << 11)
555 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
556 #define PRCMU_DSI_CLOCK_SETTING 0x0000008C
558 /* DPI 50000000 Hz */
559 #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
560 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
561 #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
563 /* D=101, N=1, R=4, SELDIV2=0 */
564 #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
566 #define PRCMU_ENABLE_PLLDSI 0x00000001
567 #define PRCMU_DISABLE_PLLDSI 0x00000000
568 #define PRCMU_RELEASE_RESET_DSS 0x0000400C
569 #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
570 /* ESC clk, div0=1, div1=1, div2=3 */
571 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
572 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
573 #define PRCMU_DSI_RESET_SW 0x00000007
575 #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
577 int db8500_prcmu_enable_dsipll(void)
581 /* Clear DSIPLL_RESETN */
582 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
583 /* Unclamp DSIPLL in/out */
584 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
586 /* Set DSI PLL FREQ */
587 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
588 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
589 /* Enable Escape clocks */
590 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
593 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
595 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
596 for (i = 0; i < 10; i++) {
597 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
598 == PRCMU_PLLDSI_LOCKP_LOCKED)
602 /* Set DSIPLL_RESETN */
603 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
607 int db8500_prcmu_disable_dsipll(void)
609 /* Disable dsi pll */
610 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
611 /* Disable escapeclock */
612 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
616 int db8500_prcmu_set_display_clocks(void)
620 spin_lock_irqsave(&clk_mgt_lock, flags);
622 /* Grab the HW semaphore. */
623 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
626 writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
627 writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
628 writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
630 /* Release the HW semaphore. */
633 spin_unlock_irqrestore(&clk_mgt_lock, flags);
638 u32 db8500_prcmu_read(unsigned int reg)
640 return readl(prcmu_base + reg);
643 void db8500_prcmu_write(unsigned int reg, u32 value)
647 spin_lock_irqsave(&prcmu_lock, flags);
648 writel(value, (prcmu_base + reg));
649 spin_unlock_irqrestore(&prcmu_lock, flags);
652 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
657 spin_lock_irqsave(&prcmu_lock, flags);
658 val = readl(prcmu_base + reg);
659 val = ((val & ~mask) | (value & mask));
660 writel(val, (prcmu_base + reg));
661 spin_unlock_irqrestore(&prcmu_lock, flags);
664 struct prcmu_fw_version *prcmu_get_fw_version(void)
666 return fw_info.valid ? &fw_info.version : NULL;
669 bool prcmu_has_arm_maxopp(void)
671 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
672 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
676 * prcmu_get_boot_status - PRCMU boot status checking
677 * Returns: the current PRCMU boot status
679 int prcmu_get_boot_status(void)
681 return readb(tcdm_base + PRCM_BOOT_STATUS);
685 * prcmu_set_rc_a2p - This function is used to run few power state sequences
686 * @val: Value to be set, i.e. transition requested
687 * Returns: 0 on success, -EINVAL on invalid argument
689 * This function is used to run the following power state sequences -
690 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
692 int prcmu_set_rc_a2p(enum romcode_write val)
694 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
696 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
701 * prcmu_get_rc_p2a - This function is used to get power state sequences
702 * Returns: the power transition that has last happened
704 * This function can return the following transitions-
705 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
707 enum romcode_read prcmu_get_rc_p2a(void)
709 return readb(tcdm_base + PRCM_ROMCODE_P2A);
713 * prcmu_get_current_mode - Return the current XP70 power mode
714 * Returns: Returns the current AP(ARM) power mode: init,
715 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
717 enum ap_pwrst prcmu_get_xp70_current_state(void)
719 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
723 * prcmu_config_clkout - Configure one of the programmable clock outputs.
724 * @clkout: The CLKOUT number (0 or 1).
725 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
726 * @div: The divider to be applied.
728 * Configures one of the programmable clock outputs (CLKOUTs).
729 * @div should be in the range [1,63] to request a configuration, or 0 to
730 * inform that the configuration is no longer requested.
732 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
734 static int requests[2];
744 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
746 if (!div && !requests[clkout])
751 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
752 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
753 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
754 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
757 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
758 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
759 PRCM_CLKOCR_CLK1TYPE);
760 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
761 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
766 spin_lock_irqsave(&clkout_lock, flags);
768 val = readl(PRCM_CLKOCR);
769 if (val & div_mask) {
771 if ((val & mask) != bits) {
773 goto unlock_and_return;
776 if ((val & mask & ~div_mask) != bits) {
778 goto unlock_and_return;
782 writel((bits | (val & ~mask)), PRCM_CLKOCR);
783 requests[clkout] += (div ? 1 : -1);
786 spin_unlock_irqrestore(&clkout_lock, flags);
791 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
795 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
797 spin_lock_irqsave(&mb0_transfer.lock, flags);
799 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
802 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
803 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
804 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
805 writeb((keep_ulp_clk ? 1 : 0),
806 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
807 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
808 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
810 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
815 u8 db8500_prcmu_get_power_state_result(void)
817 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
820 /* This function should only be called while mb0_transfer.lock is held. */
821 static void config_wakeups(void)
823 const u8 header[2] = {
824 MB0H_CONFIG_WAKEUPS_EXE,
825 MB0H_CONFIG_WAKEUPS_SLEEP
827 static u32 last_dbb_events;
828 static u32 last_abb_events;
833 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
834 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
836 abb_events = mb0_transfer.req.abb_events;
838 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
841 for (i = 0; i < 2; i++) {
842 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
844 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
845 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
846 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
847 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
849 last_dbb_events = dbb_events;
850 last_abb_events = abb_events;
853 void db8500_prcmu_enable_wakeups(u32 wakeups)
859 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
861 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
862 if (wakeups & BIT(i))
863 bits |= prcmu_wakeup_bit[i];
866 spin_lock_irqsave(&mb0_transfer.lock, flags);
868 mb0_transfer.req.dbb_wakeups = bits;
871 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
874 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
878 spin_lock_irqsave(&mb0_transfer.lock, flags);
880 mb0_transfer.req.abb_events = abb_events;
883 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
886 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
888 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
889 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
891 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
895 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
896 * @opp: The new ARM operating point to which transition is to be made
897 * Returns: 0 on success, non-zero on failure
899 * This function sets the the operating point of the ARM.
901 int db8500_prcmu_set_arm_opp(u8 opp)
905 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
910 mutex_lock(&mb1_transfer.lock);
912 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
915 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
916 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
917 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
919 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
920 wait_for_completion(&mb1_transfer.work);
922 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
923 (mb1_transfer.ack.arm_opp != opp))
926 mutex_unlock(&mb1_transfer.lock);
932 * db8500_prcmu_get_arm_opp - get the current ARM OPP
934 * Returns: the current ARM OPP
936 int db8500_prcmu_get_arm_opp(void)
938 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
942 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
944 * Returns: the current DDR OPP
946 int db8500_prcmu_get_ddr_opp(void)
948 return readb(PRCM_DDR_SUBSYS_APE_MINBW);
952 * db8500_set_ddr_opp - set the appropriate DDR OPP
953 * @opp: The new DDR operating point to which transition is to be made
954 * Returns: 0 on success, non-zero on failure
956 * This function sets the operating point of the DDR.
958 static bool enable_set_ddr_opp;
959 int db8500_prcmu_set_ddr_opp(u8 opp)
961 if (opp < DDR_100_OPP || opp > DDR_25_OPP)
963 /* Changing the DDR OPP can hang the hardware pre-v21 */
964 if (enable_set_ddr_opp)
965 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
970 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
971 static void request_even_slower_clocks(bool enable)
980 spin_lock_irqsave(&clk_mgt_lock, flags);
982 /* Grab the HW semaphore. */
983 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
986 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
990 val = readl(prcmu_base + clock_reg[i]);
991 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
993 if ((div <= 1) || (div > 15)) {
994 pr_err("prcmu: Bad clock divider %d in %s\n",
996 goto unlock_and_return;
1001 goto unlock_and_return;
1004 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1005 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1006 writel(val, prcmu_base + clock_reg[i]);
1010 /* Release the HW semaphore. */
1011 writel(0, PRCM_SEM);
1013 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1017 * db8500_set_ape_opp - set the appropriate APE OPP
1018 * @opp: The new APE operating point to which transition is to be made
1019 * Returns: 0 on success, non-zero on failure
1021 * This function sets the operating point of the APE.
1023 int db8500_prcmu_set_ape_opp(u8 opp)
1027 if (opp == mb1_transfer.ape_opp)
1030 mutex_lock(&mb1_transfer.lock);
1032 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1033 request_even_slower_clocks(false);
1035 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1038 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1041 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1042 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1043 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1044 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1046 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1047 wait_for_completion(&mb1_transfer.work);
1049 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1050 (mb1_transfer.ack.ape_opp != opp))
1054 if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1055 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1056 request_even_slower_clocks(true);
1058 mb1_transfer.ape_opp = opp;
1060 mutex_unlock(&mb1_transfer.lock);
1066 * db8500_prcmu_get_ape_opp - get the current APE OPP
1068 * Returns: the current APE OPP
1070 int db8500_prcmu_get_ape_opp(void)
1072 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1076 * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1077 * @enable: true to request the higher voltage, false to drop a request.
1079 * Calls to this function to enable and disable requests must be balanced.
1081 int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1085 static unsigned int requests;
1087 mutex_lock(&mb1_transfer.lock);
1090 if (0 != requests++)
1091 goto unlock_and_return;
1092 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1094 if (requests == 0) {
1096 goto unlock_and_return;
1097 } else if (1 != requests--) {
1098 goto unlock_and_return;
1100 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1103 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1106 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1108 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1109 wait_for_completion(&mb1_transfer.work);
1111 if ((mb1_transfer.ack.header != header) ||
1112 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1116 mutex_unlock(&mb1_transfer.lock);
1122 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1124 * This function releases the power state requirements of a USB wakeup.
1126 int prcmu_release_usb_wakeup_state(void)
1130 mutex_lock(&mb1_transfer.lock);
1132 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1135 writeb(MB1H_RELEASE_USB_WAKEUP,
1136 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1138 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1139 wait_for_completion(&mb1_transfer.work);
1141 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1142 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1145 mutex_unlock(&mb1_transfer.lock);
1150 static int request_pll(u8 clock, bool enable)
1154 if (clock == PRCMU_PLLSOC0)
1155 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1156 else if (clock == PRCMU_PLLSOC1)
1157 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1161 mutex_lock(&mb1_transfer.lock);
1163 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1166 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1167 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1169 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1170 wait_for_completion(&mb1_transfer.work);
1172 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1175 mutex_unlock(&mb1_transfer.lock);
1181 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1182 * @epod_id: The EPOD to set
1183 * @epod_state: The new EPOD state
1185 * This function sets the state of a EPOD (power domain). It may not be called
1186 * from interrupt context.
1188 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1191 bool ram_retention = false;
1194 /* check argument */
1195 BUG_ON(epod_id >= NUM_EPOD_ID);
1197 /* set flag if retention is possible */
1199 case EPOD_ID_SVAMMDSP:
1200 case EPOD_ID_SIAMMDSP:
1201 case EPOD_ID_ESRAM12:
1202 case EPOD_ID_ESRAM34:
1203 ram_retention = true;
1207 /* check argument */
1208 BUG_ON(epod_state > EPOD_STATE_ON);
1209 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1212 mutex_lock(&mb2_transfer.lock);
1214 /* wait for mailbox */
1215 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1218 /* fill in mailbox */
1219 for (i = 0; i < NUM_EPOD_ID; i++)
1220 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1221 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1223 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1225 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1228 * The current firmware version does not handle errors correctly,
1229 * and we cannot recover if there is an error.
1230 * This is expected to change when the firmware is updated.
1232 if (!wait_for_completion_timeout(&mb2_transfer.work,
1233 msecs_to_jiffies(20000))) {
1234 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1237 goto unlock_and_return;
1240 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1244 mutex_unlock(&mb2_transfer.lock);
1249 * prcmu_configure_auto_pm - Configure autonomous power management.
1250 * @sleep: Configuration for ApSleep.
1251 * @idle: Configuration for ApIdle.
1253 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1254 struct prcmu_auto_pm_config *idle)
1258 unsigned long flags;
1260 BUG_ON((sleep == NULL) || (idle == NULL));
1262 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1263 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1264 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1265 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1266 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1267 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1269 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1270 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1271 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1272 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1273 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1274 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1276 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1279 * The autonomous power management configuration is done through
1280 * fields in mailbox 2, but these fields are only used as shared
1281 * variables - i.e. there is no need to send a message.
1283 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1284 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1286 mb2_transfer.auto_pm_enabled =
1287 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1288 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1289 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1290 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1292 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1294 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1296 bool prcmu_is_auto_pm_enabled(void)
1298 return mb2_transfer.auto_pm_enabled;
1301 static int request_sysclk(bool enable)
1304 unsigned long flags;
1308 mutex_lock(&mb3_transfer.sysclk_lock);
1310 spin_lock_irqsave(&mb3_transfer.lock, flags);
1312 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1315 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1317 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1318 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1320 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1323 * The firmware only sends an ACK if we want to enable the
1324 * SysClk, and it succeeds.
1326 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1327 msecs_to_jiffies(20000))) {
1328 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1333 mutex_unlock(&mb3_transfer.sysclk_lock);
1338 static int request_timclk(bool enable)
1340 u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1343 val |= PRCM_TCR_STOP_TIMERS;
1344 writel(val, PRCM_TCR);
1349 static int request_clock(u8 clock, bool enable)
1352 unsigned long flags;
1354 spin_lock_irqsave(&clk_mgt_lock, flags);
1356 /* Grab the HW semaphore. */
1357 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1360 val = readl(prcmu_base + clk_mgt[clock].offset);
1362 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1364 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1365 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1367 writel(val, prcmu_base + clk_mgt[clock].offset);
1369 /* Release the HW semaphore. */
1370 writel(0, PRCM_SEM);
1372 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1377 static int request_sga_clock(u8 clock, bool enable)
1383 val = readl(PRCM_CGATING_BYPASS);
1384 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1387 ret = request_clock(clock, enable);
1389 if (!ret && !enable) {
1390 val = readl(PRCM_CGATING_BYPASS);
1391 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1397 static inline bool plldsi_locked(void)
1399 return (readl(PRCM_PLLDSI_LOCKP) &
1400 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1401 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1402 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1403 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1406 static int request_plldsi(bool enable)
1411 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1412 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1413 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1415 val = readl(PRCM_PLLDSI_ENABLE);
1417 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1419 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1420 writel(val, PRCM_PLLDSI_ENABLE);
1424 bool locked = plldsi_locked();
1426 for (i = 10; !locked && (i > 0); --i) {
1428 locked = plldsi_locked();
1431 writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1432 PRCM_APE_RESETN_SET);
1434 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1435 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1436 PRCM_MMIP_LS_CLAMP_SET);
1437 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1438 writel(val, PRCM_PLLDSI_ENABLE);
1442 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1447 static int request_dsiclk(u8 n, bool enable)
1451 val = readl(PRCM_DSI_PLLOUT_SEL);
1452 val &= ~dsiclk[n].divsel_mask;
1453 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1454 dsiclk[n].divsel_shift);
1455 writel(val, PRCM_DSI_PLLOUT_SEL);
1459 static int request_dsiescclk(u8 n, bool enable)
1463 val = readl(PRCM_DSITVCLK_DIV);
1464 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1465 writel(val, PRCM_DSITVCLK_DIV);
1470 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1471 * @clock: The clock for which the request is made.
1472 * @enable: Whether the clock should be enabled (true) or disabled (false).
1474 * This function should only be used by the clock implementation.
1475 * Do not use it from any other place!
1477 int db8500_prcmu_request_clock(u8 clock, bool enable)
1479 if (clock == PRCMU_SGACLK)
1480 return request_sga_clock(clock, enable);
1481 else if (clock < PRCMU_NUM_REG_CLOCKS)
1482 return request_clock(clock, enable);
1483 else if (clock == PRCMU_TIMCLK)
1484 return request_timclk(enable);
1485 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1486 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1487 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1488 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1489 else if (clock == PRCMU_PLLDSI)
1490 return request_plldsi(enable);
1491 else if (clock == PRCMU_SYSCLK)
1492 return request_sysclk(enable);
1493 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1494 return request_pll(clock, enable);
1499 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1510 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1512 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1516 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1520 if (val & PRCM_PLL_FREQ_SELDIV2)
1523 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1524 (val & PRCM_PLL_FREQ_DIV2EN) &&
1525 ((reg == PRCM_PLLSOC0_FREQ) ||
1526 (reg == PRCM_PLLARM_FREQ) ||
1527 (reg == PRCM_PLLDDR_FREQ))))
1530 (void)do_div(rate, div);
1532 return (unsigned long)rate;
1535 #define ROOT_CLOCK_RATE 38400000
1537 static unsigned long clock_rate(u8 clock)
1541 unsigned long rate = ROOT_CLOCK_RATE;
1543 val = readl(prcmu_base + clk_mgt[clock].offset);
1545 if (val & PRCM_CLK_MGT_CLK38) {
1546 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1551 val |= clk_mgt[clock].pllsw;
1552 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1554 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1555 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1556 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1557 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1558 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1559 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1563 if ((clock == PRCMU_SGACLK) &&
1564 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1565 u64 r = (rate * 10);
1567 (void)do_div(r, 25);
1568 return (unsigned long)r;
1570 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1577 static unsigned long armss_rate(void)
1582 r = readl(PRCM_ARM_CHGCLKREQ);
1584 if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1585 /* External ARMCLKFIX clock */
1587 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1589 /* Check PRCM_ARM_CHGCLKREQ divider */
1590 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1593 /* Check PRCM_ARMCLKFIX_MGT divider */
1594 r = readl(PRCM_ARMCLKFIX_MGT);
1595 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1598 } else {/* ARM PLL */
1599 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1605 static unsigned long dsiclk_rate(u8 n)
1610 divsel = readl(PRCM_DSI_PLLOUT_SEL);
1611 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1613 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1614 divsel = dsiclk[n].divsel;
1617 case PRCM_DSI_PLLOUT_SEL_PHI_4:
1619 case PRCM_DSI_PLLOUT_SEL_PHI_2:
1621 case PRCM_DSI_PLLOUT_SEL_PHI:
1622 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1629 static unsigned long dsiescclk_rate(u8 n)
1633 div = readl(PRCM_DSITVCLK_DIV);
1634 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1635 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1638 unsigned long prcmu_clock_rate(u8 clock)
1640 if (clock < PRCMU_NUM_REG_CLOCKS)
1641 return clock_rate(clock);
1642 else if (clock == PRCMU_TIMCLK)
1643 return ROOT_CLOCK_RATE / 16;
1644 else if (clock == PRCMU_SYSCLK)
1645 return ROOT_CLOCK_RATE;
1646 else if (clock == PRCMU_PLLSOC0)
1647 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1648 else if (clock == PRCMU_PLLSOC1)
1649 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1650 else if (clock == PRCMU_ARMSS)
1651 return armss_rate();
1652 else if (clock == PRCMU_PLLDDR)
1653 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1654 else if (clock == PRCMU_PLLDSI)
1655 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1657 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1658 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1659 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1660 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1665 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1667 if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1668 return ROOT_CLOCK_RATE;
1669 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1670 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1671 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1672 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1673 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1674 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1675 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1680 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1684 div = (src_rate / rate);
1687 if (rate < (src_rate / div))
1692 static long round_clock_rate(u8 clock, unsigned long rate)
1696 unsigned long src_rate;
1699 val = readl(prcmu_base + clk_mgt[clock].offset);
1700 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1701 clk_mgt[clock].branch);
1702 div = clock_divider(src_rate, rate);
1703 if (val & PRCM_CLK_MGT_CLK38) {
1704 if (clk_mgt[clock].clk38div) {
1710 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1711 u64 r = (src_rate * 10);
1713 (void)do_div(r, 25);
1715 return (unsigned long)r;
1717 rounded_rate = (src_rate / min(div, (u32)31));
1719 return rounded_rate;
1722 /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */
1723 static struct cpufreq_frequency_table db8500_cpufreq_table[] = {
1724 { .frequency = 200000, .index = ARM_EXTCLK,},
1725 { .frequency = 400000, .index = ARM_50_OPP,},
1726 { .frequency = 800000, .index = ARM_100_OPP,},
1727 { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */
1728 { .frequency = CPUFREQ_TABLE_END,},
1731 static long round_armss_rate(unsigned long rate)
1736 /* cpufreq table frequencies is in KHz. */
1739 /* Find the corresponding arm opp from the cpufreq table. */
1740 while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1741 freq = db8500_cpufreq_table[i].frequency;
1747 /* Return the last valid value, even if a match was not found. */
1751 #define MIN_PLL_VCO_RATE 600000000ULL
1752 #define MAX_PLL_VCO_RATE 1680640000ULL
1754 static long round_plldsi_rate(unsigned long rate)
1756 long rounded_rate = 0;
1757 unsigned long src_rate;
1761 src_rate = clock_rate(PRCMU_HDMICLK);
1764 for (r = 7; (rem > 0) && (r > 0); r--) {
1768 (void)do_div(d, src_rate);
1774 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1775 ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1779 if (rounded_rate == 0)
1780 rounded_rate = (long)d;
1783 if ((rate - d) < rem) {
1785 rounded_rate = (long)d;
1788 return rounded_rate;
1791 static long round_dsiclk_rate(unsigned long rate)
1794 unsigned long src_rate;
1797 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1799 div = clock_divider(src_rate, rate);
1800 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1802 return rounded_rate;
1805 static long round_dsiescclk_rate(unsigned long rate)
1808 unsigned long src_rate;
1811 src_rate = clock_rate(PRCMU_TVCLK);
1812 div = clock_divider(src_rate, rate);
1813 rounded_rate = (src_rate / min(div, (u32)255));
1815 return rounded_rate;
1818 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1820 if (clock < PRCMU_NUM_REG_CLOCKS)
1821 return round_clock_rate(clock, rate);
1822 else if (clock == PRCMU_ARMSS)
1823 return round_armss_rate(rate);
1824 else if (clock == PRCMU_PLLDSI)
1825 return round_plldsi_rate(rate);
1826 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1827 return round_dsiclk_rate(rate);
1828 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1829 return round_dsiescclk_rate(rate);
1831 return (long)prcmu_clock_rate(clock);
1834 static void set_clock_rate(u8 clock, unsigned long rate)
1838 unsigned long src_rate;
1839 unsigned long flags;
1841 spin_lock_irqsave(&clk_mgt_lock, flags);
1843 /* Grab the HW semaphore. */
1844 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1847 val = readl(prcmu_base + clk_mgt[clock].offset);
1848 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1849 clk_mgt[clock].branch);
1850 div = clock_divider(src_rate, rate);
1851 if (val & PRCM_CLK_MGT_CLK38) {
1852 if (clk_mgt[clock].clk38div) {
1854 val |= PRCM_CLK_MGT_CLK38DIV;
1856 val &= ~PRCM_CLK_MGT_CLK38DIV;
1858 } else if (clock == PRCMU_SGACLK) {
1859 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1860 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1862 u64 r = (src_rate * 10);
1864 (void)do_div(r, 25);
1866 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1870 val |= min(div, (u32)31);
1872 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1873 val |= min(div, (u32)31);
1875 writel(val, prcmu_base + clk_mgt[clock].offset);
1877 /* Release the HW semaphore. */
1878 writel(0, PRCM_SEM);
1880 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1883 static int set_armss_rate(unsigned long rate)
1887 /* cpufreq table frequencies is in KHz. */
1890 /* Find the corresponding arm opp from the cpufreq table. */
1891 while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1892 if (db8500_cpufreq_table[i].frequency == rate)
1897 if (db8500_cpufreq_table[i].frequency != rate)
1900 /* Set the new arm opp. */
1901 return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].index);
1904 static int set_plldsi_rate(unsigned long rate)
1906 unsigned long src_rate;
1911 src_rate = clock_rate(PRCMU_HDMICLK);
1914 for (r = 7; (rem > 0) && (r > 0); r--) {
1919 (void)do_div(d, src_rate);
1924 hwrate = (d * src_rate);
1925 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1926 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1928 (void)do_div(hwrate, r);
1929 if (rate < hwrate) {
1931 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1932 (r << PRCM_PLL_FREQ_R_SHIFT));
1935 if ((rate - hwrate) < rem) {
1936 rem = (rate - hwrate);
1937 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1938 (r << PRCM_PLL_FREQ_R_SHIFT));
1944 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1945 writel(pll_freq, PRCM_PLLDSI_FREQ);
1950 static void set_dsiclk_rate(u8 n, unsigned long rate)
1955 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1956 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1958 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1959 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1960 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
1962 val = readl(PRCM_DSI_PLLOUT_SEL);
1963 val &= ~dsiclk[n].divsel_mask;
1964 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1965 writel(val, PRCM_DSI_PLLOUT_SEL);
1968 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1973 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1974 val = readl(PRCM_DSITVCLK_DIV);
1975 val &= ~dsiescclk[n].div_mask;
1976 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1977 writel(val, PRCM_DSITVCLK_DIV);
1980 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1982 if (clock < PRCMU_NUM_REG_CLOCKS)
1983 set_clock_rate(clock, rate);
1984 else if (clock == PRCMU_ARMSS)
1985 return set_armss_rate(rate);
1986 else if (clock == PRCMU_PLLDSI)
1987 return set_plldsi_rate(rate);
1988 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1989 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1990 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1991 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1995 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1997 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1998 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2001 mutex_lock(&mb4_transfer.lock);
2003 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2006 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2007 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2008 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2009 writeb(DDR_PWR_STATE_ON,
2010 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2011 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2013 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2014 wait_for_completion(&mb4_transfer.work);
2016 mutex_unlock(&mb4_transfer.lock);
2021 int db8500_prcmu_config_hotdog(u8 threshold)
2023 mutex_lock(&mb4_transfer.lock);
2025 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2028 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2029 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2031 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2032 wait_for_completion(&mb4_transfer.work);
2034 mutex_unlock(&mb4_transfer.lock);
2039 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2041 mutex_lock(&mb4_transfer.lock);
2043 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2046 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2047 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2048 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2049 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2050 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2052 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2053 wait_for_completion(&mb4_transfer.work);
2055 mutex_unlock(&mb4_transfer.lock);
2060 static int config_hot_period(u16 val)
2062 mutex_lock(&mb4_transfer.lock);
2064 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2067 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2068 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2070 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2071 wait_for_completion(&mb4_transfer.work);
2073 mutex_unlock(&mb4_transfer.lock);
2078 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2080 if (cycles32k == 0xFFFF)
2083 return config_hot_period(cycles32k);
2086 int db8500_prcmu_stop_temp_sense(void)
2088 return config_hot_period(0xFFFF);
2091 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2094 mutex_lock(&mb4_transfer.lock);
2096 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2099 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2100 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2101 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2102 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2104 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2106 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2107 wait_for_completion(&mb4_transfer.work);
2109 mutex_unlock(&mb4_transfer.lock);
2115 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2117 BUG_ON(num == 0 || num > 0xf);
2118 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2119 sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2120 A9WDOG_AUTO_OFF_DIS);
2122 EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
2124 int db8500_prcmu_enable_a9wdog(u8 id)
2126 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2128 EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
2130 int db8500_prcmu_disable_a9wdog(u8 id)
2132 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2134 EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
2136 int db8500_prcmu_kick_a9wdog(u8 id)
2138 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2140 EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
2143 * timeout is 28 bit, in ms.
2145 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2147 return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2148 (id & A9WDOG_ID_MASK) |
2150 * Put the lowest 28 bits of timeout at
2151 * offset 4. Four first bits are used for id.
2153 (u8)((timeout << 4) & 0xf0),
2154 (u8)((timeout >> 4) & 0xff),
2155 (u8)((timeout >> 12) & 0xff),
2156 (u8)((timeout >> 20) & 0xff));
2158 EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
2161 * prcmu_abb_read() - Read register value(s) from the ABB.
2162 * @slave: The I2C slave address.
2163 * @reg: The (start) register address.
2164 * @value: The read out value(s).
2165 * @size: The number of registers to read.
2167 * Reads register value(s) from the ABB.
2168 * @size has to be 1 for the current firmware version.
2170 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2177 mutex_lock(&mb5_transfer.lock);
2179 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2182 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2183 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2184 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2185 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2186 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2188 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2190 if (!wait_for_completion_timeout(&mb5_transfer.work,
2191 msecs_to_jiffies(20000))) {
2192 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2196 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2200 *value = mb5_transfer.ack.value;
2202 mutex_unlock(&mb5_transfer.lock);
2208 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2209 * @slave: The I2C slave address.
2210 * @reg: The (start) register address.
2211 * @value: The value(s) to write.
2212 * @mask: The mask(s) to use.
2213 * @size: The number of registers to write.
2215 * Writes masked register value(s) to the ABB.
2216 * For each @value, only the bits set to 1 in the corresponding @mask
2217 * will be written. The other bits are not changed.
2218 * @size has to be 1 for the current firmware version.
2220 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2227 mutex_lock(&mb5_transfer.lock);
2229 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2232 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2233 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2234 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2235 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2236 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2238 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2240 if (!wait_for_completion_timeout(&mb5_transfer.work,
2241 msecs_to_jiffies(20000))) {
2242 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2246 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2249 mutex_unlock(&mb5_transfer.lock);
2255 * prcmu_abb_write() - Write register value(s) to the ABB.
2256 * @slave: The I2C slave address.
2257 * @reg: The (start) register address.
2258 * @value: The value(s) to write.
2259 * @size: The number of registers to write.
2261 * Writes register value(s) to the ABB.
2262 * @size has to be 1 for the current firmware version.
2264 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2268 return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2272 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2274 int prcmu_ac_wake_req(void)
2279 mutex_lock(&mb0_transfer.ac_wake_lock);
2281 val = readl(PRCM_HOSTACCESS_REQ);
2282 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2283 goto unlock_and_return;
2285 atomic_set(&ac_wake_req_state, 1);
2288 * Force Modem Wake-up before hostaccess_req ping-pong.
2289 * It prevents Modem to enter in Sleep while acking the hostaccess
2290 * request. The 31us delay has been calculated by HWI.
2292 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2293 writel(val, PRCM_HOSTACCESS_REQ);
2297 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2298 writel(val, PRCM_HOSTACCESS_REQ);
2300 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2301 msecs_to_jiffies(5000))) {
2302 #if defined(CONFIG_DBX500_PRCMU_DEBUG)
2303 db8500_prcmu_debug_dump(__func__, true, true);
2305 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2311 mutex_unlock(&mb0_transfer.ac_wake_lock);
2316 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2318 void prcmu_ac_sleep_req()
2322 mutex_lock(&mb0_transfer.ac_wake_lock);
2324 val = readl(PRCM_HOSTACCESS_REQ);
2325 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2326 goto unlock_and_return;
2328 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2329 PRCM_HOSTACCESS_REQ);
2331 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2332 msecs_to_jiffies(5000))) {
2333 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2337 atomic_set(&ac_wake_req_state, 0);
2340 mutex_unlock(&mb0_transfer.ac_wake_lock);
2343 bool db8500_prcmu_is_ac_wake_requested(void)
2345 return (atomic_read(&ac_wake_req_state) != 0);
2349 * db8500_prcmu_system_reset - System reset
2351 * Saves the reset reason code and then sets the APE_SOFTRST register which
2352 * fires interrupt to fw
2354 void db8500_prcmu_system_reset(u16 reset_code)
2356 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2357 writel(1, PRCM_APE_SOFTRST);
2361 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2363 * Retrieves the reset reason code stored by prcmu_system_reset() before
2366 u16 db8500_prcmu_get_reset_code(void)
2368 return readw(tcdm_base + PRCM_SW_RST_REASON);
2372 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2374 void db8500_prcmu_modem_reset(void)
2376 mutex_lock(&mb1_transfer.lock);
2378 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2381 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2382 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2383 wait_for_completion(&mb1_transfer.work);
2386 * No need to check return from PRCMU as modem should go in reset state
2387 * This state is already managed by upper layer
2390 mutex_unlock(&mb1_transfer.lock);
2393 static void ack_dbb_wakeup(void)
2395 unsigned long flags;
2397 spin_lock_irqsave(&mb0_transfer.lock, flags);
2399 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2402 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2403 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2405 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2408 static inline void print_unknown_header_warning(u8 n, u8 header)
2410 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2414 static bool read_mailbox_0(void)
2421 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2423 case MB0H_WAKEUP_EXE:
2424 case MB0H_WAKEUP_SLEEP:
2425 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2426 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2428 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2430 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2431 complete(&mb0_transfer.ac_wake_work);
2432 if (ev & WAKEUP_BIT_SYSCLK_OK)
2433 complete(&mb3_transfer.sysclk_work);
2435 ev &= mb0_transfer.req.dbb_irqs;
2437 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2438 if (ev & prcmu_irq_bit[n])
2439 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2444 print_unknown_header_warning(0, header);
2448 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2452 static bool read_mailbox_1(void)
2454 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2455 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2456 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2457 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2458 PRCM_ACK_MB1_CURRENT_APE_OPP);
2459 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2460 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2461 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2462 complete(&mb1_transfer.work);
2466 static bool read_mailbox_2(void)
2468 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2469 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2470 complete(&mb2_transfer.work);
2474 static bool read_mailbox_3(void)
2476 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2480 static bool read_mailbox_4(void)
2483 bool do_complete = true;
2485 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2490 case MB4H_HOT_PERIOD:
2491 case MB4H_A9WDOG_CONF:
2492 case MB4H_A9WDOG_EN:
2493 case MB4H_A9WDOG_DIS:
2494 case MB4H_A9WDOG_LOAD:
2495 case MB4H_A9WDOG_KICK:
2498 print_unknown_header_warning(4, header);
2499 do_complete = false;
2503 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2506 complete(&mb4_transfer.work);
2511 static bool read_mailbox_5(void)
2513 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2514 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2515 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2516 complete(&mb5_transfer.work);
2520 static bool read_mailbox_6(void)
2522 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2526 static bool read_mailbox_7(void)
2528 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2532 static bool (* const read_mailbox[NUM_MB])(void) = {
2543 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2549 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2550 if (unlikely(!bits))
2554 for (n = 0; bits; n++) {
2555 if (bits & MBOX_BIT(n)) {
2556 bits -= MBOX_BIT(n);
2557 if (read_mailbox[n]())
2558 r = IRQ_WAKE_THREAD;
2564 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2570 static void prcmu_mask_work(struct work_struct *work)
2572 unsigned long flags;
2574 spin_lock_irqsave(&mb0_transfer.lock, flags);
2578 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2581 static void prcmu_irq_mask(struct irq_data *d)
2583 unsigned long flags;
2585 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2587 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2589 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2591 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2592 schedule_work(&mb0_transfer.mask_work);
2595 static void prcmu_irq_unmask(struct irq_data *d)
2597 unsigned long flags;
2599 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2601 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2603 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2605 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2606 schedule_work(&mb0_transfer.mask_work);
2609 static void noop(struct irq_data *d)
2613 static struct irq_chip prcmu_irq_chip = {
2615 .irq_disable = prcmu_irq_mask,
2617 .irq_mask = prcmu_irq_mask,
2618 .irq_unmask = prcmu_irq_unmask,
2621 static __init char *fw_project_name(u32 project)
2624 case PRCMU_FW_PROJECT_U8500:
2626 case PRCMU_FW_PROJECT_U8400:
2628 case PRCMU_FW_PROJECT_U9500:
2630 case PRCMU_FW_PROJECT_U8500_MBB:
2632 case PRCMU_FW_PROJECT_U8500_C1:
2634 case PRCMU_FW_PROJECT_U8500_C2:
2636 case PRCMU_FW_PROJECT_U8500_C3:
2638 case PRCMU_FW_PROJECT_U8500_C4:
2640 case PRCMU_FW_PROJECT_U9500_MBL:
2642 case PRCMU_FW_PROJECT_U8500_MBL:
2644 case PRCMU_FW_PROJECT_U8500_MBL2:
2645 return "U8500 MBL2";
2646 case PRCMU_FW_PROJECT_U8520:
2648 case PRCMU_FW_PROJECT_U8420:
2650 case PRCMU_FW_PROJECT_U9540:
2652 case PRCMU_FW_PROJECT_A9420:
2654 case PRCMU_FW_PROJECT_L8540:
2656 case PRCMU_FW_PROJECT_L8580:
2663 static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2664 irq_hw_number_t hwirq)
2666 irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2668 set_irq_flags(virq, IRQF_VALID);
2673 static struct irq_domain_ops db8500_irq_ops = {
2674 .map = db8500_irq_map,
2675 .xlate = irq_domain_xlate_twocell,
2678 static int db8500_irq_init(struct device_node *np, int irq_base)
2682 /* In the device tree case, just take some IRQs */
2686 db8500_irq_domain = irq_domain_add_simple(
2687 np, NUM_PRCMU_WAKEUPS, irq_base,
2688 &db8500_irq_ops, NULL);
2690 if (!db8500_irq_domain) {
2691 pr_err("Failed to create irqdomain\n");
2695 /* All wakeups will be used, so create mappings for all */
2696 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2697 irq_create_mapping(db8500_irq_domain, i);
2702 static void dbx500_fw_version_init(struct platform_device *pdev,
2705 struct resource *res;
2706 void __iomem *tcpm_base;
2708 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2712 "Error: no prcmu tcpm memory region provided\n");
2715 tcpm_base = ioremap(res->start, resource_size(res));
2716 if (tcpm_base != NULL) {
2719 version = readl(tcpm_base + version_offset);
2720 fw_info.version.project = (version & 0xFF);
2721 fw_info.version.api_version = (version >> 8) & 0xFF;
2722 fw_info.version.func_version = (version >> 16) & 0xFF;
2723 fw_info.version.errata = (version >> 24) & 0xFF;
2724 strncpy(fw_info.version.project_name,
2725 fw_project_name(fw_info.version.project),
2726 PRCMU_FW_PROJECT_NAME_LEN);
2727 fw_info.valid = true;
2728 pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2729 fw_info.version.project_name,
2730 fw_info.version.project,
2731 fw_info.version.api_version,
2732 fw_info.version.func_version,
2733 fw_info.version.errata);
2738 void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
2741 * This is a temporary remap to bring up the clocks. It is
2742 * subsequently replaces with a real remap. After the merge of
2743 * the mailbox subsystem all of this early code goes away, and the
2744 * clock driver can probe independently. An early initcall will
2745 * still be needed, but it can be diverted into drivers/clk/ux500.
2747 prcmu_base = ioremap(phy_base, size);
2749 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2751 spin_lock_init(&mb0_transfer.lock);
2752 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2753 mutex_init(&mb0_transfer.ac_wake_lock);
2754 init_completion(&mb0_transfer.ac_wake_work);
2755 mutex_init(&mb1_transfer.lock);
2756 init_completion(&mb1_transfer.work);
2757 mb1_transfer.ape_opp = APE_NO_CHANGE;
2758 mutex_init(&mb2_transfer.lock);
2759 init_completion(&mb2_transfer.work);
2760 spin_lock_init(&mb2_transfer.auto_pm_lock);
2761 spin_lock_init(&mb3_transfer.lock);
2762 mutex_init(&mb3_transfer.sysclk_lock);
2763 init_completion(&mb3_transfer.sysclk_work);
2764 mutex_init(&mb4_transfer.lock);
2765 init_completion(&mb4_transfer.work);
2766 mutex_init(&mb5_transfer.lock);
2767 init_completion(&mb5_transfer.work);
2769 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2772 static void __init init_prcm_registers(void)
2776 val = readl(PRCM_A9PL_FORCE_CLKEN);
2777 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2778 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2779 writel(val, (PRCM_A9PL_FORCE_CLKEN));
2783 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2785 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2786 REGULATOR_SUPPLY("v-ape", NULL),
2787 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2788 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2789 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2790 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2791 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2792 /* "v-mmc" changed to "vcore" in the mainline kernel */
2793 REGULATOR_SUPPLY("vcore", "sdi0"),
2794 REGULATOR_SUPPLY("vcore", "sdi1"),
2795 REGULATOR_SUPPLY("vcore", "sdi2"),
2796 REGULATOR_SUPPLY("vcore", "sdi3"),
2797 REGULATOR_SUPPLY("vcore", "sdi4"),
2798 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2799 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2800 /* "v-uart" changed to "vcore" in the mainline kernel */
2801 REGULATOR_SUPPLY("vcore", "uart0"),
2802 REGULATOR_SUPPLY("vcore", "uart1"),
2803 REGULATOR_SUPPLY("vcore", "uart2"),
2804 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2805 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2806 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2809 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2810 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2811 /* AV8100 regulator */
2812 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2815 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2816 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2817 REGULATOR_SUPPLY("vsupply", "mcde"),
2820 /* SVA MMDSP regulator switch */
2821 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2822 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2825 /* SVA pipe regulator switch */
2826 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2827 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2830 /* SIA MMDSP regulator switch */
2831 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2832 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2835 /* SIA pipe regulator switch */
2836 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2837 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2840 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2841 REGULATOR_SUPPLY("v-mali", NULL),
2844 /* ESRAM1 and 2 regulator switch */
2845 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2846 REGULATOR_SUPPLY("esram12", "cm_control"),
2849 /* ESRAM3 and 4 regulator switch */
2850 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2851 REGULATOR_SUPPLY("v-esram34", "mcde"),
2852 REGULATOR_SUPPLY("esram34", "cm_control"),
2853 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2856 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2857 [DB8500_REGULATOR_VAPE] = {
2859 .name = "db8500-vape",
2860 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2863 .consumer_supplies = db8500_vape_consumers,
2864 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2866 [DB8500_REGULATOR_VARM] = {
2868 .name = "db8500-varm",
2869 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2872 [DB8500_REGULATOR_VMODEM] = {
2874 .name = "db8500-vmodem",
2875 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2878 [DB8500_REGULATOR_VPLL] = {
2880 .name = "db8500-vpll",
2881 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2884 [DB8500_REGULATOR_VSMPS1] = {
2886 .name = "db8500-vsmps1",
2887 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2890 [DB8500_REGULATOR_VSMPS2] = {
2892 .name = "db8500-vsmps2",
2893 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2895 .consumer_supplies = db8500_vsmps2_consumers,
2896 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2898 [DB8500_REGULATOR_VSMPS3] = {
2900 .name = "db8500-vsmps3",
2901 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2904 [DB8500_REGULATOR_VRF1] = {
2906 .name = "db8500-vrf1",
2907 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2910 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2911 /* dependency to u8500-vape is handled outside regulator framework */
2913 .name = "db8500-sva-mmdsp",
2914 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2916 .consumer_supplies = db8500_svammdsp_consumers,
2917 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2919 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2921 /* "ret" means "retention" */
2922 .name = "db8500-sva-mmdsp-ret",
2923 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2926 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2927 /* dependency to u8500-vape is handled outside regulator framework */
2929 .name = "db8500-sva-pipe",
2930 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2932 .consumer_supplies = db8500_svapipe_consumers,
2933 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2935 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2936 /* dependency to u8500-vape is handled outside regulator framework */
2938 .name = "db8500-sia-mmdsp",
2939 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2941 .consumer_supplies = db8500_siammdsp_consumers,
2942 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2944 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2946 .name = "db8500-sia-mmdsp-ret",
2947 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2950 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2951 /* dependency to u8500-vape is handled outside regulator framework */
2953 .name = "db8500-sia-pipe",
2954 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2956 .consumer_supplies = db8500_siapipe_consumers,
2957 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2959 [DB8500_REGULATOR_SWITCH_SGA] = {
2960 .supply_regulator = "db8500-vape",
2962 .name = "db8500-sga",
2963 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2965 .consumer_supplies = db8500_sga_consumers,
2966 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2969 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2970 .supply_regulator = "db8500-vape",
2972 .name = "db8500-b2r2-mcde",
2973 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2975 .consumer_supplies = db8500_b2r2_mcde_consumers,
2976 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2978 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2980 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2981 * no need to hold Vape
2984 .name = "db8500-esram12",
2985 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2987 .consumer_supplies = db8500_esram12_consumers,
2988 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2990 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2992 .name = "db8500-esram12-ret",
2993 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2996 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2998 * esram34 is set in retention and supplied by Vsafe when Vape is off,
2999 * no need to hold Vape
3002 .name = "db8500-esram34",
3003 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3005 .consumer_supplies = db8500_esram34_consumers,
3006 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
3008 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3010 .name = "db8500-esram34-ret",
3011 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3016 static struct ux500_wdt_data db8500_wdt_pdata = {
3017 .timeout = 600, /* 10 minutes */
3018 .has_28_bits_resolution = true,
3024 static struct resource db8500_thsens_resources[] = {
3026 .name = "IRQ_HOTMON_LOW",
3027 .start = IRQ_PRCMU_HOTMON_LOW,
3028 .end = IRQ_PRCMU_HOTMON_LOW,
3029 .flags = IORESOURCE_IRQ,
3032 .name = "IRQ_HOTMON_HIGH",
3033 .start = IRQ_PRCMU_HOTMON_HIGH,
3034 .end = IRQ_PRCMU_HOTMON_HIGH,
3035 .flags = IORESOURCE_IRQ,
3039 static struct db8500_thsens_platform_data db8500_thsens_data = {
3042 .type = THERMAL_TRIP_ACTIVE,
3044 [0] = "thermal-cpufreq-0",
3049 .type = THERMAL_TRIP_ACTIVE,
3051 [0] = "thermal-cpufreq-0",
3056 .type = THERMAL_TRIP_ACTIVE,
3058 [0] = "thermal-cpufreq-0",
3063 .type = THERMAL_TRIP_CRITICAL,
3068 static struct mfd_cell db8500_prcmu_devs[] = {
3070 .name = "db8500-prcmu-regulators",
3071 .of_compatible = "stericsson,db8500-prcmu-regulator",
3072 .platform_data = &db8500_regulators,
3073 .pdata_size = sizeof(db8500_regulators),
3076 .name = "cpufreq-ux500",
3077 .of_compatible = "stericsson,cpufreq-ux500",
3078 .platform_data = &db8500_cpufreq_table,
3079 .pdata_size = sizeof(db8500_cpufreq_table),
3082 .name = "ux500_wdt",
3083 .platform_data = &db8500_wdt_pdata,
3084 .pdata_size = sizeof(db8500_wdt_pdata),
3088 .name = "db8500-thermal",
3089 .num_resources = ARRAY_SIZE(db8500_thsens_resources),
3090 .resources = db8500_thsens_resources,
3091 .platform_data = &db8500_thsens_data,
3095 static void db8500_prcmu_update_cpufreq(void)
3097 if (prcmu_has_arm_maxopp()) {
3098 db8500_cpufreq_table[3].frequency = 1000000;
3099 db8500_cpufreq_table[3].index = ARM_MAX_OPP;
3103 static int db8500_prcmu_register_ab8500(struct device *parent,
3104 struct ab8500_platform_data *pdata,
3107 struct resource ab8500_resource = DEFINE_RES_IRQ(irq);
3108 struct mfd_cell ab8500_cell = {
3109 .name = "ab8500-core",
3110 .of_compatible = "stericsson,ab8500",
3111 .id = AB8500_VERSION_AB8500,
3112 .platform_data = pdata,
3113 .pdata_size = sizeof(struct ab8500_platform_data),
3114 .resources = &ab8500_resource,
3118 return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
3122 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3125 static int db8500_prcmu_probe(struct platform_device *pdev)
3127 struct device_node *np = pdev->dev.of_node;
3128 struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev);
3129 int irq = 0, err = 0;
3130 struct resource *res;
3132 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3134 dev_err(&pdev->dev, "no prcmu memory region provided\n");
3137 prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3140 "failed to ioremap prcmu register memory\n");
3143 init_prcm_registers();
3144 dbx500_fw_version_init(pdev, pdata->version_offset);
3145 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3147 dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3150 tcdm_base = devm_ioremap(&pdev->dev, res->start,
3151 resource_size(res));
3153 /* Clean up the mailbox interrupts after pre-kernel code. */
3154 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3156 irq = platform_get_irq(pdev, 0);
3158 dev_err(&pdev->dev, "no prcmu irq provided\n");
3162 err = request_threaded_irq(irq, prcmu_irq_handler,
3163 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3165 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3170 db8500_irq_init(np, pdata->irq_base);
3172 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3174 db8500_prcmu_update_cpufreq();
3176 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3177 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, db8500_irq_domain);
3179 pr_err("prcmu: Failed to add subdevices\n");
3183 err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata,
3186 mfd_remove_devices(&pdev->dev);
3187 pr_err("prcmu: Failed to add ab8500 subdevice\n");
3191 pr_info("DB8500 PRCMU initialized\n");
3196 static const struct of_device_id db8500_prcmu_match[] = {
3197 { .compatible = "stericsson,db8500-prcmu"},
3201 static struct platform_driver db8500_prcmu_driver = {
3203 .name = "db8500-prcmu",
3204 .owner = THIS_MODULE,
3205 .of_match_table = db8500_prcmu_match,
3207 .probe = db8500_prcmu_probe,
3210 static int __init db8500_prcmu_init(void)
3212 return platform_driver_register(&db8500_prcmu_driver);
3215 core_initcall(db8500_prcmu_init);
3217 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3218 MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3219 MODULE_LICENSE("GPL v2");