2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
10 * U8500 PRCM Unit interface driver
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/spinlock.h>
20 #include <linux/slab.h>
21 #include <linux/mutex.h>
22 #include <linux/completion.h>
23 #include <linux/irq.h>
24 #include <linux/jiffies.h>
25 #include <linux/bitops.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/mfd/core.h>
30 #include <linux/mfd/dbx500-prcmu.h>
31 #include <linux/regulator/db8500-prcmu.h>
32 #include <linux/regulator/machine.h>
33 #include <asm/hardware/gic.h>
34 #include <mach/hardware.h>
35 #include <mach/irqs.h>
36 #include <mach/db8500-regs.h>
38 #include "dbx500-prcmu-regs.h"
40 /* Offset for the firmware version within the TCPM */
41 #define PRCMU_FW_VERSION_OFFSET 0xA4
43 /* Index of different voltages to be used when accessing AVSData */
44 #define PRCM_AVS_BASE 0x2FC
45 #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
46 #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
47 #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
48 #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
49 #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
50 #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
51 #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
52 #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
53 #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
54 #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
55 #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
56 #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
57 #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
59 #define PRCM_AVS_VOLTAGE 0
60 #define PRCM_AVS_VOLTAGE_MASK 0x3f
61 #define PRCM_AVS_ISSLOWSTARTUP 6
62 #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
63 #define PRCM_AVS_ISMODEENABLE 7
64 #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
66 #define PRCM_BOOT_STATUS 0xFFF
67 #define PRCM_ROMCODE_A2P 0xFFE
68 #define PRCM_ROMCODE_P2A 0xFFD
69 #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
71 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
73 #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
74 #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
75 #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
76 #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
77 #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
78 #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
79 #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
80 #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
83 #define PRCM_REQ_MB0 0xFDC /* 12 bytes */
84 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
85 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
86 #define PRCM_REQ_MB3 0xE4C /* 372 bytes */
87 #define PRCM_REQ_MB4 0xE48 /* 4 bytes */
88 #define PRCM_REQ_MB5 0xE44 /* 4 bytes */
91 #define PRCM_ACK_MB0 0xE08 /* 52 bytes */
92 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
93 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
94 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
95 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
96 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
98 /* Mailbox 0 headers */
99 #define MB0H_POWER_STATE_TRANS 0
100 #define MB0H_CONFIG_WAKEUPS_EXE 1
101 #define MB0H_READ_WAKEUP_ACK 3
102 #define MB0H_CONFIG_WAKEUPS_SLEEP 4
104 #define MB0H_WAKEUP_EXE 2
105 #define MB0H_WAKEUP_SLEEP 5
108 #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
109 #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
110 #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
111 #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
112 #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
113 #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
116 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
117 #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
118 #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
119 #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
120 #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
121 #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
122 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
124 /* Mailbox 1 headers */
125 #define MB1H_ARM_APE_OPP 0x0
126 #define MB1H_RESET_MODEM 0x2
127 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
128 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
129 #define MB1H_RELEASE_USB_WAKEUP 0x5
130 #define MB1H_PLL_ON_OFF 0x6
132 /* Mailbox 1 Requests */
133 #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
134 #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
135 #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
136 #define PLL_SOC0_OFF 0x1
137 #define PLL_SOC0_ON 0x2
138 #define PLL_SOC1_OFF 0x4
139 #define PLL_SOC1_ON 0x8
142 #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
143 #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
144 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
145 #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
147 /* Mailbox 2 headers */
149 #define MB2H_AUTO_PWR 0x1
152 #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
153 #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
154 #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
155 #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
156 #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
157 #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
158 #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
159 #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
160 #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
161 #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
164 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
165 #define HWACC_PWR_ST_OK 0xFE
167 /* Mailbox 3 headers */
169 #define MB3H_SIDETONE 0x1
170 #define MB3H_SYSCLK 0xE
172 /* Mailbox 3 Requests */
173 #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
174 #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
175 #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
176 #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
177 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
178 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
179 #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
181 /* Mailbox 4 headers */
182 #define MB4H_DDR_INIT 0x0
183 #define MB4H_MEM_ST 0x1
184 #define MB4H_HOTDOG 0x12
185 #define MB4H_HOTMON 0x13
186 #define MB4H_HOT_PERIOD 0x14
187 #define MB4H_A9WDOG_CONF 0x16
188 #define MB4H_A9WDOG_EN 0x17
189 #define MB4H_A9WDOG_DIS 0x18
190 #define MB4H_A9WDOG_LOAD 0x19
191 #define MB4H_A9WDOG_KICK 0x20
193 /* Mailbox 4 Requests */
194 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
195 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
196 #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
197 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
198 #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
199 #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
200 #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
201 #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
202 #define HOTMON_CONFIG_LOW BIT(0)
203 #define HOTMON_CONFIG_HIGH BIT(1)
204 #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
205 #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
206 #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
207 #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
208 #define A9WDOG_AUTO_OFF_EN BIT(7)
209 #define A9WDOG_AUTO_OFF_DIS 0
210 #define A9WDOG_ID_MASK 0xf
212 /* Mailbox 5 Requests */
213 #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
214 #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
215 #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
216 #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
217 #define PRCMU_I2C_WRITE(slave) \
218 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
219 #define PRCMU_I2C_READ(slave) \
220 (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
221 #define PRCMU_I2C_STOP_EN BIT(3)
224 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
225 #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
226 #define I2C_WR_OK 0x1
227 #define I2C_RD_OK 0x2
231 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
237 #define WAKEUP_BIT_RTC BIT(0)
238 #define WAKEUP_BIT_RTT0 BIT(1)
239 #define WAKEUP_BIT_RTT1 BIT(2)
240 #define WAKEUP_BIT_HSI0 BIT(3)
241 #define WAKEUP_BIT_HSI1 BIT(4)
242 #define WAKEUP_BIT_CA_WAKE BIT(5)
243 #define WAKEUP_BIT_USB BIT(6)
244 #define WAKEUP_BIT_ABB BIT(7)
245 #define WAKEUP_BIT_ABB_FIFO BIT(8)
246 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
247 #define WAKEUP_BIT_CA_SLEEP BIT(10)
248 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
249 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
250 #define WAKEUP_BIT_ANC_OK BIT(13)
251 #define WAKEUP_BIT_SW_ERROR BIT(14)
252 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
253 #define WAKEUP_BIT_ARM BIT(17)
254 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
255 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
256 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
257 #define WAKEUP_BIT_GPIO0 BIT(23)
258 #define WAKEUP_BIT_GPIO1 BIT(24)
259 #define WAKEUP_BIT_GPIO2 BIT(25)
260 #define WAKEUP_BIT_GPIO3 BIT(26)
261 #define WAKEUP_BIT_GPIO4 BIT(27)
262 #define WAKEUP_BIT_GPIO5 BIT(28)
263 #define WAKEUP_BIT_GPIO6 BIT(29)
264 #define WAKEUP_BIT_GPIO7 BIT(30)
265 #define WAKEUP_BIT_GPIO8 BIT(31)
269 struct prcmu_fw_version version;
273 * This vector maps irq numbers to the bits in the bit field used in
274 * communication with the PRCMU firmware.
276 * The reason for having this is to keep the irq numbers contiguous even though
277 * the bits in the bit field are not. (The bits also have a tendency to move
278 * around, to further complicate matters.)
280 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
281 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
282 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
294 IRQ_ENTRY(HOTMON_LOW),
295 IRQ_ENTRY(HOTMON_HIGH),
296 IRQ_ENTRY(MODEM_SW_RESET_REQ),
308 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
309 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
310 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
318 WAKEUP_ENTRY(ABB_FIFO),
323 * mb0_transfer - state needed for mailbox 0 communication.
324 * @lock: The transaction lock.
325 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
327 * @mask_work: Work structure used for (un)masking wakeup interrupts.
328 * @req: Request data that need to persist between requests.
332 spinlock_t dbb_irqs_lock;
333 struct work_struct mask_work;
334 struct mutex ac_wake_lock;
335 struct completion ac_wake_work;
344 * mb1_transfer - state needed for mailbox 1 communication.
345 * @lock: The transaction lock.
346 * @work: The transaction completion structure.
347 * @ape_opp: The current APE OPP.
348 * @ack: Reply ("acknowledge") data.
352 struct completion work;
358 u8 ape_voltage_status;
363 * mb2_transfer - state needed for mailbox 2 communication.
364 * @lock: The transaction lock.
365 * @work: The transaction completion structure.
366 * @auto_pm_lock: The autonomous power management configuration lock.
367 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
368 * @req: Request data that need to persist between requests.
369 * @ack: Reply ("acknowledge") data.
373 struct completion work;
374 spinlock_t auto_pm_lock;
375 bool auto_pm_enabled;
382 * mb3_transfer - state needed for mailbox 3 communication.
383 * @lock: The request lock.
384 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
385 * @sysclk_work: Work structure used for sysclk requests.
389 struct mutex sysclk_lock;
390 struct completion sysclk_work;
394 * mb4_transfer - state needed for mailbox 4 communication.
395 * @lock: The transaction lock.
396 * @work: The transaction completion structure.
400 struct completion work;
404 * mb5_transfer - state needed for mailbox 5 communication.
405 * @lock: The transaction lock.
406 * @work: The transaction completion structure.
407 * @ack: Reply ("acknowledge") data.
411 struct completion work;
418 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
421 static DEFINE_SPINLOCK(prcmu_lock);
422 static DEFINE_SPINLOCK(clkout_lock);
424 /* Global var to runtime determine TCDM base for v2 or v1 */
425 static __iomem void *tcdm_base;
440 static DEFINE_SPINLOCK(clk_mgt_lock);
442 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
443 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
444 struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
445 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
446 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
447 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
448 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
449 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
450 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
451 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
452 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
453 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
454 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
455 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
456 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
457 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
458 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
459 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
460 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
461 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
462 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
463 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
464 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
465 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
466 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
467 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
468 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
469 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
470 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
471 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
472 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
473 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
482 static struct dsiclk dsiclk[2] = {
484 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
485 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
486 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
489 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
490 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
491 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
501 static struct dsiescclk dsiescclk[3] = {
503 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
504 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
505 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
508 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
509 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
510 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
513 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
514 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
515 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
520 * Used by MCDE to setup all necessary PRCMU registers
522 #define PRCMU_RESET_DSIPLL 0x00004000
523 #define PRCMU_UNCLAMP_DSIPLL 0x00400800
525 #define PRCMU_CLK_PLL_DIV_SHIFT 0
526 #define PRCMU_CLK_PLL_SW_SHIFT 5
527 #define PRCMU_CLK_38 (1 << 9)
528 #define PRCMU_CLK_38_SRC (1 << 10)
529 #define PRCMU_CLK_38_DIV (1 << 11)
531 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
532 #define PRCMU_DSI_CLOCK_SETTING 0x0000008C
534 /* DPI 50000000 Hz */
535 #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
536 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
537 #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
539 /* D=101, N=1, R=4, SELDIV2=0 */
540 #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
542 #define PRCMU_ENABLE_PLLDSI 0x00000001
543 #define PRCMU_DISABLE_PLLDSI 0x00000000
544 #define PRCMU_RELEASE_RESET_DSS 0x0000400C
545 #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
546 /* ESC clk, div0=1, div1=1, div2=3 */
547 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
548 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
549 #define PRCMU_DSI_RESET_SW 0x00000007
551 #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
553 int db8500_prcmu_enable_dsipll(void)
557 /* Clear DSIPLL_RESETN */
558 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
559 /* Unclamp DSIPLL in/out */
560 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
562 /* Set DSI PLL FREQ */
563 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
564 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
565 /* Enable Escape clocks */
566 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
569 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
571 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
572 for (i = 0; i < 10; i++) {
573 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
574 == PRCMU_PLLDSI_LOCKP_LOCKED)
578 /* Set DSIPLL_RESETN */
579 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
583 int db8500_prcmu_disable_dsipll(void)
585 /* Disable dsi pll */
586 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
587 /* Disable escapeclock */
588 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
592 int db8500_prcmu_set_display_clocks(void)
596 spin_lock_irqsave(&clk_mgt_lock, flags);
598 /* Grab the HW semaphore. */
599 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
602 writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
603 writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
604 writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT);
606 /* Release the HW semaphore. */
609 spin_unlock_irqrestore(&clk_mgt_lock, flags);
614 u32 db8500_prcmu_read(unsigned int reg)
616 return readl(_PRCMU_BASE + reg);
619 void db8500_prcmu_write(unsigned int reg, u32 value)
623 spin_lock_irqsave(&prcmu_lock, flags);
624 writel(value, (_PRCMU_BASE + reg));
625 spin_unlock_irqrestore(&prcmu_lock, flags);
628 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
633 spin_lock_irqsave(&prcmu_lock, flags);
634 val = readl(_PRCMU_BASE + reg);
635 val = ((val & ~mask) | (value & mask));
636 writel(val, (_PRCMU_BASE + reg));
637 spin_unlock_irqrestore(&prcmu_lock, flags);
640 struct prcmu_fw_version *prcmu_get_fw_version(void)
642 return fw_info.valid ? &fw_info.version : NULL;
645 bool prcmu_has_arm_maxopp(void)
647 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
648 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
652 * prcmu_get_boot_status - PRCMU boot status checking
653 * Returns: the current PRCMU boot status
655 int prcmu_get_boot_status(void)
657 return readb(tcdm_base + PRCM_BOOT_STATUS);
661 * prcmu_set_rc_a2p - This function is used to run few power state sequences
662 * @val: Value to be set, i.e. transition requested
663 * Returns: 0 on success, -EINVAL on invalid argument
665 * This function is used to run the following power state sequences -
666 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
668 int prcmu_set_rc_a2p(enum romcode_write val)
670 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
672 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
677 * prcmu_get_rc_p2a - This function is used to get power state sequences
678 * Returns: the power transition that has last happened
680 * This function can return the following transitions-
681 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
683 enum romcode_read prcmu_get_rc_p2a(void)
685 return readb(tcdm_base + PRCM_ROMCODE_P2A);
689 * prcmu_get_current_mode - Return the current XP70 power mode
690 * Returns: Returns the current AP(ARM) power mode: init,
691 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
693 enum ap_pwrst prcmu_get_xp70_current_state(void)
695 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
699 * prcmu_config_clkout - Configure one of the programmable clock outputs.
700 * @clkout: The CLKOUT number (0 or 1).
701 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
702 * @div: The divider to be applied.
704 * Configures one of the programmable clock outputs (CLKOUTs).
705 * @div should be in the range [1,63] to request a configuration, or 0 to
706 * inform that the configuration is no longer requested.
708 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
710 static int requests[2];
720 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
722 if (!div && !requests[clkout])
727 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
728 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
729 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
730 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
733 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
734 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
735 PRCM_CLKOCR_CLK1TYPE);
736 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
737 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
742 spin_lock_irqsave(&clkout_lock, flags);
744 val = readl(PRCM_CLKOCR);
745 if (val & div_mask) {
747 if ((val & mask) != bits) {
749 goto unlock_and_return;
752 if ((val & mask & ~div_mask) != bits) {
754 goto unlock_and_return;
758 writel((bits | (val & ~mask)), PRCM_CLKOCR);
759 requests[clkout] += (div ? 1 : -1);
762 spin_unlock_irqrestore(&clkout_lock, flags);
767 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
771 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
773 spin_lock_irqsave(&mb0_transfer.lock, flags);
775 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
778 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
779 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
780 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
781 writeb((keep_ulp_clk ? 1 : 0),
782 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
783 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
784 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
786 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
791 u8 db8500_prcmu_get_power_state_result(void)
793 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
796 /* This function decouple the gic from the prcmu */
797 int db8500_prcmu_gic_decouple(void)
799 u32 val = readl(PRCM_A9_MASK_REQ);
801 /* Set bit 0 register value to 1 */
802 writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
805 /* Make sure the register is updated */
806 readl(PRCM_A9_MASK_REQ);
808 /* Wait a few cycles for the gic mask completion */
814 /* This function recouple the gic with the prcmu */
815 int db8500_prcmu_gic_recouple(void)
817 u32 val = readl(PRCM_A9_MASK_REQ);
819 /* Set bit 0 register value to 0 */
820 writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
825 #define PRCMU_GIC_NUMBER_REGS 5
828 * This function checks if there are pending irq on the gic. It only
829 * makes sense if the gic has been decoupled before with the
830 * db8500_prcmu_gic_decouple function. Disabling an interrupt only
831 * disables the forwarding of the interrupt to any CPU interface. It
832 * does not prevent the interrupt from changing state, for example
833 * becoming pending, or active and pending if it is already
834 * active. Hence, we have to check the interrupt is pending *and* is
837 bool db8500_prcmu_gic_pending_irq(void)
839 u32 pr; /* Pending register */
840 u32 er; /* Enable register */
841 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
844 /* 5 registers. STI & PPI not skipped */
845 for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
847 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
848 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
851 return true; /* There is a pending interrupt */
858 * This function checks if there are pending interrupt on the
859 * prcmu which has been delegated to monitor the irqs with the
860 * db8500_prcmu_copy_gic_settings function.
862 bool db8500_prcmu_pending_irq(void)
867 for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
868 it = readl(PRCM_ARMITVAL31TO0 + i * 4);
869 im = readl(PRCM_ARMITMSK31TO0 + i * 4);
871 return true; /* There is a pending interrupt */
878 * This function checks if the specified cpu is in in WFI. It's usage
879 * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
880 * function. Of course passing smp_processor_id() to this function will
881 * always return false...
883 bool db8500_prcmu_is_cpu_in_wfi(int cpu)
885 return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
886 PRCM_ARM_WFI_STANDBY_WFI0;
890 * This function copies the gic SPI settings to the prcmu in order to
891 * monitor them and abort/finish the retention/off sequence or state.
893 int db8500_prcmu_copy_gic_settings(void)
895 u32 er; /* Enable register */
896 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
899 /* We skip the STI and PPI */
900 for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
901 er = readl_relaxed(dist_base +
902 GIC_DIST_ENABLE_SET + (i + 1) * 4);
903 writel(er, PRCM_ARMITMSK31TO0 + i * 4);
909 /* This function should only be called while mb0_transfer.lock is held. */
910 static void config_wakeups(void)
912 const u8 header[2] = {
913 MB0H_CONFIG_WAKEUPS_EXE,
914 MB0H_CONFIG_WAKEUPS_SLEEP
916 static u32 last_dbb_events;
917 static u32 last_abb_events;
922 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
923 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
925 abb_events = mb0_transfer.req.abb_events;
927 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
930 for (i = 0; i < 2; i++) {
931 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
933 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
934 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
935 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
936 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
938 last_dbb_events = dbb_events;
939 last_abb_events = abb_events;
942 void db8500_prcmu_enable_wakeups(u32 wakeups)
948 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
950 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
951 if (wakeups & BIT(i))
952 bits |= prcmu_wakeup_bit[i];
955 spin_lock_irqsave(&mb0_transfer.lock, flags);
957 mb0_transfer.req.dbb_wakeups = bits;
960 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
963 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
967 spin_lock_irqsave(&mb0_transfer.lock, flags);
969 mb0_transfer.req.abb_events = abb_events;
972 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
975 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
977 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
978 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
980 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
984 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
985 * @opp: The new ARM operating point to which transition is to be made
986 * Returns: 0 on success, non-zero on failure
988 * This function sets the the operating point of the ARM.
990 int db8500_prcmu_set_arm_opp(u8 opp)
994 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
999 mutex_lock(&mb1_transfer.lock);
1001 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1004 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1005 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1006 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1008 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1009 wait_for_completion(&mb1_transfer.work);
1011 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1012 (mb1_transfer.ack.arm_opp != opp))
1015 mutex_unlock(&mb1_transfer.lock);
1021 * db8500_prcmu_get_arm_opp - get the current ARM OPP
1023 * Returns: the current ARM OPP
1025 int db8500_prcmu_get_arm_opp(void)
1027 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
1031 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
1033 * Returns: the current DDR OPP
1035 int db8500_prcmu_get_ddr_opp(void)
1037 return readb(PRCM_DDR_SUBSYS_APE_MINBW);
1041 * db8500_set_ddr_opp - set the appropriate DDR OPP
1042 * @opp: The new DDR operating point to which transition is to be made
1043 * Returns: 0 on success, non-zero on failure
1045 * This function sets the operating point of the DDR.
1047 int db8500_prcmu_set_ddr_opp(u8 opp)
1049 if (opp < DDR_100_OPP || opp > DDR_25_OPP)
1051 /* Changing the DDR OPP can hang the hardware pre-v21 */
1052 if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
1053 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
1058 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
1059 static void request_even_slower_clocks(bool enable)
1061 void __iomem *clock_reg[] = {
1065 unsigned long flags;
1068 spin_lock_irqsave(&clk_mgt_lock, flags);
1070 /* Grab the HW semaphore. */
1071 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1074 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
1078 val = readl(clock_reg[i]);
1079 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
1081 if ((div <= 1) || (div > 15)) {
1082 pr_err("prcmu: Bad clock divider %d in %s\n",
1084 goto unlock_and_return;
1089 goto unlock_and_return;
1092 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1093 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1094 writel(val, clock_reg[i]);
1098 /* Release the HW semaphore. */
1099 writel(0, PRCM_SEM);
1101 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1105 * db8500_set_ape_opp - set the appropriate APE OPP
1106 * @opp: The new APE operating point to which transition is to be made
1107 * Returns: 0 on success, non-zero on failure
1109 * This function sets the operating point of the APE.
1111 int db8500_prcmu_set_ape_opp(u8 opp)
1115 if (opp == mb1_transfer.ape_opp)
1118 mutex_lock(&mb1_transfer.lock);
1120 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1121 request_even_slower_clocks(false);
1123 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1126 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1129 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1130 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1131 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1132 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1134 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1135 wait_for_completion(&mb1_transfer.work);
1137 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1138 (mb1_transfer.ack.ape_opp != opp))
1142 if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1143 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1144 request_even_slower_clocks(true);
1146 mb1_transfer.ape_opp = opp;
1148 mutex_unlock(&mb1_transfer.lock);
1154 * db8500_prcmu_get_ape_opp - get the current APE OPP
1156 * Returns: the current APE OPP
1158 int db8500_prcmu_get_ape_opp(void)
1160 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1164 * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1165 * @enable: true to request the higher voltage, false to drop a request.
1167 * Calls to this function to enable and disable requests must be balanced.
1169 int prcmu_request_ape_opp_100_voltage(bool enable)
1173 static unsigned int requests;
1175 mutex_lock(&mb1_transfer.lock);
1178 if (0 != requests++)
1179 goto unlock_and_return;
1180 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1182 if (requests == 0) {
1184 goto unlock_and_return;
1185 } else if (1 != requests--) {
1186 goto unlock_and_return;
1188 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1191 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1194 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1196 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1197 wait_for_completion(&mb1_transfer.work);
1199 if ((mb1_transfer.ack.header != header) ||
1200 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1204 mutex_unlock(&mb1_transfer.lock);
1210 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1212 * This function releases the power state requirements of a USB wakeup.
1214 int prcmu_release_usb_wakeup_state(void)
1218 mutex_lock(&mb1_transfer.lock);
1220 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1223 writeb(MB1H_RELEASE_USB_WAKEUP,
1224 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1226 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1227 wait_for_completion(&mb1_transfer.work);
1229 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1230 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1233 mutex_unlock(&mb1_transfer.lock);
1238 static int request_pll(u8 clock, bool enable)
1242 if (clock == PRCMU_PLLSOC0)
1243 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1244 else if (clock == PRCMU_PLLSOC1)
1245 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1249 mutex_lock(&mb1_transfer.lock);
1251 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1254 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1255 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1257 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1258 wait_for_completion(&mb1_transfer.work);
1260 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1263 mutex_unlock(&mb1_transfer.lock);
1269 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1270 * @epod_id: The EPOD to set
1271 * @epod_state: The new EPOD state
1273 * This function sets the state of a EPOD (power domain). It may not be called
1274 * from interrupt context.
1276 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1279 bool ram_retention = false;
1282 /* check argument */
1283 BUG_ON(epod_id >= NUM_EPOD_ID);
1285 /* set flag if retention is possible */
1287 case EPOD_ID_SVAMMDSP:
1288 case EPOD_ID_SIAMMDSP:
1289 case EPOD_ID_ESRAM12:
1290 case EPOD_ID_ESRAM34:
1291 ram_retention = true;
1295 /* check argument */
1296 BUG_ON(epod_state > EPOD_STATE_ON);
1297 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1300 mutex_lock(&mb2_transfer.lock);
1302 /* wait for mailbox */
1303 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1306 /* fill in mailbox */
1307 for (i = 0; i < NUM_EPOD_ID; i++)
1308 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1309 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1311 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1313 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1316 * The current firmware version does not handle errors correctly,
1317 * and we cannot recover if there is an error.
1318 * This is expected to change when the firmware is updated.
1320 if (!wait_for_completion_timeout(&mb2_transfer.work,
1321 msecs_to_jiffies(20000))) {
1322 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1325 goto unlock_and_return;
1328 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1332 mutex_unlock(&mb2_transfer.lock);
1337 * prcmu_configure_auto_pm - Configure autonomous power management.
1338 * @sleep: Configuration for ApSleep.
1339 * @idle: Configuration for ApIdle.
1341 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1342 struct prcmu_auto_pm_config *idle)
1346 unsigned long flags;
1348 BUG_ON((sleep == NULL) || (idle == NULL));
1350 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1351 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1352 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1353 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1354 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1355 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1357 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1358 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1359 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1360 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1361 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1362 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1364 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1367 * The autonomous power management configuration is done through
1368 * fields in mailbox 2, but these fields are only used as shared
1369 * variables - i.e. there is no need to send a message.
1371 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1372 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1374 mb2_transfer.auto_pm_enabled =
1375 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1376 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1377 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1378 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1380 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1382 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1384 bool prcmu_is_auto_pm_enabled(void)
1386 return mb2_transfer.auto_pm_enabled;
1389 static int request_sysclk(bool enable)
1392 unsigned long flags;
1396 mutex_lock(&mb3_transfer.sysclk_lock);
1398 spin_lock_irqsave(&mb3_transfer.lock, flags);
1400 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1403 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1405 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1406 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1408 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1411 * The firmware only sends an ACK if we want to enable the
1412 * SysClk, and it succeeds.
1414 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1415 msecs_to_jiffies(20000))) {
1416 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1421 mutex_unlock(&mb3_transfer.sysclk_lock);
1426 static int request_timclk(bool enable)
1428 u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1431 val |= PRCM_TCR_STOP_TIMERS;
1432 writel(val, PRCM_TCR);
1437 static int request_clock(u8 clock, bool enable)
1440 unsigned long flags;
1442 spin_lock_irqsave(&clk_mgt_lock, flags);
1444 /* Grab the HW semaphore. */
1445 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1448 val = readl(clk_mgt[clock].reg);
1450 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1452 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1453 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1455 writel(val, clk_mgt[clock].reg);
1457 /* Release the HW semaphore. */
1458 writel(0, PRCM_SEM);
1460 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1465 static int request_sga_clock(u8 clock, bool enable)
1471 val = readl(PRCM_CGATING_BYPASS);
1472 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1475 ret = request_clock(clock, enable);
1477 if (!ret && !enable) {
1478 val = readl(PRCM_CGATING_BYPASS);
1479 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1485 static inline bool plldsi_locked(void)
1487 return (readl(PRCM_PLLDSI_LOCKP) &
1488 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1489 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1490 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1491 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1494 static int request_plldsi(bool enable)
1499 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1500 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1501 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1503 val = readl(PRCM_PLLDSI_ENABLE);
1505 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1507 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1508 writel(val, PRCM_PLLDSI_ENABLE);
1512 bool locked = plldsi_locked();
1514 for (i = 10; !locked && (i > 0); --i) {
1516 locked = plldsi_locked();
1519 writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1520 PRCM_APE_RESETN_SET);
1522 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1523 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1524 PRCM_MMIP_LS_CLAMP_SET);
1525 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1526 writel(val, PRCM_PLLDSI_ENABLE);
1530 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1535 static int request_dsiclk(u8 n, bool enable)
1539 val = readl(PRCM_DSI_PLLOUT_SEL);
1540 val &= ~dsiclk[n].divsel_mask;
1541 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1542 dsiclk[n].divsel_shift);
1543 writel(val, PRCM_DSI_PLLOUT_SEL);
1547 static int request_dsiescclk(u8 n, bool enable)
1551 val = readl(PRCM_DSITVCLK_DIV);
1552 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1553 writel(val, PRCM_DSITVCLK_DIV);
1558 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1559 * @clock: The clock for which the request is made.
1560 * @enable: Whether the clock should be enabled (true) or disabled (false).
1562 * This function should only be used by the clock implementation.
1563 * Do not use it from any other place!
1565 int db8500_prcmu_request_clock(u8 clock, bool enable)
1567 if (clock == PRCMU_SGACLK)
1568 return request_sga_clock(clock, enable);
1569 else if (clock < PRCMU_NUM_REG_CLOCKS)
1570 return request_clock(clock, enable);
1571 else if (clock == PRCMU_TIMCLK)
1572 return request_timclk(enable);
1573 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1574 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1575 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1576 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1577 else if (clock == PRCMU_PLLDSI)
1578 return request_plldsi(enable);
1579 else if (clock == PRCMU_SYSCLK)
1580 return request_sysclk(enable);
1581 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1582 return request_pll(clock, enable);
1587 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1598 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1600 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1604 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1608 if (val & PRCM_PLL_FREQ_SELDIV2)
1611 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1612 (val & PRCM_PLL_FREQ_DIV2EN) &&
1613 ((reg == PRCM_PLLSOC0_FREQ) ||
1614 (reg == PRCM_PLLDDR_FREQ))))
1617 (void)do_div(rate, div);
1619 return (unsigned long)rate;
1622 #define ROOT_CLOCK_RATE 38400000
1624 static unsigned long clock_rate(u8 clock)
1628 unsigned long rate = ROOT_CLOCK_RATE;
1630 val = readl(clk_mgt[clock].reg);
1632 if (val & PRCM_CLK_MGT_CLK38) {
1633 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1638 val |= clk_mgt[clock].pllsw;
1639 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1641 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1642 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1643 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1644 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1645 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1646 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1650 if ((clock == PRCMU_SGACLK) &&
1651 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1652 u64 r = (rate * 10);
1654 (void)do_div(r, 25);
1655 return (unsigned long)r;
1657 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1664 static unsigned long dsiclk_rate(u8 n)
1669 divsel = readl(PRCM_DSI_PLLOUT_SEL);
1670 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1672 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1673 divsel = dsiclk[n].divsel;
1676 case PRCM_DSI_PLLOUT_SEL_PHI_4:
1678 case PRCM_DSI_PLLOUT_SEL_PHI_2:
1680 case PRCM_DSI_PLLOUT_SEL_PHI:
1681 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1688 static unsigned long dsiescclk_rate(u8 n)
1692 div = readl(PRCM_DSITVCLK_DIV);
1693 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1694 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1697 unsigned long prcmu_clock_rate(u8 clock)
1699 if (clock < PRCMU_NUM_REG_CLOCKS)
1700 return clock_rate(clock);
1701 else if (clock == PRCMU_TIMCLK)
1702 return ROOT_CLOCK_RATE / 16;
1703 else if (clock == PRCMU_SYSCLK)
1704 return ROOT_CLOCK_RATE;
1705 else if (clock == PRCMU_PLLSOC0)
1706 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1707 else if (clock == PRCMU_PLLSOC1)
1708 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1709 else if (clock == PRCMU_PLLDDR)
1710 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1711 else if (clock == PRCMU_PLLDSI)
1712 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1714 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1715 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1716 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1717 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1722 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1724 if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1725 return ROOT_CLOCK_RATE;
1726 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1727 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1728 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1729 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1730 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1731 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1732 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1737 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1741 div = (src_rate / rate);
1744 if (rate < (src_rate / div))
1749 static long round_clock_rate(u8 clock, unsigned long rate)
1753 unsigned long src_rate;
1756 val = readl(clk_mgt[clock].reg);
1757 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1758 clk_mgt[clock].branch);
1759 div = clock_divider(src_rate, rate);
1760 if (val & PRCM_CLK_MGT_CLK38) {
1761 if (clk_mgt[clock].clk38div) {
1767 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1768 u64 r = (src_rate * 10);
1770 (void)do_div(r, 25);
1772 return (unsigned long)r;
1774 rounded_rate = (src_rate / min(div, (u32)31));
1776 return rounded_rate;
1779 #define MIN_PLL_VCO_RATE 600000000ULL
1780 #define MAX_PLL_VCO_RATE 1680640000ULL
1782 static long round_plldsi_rate(unsigned long rate)
1784 long rounded_rate = 0;
1785 unsigned long src_rate;
1789 src_rate = clock_rate(PRCMU_HDMICLK);
1792 for (r = 7; (rem > 0) && (r > 0); r--) {
1796 (void)do_div(d, src_rate);
1802 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1803 ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1807 if (rounded_rate == 0)
1808 rounded_rate = (long)d;
1811 if ((rate - d) < rem) {
1813 rounded_rate = (long)d;
1816 return rounded_rate;
1819 static long round_dsiclk_rate(unsigned long rate)
1822 unsigned long src_rate;
1825 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1827 div = clock_divider(src_rate, rate);
1828 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1830 return rounded_rate;
1833 static long round_dsiescclk_rate(unsigned long rate)
1836 unsigned long src_rate;
1839 src_rate = clock_rate(PRCMU_TVCLK);
1840 div = clock_divider(src_rate, rate);
1841 rounded_rate = (src_rate / min(div, (u32)255));
1843 return rounded_rate;
1846 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1848 if (clock < PRCMU_NUM_REG_CLOCKS)
1849 return round_clock_rate(clock, rate);
1850 else if (clock == PRCMU_PLLDSI)
1851 return round_plldsi_rate(rate);
1852 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1853 return round_dsiclk_rate(rate);
1854 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1855 return round_dsiescclk_rate(rate);
1857 return (long)prcmu_clock_rate(clock);
1860 static void set_clock_rate(u8 clock, unsigned long rate)
1864 unsigned long src_rate;
1865 unsigned long flags;
1867 spin_lock_irqsave(&clk_mgt_lock, flags);
1869 /* Grab the HW semaphore. */
1870 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1873 val = readl(clk_mgt[clock].reg);
1874 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1875 clk_mgt[clock].branch);
1876 div = clock_divider(src_rate, rate);
1877 if (val & PRCM_CLK_MGT_CLK38) {
1878 if (clk_mgt[clock].clk38div) {
1880 val |= PRCM_CLK_MGT_CLK38DIV;
1882 val &= ~PRCM_CLK_MGT_CLK38DIV;
1884 } else if (clock == PRCMU_SGACLK) {
1885 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1886 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1888 u64 r = (src_rate * 10);
1890 (void)do_div(r, 25);
1892 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1896 val |= min(div, (u32)31);
1898 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1899 val |= min(div, (u32)31);
1901 writel(val, clk_mgt[clock].reg);
1903 /* Release the HW semaphore. */
1904 writel(0, PRCM_SEM);
1906 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1909 static int set_plldsi_rate(unsigned long rate)
1911 unsigned long src_rate;
1916 src_rate = clock_rate(PRCMU_HDMICLK);
1919 for (r = 7; (rem > 0) && (r > 0); r--) {
1924 (void)do_div(d, src_rate);
1929 hwrate = (d * src_rate);
1930 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1931 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1933 (void)do_div(hwrate, r);
1934 if (rate < hwrate) {
1936 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1937 (r << PRCM_PLL_FREQ_R_SHIFT));
1940 if ((rate - hwrate) < rem) {
1941 rem = (rate - hwrate);
1942 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1943 (r << PRCM_PLL_FREQ_R_SHIFT));
1949 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1950 writel(pll_freq, PRCM_PLLDSI_FREQ);
1955 static void set_dsiclk_rate(u8 n, unsigned long rate)
1960 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1961 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1963 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1964 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1965 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
1967 val = readl(PRCM_DSI_PLLOUT_SEL);
1968 val &= ~dsiclk[n].divsel_mask;
1969 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1970 writel(val, PRCM_DSI_PLLOUT_SEL);
1973 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1978 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1979 val = readl(PRCM_DSITVCLK_DIV);
1980 val &= ~dsiescclk[n].div_mask;
1981 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1982 writel(val, PRCM_DSITVCLK_DIV);
1985 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1987 if (clock < PRCMU_NUM_REG_CLOCKS)
1988 set_clock_rate(clock, rate);
1989 else if (clock == PRCMU_PLLDSI)
1990 return set_plldsi_rate(rate);
1991 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1992 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1993 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1994 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1998 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
2000 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
2001 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2004 mutex_lock(&mb4_transfer.lock);
2006 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2009 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2010 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2011 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2012 writeb(DDR_PWR_STATE_ON,
2013 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2014 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2016 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2017 wait_for_completion(&mb4_transfer.work);
2019 mutex_unlock(&mb4_transfer.lock);
2024 int db8500_prcmu_config_hotdog(u8 threshold)
2026 mutex_lock(&mb4_transfer.lock);
2028 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2031 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2032 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2034 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2035 wait_for_completion(&mb4_transfer.work);
2037 mutex_unlock(&mb4_transfer.lock);
2042 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2044 mutex_lock(&mb4_transfer.lock);
2046 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2049 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2050 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2051 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2052 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2053 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2055 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2056 wait_for_completion(&mb4_transfer.work);
2058 mutex_unlock(&mb4_transfer.lock);
2063 static int config_hot_period(u16 val)
2065 mutex_lock(&mb4_transfer.lock);
2067 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2070 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2071 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2073 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2074 wait_for_completion(&mb4_transfer.work);
2076 mutex_unlock(&mb4_transfer.lock);
2081 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2083 if (cycles32k == 0xFFFF)
2086 return config_hot_period(cycles32k);
2089 int db8500_prcmu_stop_temp_sense(void)
2091 return config_hot_period(0xFFFF);
2094 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2097 mutex_lock(&mb4_transfer.lock);
2099 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2102 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2103 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2104 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2105 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2107 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2109 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2110 wait_for_completion(&mb4_transfer.work);
2112 mutex_unlock(&mb4_transfer.lock);
2118 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2120 BUG_ON(num == 0 || num > 0xf);
2121 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2122 sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2123 A9WDOG_AUTO_OFF_DIS);
2126 int db8500_prcmu_enable_a9wdog(u8 id)
2128 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2131 int db8500_prcmu_disable_a9wdog(u8 id)
2133 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2136 int db8500_prcmu_kick_a9wdog(u8 id)
2138 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2142 * timeout is 28 bit, in ms.
2144 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2146 return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2147 (id & A9WDOG_ID_MASK) |
2149 * Put the lowest 28 bits of timeout at
2150 * offset 4. Four first bits are used for id.
2152 (u8)((timeout << 4) & 0xf0),
2153 (u8)((timeout >> 4) & 0xff),
2154 (u8)((timeout >> 12) & 0xff),
2155 (u8)((timeout >> 20) & 0xff));
2159 * prcmu_abb_read() - Read register value(s) from the ABB.
2160 * @slave: The I2C slave address.
2161 * @reg: The (start) register address.
2162 * @value: The read out value(s).
2163 * @size: The number of registers to read.
2165 * Reads register value(s) from the ABB.
2166 * @size has to be 1 for the current firmware version.
2168 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2175 mutex_lock(&mb5_transfer.lock);
2177 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2180 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2181 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2182 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2183 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2184 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2186 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2188 if (!wait_for_completion_timeout(&mb5_transfer.work,
2189 msecs_to_jiffies(20000))) {
2190 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2194 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2198 *value = mb5_transfer.ack.value;
2200 mutex_unlock(&mb5_transfer.lock);
2206 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2207 * @slave: The I2C slave address.
2208 * @reg: The (start) register address.
2209 * @value: The value(s) to write.
2210 * @mask: The mask(s) to use.
2211 * @size: The number of registers to write.
2213 * Writes masked register value(s) to the ABB.
2214 * For each @value, only the bits set to 1 in the corresponding @mask
2215 * will be written. The other bits are not changed.
2216 * @size has to be 1 for the current firmware version.
2218 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2225 mutex_lock(&mb5_transfer.lock);
2227 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2230 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2231 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2232 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2233 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2234 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2236 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2238 if (!wait_for_completion_timeout(&mb5_transfer.work,
2239 msecs_to_jiffies(20000))) {
2240 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2244 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2247 mutex_unlock(&mb5_transfer.lock);
2253 * prcmu_abb_write() - Write register value(s) to the ABB.
2254 * @slave: The I2C slave address.
2255 * @reg: The (start) register address.
2256 * @value: The value(s) to write.
2257 * @size: The number of registers to write.
2259 * Writes register value(s) to the ABB.
2260 * @size has to be 1 for the current firmware version.
2262 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2266 return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2270 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2272 void prcmu_ac_wake_req(void)
2277 mutex_lock(&mb0_transfer.ac_wake_lock);
2279 val = readl(PRCM_HOSTACCESS_REQ);
2280 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2281 goto unlock_and_return;
2283 atomic_set(&ac_wake_req_state, 1);
2286 writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ);
2288 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2289 msecs_to_jiffies(5000))) {
2290 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2292 goto unlock_and_return;
2296 * The modem can generate an AC_WAKE_ACK, and then still go to sleep.
2297 * As a workaround, we wait, and then check that the modem is indeed
2298 * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS
2299 * register, which may not be the whole truth).
2302 status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2));
2303 if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE |
2304 PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) {
2305 pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n",
2308 writel(val, PRCM_HOSTACCESS_REQ);
2309 if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2310 msecs_to_jiffies(5000)))
2312 pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n",
2317 mutex_unlock(&mb0_transfer.ac_wake_lock);
2321 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2323 void prcmu_ac_sleep_req()
2327 mutex_lock(&mb0_transfer.ac_wake_lock);
2329 val = readl(PRCM_HOSTACCESS_REQ);
2330 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2331 goto unlock_and_return;
2333 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2334 PRCM_HOSTACCESS_REQ);
2336 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2337 msecs_to_jiffies(5000))) {
2338 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2342 atomic_set(&ac_wake_req_state, 0);
2345 mutex_unlock(&mb0_transfer.ac_wake_lock);
2348 bool db8500_prcmu_is_ac_wake_requested(void)
2350 return (atomic_read(&ac_wake_req_state) != 0);
2354 * db8500_prcmu_system_reset - System reset
2356 * Saves the reset reason code and then sets the APE_SOFTRST register which
2357 * fires interrupt to fw
2359 void db8500_prcmu_system_reset(u16 reset_code)
2361 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2362 writel(1, PRCM_APE_SOFTRST);
2366 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2368 * Retrieves the reset reason code stored by prcmu_system_reset() before
2371 u16 db8500_prcmu_get_reset_code(void)
2373 return readw(tcdm_base + PRCM_SW_RST_REASON);
2377 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2379 void db8500_prcmu_modem_reset(void)
2381 mutex_lock(&mb1_transfer.lock);
2383 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2386 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2387 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2388 wait_for_completion(&mb1_transfer.work);
2391 * No need to check return from PRCMU as modem should go in reset state
2392 * This state is already managed by upper layer
2395 mutex_unlock(&mb1_transfer.lock);
2398 static void ack_dbb_wakeup(void)
2400 unsigned long flags;
2402 spin_lock_irqsave(&mb0_transfer.lock, flags);
2404 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2407 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2408 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2410 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2413 static inline void print_unknown_header_warning(u8 n, u8 header)
2415 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2419 static bool read_mailbox_0(void)
2426 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2428 case MB0H_WAKEUP_EXE:
2429 case MB0H_WAKEUP_SLEEP:
2430 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2431 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2433 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2435 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2436 complete(&mb0_transfer.ac_wake_work);
2437 if (ev & WAKEUP_BIT_SYSCLK_OK)
2438 complete(&mb3_transfer.sysclk_work);
2440 ev &= mb0_transfer.req.dbb_irqs;
2442 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2443 if (ev & prcmu_irq_bit[n])
2444 generic_handle_irq(IRQ_PRCMU_BASE + n);
2449 print_unknown_header_warning(0, header);
2453 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2457 static bool read_mailbox_1(void)
2459 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2460 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2461 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2462 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2463 PRCM_ACK_MB1_CURRENT_APE_OPP);
2464 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2465 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2466 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2467 complete(&mb1_transfer.work);
2471 static bool read_mailbox_2(void)
2473 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2474 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2475 complete(&mb2_transfer.work);
2479 static bool read_mailbox_3(void)
2481 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2485 static bool read_mailbox_4(void)
2488 bool do_complete = true;
2490 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2495 case MB4H_HOT_PERIOD:
2496 case MB4H_A9WDOG_CONF:
2497 case MB4H_A9WDOG_EN:
2498 case MB4H_A9WDOG_DIS:
2499 case MB4H_A9WDOG_LOAD:
2500 case MB4H_A9WDOG_KICK:
2503 print_unknown_header_warning(4, header);
2504 do_complete = false;
2508 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2511 complete(&mb4_transfer.work);
2516 static bool read_mailbox_5(void)
2518 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2519 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2520 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2521 complete(&mb5_transfer.work);
2525 static bool read_mailbox_6(void)
2527 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2531 static bool read_mailbox_7(void)
2533 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2537 static bool (* const read_mailbox[NUM_MB])(void) = {
2548 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2554 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2555 if (unlikely(!bits))
2559 for (n = 0; bits; n++) {
2560 if (bits & MBOX_BIT(n)) {
2561 bits -= MBOX_BIT(n);
2562 if (read_mailbox[n]())
2563 r = IRQ_WAKE_THREAD;
2569 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2575 static void prcmu_mask_work(struct work_struct *work)
2577 unsigned long flags;
2579 spin_lock_irqsave(&mb0_transfer.lock, flags);
2583 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2586 static void prcmu_irq_mask(struct irq_data *d)
2588 unsigned long flags;
2590 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2592 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
2594 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2596 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2597 schedule_work(&mb0_transfer.mask_work);
2600 static void prcmu_irq_unmask(struct irq_data *d)
2602 unsigned long flags;
2604 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2606 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
2608 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2610 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2611 schedule_work(&mb0_transfer.mask_work);
2614 static void noop(struct irq_data *d)
2618 static struct irq_chip prcmu_irq_chip = {
2620 .irq_disable = prcmu_irq_mask,
2622 .irq_mask = prcmu_irq_mask,
2623 .irq_unmask = prcmu_irq_unmask,
2626 static char *fw_project_name(u8 project)
2629 case PRCMU_FW_PROJECT_U8500:
2631 case PRCMU_FW_PROJECT_U8500_C2:
2633 case PRCMU_FW_PROJECT_U9500:
2635 case PRCMU_FW_PROJECT_U9500_C2:
2637 case PRCMU_FW_PROJECT_U8520:
2639 case PRCMU_FW_PROJECT_U8420:
2646 void __init db8500_prcmu_early_init(void)
2649 if (cpu_is_u8500v2()) {
2650 void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
2652 if (tcpm_base != NULL) {
2654 version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET);
2655 fw_info.version.project = version & 0xFF;
2656 fw_info.version.api_version = (version >> 8) & 0xFF;
2657 fw_info.version.func_version = (version >> 16) & 0xFF;
2658 fw_info.version.errata = (version >> 24) & 0xFF;
2659 fw_info.valid = true;
2660 pr_info("PRCMU firmware: %s, version %d.%d.%d\n",
2661 fw_project_name(fw_info.version.project),
2662 (version >> 8) & 0xFF, (version >> 16) & 0xFF,
2663 (version >> 24) & 0xFF);
2667 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
2669 pr_err("prcmu: Unsupported chip version\n");
2673 spin_lock_init(&mb0_transfer.lock);
2674 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2675 mutex_init(&mb0_transfer.ac_wake_lock);
2676 init_completion(&mb0_transfer.ac_wake_work);
2677 mutex_init(&mb1_transfer.lock);
2678 init_completion(&mb1_transfer.work);
2679 mb1_transfer.ape_opp = APE_NO_CHANGE;
2680 mutex_init(&mb2_transfer.lock);
2681 init_completion(&mb2_transfer.work);
2682 spin_lock_init(&mb2_transfer.auto_pm_lock);
2683 spin_lock_init(&mb3_transfer.lock);
2684 mutex_init(&mb3_transfer.sysclk_lock);
2685 init_completion(&mb3_transfer.sysclk_work);
2686 mutex_init(&mb4_transfer.lock);
2687 init_completion(&mb4_transfer.work);
2688 mutex_init(&mb5_transfer.lock);
2689 init_completion(&mb5_transfer.work);
2691 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2693 /* Initalize irqs. */
2694 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) {
2697 irq = IRQ_PRCMU_BASE + i;
2698 irq_set_chip_and_handler(irq, &prcmu_irq_chip,
2700 set_irq_flags(irq, IRQF_VALID);
2704 static void __init init_prcm_registers(void)
2708 val = readl(PRCM_A9PL_FORCE_CLKEN);
2709 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2710 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2711 writel(val, (PRCM_A9PL_FORCE_CLKEN));
2715 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2717 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2718 REGULATOR_SUPPLY("v-ape", NULL),
2719 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2720 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2721 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2722 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2723 /* "v-mmc" changed to "vcore" in the mainline kernel */
2724 REGULATOR_SUPPLY("vcore", "sdi0"),
2725 REGULATOR_SUPPLY("vcore", "sdi1"),
2726 REGULATOR_SUPPLY("vcore", "sdi2"),
2727 REGULATOR_SUPPLY("vcore", "sdi3"),
2728 REGULATOR_SUPPLY("vcore", "sdi4"),
2729 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2730 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2731 /* "v-uart" changed to "vcore" in the mainline kernel */
2732 REGULATOR_SUPPLY("vcore", "uart0"),
2733 REGULATOR_SUPPLY("vcore", "uart1"),
2734 REGULATOR_SUPPLY("vcore", "uart2"),
2735 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2736 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2739 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2740 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2741 /* AV8100 regulator */
2742 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2745 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2746 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2747 REGULATOR_SUPPLY("vsupply", "mcde"),
2750 /* SVA MMDSP regulator switch */
2751 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2752 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2755 /* SVA pipe regulator switch */
2756 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2757 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2760 /* SIA MMDSP regulator switch */
2761 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2762 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2765 /* SIA pipe regulator switch */
2766 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2767 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2770 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2771 REGULATOR_SUPPLY("v-mali", NULL),
2774 /* ESRAM1 and 2 regulator switch */
2775 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2776 REGULATOR_SUPPLY("esram12", "cm_control"),
2779 /* ESRAM3 and 4 regulator switch */
2780 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2781 REGULATOR_SUPPLY("v-esram34", "mcde"),
2782 REGULATOR_SUPPLY("esram34", "cm_control"),
2783 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2786 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2787 [DB8500_REGULATOR_VAPE] = {
2789 .name = "db8500-vape",
2790 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2793 .consumer_supplies = db8500_vape_consumers,
2794 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2796 [DB8500_REGULATOR_VARM] = {
2798 .name = "db8500-varm",
2799 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2802 [DB8500_REGULATOR_VMODEM] = {
2804 .name = "db8500-vmodem",
2805 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2808 [DB8500_REGULATOR_VPLL] = {
2810 .name = "db8500-vpll",
2811 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2814 [DB8500_REGULATOR_VSMPS1] = {
2816 .name = "db8500-vsmps1",
2817 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2820 [DB8500_REGULATOR_VSMPS2] = {
2822 .name = "db8500-vsmps2",
2823 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2825 .consumer_supplies = db8500_vsmps2_consumers,
2826 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2828 [DB8500_REGULATOR_VSMPS3] = {
2830 .name = "db8500-vsmps3",
2831 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2834 [DB8500_REGULATOR_VRF1] = {
2836 .name = "db8500-vrf1",
2837 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2840 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2841 /* dependency to u8500-vape is handled outside regulator framework */
2843 .name = "db8500-sva-mmdsp",
2844 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2846 .consumer_supplies = db8500_svammdsp_consumers,
2847 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2849 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2851 /* "ret" means "retention" */
2852 .name = "db8500-sva-mmdsp-ret",
2853 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2856 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2857 /* dependency to u8500-vape is handled outside regulator framework */
2859 .name = "db8500-sva-pipe",
2860 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2862 .consumer_supplies = db8500_svapipe_consumers,
2863 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2865 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2866 /* dependency to u8500-vape is handled outside regulator framework */
2868 .name = "db8500-sia-mmdsp",
2869 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2871 .consumer_supplies = db8500_siammdsp_consumers,
2872 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2874 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2876 .name = "db8500-sia-mmdsp-ret",
2877 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2880 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2881 /* dependency to u8500-vape is handled outside regulator framework */
2883 .name = "db8500-sia-pipe",
2884 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2886 .consumer_supplies = db8500_siapipe_consumers,
2887 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2889 [DB8500_REGULATOR_SWITCH_SGA] = {
2890 .supply_regulator = "db8500-vape",
2892 .name = "db8500-sga",
2893 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2895 .consumer_supplies = db8500_sga_consumers,
2896 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2899 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2900 .supply_regulator = "db8500-vape",
2902 .name = "db8500-b2r2-mcde",
2903 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2905 .consumer_supplies = db8500_b2r2_mcde_consumers,
2906 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2908 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2910 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2911 * no need to hold Vape
2914 .name = "db8500-esram12",
2915 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2917 .consumer_supplies = db8500_esram12_consumers,
2918 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2920 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2922 .name = "db8500-esram12-ret",
2923 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2926 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2928 * esram34 is set in retention and supplied by Vsafe when Vape is off,
2929 * no need to hold Vape
2932 .name = "db8500-esram34",
2933 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2935 .consumer_supplies = db8500_esram34_consumers,
2936 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
2938 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
2940 .name = "db8500-esram34-ret",
2941 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2946 static struct mfd_cell db8500_prcmu_devs[] = {
2948 .name = "db8500-prcmu-regulators",
2949 .platform_data = &db8500_regulators,
2950 .pdata_size = sizeof(db8500_regulators),
2953 .name = "cpufreq-u8500",
2958 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
2961 static int __init db8500_prcmu_probe(struct platform_device *pdev)
2968 init_prcm_registers();
2970 /* Clean up the mailbox interrupts after pre-kernel code. */
2971 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
2973 err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler,
2974 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
2976 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
2981 if (cpu_is_u8500v20_or_later())
2982 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
2984 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
2985 ARRAY_SIZE(db8500_prcmu_devs), NULL,
2989 pr_err("prcmu: Failed to add subdevices\n");
2991 pr_info("DB8500 PRCMU initialized\n");
2997 static struct platform_driver db8500_prcmu_driver = {
2999 .name = "db8500-prcmu",
3000 .owner = THIS_MODULE,
3004 static int __init db8500_prcmu_init(void)
3006 return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe);
3009 arch_initcall(db8500_prcmu_init);
3011 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3012 MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3013 MODULE_LICENSE("GPL v2");