drivers/mfd/db8500-prcmu.c

   1 /*
   2  * Copyright (C) STMicroelectronics 2009
   3  * Copyright (C) ST-Ericsson SA 2010
   4  *
   5  * License Terms: GNU General Public License v2
   6  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
   7  * Author: Sundar Iyer <sundar.iyer@stericsson.com>
   8  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
   9  *
  10  * U8500 PRCM Unit interface driver
  11  *
  12  */
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/io.h>
  20 #include <linux/slab.h>
  21 #include <linux/mutex.h>
  22 #include <linux/completion.h>
  23 #include <linux/irq.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/bitops.h>
  26 #include <linux/fs.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/mfd/core.h>
  30 #include <linux/mfd/dbx500-prcmu.h>
  31 #include <linux/regulator/db8500-prcmu.h>
  32 #include <linux/regulator/machine.h>
  33 #include <asm/hardware/gic.h>
  34 #include <mach/hardware.h>
  35 #include <mach/irqs.h>
  36 #include <mach/db8500-regs.h>
  37 #include <mach/id.h>
  38 #include "dbx500-prcmu-regs.h"
  39
  40 /* Offset for the firmware version within the TCPM */
  41 #define PRCMU_FW_VERSION_OFFSET 0xA4
  42
  43 /* Index of different voltages to be used when accessing AVSData */
  44 #define PRCM_AVS_BASE           0x2FC
  45 #define PRCM_AVS_VBB_RET        (PRCM_AVS_BASE + 0x0)
  46 #define PRCM_AVS_VBB_MAX_OPP    (PRCM_AVS_BASE + 0x1)
  47 #define PRCM_AVS_VBB_100_OPP    (PRCM_AVS_BASE + 0x2)
  48 #define PRCM_AVS_VBB_50_OPP     (PRCM_AVS_BASE + 0x3)
  49 #define PRCM_AVS_VARM_MAX_OPP   (PRCM_AVS_BASE + 0x4)
  50 #define PRCM_AVS_VARM_100_OPP   (PRCM_AVS_BASE + 0x5)
  51 #define PRCM_AVS_VARM_50_OPP    (PRCM_AVS_BASE + 0x6)
  52 #define PRCM_AVS_VARM_RET       (PRCM_AVS_BASE + 0x7)
  53 #define PRCM_AVS_VAPE_100_OPP   (PRCM_AVS_BASE + 0x8)
  54 #define PRCM_AVS_VAPE_50_OPP    (PRCM_AVS_BASE + 0x9)
  55 #define PRCM_AVS_VMOD_100_OPP   (PRCM_AVS_BASE + 0xA)
  56 #define PRCM_AVS_VMOD_50_OPP    (PRCM_AVS_BASE + 0xB)
  57 #define PRCM_AVS_VSAFE          (PRCM_AVS_BASE + 0xC)
  58
  59 #define PRCM_AVS_VOLTAGE                0
  60 #define PRCM_AVS_VOLTAGE_MASK           0x3f
  61 #define PRCM_AVS_ISSLOWSTARTUP          6
  62 #define PRCM_AVS_ISSLOWSTARTUP_MASK     (1 << PRCM_AVS_ISSLOWSTARTUP)
  63 #define PRCM_AVS_ISMODEENABLE           7
  64 #define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
  65
  66 #define PRCM_BOOT_STATUS        0xFFF
  67 #define PRCM_ROMCODE_A2P        0xFFE
  68 #define PRCM_ROMCODE_P2A        0xFFD
  69 #define PRCM_XP70_CUR_PWR_STATE 0xFFC      /* 4 BYTES */
  70
  71 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
  72
  73 #define _PRCM_MBOX_HEADER               0xFE8 /* 16 bytes */
  74 #define PRCM_MBOX_HEADER_REQ_MB0        (_PRCM_MBOX_HEADER + 0x0)
  75 #define PRCM_MBOX_HEADER_REQ_MB1        (_PRCM_MBOX_HEADER + 0x1)
  76 #define PRCM_MBOX_HEADER_REQ_MB2        (_PRCM_MBOX_HEADER + 0x2)
  77 #define PRCM_MBOX_HEADER_REQ_MB3        (_PRCM_MBOX_HEADER + 0x3)
  78 #define PRCM_MBOX_HEADER_REQ_MB4        (_PRCM_MBOX_HEADER + 0x4)
  79 #define PRCM_MBOX_HEADER_REQ_MB5        (_PRCM_MBOX_HEADER + 0x5)
  80 #define PRCM_MBOX_HEADER_ACK_MB0        (_PRCM_MBOX_HEADER + 0x8)
  81
  82 /* Req Mailboxes */
  83 #define PRCM_REQ_MB0 0xFDC /* 12 bytes  */
  84 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes  */
  85 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes  */
  86 #define PRCM_REQ_MB3 0xE4C /* 372 bytes  */
  87 #define PRCM_REQ_MB4 0xE48 /* 4 bytes  */
  88 #define PRCM_REQ_MB5 0xE44 /* 4 bytes  */
  89
  90 /* Ack Mailboxes */
  91 #define PRCM_ACK_MB0 0xE08 /* 52 bytes  */
  92 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
  93 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
  94 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
  95 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
  96 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
  97
  98 /* Mailbox 0 headers */
  99 #define MB0H_POWER_STATE_TRANS          0
 100 #define MB0H_CONFIG_WAKEUPS_EXE         1
 101 #define MB0H_READ_WAKEUP_ACK            3
 102 #define MB0H_CONFIG_WAKEUPS_SLEEP       4
 103
 104 #define MB0H_WAKEUP_EXE 2
 105 #define MB0H_WAKEUP_SLEEP 5
 106
 107 /* Mailbox 0 REQs */
 108 #define PRCM_REQ_MB0_AP_POWER_STATE     (PRCM_REQ_MB0 + 0x0)
 109 #define PRCM_REQ_MB0_AP_PLL_STATE       (PRCM_REQ_MB0 + 0x1)
 110 #define PRCM_REQ_MB0_ULP_CLOCK_STATE    (PRCM_REQ_MB0 + 0x2)
 111 #define PRCM_REQ_MB0_DO_NOT_WFI         (PRCM_REQ_MB0 + 0x3)
 112 #define PRCM_REQ_MB0_WAKEUP_8500        (PRCM_REQ_MB0 + 0x4)
 113 #define PRCM_REQ_MB0_WAKEUP_4500        (PRCM_REQ_MB0 + 0x8)
 114
 115 /* Mailbox 0 ACKs */
 116 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS  (PRCM_ACK_MB0 + 0x0)
 117 #define PRCM_ACK_MB0_READ_POINTER       (PRCM_ACK_MB0 + 0x1)
 118 #define PRCM_ACK_MB0_WAKEUP_0_8500      (PRCM_ACK_MB0 + 0x4)
 119 #define PRCM_ACK_MB0_WAKEUP_0_4500      (PRCM_ACK_MB0 + 0x8)
 120 #define PRCM_ACK_MB0_WAKEUP_1_8500      (PRCM_ACK_MB0 + 0x1C)
 121 #define PRCM_ACK_MB0_WAKEUP_1_4500      (PRCM_ACK_MB0 + 0x20)
 122 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
 123
 124 /* Mailbox 1 headers */
 125 #define MB1H_ARM_APE_OPP 0x0
 126 #define MB1H_RESET_MODEM 0x2
 127 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
 128 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
 129 #define MB1H_RELEASE_USB_WAKEUP 0x5
 130 #define MB1H_PLL_ON_OFF 0x6
 131
 132 /* Mailbox 1 Requests */
 133 #define PRCM_REQ_MB1_ARM_OPP                    (PRCM_REQ_MB1 + 0x0)
 134 #define PRCM_REQ_MB1_APE_OPP                    (PRCM_REQ_MB1 + 0x1)
 135 #define PRCM_REQ_MB1_PLL_ON_OFF                 (PRCM_REQ_MB1 + 0x4)
 136 #define PLL_SOC0_OFF    0x1
 137 #define PLL_SOC0_ON     0x2
 138 #define PLL_SOC1_OFF    0x4
 139 #define PLL_SOC1_ON     0x8
 140
 141 /* Mailbox 1 ACKs */
 142 #define PRCM_ACK_MB1_CURRENT_ARM_OPP    (PRCM_ACK_MB1 + 0x0)
 143 #define PRCM_ACK_MB1_CURRENT_APE_OPP    (PRCM_ACK_MB1 + 0x1)
 144 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
 145 #define PRCM_ACK_MB1_DVFS_STATUS        (PRCM_ACK_MB1 + 0x3)
 146
 147 /* Mailbox 2 headers */
 148 #define MB2H_DPS        0x0
 149 #define MB2H_AUTO_PWR   0x1
 150
 151 /* Mailbox 2 REQs */
 152 #define PRCM_REQ_MB2_SVA_MMDSP          (PRCM_REQ_MB2 + 0x0)
 153 #define PRCM_REQ_MB2_SVA_PIPE           (PRCM_REQ_MB2 + 0x1)
 154 #define PRCM_REQ_MB2_SIA_MMDSP          (PRCM_REQ_MB2 + 0x2)
 155 #define PRCM_REQ_MB2_SIA_PIPE           (PRCM_REQ_MB2 + 0x3)
 156 #define PRCM_REQ_MB2_SGA                (PRCM_REQ_MB2 + 0x4)
 157 #define PRCM_REQ_MB2_B2R2_MCDE          (PRCM_REQ_MB2 + 0x5)
 158 #define PRCM_REQ_MB2_ESRAM12            (PRCM_REQ_MB2 + 0x6)
 159 #define PRCM_REQ_MB2_ESRAM34            (PRCM_REQ_MB2 + 0x7)
 160 #define PRCM_REQ_MB2_AUTO_PM_SLEEP      (PRCM_REQ_MB2 + 0x8)
 161 #define PRCM_REQ_MB2_AUTO_PM_IDLE       (PRCM_REQ_MB2 + 0xC)
 162
 163 /* Mailbox 2 ACKs */
 164 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
 165 #define HWACC_PWR_ST_OK 0xFE
 166
 167 /* Mailbox 3 headers */
 168 #define MB3H_ANC        0x0
 169 #define MB3H_SIDETONE   0x1
 170 #define MB3H_SYSCLK     0xE
 171
 172 /* Mailbox 3 Requests */
 173 #define PRCM_REQ_MB3_ANC_FIR_COEFF      (PRCM_REQ_MB3 + 0x0)
 174 #define PRCM_REQ_MB3_ANC_IIR_COEFF      (PRCM_REQ_MB3 + 0x20)
 175 #define PRCM_REQ_MB3_ANC_SHIFTER        (PRCM_REQ_MB3 + 0x60)
 176 #define PRCM_REQ_MB3_ANC_WARP           (PRCM_REQ_MB3 + 0x64)
 177 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN  (PRCM_REQ_MB3 + 0x68)
 178 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
 179 #define PRCM_REQ_MB3_SYSCLK_MGT         (PRCM_REQ_MB3 + 0x16C)
 180
 181 /* Mailbox 4 headers */
 182 #define MB4H_DDR_INIT   0x0
 183 #define MB4H_MEM_ST     0x1
 184 #define MB4H_HOTDOG     0x12
 185 #define MB4H_HOTMON     0x13
 186 #define MB4H_HOT_PERIOD 0x14
 187 #define MB4H_A9WDOG_CONF 0x16
 188 #define MB4H_A9WDOG_EN   0x17
 189 #define MB4H_A9WDOG_DIS  0x18
 190 #define MB4H_A9WDOG_LOAD 0x19
 191 #define MB4H_A9WDOG_KICK 0x20
 192
 193 /* Mailbox 4 Requests */
 194 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE       (PRCM_REQ_MB4 + 0x0)
 195 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE        (PRCM_REQ_MB4 + 0x1)
 196 #define PRCM_REQ_MB4_ESRAM0_ST                  (PRCM_REQ_MB4 + 0x3)
 197 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD           (PRCM_REQ_MB4 + 0x0)
 198 #define PRCM_REQ_MB4_HOTMON_LOW                 (PRCM_REQ_MB4 + 0x0)
 199 #define PRCM_REQ_MB4_HOTMON_HIGH                (PRCM_REQ_MB4 + 0x1)
 200 #define PRCM_REQ_MB4_HOTMON_CONFIG              (PRCM_REQ_MB4 + 0x2)
 201 #define PRCM_REQ_MB4_HOT_PERIOD                 (PRCM_REQ_MB4 + 0x0)
 202 #define HOTMON_CONFIG_LOW                       BIT(0)
 203 #define HOTMON_CONFIG_HIGH                      BIT(1)
 204 #define PRCM_REQ_MB4_A9WDOG_0                   (PRCM_REQ_MB4 + 0x0)
 205 #define PRCM_REQ_MB4_A9WDOG_1                   (PRCM_REQ_MB4 + 0x1)
 206 #define PRCM_REQ_MB4_A9WDOG_2                   (PRCM_REQ_MB4 + 0x2)
 207 #define PRCM_REQ_MB4_A9WDOG_3                   (PRCM_REQ_MB4 + 0x3)
 208 #define A9WDOG_AUTO_OFF_EN                      BIT(7)
 209 #define A9WDOG_AUTO_OFF_DIS                     0
 210 #define A9WDOG_ID_MASK                          0xf
 211
 212 /* Mailbox 5 Requests */
 213 #define PRCM_REQ_MB5_I2C_SLAVE_OP       (PRCM_REQ_MB5 + 0x0)
 214 #define PRCM_REQ_MB5_I2C_HW_BITS        (PRCM_REQ_MB5 + 0x1)
 215 #define PRCM_REQ_MB5_I2C_REG            (PRCM_REQ_MB5 + 0x2)
 216 #define PRCM_REQ_MB5_I2C_VAL            (PRCM_REQ_MB5 + 0x3)
 217 #define PRCMU_I2C_WRITE(slave) \
 218         (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
 219 #define PRCMU_I2C_READ(slave) \
 220         (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
 221 #define PRCMU_I2C_STOP_EN               BIT(3)
 222
 223 /* Mailbox 5 ACKs */
 224 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
 225 #define PRCM_ACK_MB5_I2C_VAL    (PRCM_ACK_MB5 + 0x3)
 226 #define I2C_WR_OK 0x1
 227 #define I2C_RD_OK 0x2
 228
 229 #define NUM_MB 8
 230 #define MBOX_BIT BIT
 231 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
 232
 233 /*
 234  * Wakeups/IRQs
 235  */
 236
 237 #define WAKEUP_BIT_RTC BIT(0)
 238 #define WAKEUP_BIT_RTT0 BIT(1)
 239 #define WAKEUP_BIT_RTT1 BIT(2)
 240 #define WAKEUP_BIT_HSI0 BIT(3)
 241 #define WAKEUP_BIT_HSI1 BIT(4)
 242 #define WAKEUP_BIT_CA_WAKE BIT(5)
 243 #define WAKEUP_BIT_USB BIT(6)
 244 #define WAKEUP_BIT_ABB BIT(7)
 245 #define WAKEUP_BIT_ABB_FIFO BIT(8)
 246 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
 247 #define WAKEUP_BIT_CA_SLEEP BIT(10)
 248 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
 249 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
 250 #define WAKEUP_BIT_ANC_OK BIT(13)
 251 #define WAKEUP_BIT_SW_ERROR BIT(14)
 252 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
 253 #define WAKEUP_BIT_ARM BIT(17)
 254 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
 255 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
 256 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
 257 #define WAKEUP_BIT_GPIO0 BIT(23)
 258 #define WAKEUP_BIT_GPIO1 BIT(24)
 259 #define WAKEUP_BIT_GPIO2 BIT(25)
 260 #define WAKEUP_BIT_GPIO3 BIT(26)
 261 #define WAKEUP_BIT_GPIO4 BIT(27)
 262 #define WAKEUP_BIT_GPIO5 BIT(28)
 263 #define WAKEUP_BIT_GPIO6 BIT(29)
 264 #define WAKEUP_BIT_GPIO7 BIT(30)
 265 #define WAKEUP_BIT_GPIO8 BIT(31)
 266
 267 static struct {
 268         bool valid;
 269         struct prcmu_fw_version version;
 270 } fw_info;
 271
 272 /*
 273  * This vector maps irq numbers to the bits in the bit field used in
 274  * communication with the PRCMU firmware.
 275  *
 276  * The reason for having this is to keep the irq numbers contiguous even though
 277  * the bits in the bit field are not. (The bits also have a tendency to move
 278  * around, to further complicate matters.)
 279  */
 280 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
 281 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
 282 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
 283         IRQ_ENTRY(RTC),
 284         IRQ_ENTRY(RTT0),
 285         IRQ_ENTRY(RTT1),
 286         IRQ_ENTRY(HSI0),
 287         IRQ_ENTRY(HSI1),
 288         IRQ_ENTRY(CA_WAKE),
 289         IRQ_ENTRY(USB),
 290         IRQ_ENTRY(ABB),
 291         IRQ_ENTRY(ABB_FIFO),
 292         IRQ_ENTRY(CA_SLEEP),
 293         IRQ_ENTRY(ARM),
 294         IRQ_ENTRY(HOTMON_LOW),
 295         IRQ_ENTRY(HOTMON_HIGH),
 296         IRQ_ENTRY(MODEM_SW_RESET_REQ),
 297         IRQ_ENTRY(GPIO0),
 298         IRQ_ENTRY(GPIO1),
 299         IRQ_ENTRY(GPIO2),
 300         IRQ_ENTRY(GPIO3),
 301         IRQ_ENTRY(GPIO4),
 302         IRQ_ENTRY(GPIO5),
 303         IRQ_ENTRY(GPIO6),
 304         IRQ_ENTRY(GPIO7),
 305         IRQ_ENTRY(GPIO8)
 306 };
 307
 308 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
 309 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
 310 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
 311         WAKEUP_ENTRY(RTC),
 312         WAKEUP_ENTRY(RTT0),
 313         WAKEUP_ENTRY(RTT1),
 314         WAKEUP_ENTRY(HSI0),
 315         WAKEUP_ENTRY(HSI1),
 316         WAKEUP_ENTRY(USB),
 317         WAKEUP_ENTRY(ABB),
 318         WAKEUP_ENTRY(ABB_FIFO),
 319         WAKEUP_ENTRY(ARM)
 320 };
 321
 322 /*
 323  * mb0_transfer - state needed for mailbox 0 communication.
 324  * @lock:               The transaction lock.
 325  * @dbb_events_lock:    A lock used to handle concurrent access to (parts of)
 326  *                      the request data.
 327  * @mask_work:          Work structure used for (un)masking wakeup interrupts.
 328  * @req:                Request data that need to persist between requests.
 329  */
 330 static struct {
 331         spinlock_t lock;
 332         spinlock_t dbb_irqs_lock;
 333         struct work_struct mask_work;
 334         struct mutex ac_wake_lock;
 335         struct completion ac_wake_work;
 336         struct {
 337                 u32 dbb_irqs;
 338                 u32 dbb_wakeups;
 339                 u32 abb_events;
 340         } req;
 341 } mb0_transfer;
 342
 343 /*
 344  * mb1_transfer - state needed for mailbox 1 communication.
 345  * @lock:       The transaction lock.
 346  * @work:       The transaction completion structure.
 347  * @ape_opp:    The current APE OPP.
 348  * @ack:        Reply ("acknowledge") data.
 349  */
 350 static struct {
 351         struct mutex lock;
 352         struct completion work;
 353         u8 ape_opp;
 354         struct {
 355                 u8 header;
 356                 u8 arm_opp;
 357                 u8 ape_opp;
 358                 u8 ape_voltage_status;
 359         } ack;
 360 } mb1_transfer;
 361
 362 /*
 363  * mb2_transfer - state needed for mailbox 2 communication.
 364  * @lock:            The transaction lock.
 365  * @work:            The transaction completion structure.
 366  * @auto_pm_lock:    The autonomous power management configuration lock.
 367  * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
 368  * @req:             Request data that need to persist between requests.
 369  * @ack:             Reply ("acknowledge") data.
 370  */
 371 static struct {
 372         struct mutex lock;
 373         struct completion work;
 374         spinlock_t auto_pm_lock;
 375         bool auto_pm_enabled;
 376         struct {
 377                 u8 status;
 378         } ack;
 379 } mb2_transfer;
 380
 381 /*
 382  * mb3_transfer - state needed for mailbox 3 communication.
 383  * @lock:               The request lock.
 384  * @sysclk_lock:        A lock used to handle concurrent sysclk requests.
 385  * @sysclk_work:        Work structure used for sysclk requests.
 386  */
 387 static struct {
 388         spinlock_t lock;
 389         struct mutex sysclk_lock;
 390         struct completion sysclk_work;
 391 } mb3_transfer;
 392
 393 /*
 394  * mb4_transfer - state needed for mailbox 4 communication.
 395  * @lock:       The transaction lock.
 396  * @work:       The transaction completion structure.
 397  */
 398 static struct {
 399         struct mutex lock;
 400         struct completion work;
 401 } mb4_transfer;
 402
 403 /*
 404  * mb5_transfer - state needed for mailbox 5 communication.
 405  * @lock:       The transaction lock.
 406  * @work:       The transaction completion structure.
 407  * @ack:        Reply ("acknowledge") data.
 408  */
 409 static struct {
 410         struct mutex lock;
 411         struct completion work;
 412         struct {
 413                 u8 status;
 414                 u8 value;
 415         } ack;
 416 } mb5_transfer;
 417
 418 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
 419
 420 /* Spinlocks */
 421 static DEFINE_SPINLOCK(prcmu_lock);
 422 static DEFINE_SPINLOCK(clkout_lock);
 423
 424 /* Global var to runtime determine TCDM base for v2 or v1 */
 425 static __iomem void *tcdm_base;
 426
 427 struct clk_mgt {
 428         void __iomem *reg;
 429         u32 pllsw;
 430         int branch;
 431         bool clk38div;
 432 };
 433
 434 enum {
 435         PLL_RAW,
 436         PLL_FIX,
 437         PLL_DIV
 438 };
 439
 440 static DEFINE_SPINLOCK(clk_mgt_lock);
 441
 442 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
 443         { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
 444 struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
 445         CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
 446         CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
 447         CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
 448         CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
 449         CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
 450         CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
 451         CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
 452         CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
 453         CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
 454         CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
 455         CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
 456         CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
 457         CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
 458         CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
 459         CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
 460         CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
 461         CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
 462         CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
 463         CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
 464         CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
 465         CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
 466         CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
 467         CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
 468         CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
 469         CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
 470         CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
 471         CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
 472         CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
 473         CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
 474 };
 475
 476 struct dsiclk {
 477         u32 divsel_mask;
 478         u32 divsel_shift;
 479         u32 divsel;
 480 };
 481
 482 static struct dsiclk dsiclk[2] = {
 483         {
 484                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
 485                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
 486                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 487         },
 488         {
 489                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
 490                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
 491                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 492         }
 493 };
 494
 495 struct dsiescclk {
 496         u32 en;
 497         u32 div_mask;
 498         u32 div_shift;
 499 };
 500
 501 static struct dsiescclk dsiescclk[3] = {
 502         {
 503                 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
 504                 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
 505                 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
 506         },
 507         {
 508                 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
 509                 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
 510                 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
 511         },
 512         {
 513                 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
 514                 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
 515                 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
 516         }
 517 };
 518
 519 static struct regulator *hwacc_regulator[NUM_HW_ACC];
 520 static struct regulator *hwacc_ret_regulator[NUM_HW_ACC];
 521
 522 static bool hwacc_enabled[NUM_HW_ACC];
 523 static bool hwacc_ret_enabled[NUM_HW_ACC];
 524
 525 static const char *hwacc_regulator_name[NUM_HW_ACC] = {
 526         [HW_ACC_SVAMMDSP]       = "hwacc-sva-mmdsp",
 527         [HW_ACC_SVAPIPE]        = "hwacc-sva-pipe",
 528         [HW_ACC_SIAMMDSP]       = "hwacc-sia-mmdsp",
 529         [HW_ACC_SIAPIPE]        = "hwacc-sia-pipe",
 530         [HW_ACC_SGA]            = "hwacc-sga",
 531         [HW_ACC_B2R2]           = "hwacc-b2r2",
 532         [HW_ACC_MCDE]           = "hwacc-mcde",
 533         [HW_ACC_ESRAM1]         = "hwacc-esram1",
 534         [HW_ACC_ESRAM2]         = "hwacc-esram2",
 535         [HW_ACC_ESRAM3]         = "hwacc-esram3",
 536         [HW_ACC_ESRAM4]         = "hwacc-esram4",
 537 };
 538
 539 static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = {
 540         [HW_ACC_SVAMMDSP]       = "hwacc-sva-mmdsp-ret",
 541         [HW_ACC_SIAMMDSP]       = "hwacc-sia-mmdsp-ret",
 542         [HW_ACC_ESRAM1]         = "hwacc-esram1-ret",
 543         [HW_ACC_ESRAM2]         = "hwacc-esram2-ret",
 544         [HW_ACC_ESRAM3]         = "hwacc-esram3-ret",
 545         [HW_ACC_ESRAM4]         = "hwacc-esram4-ret",
 546 };
 547
 548 /*
 549 * Used by MCDE to setup all necessary PRCMU registers
 550 */
 551 #define PRCMU_RESET_DSIPLL              0x00004000
 552 #define PRCMU_UNCLAMP_DSIPLL            0x00400800
 553
 554 #define PRCMU_CLK_PLL_DIV_SHIFT         0
 555 #define PRCMU_CLK_PLL_SW_SHIFT          5
 556 #define PRCMU_CLK_38                    (1 << 9)
 557 #define PRCMU_CLK_38_SRC                (1 << 10)
 558 #define PRCMU_CLK_38_DIV                (1 << 11)
 559
 560 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
 561 #define PRCMU_DSI_CLOCK_SETTING         0x0000008C
 562
 563 /* DPI 50000000 Hz */
 564 #define PRCMU_DPI_CLOCK_SETTING         ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
 565                                           (16 << PRCMU_CLK_PLL_DIV_SHIFT))
 566 #define PRCMU_DSI_LP_CLOCK_SETTING      0x00000E00
 567
 568 /* D=101, N=1, R=4, SELDIV2=0 */
 569 #define PRCMU_PLLDSI_FREQ_SETTING       0x00040165
 570
 571 #define PRCMU_ENABLE_PLLDSI             0x00000001
 572 #define PRCMU_DISABLE_PLLDSI            0x00000000
 573 #define PRCMU_RELEASE_RESET_DSS         0x0000400C
 574 #define PRCMU_DSI_PLLOUT_SEL_SETTING    0x00000202
 575 /* ESC clk, div0=1, div1=1, div2=3 */
 576 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV   0x07030101
 577 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV  0x00030101
 578 #define PRCMU_DSI_RESET_SW              0x00000007
 579
 580 #define PRCMU_PLLDSI_LOCKP_LOCKED       0x3
 581
 582 int db8500_prcmu_enable_dsipll(void)
 583 {
 584         int i;
 585
 586         /* Clear DSIPLL_RESETN */
 587         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
 588         /* Unclamp DSIPLL in/out */
 589         writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
 590
 591         /* Set DSI PLL FREQ */
 592         writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
 593         writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
 594         /* Enable Escape clocks */
 595         writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 596
 597         /* Start DSI PLL */
 598         writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 599         /* Reset DSI PLL */
 600         writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
 601         for (i = 0; i < 10; i++) {
 602                 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
 603                                         == PRCMU_PLLDSI_LOCKP_LOCKED)
 604                         break;
 605                 udelay(100);
 606         }
 607         /* Set DSIPLL_RESETN */
 608         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
 609         return 0;
 610 }
 611
 612 int db8500_prcmu_disable_dsipll(void)
 613 {
 614         /* Disable dsi pll */
 615         writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 616         /* Disable  escapeclock */
 617         writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 618         return 0;
 619 }
 620
 621 int db8500_prcmu_set_display_clocks(void)
 622 {
 623         unsigned long flags;
 624
 625         spin_lock_irqsave(&clk_mgt_lock, flags);
 626
 627         /* Grab the HW semaphore. */
 628         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
 629                 cpu_relax();
 630
 631         writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
 632         writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
 633         writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT);
 634
 635         /* Release the HW semaphore. */
 636         writel(0, PRCM_SEM);
 637
 638         spin_unlock_irqrestore(&clk_mgt_lock, flags);
 639
 640         return 0;
 641 }
 642
 643 u32 db8500_prcmu_read(unsigned int reg)
 644 {
 645         return readl(_PRCMU_BASE + reg);
 646 }
 647
 648 void db8500_prcmu_write(unsigned int reg, u32 value)
 649 {
 650         unsigned long flags;
 651
 652         spin_lock_irqsave(&prcmu_lock, flags);
 653         writel(value, (_PRCMU_BASE + reg));
 654         spin_unlock_irqrestore(&prcmu_lock, flags);
 655 }
 656
 657 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
 658 {
 659         u32 val;
 660         unsigned long flags;
 661
 662         spin_lock_irqsave(&prcmu_lock, flags);
 663         val = readl(_PRCMU_BASE + reg);
 664         val = ((val & ~mask) | (value & mask));
 665         writel(val, (_PRCMU_BASE + reg));
 666         spin_unlock_irqrestore(&prcmu_lock, flags);
 667 }
 668
 669 struct prcmu_fw_version *prcmu_get_fw_version(void)
 670 {
 671         return fw_info.valid ? &fw_info.version : NULL;
 672 }
 673
 674 bool prcmu_has_arm_maxopp(void)
 675 {
 676         return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
 677                 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
 678 }
 679
 680 /**
 681  * prcmu_get_boot_status - PRCMU boot status checking
 682  * Returns: the current PRCMU boot status
 683  */
 684 int prcmu_get_boot_status(void)
 685 {
 686         return readb(tcdm_base + PRCM_BOOT_STATUS);
 687 }
 688
 689 /**
 690  * prcmu_set_rc_a2p - This function is used to run few power state sequences
 691  * @val: Value to be set, i.e. transition requested
 692  * Returns: 0 on success, -EINVAL on invalid argument
 693  *
 694  * This function is used to run the following power state sequences -
 695  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 696  */
 697 int prcmu_set_rc_a2p(enum romcode_write val)
 698 {
 699         if (val < RDY_2_DS || val > RDY_2_XP70_RST)
 700                 return -EINVAL;
 701         writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
 702         return 0;
 703 }
 704
 705 /**
 706  * prcmu_get_rc_p2a - This function is used to get power state sequences
 707  * Returns: the power transition that has last happened
 708  *
 709  * This function can return the following transitions-
 710  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 711  */
 712 enum romcode_read prcmu_get_rc_p2a(void)
 713 {
 714         return readb(tcdm_base + PRCM_ROMCODE_P2A);
 715 }
 716
 717 /**
 718  * prcmu_get_current_mode - Return the current XP70 power mode
 719  * Returns: Returns the current AP(ARM) power mode: init,
 720  * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
 721  */
 722 enum ap_pwrst prcmu_get_xp70_current_state(void)
 723 {
 724         return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
 725 }
 726
 727 /**
 728  * prcmu_config_clkout - Configure one of the programmable clock outputs.
 729  * @clkout:     The CLKOUT number (0 or 1).
 730  * @source:     The clock to be used (one of the PRCMU_CLKSRC_*).
 731  * @div:        The divider to be applied.
 732  *
 733  * Configures one of the programmable clock outputs (CLKOUTs).
 734  * @div should be in the range [1,63] to request a configuration, or 0 to
 735  * inform that the configuration is no longer requested.
 736  */
 737 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
 738 {
 739         static int requests[2];
 740         int r = 0;
 741         unsigned long flags;
 742         u32 val;
 743         u32 bits;
 744         u32 mask;
 745         u32 div_mask;
 746
 747         BUG_ON(clkout > 1);
 748         BUG_ON(div > 63);
 749         BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
 750
 751         if (!div && !requests[clkout])
 752                 return -EINVAL;
 753
 754         switch (clkout) {
 755         case 0:
 756                 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
 757                 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
 758                 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
 759                         (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
 760                 break;
 761         case 1:
 762                 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
 763                 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
 764                         PRCM_CLKOCR_CLK1TYPE);
 765                 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
 766                         (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
 767                 break;
 768         }
 769         bits &= mask;
 770
 771         spin_lock_irqsave(&clkout_lock, flags);
 772
 773         val = readl(PRCM_CLKOCR);
 774         if (val & div_mask) {
 775                 if (div) {
 776                         if ((val & mask) != bits) {
 777                                 r = -EBUSY;
 778                                 goto unlock_and_return;
 779                         }
 780                 } else {
 781                         if ((val & mask & ~div_mask) != bits) {
 782                                 r = -EINVAL;
 783                                 goto unlock_and_return;
 784                         }
 785                 }
 786         }
 787         writel((bits | (val & ~mask)), PRCM_CLKOCR);
 788         requests[clkout] += (div ? 1 : -1);
 789
 790 unlock_and_return:
 791         spin_unlock_irqrestore(&clkout_lock, flags);
 792
 793         return r;
 794 }
 795
 796 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
 797 {
 798         unsigned long flags;
 799
 800         BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
 801
 802         spin_lock_irqsave(&mb0_transfer.lock, flags);
 803
 804         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 805                 cpu_relax();
 806
 807         writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 808         writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
 809         writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
 810         writeb((keep_ulp_clk ? 1 : 0),
 811                 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
 812         writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
 813         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 814
 815         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 816
 817         return 0;
 818 }
 819
 820 u8 db8500_prcmu_get_power_state_result(void)
 821 {
 822         return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
 823 }
 824
 825 /* This function decouple the gic from the prcmu */
 826 int db8500_prcmu_gic_decouple(void)
 827 {
 828         u32 val = readl(PRCM_A9_MASK_REQ);
 829
 830         /* Set bit 0 register value to 1 */
 831         writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
 832                PRCM_A9_MASK_REQ);
 833
 834         /* Make sure the register is updated */
 835         readl(PRCM_A9_MASK_REQ);
 836
 837         /* Wait a few cycles for the gic mask completion */
 838         udelay(1);
 839
 840         return 0;
 841 }
 842
 843 /* This function recouple the gic with the prcmu */
 844 int db8500_prcmu_gic_recouple(void)
 845 {
 846         u32 val = readl(PRCM_A9_MASK_REQ);
 847
 848         /* Set bit 0 register value to 0 */
 849         writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
 850
 851         return 0;
 852 }
 853
 854 #define PRCMU_GIC_NUMBER_REGS 5
 855
 856 /*
 857  * This function checks if there are pending irq on the gic. It only
 858  * makes sense if the gic has been decoupled before with the
 859  * db8500_prcmu_gic_decouple function. Disabling an interrupt only
 860  * disables the forwarding of the interrupt to any CPU interface. It
 861  * does not prevent the interrupt from changing state, for example
 862  * becoming pending, or active and pending if it is already
 863  * active. Hence, we have to check the interrupt is pending *and* is
 864  * active.
 865  */
 866 bool db8500_prcmu_gic_pending_irq(void)
 867 {
 868         u32 pr; /* Pending register */
 869         u32 er; /* Enable register */
 870         void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
 871         int i;
 872
 873         /* 5 registers. STI & PPI not skipped */
 874         for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
 875
 876                 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
 877                 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 878
 879                 if (pr & er)
 880                         return true; /* There is a pending interrupt */
 881         }
 882
 883         return false;
 884 }
 885
 886 /*
 887  * This function checks if there are pending interrupt on the
 888  * prcmu which has been delegated to monitor the irqs with the
 889  * db8500_prcmu_copy_gic_settings function.
 890  */
 891 bool db8500_prcmu_pending_irq(void)
 892 {
 893         u32 it, im;
 894         int i;
 895
 896         for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
 897                 it = readl(PRCM_ARMITVAL31TO0 + i * 4);
 898                 im = readl(PRCM_ARMITMSK31TO0 + i * 4);
 899                 if (it & im)
 900                         return true; /* There is a pending interrupt */
 901         }
 902
 903         return false;
 904 }
 905
 906 /*
 907  * This function checks if the specified cpu is in in WFI. It's usage
 908  * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
 909  * function. Of course passing smp_processor_id() to this function will
 910  * always return false...
 911  */
 912 bool db8500_prcmu_is_cpu_in_wfi(int cpu)
 913 {
 914         return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
 915                      PRCM_ARM_WFI_STANDBY_WFI0;
 916 }
 917
 918 /*
 919  * This function copies the gic SPI settings to the prcmu in order to
 920  * monitor them and abort/finish the retention/off sequence or state.
 921  */
 922 int db8500_prcmu_copy_gic_settings(void)
 923 {
 924         u32 er; /* Enable register */
 925         void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
 926         int i;
 927
 928         /* We skip the STI and PPI */
 929         for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
 930                 er = readl_relaxed(dist_base +
 931                                    GIC_DIST_ENABLE_SET + (i + 1) * 4);
 932                 writel(er, PRCM_ARMITMSK31TO0 + i * 4);
 933         }
 934
 935         return 0;
 936 }
 937
 938 /* This function should only be called while mb0_transfer.lock is held. */
 939 static void config_wakeups(void)
 940 {
 941         const u8 header[2] = {
 942                 MB0H_CONFIG_WAKEUPS_EXE,
 943                 MB0H_CONFIG_WAKEUPS_SLEEP
 944         };
 945         static u32 last_dbb_events;
 946         static u32 last_abb_events;
 947         u32 dbb_events;
 948         u32 abb_events;
 949         unsigned int i;
 950
 951         dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
 952         dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
 953
 954         abb_events = mb0_transfer.req.abb_events;
 955
 956         if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
 957                 return;
 958
 959         for (i = 0; i < 2; i++) {
 960                 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 961                         cpu_relax();
 962                 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
 963                 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
 964                 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 965                 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 966         }
 967         last_dbb_events = dbb_events;
 968         last_abb_events = abb_events;
 969 }
 970
 971 void db8500_prcmu_enable_wakeups(u32 wakeups)
 972 {
 973         unsigned long flags;
 974         u32 bits;
 975         int i;
 976
 977         BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
 978
 979         for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
 980                 if (wakeups & BIT(i))
 981                         bits |= prcmu_wakeup_bit[i];
 982         }
 983
 984         spin_lock_irqsave(&mb0_transfer.lock, flags);
 985
 986         mb0_transfer.req.dbb_wakeups = bits;
 987         config_wakeups();
 988
 989         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 990 }
 991
 992 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
 993 {
 994         unsigned long flags;
 995
 996         spin_lock_irqsave(&mb0_transfer.lock, flags);
 997
 998         mb0_transfer.req.abb_events = abb_events;
 999         config_wakeups();
1000
1001         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
1002 }
1003
1004 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
1005 {
1006         if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
1007                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
1008         else
1009                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
1010 }
1011
1012 /**
1013  * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
1014  * @opp: The new ARM operating point to which transition is to be made
1015  * Returns: 0 on success, non-zero on failure
1016  *
1017  * This function sets the the operating point of the ARM.
1018  */
1019 int db8500_prcmu_set_arm_opp(u8 opp)
1020 {
1021         int r;
1022
1023         if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
1024                 return -EINVAL;
1025
1026         r = 0;
1027
1028         mutex_lock(&mb1_transfer.lock);
1029
1030         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1031                 cpu_relax();
1032
1033         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1034         writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1035         writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1036
1037         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1038         wait_for_completion(&mb1_transfer.work);
1039
1040         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1041                 (mb1_transfer.ack.arm_opp != opp))
1042                 r = -EIO;
1043
1044         mutex_unlock(&mb1_transfer.lock);
1045
1046         return r;
1047 }
1048
1049 /**
1050  * db8500_prcmu_get_arm_opp - get the current ARM OPP
1051  *
1052  * Returns: the current ARM OPP
1053  */
1054 int db8500_prcmu_get_arm_opp(void)
1055 {
1056         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
1057 }
1058
1059 /**
1060  * db8500_prcmu_get_ddr_opp - get the current DDR OPP
1061  *
1062  * Returns: the current DDR OPP
1063  */
1064 int db8500_prcmu_get_ddr_opp(void)
1065 {
1066         return readb(PRCM_DDR_SUBSYS_APE_MINBW);
1067 }
1068
1069 /**
1070  * db8500_set_ddr_opp - set the appropriate DDR OPP
1071  * @opp: The new DDR operating point to which transition is to be made
1072  * Returns: 0 on success, non-zero on failure
1073  *
1074  * This function sets the operating point of the DDR.
1075  */
1076 int db8500_prcmu_set_ddr_opp(u8 opp)
1077 {
1078         if (opp < DDR_100_OPP || opp > DDR_25_OPP)
1079                 return -EINVAL;
1080         /* Changing the DDR OPP can hang the hardware pre-v21 */
1081         if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
1082                 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
1083
1084         return 0;
1085 }
1086
1087 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
1088 static void request_even_slower_clocks(bool enable)
1089 {
1090         void __iomem *clock_reg[] = {
1091                 PRCM_ACLK_MGT,
1092                 PRCM_DMACLK_MGT
1093         };
1094         unsigned long flags;
1095         unsigned int i;
1096
1097         spin_lock_irqsave(&clk_mgt_lock, flags);
1098
1099         /* Grab the HW semaphore. */
1100         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1101                 cpu_relax();
1102
1103         for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
1104                 u32 val;
1105                 u32 div;
1106
1107                 val = readl(clock_reg[i]);
1108                 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
1109                 if (enable) {
1110                         if ((div <= 1) || (div > 15)) {
1111                                 pr_err("prcmu: Bad clock divider %d in %s\n",
1112                                         div, __func__);
1113                                 goto unlock_and_return;
1114                         }
1115                         div <<= 1;
1116                 } else {
1117                         if (div <= 2)
1118                                 goto unlock_and_return;
1119                         div >>= 1;
1120                 }
1121                 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1122                         (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1123                 writel(val, clock_reg[i]);
1124         }
1125
1126 unlock_and_return:
1127         /* Release the HW semaphore. */
1128         writel(0, PRCM_SEM);
1129
1130         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1131 }
1132
1133 /**
1134  * db8500_set_ape_opp - set the appropriate APE OPP
1135  * @opp: The new APE operating point to which transition is to be made
1136  * Returns: 0 on success, non-zero on failure
1137  *
1138  * This function sets the operating point of the APE.
1139  */
1140 int db8500_prcmu_set_ape_opp(u8 opp)
1141 {
1142         int r = 0;
1143
1144         if (opp == mb1_transfer.ape_opp)
1145                 return 0;
1146
1147         mutex_lock(&mb1_transfer.lock);
1148
1149         if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1150                 request_even_slower_clocks(false);
1151
1152         if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1153                 goto skip_message;
1154
1155         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1156                 cpu_relax();
1157
1158         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1159         writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1160         writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1161                 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1162
1163         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1164         wait_for_completion(&mb1_transfer.work);
1165
1166         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1167                 (mb1_transfer.ack.ape_opp != opp))
1168                 r = -EIO;
1169
1170 skip_message:
1171         if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1172                 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1173                 request_even_slower_clocks(true);
1174         if (!r)
1175                 mb1_transfer.ape_opp = opp;
1176
1177         mutex_unlock(&mb1_transfer.lock);
1178
1179         return r;
1180 }
1181
1182 /**
1183  * db8500_prcmu_get_ape_opp - get the current APE OPP
1184  *
1185  * Returns: the current APE OPP
1186  */
1187 int db8500_prcmu_get_ape_opp(void)
1188 {
1189         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1190 }
1191
1192 /**
1193  * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1194  * @enable: true to request the higher voltage, false to drop a request.
1195  *
1196  * Calls to this function to enable and disable requests must be balanced.
1197  */
1198 int prcmu_request_ape_opp_100_voltage(bool enable)
1199 {
1200         int r = 0;
1201         u8 header;
1202         static unsigned int requests;
1203
1204         mutex_lock(&mb1_transfer.lock);
1205
1206         if (enable) {
1207                 if (0 != requests++)
1208                         goto unlock_and_return;
1209                 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1210         } else {
1211                 if (requests == 0) {
1212                         r = -EIO;
1213                         goto unlock_and_return;
1214                 } else if (1 != requests--) {
1215                         goto unlock_and_return;
1216                 }
1217                 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1218         }
1219
1220         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1221                 cpu_relax();
1222
1223         writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1224
1225         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1226         wait_for_completion(&mb1_transfer.work);
1227
1228         if ((mb1_transfer.ack.header != header) ||
1229                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1230                 r = -EIO;
1231
1232 unlock_and_return:
1233         mutex_unlock(&mb1_transfer.lock);
1234
1235         return r;
1236 }
1237
1238 /**
1239  * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1240  *
1241  * This function releases the power state requirements of a USB wakeup.
1242  */
1243 int prcmu_release_usb_wakeup_state(void)
1244 {
1245         int r = 0;
1246
1247         mutex_lock(&mb1_transfer.lock);
1248
1249         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1250                 cpu_relax();
1251
1252         writeb(MB1H_RELEASE_USB_WAKEUP,
1253                 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1254
1255         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1256         wait_for_completion(&mb1_transfer.work);
1257
1258         if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1259                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1260                 r = -EIO;
1261
1262         mutex_unlock(&mb1_transfer.lock);
1263
1264         return r;
1265 }
1266
1267 static int request_pll(u8 clock, bool enable)
1268 {
1269         int r = 0;
1270
1271         if (clock == PRCMU_PLLSOC0)
1272                 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1273         else if (clock == PRCMU_PLLSOC1)
1274                 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1275         else
1276                 return -EINVAL;
1277
1278         mutex_lock(&mb1_transfer.lock);
1279
1280         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1281                 cpu_relax();
1282
1283         writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1284         writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1285
1286         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1287         wait_for_completion(&mb1_transfer.work);
1288
1289         if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1290                 r = -EIO;
1291
1292         mutex_unlock(&mb1_transfer.lock);
1293
1294         return r;
1295 }
1296
1297 /**
1298  * prcmu_set_hwacc - set the power state of a h/w accelerator
1299  * @hwacc_dev: The hardware accelerator (enum hw_acc_dev).
1300  * @state: The new power state (enum hw_acc_state).
1301  *
1302  * This function sets the power state of a hardware accelerator.
1303  * This function should not be called from interrupt context.
1304  *
1305  * NOTE! Deprecated, to be removed when all users switched over to use the
1306  * regulator framework API.
1307  */
1308 int prcmu_set_hwacc(u16 hwacc_dev, u8 state)
1309 {
1310         int r = 0;
1311         bool ram_retention = false;
1312         bool enable, enable_ret;
1313
1314         /* check argument */
1315         BUG_ON(hwacc_dev >= NUM_HW_ACC);
1316
1317         /* get state of switches */
1318         enable = hwacc_enabled[hwacc_dev];
1319         enable_ret = hwacc_ret_enabled[hwacc_dev];
1320
1321         /* set flag if retention is possible */
1322         switch (hwacc_dev) {
1323         case HW_ACC_SVAMMDSP:
1324         case HW_ACC_SIAMMDSP:
1325         case HW_ACC_ESRAM1:
1326         case HW_ACC_ESRAM2:
1327         case HW_ACC_ESRAM3:
1328         case HW_ACC_ESRAM4:
1329                 ram_retention = true;
1330                 break;
1331         }
1332
1333         /* check argument */
1334         BUG_ON(state > HW_ON);
1335         BUG_ON(state == HW_OFF_RAMRET && !ram_retention);
1336
1337         /* modify enable flags */
1338         switch (state) {
1339         case HW_OFF:
1340                 enable_ret = false;
1341                 enable = false;
1342                 break;
1343         case HW_ON:
1344                 enable = true;
1345                 break;
1346         case HW_OFF_RAMRET:
1347                 enable_ret = true;
1348                 enable = false;
1349                 break;
1350         }
1351
1352         /* get regulator (lazy) */
1353         if (hwacc_regulator[hwacc_dev] == NULL) {
1354                 hwacc_regulator[hwacc_dev] = regulator_get(NULL,
1355                         hwacc_regulator_name[hwacc_dev]);
1356                 if (IS_ERR(hwacc_regulator[hwacc_dev])) {
1357                         pr_err("prcmu: failed to get supply %s\n",
1358                                 hwacc_regulator_name[hwacc_dev]);
1359                         r = PTR_ERR(hwacc_regulator[hwacc_dev]);
1360                         goto out;
1361                 }
1362         }
1363
1364         if (ram_retention) {
1365                 if (hwacc_ret_regulator[hwacc_dev] == NULL) {
1366                         hwacc_ret_regulator[hwacc_dev] = regulator_get(NULL,
1367                                 hwacc_ret_regulator_name[hwacc_dev]);
1368                         if (IS_ERR(hwacc_ret_regulator[hwacc_dev])) {
1369                                 pr_err("prcmu: failed to get supply %s\n",
1370                                         hwacc_ret_regulator_name[hwacc_dev]);
1371                                 r = PTR_ERR(hwacc_ret_regulator[hwacc_dev]);
1372                                 goto out;
1373                         }
1374                 }
1375         }
1376
1377         /* set regulators */
1378         if (ram_retention) {
1379                 if (enable_ret && !hwacc_ret_enabled[hwacc_dev]) {
1380                         r = regulator_enable(hwacc_ret_regulator[hwacc_dev]);
1381                         if (r < 0) {
1382                                 pr_err("prcmu_set_hwacc: ret enable failed\n");
1383                                 goto out;
1384                         }
1385                         hwacc_ret_enabled[hwacc_dev] = true;
1386                 }
1387         }
1388
1389         if (enable && !hwacc_enabled[hwacc_dev]) {
1390                 r = regulator_enable(hwacc_regulator[hwacc_dev]);
1391                 if (r < 0) {
1392                         pr_err("prcmu_set_hwacc: enable failed\n");
1393                         goto out;
1394                 }
1395                 hwacc_enabled[hwacc_dev] = true;
1396         }
1397
1398         if (!enable && hwacc_enabled[hwacc_dev]) {
1399                 r = regulator_disable(hwacc_regulator[hwacc_dev]);
1400                 if (r < 0) {
1401                         pr_err("prcmu_set_hwacc: disable failed\n");
1402                         goto out;
1403                 }
1404                 hwacc_enabled[hwacc_dev] = false;
1405         }
1406
1407         if (ram_retention) {
1408                 if (!enable_ret && hwacc_ret_enabled[hwacc_dev]) {
1409                         r = regulator_disable(hwacc_ret_regulator[hwacc_dev]);
1410                         if (r < 0) {
1411                                 pr_err("prcmu_set_hwacc: ret disable failed\n");
1412                                 goto out;
1413                         }
1414                         hwacc_ret_enabled[hwacc_dev] = false;
1415                 }
1416         }
1417
1418 out:
1419         return r;
1420 }
1421 EXPORT_SYMBOL(prcmu_set_hwacc);
1422
1423 /**
1424  * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1425  * @epod_id: The EPOD to set
1426  * @epod_state: The new EPOD state
1427  *
1428  * This function sets the state of a EPOD (power domain). It may not be called
1429  * from interrupt context.
1430  */
1431 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1432 {
1433         int r = 0;
1434         bool ram_retention = false;
1435         int i;
1436
1437         /* check argument */
1438         BUG_ON(epod_id >= NUM_EPOD_ID);
1439
1440         /* set flag if retention is possible */
1441         switch (epod_id) {
1442         case EPOD_ID_SVAMMDSP:
1443         case EPOD_ID_SIAMMDSP:
1444         case EPOD_ID_ESRAM12:
1445         case EPOD_ID_ESRAM34:
1446                 ram_retention = true;
1447                 break;
1448         }
1449
1450         /* check argument */
1451         BUG_ON(epod_state > EPOD_STATE_ON);
1452         BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1453
1454         /* get lock */
1455         mutex_lock(&mb2_transfer.lock);
1456
1457         /* wait for mailbox */
1458         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1459                 cpu_relax();
1460
1461         /* fill in mailbox */
1462         for (i = 0; i < NUM_EPOD_ID; i++)
1463                 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1464         writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1465
1466         writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1467
1468         writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1469
1470         /*
1471          * The current firmware version does not handle errors correctly,
1472          * and we cannot recover if there is an error.
1473          * This is expected to change when the firmware is updated.
1474          */
1475         if (!wait_for_completion_timeout(&mb2_transfer.work,
1476                         msecs_to_jiffies(20000))) {
1477                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1478                         __func__);
1479                 r = -EIO;
1480                 goto unlock_and_return;
1481         }
1482
1483         if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1484                 r = -EIO;
1485
1486 unlock_and_return:
1487         mutex_unlock(&mb2_transfer.lock);
1488         return r;
1489 }
1490
1491 /**
1492  * prcmu_configure_auto_pm - Configure autonomous power management.
1493  * @sleep: Configuration for ApSleep.
1494  * @idle:  Configuration for ApIdle.
1495  */
1496 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1497         struct prcmu_auto_pm_config *idle)
1498 {
1499         u32 sleep_cfg;
1500         u32 idle_cfg;
1501         unsigned long flags;
1502
1503         BUG_ON((sleep == NULL) || (idle == NULL));
1504
1505         sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1506         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1507         sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1508         sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1509         sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1510         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1511
1512         idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1513         idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1514         idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1515         idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1516         idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1517         idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1518
1519         spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1520
1521         /*
1522          * The autonomous power management configuration is done through
1523          * fields in mailbox 2, but these fields are only used as shared
1524          * variables - i.e. there is no need to send a message.
1525          */
1526         writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1527         writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1528
1529         mb2_transfer.auto_pm_enabled =
1530                 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1531                  (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1532                  (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1533                  (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1534
1535         spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1536 }
1537 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1538
1539 bool prcmu_is_auto_pm_enabled(void)
1540 {
1541         return mb2_transfer.auto_pm_enabled;
1542 }
1543
1544 static int request_sysclk(bool enable)
1545 {
1546         int r;
1547         unsigned long flags;
1548
1549         r = 0;
1550
1551         mutex_lock(&mb3_transfer.sysclk_lock);
1552
1553         spin_lock_irqsave(&mb3_transfer.lock, flags);
1554
1555         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1556                 cpu_relax();
1557
1558         writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1559
1560         writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1561         writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1562
1563         spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1564
1565         /*
1566          * The firmware only sends an ACK if we want to enable the
1567          * SysClk, and it succeeds.
1568          */
1569         if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1570                         msecs_to_jiffies(20000))) {
1571                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1572                         __func__);
1573                 r = -EIO;
1574         }
1575
1576         mutex_unlock(&mb3_transfer.sysclk_lock);
1577
1578         return r;
1579 }
1580
1581 static int request_timclk(bool enable)
1582 {
1583         u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1584
1585         if (!enable)
1586                 val |= PRCM_TCR_STOP_TIMERS;
1587         writel(val, PRCM_TCR);
1588
1589         return 0;
1590 }
1591
1592 static int request_clock(u8 clock, bool enable)
1593 {
1594         u32 val;
1595         unsigned long flags;
1596
1597         spin_lock_irqsave(&clk_mgt_lock, flags);
1598
1599         /* Grab the HW semaphore. */
1600         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1601                 cpu_relax();
1602
1603         val = readl(clk_mgt[clock].reg);
1604         if (enable) {
1605                 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1606         } else {
1607                 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1608                 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1609         }
1610         writel(val, clk_mgt[clock].reg);
1611
1612         /* Release the HW semaphore. */
1613         writel(0, PRCM_SEM);
1614
1615         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1616
1617         return 0;
1618 }
1619
1620 static int request_sga_clock(u8 clock, bool enable)
1621 {
1622         u32 val;
1623         int ret;
1624
1625         if (enable) {
1626                 val = readl(PRCM_CGATING_BYPASS);
1627                 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1628         }
1629
1630         ret = request_clock(clock, enable);
1631
1632         if (!ret && !enable) {
1633                 val = readl(PRCM_CGATING_BYPASS);
1634                 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1635         }
1636
1637         return ret;
1638 }
1639
1640 static inline bool plldsi_locked(void)
1641 {
1642         return (readl(PRCM_PLLDSI_LOCKP) &
1643                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1644                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1645                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1646                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1647 }
1648
1649 static int request_plldsi(bool enable)
1650 {
1651         int r = 0;
1652         u32 val;
1653
1654         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1655                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1656                 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1657
1658         val = readl(PRCM_PLLDSI_ENABLE);
1659         if (enable)
1660                 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1661         else
1662                 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1663         writel(val, PRCM_PLLDSI_ENABLE);
1664
1665         if (enable) {
1666                 unsigned int i;
1667                 bool locked = plldsi_locked();
1668
1669                 for (i = 10; !locked && (i > 0); --i) {
1670                         udelay(100);
1671                         locked = plldsi_locked();
1672                 }
1673                 if (locked) {
1674                         writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1675                                 PRCM_APE_RESETN_SET);
1676                 } else {
1677                         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1678                                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1679                                 PRCM_MMIP_LS_CLAMP_SET);
1680                         val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1681                         writel(val, PRCM_PLLDSI_ENABLE);
1682                         r = -EAGAIN;
1683                 }
1684         } else {
1685                 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1686         }
1687         return r;
1688 }
1689
1690 static int request_dsiclk(u8 n, bool enable)
1691 {
1692         u32 val;
1693
1694         val = readl(PRCM_DSI_PLLOUT_SEL);
1695         val &= ~dsiclk[n].divsel_mask;
1696         val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1697                 dsiclk[n].divsel_shift);
1698         writel(val, PRCM_DSI_PLLOUT_SEL);
1699         return 0;
1700 }
1701
1702 static int request_dsiescclk(u8 n, bool enable)
1703 {
1704         u32 val;
1705
1706         val = readl(PRCM_DSITVCLK_DIV);
1707         enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1708         writel(val, PRCM_DSITVCLK_DIV);
1709         return 0;
1710 }
1711
1712 /**
1713  * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1714  * @clock:      The clock for which the request is made.
1715  * @enable:     Whether the clock should be enabled (true) or disabled (false).
1716  *
1717  * This function should only be used by the clock implementation.
1718  * Do not use it from any other place!
1719  */
1720 int db8500_prcmu_request_clock(u8 clock, bool enable)
1721 {
1722         if (clock == PRCMU_SGACLK)
1723                 return request_sga_clock(clock, enable);
1724         else if (clock < PRCMU_NUM_REG_CLOCKS)
1725                 return request_clock(clock, enable);
1726         else if (clock == PRCMU_TIMCLK)
1727                 return request_timclk(enable);
1728         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1729                 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1730         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1731                 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1732         else if (clock == PRCMU_PLLDSI)
1733                 return request_plldsi(enable);
1734         else if (clock == PRCMU_SYSCLK)
1735                 return request_sysclk(enable);
1736         else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1737                 return request_pll(clock, enable);
1738         else
1739                 return -EINVAL;
1740 }
1741
1742 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1743         int branch)
1744 {
1745         u64 rate;
1746         u32 val;
1747         u32 d;
1748         u32 div = 1;
1749
1750         val = readl(reg);
1751
1752         rate = src_rate;
1753         rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1754
1755         d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1756         if (d > 1)
1757                 div *= d;
1758
1759         d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1760         if (d > 1)
1761                 div *= d;
1762
1763         if (val & PRCM_PLL_FREQ_SELDIV2)
1764                 div *= 2;
1765
1766         if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1767                 (val & PRCM_PLL_FREQ_DIV2EN) &&
1768                 ((reg == PRCM_PLLSOC0_FREQ) ||
1769                  (reg == PRCM_PLLDDR_FREQ))))
1770                 div *= 2;
1771
1772         (void)do_div(rate, div);
1773
1774         return (unsigned long)rate;
1775 }
1776
1777 #define ROOT_CLOCK_RATE 38400000
1778
1779 static unsigned long clock_rate(u8 clock)
1780 {
1781         u32 val;
1782         u32 pllsw;
1783         unsigned long rate = ROOT_CLOCK_RATE;
1784
1785         val = readl(clk_mgt[clock].reg);
1786
1787         if (val & PRCM_CLK_MGT_CLK38) {
1788                 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1789                         rate /= 2;
1790                 return rate;
1791         }
1792
1793         val |= clk_mgt[clock].pllsw;
1794         pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1795
1796         if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1797                 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1798         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1799                 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1800         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1801                 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1802         else
1803                 return 0;
1804
1805         if ((clock == PRCMU_SGACLK) &&
1806                 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1807                 u64 r = (rate * 10);
1808
1809                 (void)do_div(r, 25);
1810                 return (unsigned long)r;
1811         }
1812         val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1813         if (val)
1814                 return rate / val;
1815         else
1816                 return 0;
1817 }
1818
1819 static unsigned long dsiclk_rate(u8 n)
1820 {
1821         u32 divsel;
1822         u32 div = 1;
1823
1824         divsel = readl(PRCM_DSI_PLLOUT_SEL);
1825         divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1826
1827         if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1828                 divsel = dsiclk[n].divsel;
1829
1830         switch (divsel) {
1831         case PRCM_DSI_PLLOUT_SEL_PHI_4:
1832                 div *= 2;
1833         case PRCM_DSI_PLLOUT_SEL_PHI_2:
1834                 div *= 2;
1835         case PRCM_DSI_PLLOUT_SEL_PHI:
1836                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1837                         PLL_RAW) / div;
1838         default:
1839                 return 0;
1840         }
1841 }
1842
1843 static unsigned long dsiescclk_rate(u8 n)
1844 {
1845         u32 div;
1846
1847         div = readl(PRCM_DSITVCLK_DIV);
1848         div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1849         return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1850 }
1851
1852 unsigned long prcmu_clock_rate(u8 clock)
1853 {
1854         if (clock < PRCMU_NUM_REG_CLOCKS)
1855                 return clock_rate(clock);
1856         else if (clock == PRCMU_TIMCLK)
1857                 return ROOT_CLOCK_RATE / 16;
1858         else if (clock == PRCMU_SYSCLK)
1859                 return ROOT_CLOCK_RATE;
1860         else if (clock == PRCMU_PLLSOC0)
1861                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1862         else if (clock == PRCMU_PLLSOC1)
1863                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1864         else if (clock == PRCMU_PLLDDR)
1865                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1866         else if (clock == PRCMU_PLLDSI)
1867                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1868                         PLL_RAW);
1869         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1870                 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1871         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1872                 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1873         else
1874                 return 0;
1875 }
1876
1877 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1878 {
1879         if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1880                 return ROOT_CLOCK_RATE;
1881         clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1882         if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1883                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1884         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1885                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1886         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1887                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1888         else
1889                 return 0;
1890 }
1891
1892 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1893 {
1894         u32 div;
1895
1896         div = (src_rate / rate);
1897         if (div == 0)
1898                 return 1;
1899         if (rate < (src_rate / div))
1900                 div++;
1901         return div;
1902 }
1903
1904 static long round_clock_rate(u8 clock, unsigned long rate)
1905 {
1906         u32 val;
1907         u32 div;
1908         unsigned long src_rate;
1909         long rounded_rate;
1910
1911         val = readl(clk_mgt[clock].reg);
1912         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1913                 clk_mgt[clock].branch);
1914         div = clock_divider(src_rate, rate);
1915         if (val & PRCM_CLK_MGT_CLK38) {
1916                 if (clk_mgt[clock].clk38div) {
1917                         if (div > 2)
1918                                 div = 2;
1919                 } else {
1920                         div = 1;
1921                 }
1922         } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1923                 u64 r = (src_rate * 10);
1924
1925                 (void)do_div(r, 25);
1926                 if (r <= rate)
1927                         return (unsigned long)r;
1928         }
1929         rounded_rate = (src_rate / min(div, (u32)31));
1930
1931         return rounded_rate;
1932 }
1933
1934 #define MIN_PLL_VCO_RATE 600000000ULL
1935 #define MAX_PLL_VCO_RATE 1680640000ULL
1936
1937 static long round_plldsi_rate(unsigned long rate)
1938 {
1939         long rounded_rate = 0;
1940         unsigned long src_rate;
1941         unsigned long rem;
1942         u32 r;
1943
1944         src_rate = clock_rate(PRCMU_HDMICLK);
1945         rem = rate;
1946
1947         for (r = 7; (rem > 0) && (r > 0); r--) {
1948                 u64 d;
1949
1950                 d = (r * rate);
1951                 (void)do_div(d, src_rate);
1952                 if (d < 6)
1953                         d = 6;
1954                 else if (d > 255)
1955                         d = 255;
1956                 d *= src_rate;
1957                 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1958                         ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1959                         continue;
1960                 (void)do_div(d, r);
1961                 if (rate < d) {
1962                         if (rounded_rate == 0)
1963                                 rounded_rate = (long)d;
1964                         break;
1965                 }
1966                 if ((rate - d) < rem) {
1967                         rem = (rate - d);
1968                         rounded_rate = (long)d;
1969                 }
1970         }
1971         return rounded_rate;
1972 }
1973
1974 static long round_dsiclk_rate(unsigned long rate)
1975 {
1976         u32 div;
1977         unsigned long src_rate;
1978         long rounded_rate;
1979
1980         src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1981                 PLL_RAW);
1982         div = clock_divider(src_rate, rate);
1983         rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1984
1985         return rounded_rate;
1986 }
1987
1988 static long round_dsiescclk_rate(unsigned long rate)
1989 {
1990         u32 div;
1991         unsigned long src_rate;
1992         long rounded_rate;
1993
1994         src_rate = clock_rate(PRCMU_TVCLK);
1995         div = clock_divider(src_rate, rate);
1996         rounded_rate = (src_rate / min(div, (u32)255));
1997
1998         return rounded_rate;
1999 }
2000
2001 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
2002 {
2003         if (clock < PRCMU_NUM_REG_CLOCKS)
2004                 return round_clock_rate(clock, rate);
2005         else if (clock == PRCMU_PLLDSI)
2006                 return round_plldsi_rate(rate);
2007         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
2008                 return round_dsiclk_rate(rate);
2009         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
2010                 return round_dsiescclk_rate(rate);
2011         else
2012                 return (long)prcmu_clock_rate(clock);
2013 }
2014
2015 static void set_clock_rate(u8 clock, unsigned long rate)
2016 {
2017         u32 val;
2018         u32 div;
2019         unsigned long src_rate;
2020         unsigned long flags;
2021
2022         spin_lock_irqsave(&clk_mgt_lock, flags);
2023
2024         /* Grab the HW semaphore. */
2025         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
2026                 cpu_relax();
2027
2028         val = readl(clk_mgt[clock].reg);
2029         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
2030                 clk_mgt[clock].branch);
2031         div = clock_divider(src_rate, rate);
2032         if (val & PRCM_CLK_MGT_CLK38) {
2033                 if (clk_mgt[clock].clk38div) {
2034                         if (div > 1)
2035                                 val |= PRCM_CLK_MGT_CLK38DIV;
2036                         else
2037                                 val &= ~PRCM_CLK_MGT_CLK38DIV;
2038                 }
2039         } else if (clock == PRCMU_SGACLK) {
2040                 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
2041                         PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
2042                 if (div == 3) {
2043                         u64 r = (src_rate * 10);
2044
2045                         (void)do_div(r, 25);
2046                         if (r <= rate) {
2047                                 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
2048                                 div = 0;
2049                         }
2050                 }
2051                 val |= min(div, (u32)31);
2052         } else {
2053                 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
2054                 val |= min(div, (u32)31);
2055         }
2056         writel(val, clk_mgt[clock].reg);
2057
2058         /* Release the HW semaphore. */
2059         writel(0, PRCM_SEM);
2060
2061         spin_unlock_irqrestore(&clk_mgt_lock, flags);
2062 }
2063
2064 static int set_plldsi_rate(unsigned long rate)
2065 {
2066         unsigned long src_rate;
2067         unsigned long rem;
2068         u32 pll_freq = 0;
2069         u32 r;
2070
2071         src_rate = clock_rate(PRCMU_HDMICLK);
2072         rem = rate;
2073
2074         for (r = 7; (rem > 0) && (r > 0); r--) {
2075                 u64 d;
2076                 u64 hwrate;
2077
2078                 d = (r * rate);
2079                 (void)do_div(d, src_rate);
2080                 if (d < 6)
2081                         d = 6;
2082                 else if (d > 255)
2083                         d = 255;
2084                 hwrate = (d * src_rate);
2085                 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
2086                         ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
2087                         continue;
2088                 (void)do_div(hwrate, r);
2089                 if (rate < hwrate) {
2090                         if (pll_freq == 0)
2091                                 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
2092                                         (r << PRCM_PLL_FREQ_R_SHIFT));
2093                         break;
2094                 }
2095                 if ((rate - hwrate) < rem) {
2096                         rem = (rate - hwrate);
2097                         pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
2098                                 (r << PRCM_PLL_FREQ_R_SHIFT));
2099                 }
2100         }
2101         if (pll_freq == 0)
2102                 return -EINVAL;
2103
2104         pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
2105         writel(pll_freq, PRCM_PLLDSI_FREQ);
2106
2107         return 0;
2108 }
2109
2110 static void set_dsiclk_rate(u8 n, unsigned long rate)
2111 {
2112         u32 val;
2113         u32 div;
2114
2115         div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
2116                         clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
2117
2118         dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
2119                            (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
2120                            /* else */   PRCM_DSI_PLLOUT_SEL_PHI_4;
2121
2122         val = readl(PRCM_DSI_PLLOUT_SEL);
2123         val &= ~dsiclk[n].divsel_mask;
2124         val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
2125         writel(val, PRCM_DSI_PLLOUT_SEL);
2126 }
2127
2128 static void set_dsiescclk_rate(u8 n, unsigned long rate)
2129 {
2130         u32 val;
2131         u32 div;
2132
2133         div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
2134         val = readl(PRCM_DSITVCLK_DIV);
2135         val &= ~dsiescclk[n].div_mask;
2136         val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
2137         writel(val, PRCM_DSITVCLK_DIV);
2138 }
2139
2140 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
2141 {
2142         if (clock < PRCMU_NUM_REG_CLOCKS)
2143                 set_clock_rate(clock, rate);
2144         else if (clock == PRCMU_PLLDSI)
2145                 return set_plldsi_rate(rate);
2146         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
2147                 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
2148         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
2149                 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
2150         return 0;
2151 }
2152
2153 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
2154 {
2155         if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
2156             (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2157                 return -EINVAL;
2158
2159         mutex_lock(&mb4_transfer.lock);
2160
2161         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2162                 cpu_relax();
2163
2164         writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2165         writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2166                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2167         writeb(DDR_PWR_STATE_ON,
2168                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2169         writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2170
2171         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2172         wait_for_completion(&mb4_transfer.work);
2173
2174         mutex_unlock(&mb4_transfer.lock);
2175
2176         return 0;
2177 }
2178
2179 int db8500_prcmu_config_hotdog(u8 threshold)
2180 {
2181         mutex_lock(&mb4_transfer.lock);
2182
2183         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2184                 cpu_relax();
2185
2186         writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2187         writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2188
2189         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2190         wait_for_completion(&mb4_transfer.work);
2191
2192         mutex_unlock(&mb4_transfer.lock);
2193
2194         return 0;
2195 }
2196
2197 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2198 {
2199         mutex_lock(&mb4_transfer.lock);
2200
2201         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2202                 cpu_relax();
2203
2204         writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2205         writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2206         writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2207                 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2208         writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2209
2210         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2211         wait_for_completion(&mb4_transfer.work);
2212
2213         mutex_unlock(&mb4_transfer.lock);
2214
2215         return 0;
2216 }
2217
2218 static int config_hot_period(u16 val)
2219 {
2220         mutex_lock(&mb4_transfer.lock);
2221
2222         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2223                 cpu_relax();
2224
2225         writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2226         writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2227
2228         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2229         wait_for_completion(&mb4_transfer.work);
2230
2231         mutex_unlock(&mb4_transfer.lock);
2232
2233         return 0;
2234 }
2235
2236 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2237 {
2238         if (cycles32k == 0xFFFF)
2239                 return -EINVAL;
2240
2241         return config_hot_period(cycles32k);
2242 }
2243
2244 int db8500_prcmu_stop_temp_sense(void)
2245 {
2246         return config_hot_period(0xFFFF);
2247 }
2248
2249 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2250 {
2251
2252         mutex_lock(&mb4_transfer.lock);
2253
2254         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2255                 cpu_relax();
2256
2257         writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2258         writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2259         writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2260         writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2261
2262         writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2263
2264         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2265         wait_for_completion(&mb4_transfer.work);
2266
2267         mutex_unlock(&mb4_transfer.lock);
2268
2269         return 0;
2270
2271 }
2272
2273 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2274 {
2275         BUG_ON(num == 0 || num > 0xf);
2276         return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2277                             sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2278                             A9WDOG_AUTO_OFF_DIS);
2279 }
2280
2281 int db8500_prcmu_enable_a9wdog(u8 id)
2282 {
2283         return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2284 }
2285
2286 int db8500_prcmu_disable_a9wdog(u8 id)
2287 {
2288         return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2289 }
2290
2291 int db8500_prcmu_kick_a9wdog(u8 id)
2292 {
2293         return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2294 }
2295
2296 /*
2297  * timeout is 28 bit, in ms.
2298  */
2299 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2300 {
2301         return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2302                             (id & A9WDOG_ID_MASK) |
2303                             /*
2304                              * Put the lowest 28 bits of timeout at
2305                              * offset 4. Four first bits are used for id.
2306                              */
2307                             (u8)((timeout << 4) & 0xf0),
2308                             (u8)((timeout >> 4) & 0xff),
2309                             (u8)((timeout >> 12) & 0xff),
2310                             (u8)((timeout >> 20) & 0xff));
2311 }
2312
2313 /**
2314  * prcmu_abb_read() - Read register value(s) from the ABB.
2315  * @slave:      The I2C slave address.
2316  * @reg:        The (start) register address.
2317  * @value:      The read out value(s).
2318  * @size:       The number of registers to read.
2319  *
2320  * Reads register value(s) from the ABB.
2321  * @size has to be 1 for the current firmware version.
2322  */
2323 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2324 {
2325         int r;
2326
2327         if (size != 1)
2328                 return -EINVAL;
2329
2330         mutex_lock(&mb5_transfer.lock);
2331
2332         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2333                 cpu_relax();
2334
2335         writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2336         writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2337         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2338         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2339         writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2340
2341         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2342
2343         if (!wait_for_completion_timeout(&mb5_transfer.work,
2344                                 msecs_to_jiffies(20000))) {
2345                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2346                         __func__);
2347                 r = -EIO;
2348         } else {
2349                 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2350         }
2351
2352         if (!r)
2353                 *value = mb5_transfer.ack.value;
2354
2355         mutex_unlock(&mb5_transfer.lock);
2356
2357         return r;
2358 }
2359
2360 /**
2361  * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2362  * @slave:      The I2C slave address.
2363  * @reg:        The (start) register address.
2364  * @value:      The value(s) to write.
2365  * @mask:       The mask(s) to use.
2366  * @size:       The number of registers to write.
2367  *
2368  * Writes masked register value(s) to the ABB.
2369  * For each @value, only the bits set to 1 in the corresponding @mask
2370  * will be written. The other bits are not changed.
2371  * @size has to be 1 for the current firmware version.
2372  */
2373 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2374 {
2375         int r;
2376
2377         if (size != 1)
2378                 return -EINVAL;
2379
2380         mutex_lock(&mb5_transfer.lock);
2381
2382         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2383                 cpu_relax();
2384
2385         writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2386         writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2387         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2388         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2389         writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2390
2391         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2392
2393         if (!wait_for_completion_timeout(&mb5_transfer.work,
2394                                 msecs_to_jiffies(20000))) {
2395                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2396                         __func__);
2397                 r = -EIO;
2398         } else {
2399                 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2400         }
2401
2402         mutex_unlock(&mb5_transfer.lock);
2403
2404         return r;
2405 }
2406
2407 /**
2408  * prcmu_abb_write() - Write register value(s) to the ABB.
2409  * @slave:      The I2C slave address.
2410  * @reg:        The (start) register address.
2411  * @value:      The value(s) to write.
2412  * @size:       The number of registers to write.
2413  *
2414  * Writes register value(s) to the ABB.
2415  * @size has to be 1 for the current firmware version.
2416  */
2417 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2418 {
2419         u8 mask = ~0;
2420
2421         return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2422 }
2423
2424 /**
2425  * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2426  */
2427 void prcmu_ac_wake_req(void)
2428 {
2429         u32 val;
2430         u32 status;
2431
2432         mutex_lock(&mb0_transfer.ac_wake_lock);
2433
2434         val = readl(PRCM_HOSTACCESS_REQ);
2435         if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2436                 goto unlock_and_return;
2437
2438         atomic_set(&ac_wake_req_state, 1);
2439
2440 retry:
2441         writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ);
2442
2443         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2444                         msecs_to_jiffies(5000))) {
2445                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2446                         __func__);
2447                 goto unlock_and_return;
2448         }
2449
2450         /*
2451          * The modem can generate an AC_WAKE_ACK, and then still go to sleep.
2452          * As a workaround, we wait, and then check that the modem is indeed
2453          * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS
2454          * register, which may not be the whole truth).
2455          */
2456         udelay(400);
2457         status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2));
2458         if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE |
2459                         PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) {
2460                 pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n",
2461                         __func__, status);
2462                 udelay(1200);
2463                 writel(val, PRCM_HOSTACCESS_REQ);
2464                 if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2465                                 msecs_to_jiffies(5000)))
2466                         goto retry;
2467                 pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n",
2468                         __func__);
2469         }
2470
2471 unlock_and_return:
2472         mutex_unlock(&mb0_transfer.ac_wake_lock);
2473 }
2474
2475 /**
2476  * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2477  */
2478 void prcmu_ac_sleep_req()
2479 {
2480         u32 val;
2481
2482         mutex_lock(&mb0_transfer.ac_wake_lock);
2483
2484         val = readl(PRCM_HOSTACCESS_REQ);
2485         if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2486                 goto unlock_and_return;
2487
2488         writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2489                 PRCM_HOSTACCESS_REQ);
2490
2491         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2492                         msecs_to_jiffies(5000))) {
2493                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2494                         __func__);
2495         }
2496
2497         atomic_set(&ac_wake_req_state, 0);
2498
2499 unlock_and_return:
2500         mutex_unlock(&mb0_transfer.ac_wake_lock);
2501 }
2502
2503 bool db8500_prcmu_is_ac_wake_requested(void)
2504 {
2505         return (atomic_read(&ac_wake_req_state) != 0);
2506 }
2507
2508 /**
2509  * db8500_prcmu_system_reset - System reset
2510  *
2511  * Saves the reset reason code and then sets the APE_SOFTRST register which
2512  * fires interrupt to fw
2513  */
2514 void db8500_prcmu_system_reset(u16 reset_code)
2515 {
2516         writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2517         writel(1, PRCM_APE_SOFTRST);
2518 }
2519
2520 /**
2521  * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2522  *
2523  * Retrieves the reset reason code stored by prcmu_system_reset() before
2524  * last restart.
2525  */
2526 u16 db8500_prcmu_get_reset_code(void)
2527 {
2528         return readw(tcdm_base + PRCM_SW_RST_REASON);
2529 }
2530
2531 /**
2532  * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2533  */
2534 void db8500_prcmu_modem_reset(void)
2535 {
2536         mutex_lock(&mb1_transfer.lock);
2537
2538         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2539                 cpu_relax();
2540
2541         writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2542         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2543         wait_for_completion(&mb1_transfer.work);
2544
2545         /*
2546          * No need to check return from PRCMU as modem should go in reset state
2547          * This state is already managed by upper layer
2548          */
2549
2550         mutex_unlock(&mb1_transfer.lock);
2551 }
2552
2553 static void ack_dbb_wakeup(void)
2554 {
2555         unsigned long flags;
2556
2557         spin_lock_irqsave(&mb0_transfer.lock, flags);
2558
2559         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2560                 cpu_relax();
2561
2562         writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2563         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2564
2565         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2566 }
2567
2568 static inline void print_unknown_header_warning(u8 n, u8 header)
2569 {
2570         pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2571                 header, n);
2572 }
2573
2574 static bool read_mailbox_0(void)
2575 {
2576         bool r;
2577         u32 ev;
2578         unsigned int n;
2579         u8 header;
2580
2581         header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2582         switch (header) {
2583         case MB0H_WAKEUP_EXE:
2584         case MB0H_WAKEUP_SLEEP:
2585                 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2586                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2587                 else
2588                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2589
2590                 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2591                         complete(&mb0_transfer.ac_wake_work);
2592                 if (ev & WAKEUP_BIT_SYSCLK_OK)
2593                         complete(&mb3_transfer.sysclk_work);
2594
2595                 ev &= mb0_transfer.req.dbb_irqs;
2596
2597                 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2598                         if (ev & prcmu_irq_bit[n])
2599                                 generic_handle_irq(IRQ_PRCMU_BASE + n);
2600                 }
2601                 r = true;
2602                 break;
2603         default:
2604                 print_unknown_header_warning(0, header);
2605                 r = false;
2606                 break;
2607         }
2608         writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2609         return r;
2610 }
2611
2612 static bool read_mailbox_1(void)
2613 {
2614         mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2615         mb1_transfer.ack.arm_opp = readb(tcdm_base +
2616                 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2617         mb1_transfer.ack.ape_opp = readb(tcdm_base +
2618                 PRCM_ACK_MB1_CURRENT_APE_OPP);
2619         mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2620                 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2621         writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2622         complete(&mb1_transfer.work);
2623         return false;
2624 }
2625
2626 static bool read_mailbox_2(void)
2627 {
2628         mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2629         writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2630         complete(&mb2_transfer.work);
2631         return false;
2632 }
2633
2634 static bool read_mailbox_3(void)
2635 {
2636         writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2637         return false;
2638 }
2639
2640 static bool read_mailbox_4(void)
2641 {
2642         u8 header;
2643         bool do_complete = true;
2644
2645         header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2646         switch (header) {
2647         case MB4H_MEM_ST:
2648         case MB4H_HOTDOG:
2649         case MB4H_HOTMON:
2650         case MB4H_HOT_PERIOD:
2651         case MB4H_A9WDOG_CONF:
2652         case MB4H_A9WDOG_EN:
2653         case MB4H_A9WDOG_DIS:
2654         case MB4H_A9WDOG_LOAD:
2655         case MB4H_A9WDOG_KICK:
2656                 break;
2657         default:
2658                 print_unknown_header_warning(4, header);
2659                 do_complete = false;
2660                 break;
2661         }
2662
2663         writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2664
2665         if (do_complete)
2666                 complete(&mb4_transfer.work);
2667
2668         return false;
2669 }
2670
2671 static bool read_mailbox_5(void)
2672 {
2673         mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2674         mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2675         writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2676         complete(&mb5_transfer.work);
2677         return false;
2678 }
2679
2680 static bool read_mailbox_6(void)
2681 {
2682         writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2683         return false;
2684 }
2685
2686 static bool read_mailbox_7(void)
2687 {
2688         writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2689         return false;
2690 }
2691
2692 static bool (* const read_mailbox[NUM_MB])(void) = {
2693         read_mailbox_0,
2694         read_mailbox_1,
2695         read_mailbox_2,
2696         read_mailbox_3,
2697         read_mailbox_4,
2698         read_mailbox_5,
2699         read_mailbox_6,
2700         read_mailbox_7
2701 };
2702
2703 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2704 {
2705         u32 bits;
2706         u8 n;
2707         irqreturn_t r;
2708
2709         bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2710         if (unlikely(!bits))
2711                 return IRQ_NONE;
2712
2713         r = IRQ_HANDLED;
2714         for (n = 0; bits; n++) {
2715                 if (bits & MBOX_BIT(n)) {
2716                         bits -= MBOX_BIT(n);
2717                         if (read_mailbox[n]())
2718                                 r = IRQ_WAKE_THREAD;
2719                 }
2720         }
2721         return r;
2722 }
2723
2724 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2725 {
2726         ack_dbb_wakeup();
2727         return IRQ_HANDLED;
2728 }
2729
2730 static void prcmu_mask_work(struct work_struct *work)
2731 {
2732         unsigned long flags;
2733
2734         spin_lock_irqsave(&mb0_transfer.lock, flags);
2735
2736         config_wakeups();
2737
2738         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2739 }
2740
2741 static void prcmu_irq_mask(struct irq_data *d)
2742 {
2743         unsigned long flags;
2744
2745         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2746
2747         mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
2748
2749         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2750
2751         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2752                 schedule_work(&mb0_transfer.mask_work);
2753 }
2754
2755 static void prcmu_irq_unmask(struct irq_data *d)
2756 {
2757         unsigned long flags;
2758
2759         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2760
2761         mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
2762
2763         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2764
2765         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2766                 schedule_work(&mb0_transfer.mask_work);
2767 }
2768
2769 static void noop(struct irq_data *d)
2770 {
2771 }
2772
2773 static struct irq_chip prcmu_irq_chip = {
2774         .name           = "prcmu",
2775         .irq_disable    = prcmu_irq_mask,
2776         .irq_ack        = noop,
2777         .irq_mask       = prcmu_irq_mask,
2778         .irq_unmask     = prcmu_irq_unmask,
2779 };
2780
2781 static char *fw_project_name(u8 project)
2782 {
2783         switch (project) {
2784         case PRCMU_FW_PROJECT_U8500:
2785                 return "U8500";
2786         case PRCMU_FW_PROJECT_U8500_C2:
2787                 return "U8500 C2";
2788         case PRCMU_FW_PROJECT_U9500:
2789                 return "U9500";
2790         case PRCMU_FW_PROJECT_U9500_C2:
2791                 return "U9500 C2";
2792         default:
2793                 return "Unknown";
2794         }
2795 }
2796
2797 void __init db8500_prcmu_early_init(void)
2798 {
2799         unsigned int i;
2800         if (cpu_is_u8500v2()) {
2801                 void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
2802
2803                 if (tcpm_base != NULL) {
2804                         u32 version;
2805                         version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET);
2806                         fw_info.version.project = version & 0xFF;
2807                         fw_info.version.api_version = (version >> 8) & 0xFF;
2808                         fw_info.version.func_version = (version >> 16) & 0xFF;
2809                         fw_info.version.errata = (version >> 24) & 0xFF;
2810                         fw_info.valid = true;
2811                         pr_info("PRCMU firmware: %s, version %d.%d.%d\n",
2812                                 fw_project_name(fw_info.version.project),
2813                                 (version >> 8) & 0xFF, (version >> 16) & 0xFF,
2814                                 (version >> 24) & 0xFF);
2815                         iounmap(tcpm_base);
2816                 }
2817
2818                 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
2819         } else {
2820                 pr_err("prcmu: Unsupported chip version\n");
2821                 BUG();
2822         }
2823
2824         spin_lock_init(&mb0_transfer.lock);
2825         spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2826         mutex_init(&mb0_transfer.ac_wake_lock);
2827         init_completion(&mb0_transfer.ac_wake_work);
2828         mutex_init(&mb1_transfer.lock);
2829         init_completion(&mb1_transfer.work);
2830         mb1_transfer.ape_opp = APE_NO_CHANGE;
2831         mutex_init(&mb2_transfer.lock);
2832         init_completion(&mb2_transfer.work);
2833         spin_lock_init(&mb2_transfer.auto_pm_lock);
2834         spin_lock_init(&mb3_transfer.lock);
2835         mutex_init(&mb3_transfer.sysclk_lock);
2836         init_completion(&mb3_transfer.sysclk_work);
2837         mutex_init(&mb4_transfer.lock);
2838         init_completion(&mb4_transfer.work);
2839         mutex_init(&mb5_transfer.lock);
2840         init_completion(&mb5_transfer.work);
2841
2842         INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2843
2844         /* Initalize irqs. */
2845         for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) {
2846                 unsigned int irq;
2847
2848                 irq = IRQ_PRCMU_BASE + i;
2849                 irq_set_chip_and_handler(irq, &prcmu_irq_chip,
2850                                          handle_simple_irq);
2851                 set_irq_flags(irq, IRQF_VALID);
2852         }
2853 }
2854
2855 static void __init init_prcm_registers(void)
2856 {
2857         u32 val;
2858
2859         val = readl(PRCM_A9PL_FORCE_CLKEN);
2860         val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2861                 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2862         writel(val, (PRCM_A9PL_FORCE_CLKEN));
2863 }
2864
2865 /*
2866  * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2867  */
2868 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2869         REGULATOR_SUPPLY("v-ape", NULL),
2870         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2871         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2872         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2873         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2874         /* "v-mmc" changed to "vcore" in the mainline kernel */
2875         REGULATOR_SUPPLY("vcore", "sdi0"),
2876         REGULATOR_SUPPLY("vcore", "sdi1"),
2877         REGULATOR_SUPPLY("vcore", "sdi2"),
2878         REGULATOR_SUPPLY("vcore", "sdi3"),
2879         REGULATOR_SUPPLY("vcore", "sdi4"),
2880         REGULATOR_SUPPLY("v-dma", "dma40.0"),
2881         REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2882         /* "v-uart" changed to "vcore" in the mainline kernel */
2883         REGULATOR_SUPPLY("vcore", "uart0"),
2884         REGULATOR_SUPPLY("vcore", "uart1"),
2885         REGULATOR_SUPPLY("vcore", "uart2"),
2886         REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2887         REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2888 };
2889
2890 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2891         REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2892         /* AV8100 regulator */
2893         REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2894 };
2895
2896 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2897         REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2898         REGULATOR_SUPPLY("vsupply", "mcde"),
2899 };
2900
2901 /* SVA MMDSP regulator switch */
2902 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2903         REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2904 };
2905
2906 /* SVA pipe regulator switch */
2907 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2908         REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2909 };
2910
2911 /* SIA MMDSP regulator switch */
2912 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2913         REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2914 };
2915
2916 /* SIA pipe regulator switch */
2917 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2918         REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2919 };
2920
2921 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2922         REGULATOR_SUPPLY("v-mali", NULL),
2923 };
2924
2925 /* ESRAM1 and 2 regulator switch */
2926 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2927         REGULATOR_SUPPLY("esram12", "cm_control"),
2928 };
2929
2930 /* ESRAM3 and 4 regulator switch */
2931 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2932         REGULATOR_SUPPLY("v-esram34", "mcde"),
2933         REGULATOR_SUPPLY("esram34", "cm_control"),
2934         REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2935 };
2936
2937 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2938         [DB8500_REGULATOR_VAPE] = {
2939                 .constraints = {
2940                         .name = "db8500-vape",
2941                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2942                 },
2943                 .consumer_supplies = db8500_vape_consumers,
2944                 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2945         },
2946         [DB8500_REGULATOR_VARM] = {
2947                 .constraints = {
2948                         .name = "db8500-varm",
2949                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2950                 },
2951         },
2952         [DB8500_REGULATOR_VMODEM] = {
2953                 .constraints = {
2954                         .name = "db8500-vmodem",
2955                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2956                 },
2957         },
2958         [DB8500_REGULATOR_VPLL] = {
2959                 .constraints = {
2960                         .name = "db8500-vpll",
2961                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2962                 },
2963         },
2964         [DB8500_REGULATOR_VSMPS1] = {
2965                 .constraints = {
2966                         .name = "db8500-vsmps1",
2967                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2968                 },
2969         },
2970         [DB8500_REGULATOR_VSMPS2] = {
2971                 .constraints = {
2972                         .name = "db8500-vsmps2",
2973                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2974                 },
2975                 .consumer_supplies = db8500_vsmps2_consumers,
2976                 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2977         },
2978         [DB8500_REGULATOR_VSMPS3] = {
2979                 .constraints = {
2980                         .name = "db8500-vsmps3",
2981                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2982                 },
2983         },
2984         [DB8500_REGULATOR_VRF1] = {
2985                 .constraints = {
2986                         .name = "db8500-vrf1",
2987                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2988                 },
2989         },
2990         [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2991                 /* dependency to u8500-vape is handled outside regulator framework */
2992                 .constraints = {
2993                         .name = "db8500-sva-mmdsp",
2994                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2995                 },
2996                 .consumer_supplies = db8500_svammdsp_consumers,
2997                 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2998         },
2999         [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
3000                 .constraints = {
3001                         /* "ret" means "retention" */
3002                         .name = "db8500-sva-mmdsp-ret",
3003                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3004                 },
3005         },
3006         [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
3007                 /* dependency to u8500-vape is handled outside regulator framework */
3008                 .constraints = {
3009                         .name = "db8500-sva-pipe",
3010                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3011                 },
3012                 .consumer_supplies = db8500_svapipe_consumers,
3013                 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
3014         },
3015         [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
3016                 /* dependency to u8500-vape is handled outside regulator framework */
3017                 .constraints = {
3018                         .name = "db8500-sia-mmdsp",
3019                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3020                 },
3021                 .consumer_supplies = db8500_siammdsp_consumers,
3022                 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
3023         },
3024         [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
3025                 .constraints = {
3026                         .name = "db8500-sia-mmdsp-ret",
3027                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3028                 },
3029         },
3030         [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
3031                 /* dependency to u8500-vape is handled outside regulator framework */
3032                 .constraints = {
3033                         .name = "db8500-sia-pipe",
3034                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3035                 },
3036                 .consumer_supplies = db8500_siapipe_consumers,
3037                 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
3038         },
3039         [DB8500_REGULATOR_SWITCH_SGA] = {
3040                 .supply_regulator = "db8500-vape",
3041                 .constraints = {
3042                         .name = "db8500-sga",
3043                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3044                 },
3045                 .consumer_supplies = db8500_sga_consumers,
3046                 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
3047
3048         },
3049         [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
3050                 .supply_regulator = "db8500-vape",
3051                 .constraints = {
3052                         .name = "db8500-b2r2-mcde",
3053                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3054                 },
3055                 .consumer_supplies = db8500_b2r2_mcde_consumers,
3056                 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
3057         },
3058         [DB8500_REGULATOR_SWITCH_ESRAM12] = {
3059                 /*
3060                  * esram12 is set in retention and supplied by Vsafe when Vape is off,
3061                  * no need to hold Vape
3062                  */
3063                 .constraints = {
3064                         .name = "db8500-esram12",
3065                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3066                 },
3067                 .consumer_supplies = db8500_esram12_consumers,
3068                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
3069         },
3070         [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
3071                 .constraints = {
3072                         .name = "db8500-esram12-ret",
3073                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3074                 },
3075         },
3076         [DB8500_REGULATOR_SWITCH_ESRAM34] = {
3077                 /*
3078                  * esram34 is set in retention and supplied by Vsafe when Vape is off,
3079                  * no need to hold Vape
3080                  */
3081                 .constraints = {
3082                         .name = "db8500-esram34",
3083                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3084                 },
3085                 .consumer_supplies = db8500_esram34_consumers,
3086                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
3087         },
3088         [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3089                 .constraints = {
3090                         .name = "db8500-esram34-ret",
3091                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3092                 },
3093         },
3094 };
3095
3096 static struct mfd_cell db8500_prcmu_devs[] = {
3097         {
3098                 .name = "db8500-prcmu-regulators",
3099                 .platform_data = &db8500_regulators,
3100                 .pdata_size = sizeof(db8500_regulators),
3101         },
3102         {
3103                 .name = "cpufreq-u8500",
3104         },
3105 };
3106
3107 /**
3108  * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3109  *
3110  */
3111 static int __init db8500_prcmu_probe(struct platform_device *pdev)
3112 {
3113         int err = 0;
3114
3115         if (ux500_is_svp())
3116                 return -ENODEV;
3117
3118         init_prcm_registers();
3119
3120         /* Clean up the mailbox interrupts after pre-kernel code. */
3121         writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3122
3123         err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler,
3124                 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3125         if (err < 0) {
3126                 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3127                 err = -EBUSY;
3128                 goto no_irq_return;
3129         }
3130
3131         if (cpu_is_u8500v20_or_later())
3132                 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3133
3134         err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3135                               ARRAY_SIZE(db8500_prcmu_devs), NULL,
3136                               0);
3137
3138         if (err)
3139                 pr_err("prcmu: Failed to add subdevices\n");
3140         else
3141                 pr_info("DB8500 PRCMU initialized\n");
3142
3143 no_irq_return:
3144         return err;
3145 }
3146
3147 static struct platform_driver db8500_prcmu_driver = {
3148         .driver = {
3149                 .name = "db8500-prcmu",
3150                 .owner = THIS_MODULE,
3151         },
3152 };
3153
3154 static int __init db8500_prcmu_init(void)
3155 {
3156         return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe);
3157 }
3158
3159 arch_initcall(db8500_prcmu_init);
3160
3161 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3162 MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3163 MODULE_LICENSE("GPL v2");