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Merge tag 'drm-intel-next-fixes-2014-12-30' of git://anongit.freedesktop.org/drm...
[karo-tx-linux.git] / drivers / mfd / db8500-prcmu.c
1 /*
2  * Copyright (C) STMicroelectronics 2009
3  * Copyright (C) ST-Ericsson SA 2010
4  *
5  * License Terms: GNU General Public License v2
6  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7  * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
9  *
10  * U8500 PRCM Unit interface driver
11  *
12  */
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/spinlock.h>
19 #include <linux/io.h>
20 #include <linux/slab.h>
21 #include <linux/mutex.h>
22 #include <linux/completion.h>
23 #include <linux/irq.h>
24 #include <linux/jiffies.h>
25 #include <linux/bitops.h>
26 #include <linux/fs.h>
27 #include <linux/of.h>
28 #include <linux/of_irq.h>
29 #include <linux/platform_device.h>
30 #include <linux/uaccess.h>
31 #include <linux/mfd/core.h>
32 #include <linux/mfd/dbx500-prcmu.h>
33 #include <linux/mfd/abx500/ab8500.h>
34 #include <linux/regulator/db8500-prcmu.h>
35 #include <linux/regulator/machine.h>
36 #include <linux/cpufreq.h>
37 #include <linux/platform_data/ux500_wdt.h>
38 #include <linux/platform_data/db8500_thermal.h>
39 #include "dbx500-prcmu-regs.h"
40
41 /* Index of different voltages to be used when accessing AVSData */
42 #define PRCM_AVS_BASE           0x2FC
43 #define PRCM_AVS_VBB_RET        (PRCM_AVS_BASE + 0x0)
44 #define PRCM_AVS_VBB_MAX_OPP    (PRCM_AVS_BASE + 0x1)
45 #define PRCM_AVS_VBB_100_OPP    (PRCM_AVS_BASE + 0x2)
46 #define PRCM_AVS_VBB_50_OPP     (PRCM_AVS_BASE + 0x3)
47 #define PRCM_AVS_VARM_MAX_OPP   (PRCM_AVS_BASE + 0x4)
48 #define PRCM_AVS_VARM_100_OPP   (PRCM_AVS_BASE + 0x5)
49 #define PRCM_AVS_VARM_50_OPP    (PRCM_AVS_BASE + 0x6)
50 #define PRCM_AVS_VARM_RET       (PRCM_AVS_BASE + 0x7)
51 #define PRCM_AVS_VAPE_100_OPP   (PRCM_AVS_BASE + 0x8)
52 #define PRCM_AVS_VAPE_50_OPP    (PRCM_AVS_BASE + 0x9)
53 #define PRCM_AVS_VMOD_100_OPP   (PRCM_AVS_BASE + 0xA)
54 #define PRCM_AVS_VMOD_50_OPP    (PRCM_AVS_BASE + 0xB)
55 #define PRCM_AVS_VSAFE          (PRCM_AVS_BASE + 0xC)
56
57 #define PRCM_AVS_VOLTAGE                0
58 #define PRCM_AVS_VOLTAGE_MASK           0x3f
59 #define PRCM_AVS_ISSLOWSTARTUP          6
60 #define PRCM_AVS_ISSLOWSTARTUP_MASK     (1 << PRCM_AVS_ISSLOWSTARTUP)
61 #define PRCM_AVS_ISMODEENABLE           7
62 #define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
63
64 #define PRCM_BOOT_STATUS        0xFFF
65 #define PRCM_ROMCODE_A2P        0xFFE
66 #define PRCM_ROMCODE_P2A        0xFFD
67 #define PRCM_XP70_CUR_PWR_STATE 0xFFC      /* 4 BYTES */
68
69 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
70
71 #define _PRCM_MBOX_HEADER               0xFE8 /* 16 bytes */
72 #define PRCM_MBOX_HEADER_REQ_MB0        (_PRCM_MBOX_HEADER + 0x0)
73 #define PRCM_MBOX_HEADER_REQ_MB1        (_PRCM_MBOX_HEADER + 0x1)
74 #define PRCM_MBOX_HEADER_REQ_MB2        (_PRCM_MBOX_HEADER + 0x2)
75 #define PRCM_MBOX_HEADER_REQ_MB3        (_PRCM_MBOX_HEADER + 0x3)
76 #define PRCM_MBOX_HEADER_REQ_MB4        (_PRCM_MBOX_HEADER + 0x4)
77 #define PRCM_MBOX_HEADER_REQ_MB5        (_PRCM_MBOX_HEADER + 0x5)
78 #define PRCM_MBOX_HEADER_ACK_MB0        (_PRCM_MBOX_HEADER + 0x8)
79
80 /* Req Mailboxes */
81 #define PRCM_REQ_MB0 0xFDC /* 12 bytes  */
82 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes  */
83 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes  */
84 #define PRCM_REQ_MB3 0xE4C /* 372 bytes  */
85 #define PRCM_REQ_MB4 0xE48 /* 4 bytes  */
86 #define PRCM_REQ_MB5 0xE44 /* 4 bytes  */
87
88 /* Ack Mailboxes */
89 #define PRCM_ACK_MB0 0xE08 /* 52 bytes  */
90 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
91 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
92 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
93 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
94 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
95
96 /* Mailbox 0 headers */
97 #define MB0H_POWER_STATE_TRANS          0
98 #define MB0H_CONFIG_WAKEUPS_EXE         1
99 #define MB0H_READ_WAKEUP_ACK            3
100 #define MB0H_CONFIG_WAKEUPS_SLEEP       4
101
102 #define MB0H_WAKEUP_EXE 2
103 #define MB0H_WAKEUP_SLEEP 5
104
105 /* Mailbox 0 REQs */
106 #define PRCM_REQ_MB0_AP_POWER_STATE     (PRCM_REQ_MB0 + 0x0)
107 #define PRCM_REQ_MB0_AP_PLL_STATE       (PRCM_REQ_MB0 + 0x1)
108 #define PRCM_REQ_MB0_ULP_CLOCK_STATE    (PRCM_REQ_MB0 + 0x2)
109 #define PRCM_REQ_MB0_DO_NOT_WFI         (PRCM_REQ_MB0 + 0x3)
110 #define PRCM_REQ_MB0_WAKEUP_8500        (PRCM_REQ_MB0 + 0x4)
111 #define PRCM_REQ_MB0_WAKEUP_4500        (PRCM_REQ_MB0 + 0x8)
112
113 /* Mailbox 0 ACKs */
114 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS  (PRCM_ACK_MB0 + 0x0)
115 #define PRCM_ACK_MB0_READ_POINTER       (PRCM_ACK_MB0 + 0x1)
116 #define PRCM_ACK_MB0_WAKEUP_0_8500      (PRCM_ACK_MB0 + 0x4)
117 #define PRCM_ACK_MB0_WAKEUP_0_4500      (PRCM_ACK_MB0 + 0x8)
118 #define PRCM_ACK_MB0_WAKEUP_1_8500      (PRCM_ACK_MB0 + 0x1C)
119 #define PRCM_ACK_MB0_WAKEUP_1_4500      (PRCM_ACK_MB0 + 0x20)
120 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
121
122 /* Mailbox 1 headers */
123 #define MB1H_ARM_APE_OPP 0x0
124 #define MB1H_RESET_MODEM 0x2
125 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
126 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
127 #define MB1H_RELEASE_USB_WAKEUP 0x5
128 #define MB1H_PLL_ON_OFF 0x6
129
130 /* Mailbox 1 Requests */
131 #define PRCM_REQ_MB1_ARM_OPP                    (PRCM_REQ_MB1 + 0x0)
132 #define PRCM_REQ_MB1_APE_OPP                    (PRCM_REQ_MB1 + 0x1)
133 #define PRCM_REQ_MB1_PLL_ON_OFF                 (PRCM_REQ_MB1 + 0x4)
134 #define PLL_SOC0_OFF    0x1
135 #define PLL_SOC0_ON     0x2
136 #define PLL_SOC1_OFF    0x4
137 #define PLL_SOC1_ON     0x8
138
139 /* Mailbox 1 ACKs */
140 #define PRCM_ACK_MB1_CURRENT_ARM_OPP    (PRCM_ACK_MB1 + 0x0)
141 #define PRCM_ACK_MB1_CURRENT_APE_OPP    (PRCM_ACK_MB1 + 0x1)
142 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
143 #define PRCM_ACK_MB1_DVFS_STATUS        (PRCM_ACK_MB1 + 0x3)
144
145 /* Mailbox 2 headers */
146 #define MB2H_DPS        0x0
147 #define MB2H_AUTO_PWR   0x1
148
149 /* Mailbox 2 REQs */
150 #define PRCM_REQ_MB2_SVA_MMDSP          (PRCM_REQ_MB2 + 0x0)
151 #define PRCM_REQ_MB2_SVA_PIPE           (PRCM_REQ_MB2 + 0x1)
152 #define PRCM_REQ_MB2_SIA_MMDSP          (PRCM_REQ_MB2 + 0x2)
153 #define PRCM_REQ_MB2_SIA_PIPE           (PRCM_REQ_MB2 + 0x3)
154 #define PRCM_REQ_MB2_SGA                (PRCM_REQ_MB2 + 0x4)
155 #define PRCM_REQ_MB2_B2R2_MCDE          (PRCM_REQ_MB2 + 0x5)
156 #define PRCM_REQ_MB2_ESRAM12            (PRCM_REQ_MB2 + 0x6)
157 #define PRCM_REQ_MB2_ESRAM34            (PRCM_REQ_MB2 + 0x7)
158 #define PRCM_REQ_MB2_AUTO_PM_SLEEP      (PRCM_REQ_MB2 + 0x8)
159 #define PRCM_REQ_MB2_AUTO_PM_IDLE       (PRCM_REQ_MB2 + 0xC)
160
161 /* Mailbox 2 ACKs */
162 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
163 #define HWACC_PWR_ST_OK 0xFE
164
165 /* Mailbox 3 headers */
166 #define MB3H_ANC        0x0
167 #define MB3H_SIDETONE   0x1
168 #define MB3H_SYSCLK     0xE
169
170 /* Mailbox 3 Requests */
171 #define PRCM_REQ_MB3_ANC_FIR_COEFF      (PRCM_REQ_MB3 + 0x0)
172 #define PRCM_REQ_MB3_ANC_IIR_COEFF      (PRCM_REQ_MB3 + 0x20)
173 #define PRCM_REQ_MB3_ANC_SHIFTER        (PRCM_REQ_MB3 + 0x60)
174 #define PRCM_REQ_MB3_ANC_WARP           (PRCM_REQ_MB3 + 0x64)
175 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN  (PRCM_REQ_MB3 + 0x68)
176 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
177 #define PRCM_REQ_MB3_SYSCLK_MGT         (PRCM_REQ_MB3 + 0x16C)
178
179 /* Mailbox 4 headers */
180 #define MB4H_DDR_INIT   0x0
181 #define MB4H_MEM_ST     0x1
182 #define MB4H_HOTDOG     0x12
183 #define MB4H_HOTMON     0x13
184 #define MB4H_HOT_PERIOD 0x14
185 #define MB4H_A9WDOG_CONF 0x16
186 #define MB4H_A9WDOG_EN   0x17
187 #define MB4H_A9WDOG_DIS  0x18
188 #define MB4H_A9WDOG_LOAD 0x19
189 #define MB4H_A9WDOG_KICK 0x20
190
191 /* Mailbox 4 Requests */
192 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE       (PRCM_REQ_MB4 + 0x0)
193 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE        (PRCM_REQ_MB4 + 0x1)
194 #define PRCM_REQ_MB4_ESRAM0_ST                  (PRCM_REQ_MB4 + 0x3)
195 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD           (PRCM_REQ_MB4 + 0x0)
196 #define PRCM_REQ_MB4_HOTMON_LOW                 (PRCM_REQ_MB4 + 0x0)
197 #define PRCM_REQ_MB4_HOTMON_HIGH                (PRCM_REQ_MB4 + 0x1)
198 #define PRCM_REQ_MB4_HOTMON_CONFIG              (PRCM_REQ_MB4 + 0x2)
199 #define PRCM_REQ_MB4_HOT_PERIOD                 (PRCM_REQ_MB4 + 0x0)
200 #define HOTMON_CONFIG_LOW                       BIT(0)
201 #define HOTMON_CONFIG_HIGH                      BIT(1)
202 #define PRCM_REQ_MB4_A9WDOG_0                   (PRCM_REQ_MB4 + 0x0)
203 #define PRCM_REQ_MB4_A9WDOG_1                   (PRCM_REQ_MB4 + 0x1)
204 #define PRCM_REQ_MB4_A9WDOG_2                   (PRCM_REQ_MB4 + 0x2)
205 #define PRCM_REQ_MB4_A9WDOG_3                   (PRCM_REQ_MB4 + 0x3)
206 #define A9WDOG_AUTO_OFF_EN                      BIT(7)
207 #define A9WDOG_AUTO_OFF_DIS                     0
208 #define A9WDOG_ID_MASK                          0xf
209
210 /* Mailbox 5 Requests */
211 #define PRCM_REQ_MB5_I2C_SLAVE_OP       (PRCM_REQ_MB5 + 0x0)
212 #define PRCM_REQ_MB5_I2C_HW_BITS        (PRCM_REQ_MB5 + 0x1)
213 #define PRCM_REQ_MB5_I2C_REG            (PRCM_REQ_MB5 + 0x2)
214 #define PRCM_REQ_MB5_I2C_VAL            (PRCM_REQ_MB5 + 0x3)
215 #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
216 #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
217 #define PRCMU_I2C_STOP_EN               BIT(3)
218
219 /* Mailbox 5 ACKs */
220 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
221 #define PRCM_ACK_MB5_I2C_VAL    (PRCM_ACK_MB5 + 0x3)
222 #define I2C_WR_OK 0x1
223 #define I2C_RD_OK 0x2
224
225 #define NUM_MB 8
226 #define MBOX_BIT BIT
227 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
228
229 /*
230  * Wakeups/IRQs
231  */
232
233 #define WAKEUP_BIT_RTC BIT(0)
234 #define WAKEUP_BIT_RTT0 BIT(1)
235 #define WAKEUP_BIT_RTT1 BIT(2)
236 #define WAKEUP_BIT_HSI0 BIT(3)
237 #define WAKEUP_BIT_HSI1 BIT(4)
238 #define WAKEUP_BIT_CA_WAKE BIT(5)
239 #define WAKEUP_BIT_USB BIT(6)
240 #define WAKEUP_BIT_ABB BIT(7)
241 #define WAKEUP_BIT_ABB_FIFO BIT(8)
242 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
243 #define WAKEUP_BIT_CA_SLEEP BIT(10)
244 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
245 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
246 #define WAKEUP_BIT_ANC_OK BIT(13)
247 #define WAKEUP_BIT_SW_ERROR BIT(14)
248 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
249 #define WAKEUP_BIT_ARM BIT(17)
250 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
251 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
252 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
253 #define WAKEUP_BIT_GPIO0 BIT(23)
254 #define WAKEUP_BIT_GPIO1 BIT(24)
255 #define WAKEUP_BIT_GPIO2 BIT(25)
256 #define WAKEUP_BIT_GPIO3 BIT(26)
257 #define WAKEUP_BIT_GPIO4 BIT(27)
258 #define WAKEUP_BIT_GPIO5 BIT(28)
259 #define WAKEUP_BIT_GPIO6 BIT(29)
260 #define WAKEUP_BIT_GPIO7 BIT(30)
261 #define WAKEUP_BIT_GPIO8 BIT(31)
262
263 static struct {
264         bool valid;
265         struct prcmu_fw_version version;
266 } fw_info;
267
268 static struct irq_domain *db8500_irq_domain;
269
270 /*
271  * This vector maps irq numbers to the bits in the bit field used in
272  * communication with the PRCMU firmware.
273  *
274  * The reason for having this is to keep the irq numbers contiguous even though
275  * the bits in the bit field are not. (The bits also have a tendency to move
276  * around, to further complicate matters.)
277  */
278 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
279 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
280
281 #define IRQ_PRCMU_RTC 0
282 #define IRQ_PRCMU_RTT0 1
283 #define IRQ_PRCMU_RTT1 2
284 #define IRQ_PRCMU_HSI0 3
285 #define IRQ_PRCMU_HSI1 4
286 #define IRQ_PRCMU_CA_WAKE 5
287 #define IRQ_PRCMU_USB 6
288 #define IRQ_PRCMU_ABB 7
289 #define IRQ_PRCMU_ABB_FIFO 8
290 #define IRQ_PRCMU_ARM 9
291 #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
292 #define IRQ_PRCMU_GPIO0 11
293 #define IRQ_PRCMU_GPIO1 12
294 #define IRQ_PRCMU_GPIO2 13
295 #define IRQ_PRCMU_GPIO3 14
296 #define IRQ_PRCMU_GPIO4 15
297 #define IRQ_PRCMU_GPIO5 16
298 #define IRQ_PRCMU_GPIO6 17
299 #define IRQ_PRCMU_GPIO7 18
300 #define IRQ_PRCMU_GPIO8 19
301 #define IRQ_PRCMU_CA_SLEEP 20
302 #define IRQ_PRCMU_HOTMON_LOW 21
303 #define IRQ_PRCMU_HOTMON_HIGH 22
304 #define NUM_PRCMU_WAKEUPS 23
305
306 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
307         IRQ_ENTRY(RTC),
308         IRQ_ENTRY(RTT0),
309         IRQ_ENTRY(RTT1),
310         IRQ_ENTRY(HSI0),
311         IRQ_ENTRY(HSI1),
312         IRQ_ENTRY(CA_WAKE),
313         IRQ_ENTRY(USB),
314         IRQ_ENTRY(ABB),
315         IRQ_ENTRY(ABB_FIFO),
316         IRQ_ENTRY(CA_SLEEP),
317         IRQ_ENTRY(ARM),
318         IRQ_ENTRY(HOTMON_LOW),
319         IRQ_ENTRY(HOTMON_HIGH),
320         IRQ_ENTRY(MODEM_SW_RESET_REQ),
321         IRQ_ENTRY(GPIO0),
322         IRQ_ENTRY(GPIO1),
323         IRQ_ENTRY(GPIO2),
324         IRQ_ENTRY(GPIO3),
325         IRQ_ENTRY(GPIO4),
326         IRQ_ENTRY(GPIO5),
327         IRQ_ENTRY(GPIO6),
328         IRQ_ENTRY(GPIO7),
329         IRQ_ENTRY(GPIO8)
330 };
331
332 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
333 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
334 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
335         WAKEUP_ENTRY(RTC),
336         WAKEUP_ENTRY(RTT0),
337         WAKEUP_ENTRY(RTT1),
338         WAKEUP_ENTRY(HSI0),
339         WAKEUP_ENTRY(HSI1),
340         WAKEUP_ENTRY(USB),
341         WAKEUP_ENTRY(ABB),
342         WAKEUP_ENTRY(ABB_FIFO),
343         WAKEUP_ENTRY(ARM)
344 };
345
346 /*
347  * mb0_transfer - state needed for mailbox 0 communication.
348  * @lock:               The transaction lock.
349  * @dbb_events_lock:    A lock used to handle concurrent access to (parts of)
350  *                      the request data.
351  * @mask_work:          Work structure used for (un)masking wakeup interrupts.
352  * @req:                Request data that need to persist between requests.
353  */
354 static struct {
355         spinlock_t lock;
356         spinlock_t dbb_irqs_lock;
357         struct work_struct mask_work;
358         struct mutex ac_wake_lock;
359         struct completion ac_wake_work;
360         struct {
361                 u32 dbb_irqs;
362                 u32 dbb_wakeups;
363                 u32 abb_events;
364         } req;
365 } mb0_transfer;
366
367 /*
368  * mb1_transfer - state needed for mailbox 1 communication.
369  * @lock:       The transaction lock.
370  * @work:       The transaction completion structure.
371  * @ape_opp:    The current APE OPP.
372  * @ack:        Reply ("acknowledge") data.
373  */
374 static struct {
375         struct mutex lock;
376         struct completion work;
377         u8 ape_opp;
378         struct {
379                 u8 header;
380                 u8 arm_opp;
381                 u8 ape_opp;
382                 u8 ape_voltage_status;
383         } ack;
384 } mb1_transfer;
385
386 /*
387  * mb2_transfer - state needed for mailbox 2 communication.
388  * @lock:            The transaction lock.
389  * @work:            The transaction completion structure.
390  * @auto_pm_lock:    The autonomous power management configuration lock.
391  * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
392  * @req:             Request data that need to persist between requests.
393  * @ack:             Reply ("acknowledge") data.
394  */
395 static struct {
396         struct mutex lock;
397         struct completion work;
398         spinlock_t auto_pm_lock;
399         bool auto_pm_enabled;
400         struct {
401                 u8 status;
402         } ack;
403 } mb2_transfer;
404
405 /*
406  * mb3_transfer - state needed for mailbox 3 communication.
407  * @lock:               The request lock.
408  * @sysclk_lock:        A lock used to handle concurrent sysclk requests.
409  * @sysclk_work:        Work structure used for sysclk requests.
410  */
411 static struct {
412         spinlock_t lock;
413         struct mutex sysclk_lock;
414         struct completion sysclk_work;
415 } mb3_transfer;
416
417 /*
418  * mb4_transfer - state needed for mailbox 4 communication.
419  * @lock:       The transaction lock.
420  * @work:       The transaction completion structure.
421  */
422 static struct {
423         struct mutex lock;
424         struct completion work;
425 } mb4_transfer;
426
427 /*
428  * mb5_transfer - state needed for mailbox 5 communication.
429  * @lock:       The transaction lock.
430  * @work:       The transaction completion structure.
431  * @ack:        Reply ("acknowledge") data.
432  */
433 static struct {
434         struct mutex lock;
435         struct completion work;
436         struct {
437                 u8 status;
438                 u8 value;
439         } ack;
440 } mb5_transfer;
441
442 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
443
444 /* Spinlocks */
445 static DEFINE_SPINLOCK(prcmu_lock);
446 static DEFINE_SPINLOCK(clkout_lock);
447
448 /* Global var to runtime determine TCDM base for v2 or v1 */
449 static __iomem void *tcdm_base;
450 static __iomem void *prcmu_base;
451
452 struct clk_mgt {
453         u32 offset;
454         u32 pllsw;
455         int branch;
456         bool clk38div;
457 };
458
459 enum {
460         PLL_RAW,
461         PLL_FIX,
462         PLL_DIV
463 };
464
465 static DEFINE_SPINLOCK(clk_mgt_lock);
466
467 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
468         { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
469 static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
470         CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
471         CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
472         CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
473         CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
474         CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
475         CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
476         CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
477         CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
478         CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
479         CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
480         CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
481         CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
482         CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
483         CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
484         CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
485         CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
486         CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
487         CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
488         CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
489         CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
490         CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
491         CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
492         CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
493         CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
494         CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
495         CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
496         CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
497         CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
498         CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
499 };
500
501 struct dsiclk {
502         u32 divsel_mask;
503         u32 divsel_shift;
504         u32 divsel;
505 };
506
507 static struct dsiclk dsiclk[2] = {
508         {
509                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
510                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
511                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
512         },
513         {
514                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
515                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
516                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
517         }
518 };
519
520 struct dsiescclk {
521         u32 en;
522         u32 div_mask;
523         u32 div_shift;
524 };
525
526 static struct dsiescclk dsiescclk[3] = {
527         {
528                 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
529                 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
530                 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
531         },
532         {
533                 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
534                 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
535                 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
536         },
537         {
538                 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
539                 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
540                 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
541         }
542 };
543
544
545 /*
546 * Used by MCDE to setup all necessary PRCMU registers
547 */
548 #define PRCMU_RESET_DSIPLL              0x00004000
549 #define PRCMU_UNCLAMP_DSIPLL            0x00400800
550
551 #define PRCMU_CLK_PLL_DIV_SHIFT         0
552 #define PRCMU_CLK_PLL_SW_SHIFT          5
553 #define PRCMU_CLK_38                    (1 << 9)
554 #define PRCMU_CLK_38_SRC                (1 << 10)
555 #define PRCMU_CLK_38_DIV                (1 << 11)
556
557 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
558 #define PRCMU_DSI_CLOCK_SETTING         0x0000008C
559
560 /* DPI 50000000 Hz */
561 #define PRCMU_DPI_CLOCK_SETTING         ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
562                                           (16 << PRCMU_CLK_PLL_DIV_SHIFT))
563 #define PRCMU_DSI_LP_CLOCK_SETTING      0x00000E00
564
565 /* D=101, N=1, R=4, SELDIV2=0 */
566 #define PRCMU_PLLDSI_FREQ_SETTING       0x00040165
567
568 #define PRCMU_ENABLE_PLLDSI             0x00000001
569 #define PRCMU_DISABLE_PLLDSI            0x00000000
570 #define PRCMU_RELEASE_RESET_DSS         0x0000400C
571 #define PRCMU_DSI_PLLOUT_SEL_SETTING    0x00000202
572 /* ESC clk, div0=1, div1=1, div2=3 */
573 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV   0x07030101
574 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV  0x00030101
575 #define PRCMU_DSI_RESET_SW              0x00000007
576
577 #define PRCMU_PLLDSI_LOCKP_LOCKED       0x3
578
579 int db8500_prcmu_enable_dsipll(void)
580 {
581         int i;
582
583         /* Clear DSIPLL_RESETN */
584         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
585         /* Unclamp DSIPLL in/out */
586         writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
587
588         /* Set DSI PLL FREQ */
589         writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
590         writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
591         /* Enable Escape clocks */
592         writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
593
594         /* Start DSI PLL */
595         writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
596         /* Reset DSI PLL */
597         writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
598         for (i = 0; i < 10; i++) {
599                 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
600                                         == PRCMU_PLLDSI_LOCKP_LOCKED)
601                         break;
602                 udelay(100);
603         }
604         /* Set DSIPLL_RESETN */
605         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
606         return 0;
607 }
608
609 int db8500_prcmu_disable_dsipll(void)
610 {
611         /* Disable dsi pll */
612         writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
613         /* Disable  escapeclock */
614         writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
615         return 0;
616 }
617
618 int db8500_prcmu_set_display_clocks(void)
619 {
620         unsigned long flags;
621
622         spin_lock_irqsave(&clk_mgt_lock, flags);
623
624         /* Grab the HW semaphore. */
625         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
626                 cpu_relax();
627
628         writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
629         writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
630         writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
631
632         /* Release the HW semaphore. */
633         writel(0, PRCM_SEM);
634
635         spin_unlock_irqrestore(&clk_mgt_lock, flags);
636
637         return 0;
638 }
639
640 u32 db8500_prcmu_read(unsigned int reg)
641 {
642         return readl(prcmu_base + reg);
643 }
644
645 void db8500_prcmu_write(unsigned int reg, u32 value)
646 {
647         unsigned long flags;
648
649         spin_lock_irqsave(&prcmu_lock, flags);
650         writel(value, (prcmu_base + reg));
651         spin_unlock_irqrestore(&prcmu_lock, flags);
652 }
653
654 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
655 {
656         u32 val;
657         unsigned long flags;
658
659         spin_lock_irqsave(&prcmu_lock, flags);
660         val = readl(prcmu_base + reg);
661         val = ((val & ~mask) | (value & mask));
662         writel(val, (prcmu_base + reg));
663         spin_unlock_irqrestore(&prcmu_lock, flags);
664 }
665
666 struct prcmu_fw_version *prcmu_get_fw_version(void)
667 {
668         return fw_info.valid ? &fw_info.version : NULL;
669 }
670
671 bool prcmu_has_arm_maxopp(void)
672 {
673         return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
674                 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
675 }
676
677 /**
678  * prcmu_get_boot_status - PRCMU boot status checking
679  * Returns: the current PRCMU boot status
680  */
681 int prcmu_get_boot_status(void)
682 {
683         return readb(tcdm_base + PRCM_BOOT_STATUS);
684 }
685
686 /**
687  * prcmu_set_rc_a2p - This function is used to run few power state sequences
688  * @val: Value to be set, i.e. transition requested
689  * Returns: 0 on success, -EINVAL on invalid argument
690  *
691  * This function is used to run the following power state sequences -
692  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
693  */
694 int prcmu_set_rc_a2p(enum romcode_write val)
695 {
696         if (val < RDY_2_DS || val > RDY_2_XP70_RST)
697                 return -EINVAL;
698         writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
699         return 0;
700 }
701
702 /**
703  * prcmu_get_rc_p2a - This function is used to get power state sequences
704  * Returns: the power transition that has last happened
705  *
706  * This function can return the following transitions-
707  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
708  */
709 enum romcode_read prcmu_get_rc_p2a(void)
710 {
711         return readb(tcdm_base + PRCM_ROMCODE_P2A);
712 }
713
714 /**
715  * prcmu_get_current_mode - Return the current XP70 power mode
716  * Returns: Returns the current AP(ARM) power mode: init,
717  * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
718  */
719 enum ap_pwrst prcmu_get_xp70_current_state(void)
720 {
721         return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
722 }
723
724 /**
725  * prcmu_config_clkout - Configure one of the programmable clock outputs.
726  * @clkout:     The CLKOUT number (0 or 1).
727  * @source:     The clock to be used (one of the PRCMU_CLKSRC_*).
728  * @div:        The divider to be applied.
729  *
730  * Configures one of the programmable clock outputs (CLKOUTs).
731  * @div should be in the range [1,63] to request a configuration, or 0 to
732  * inform that the configuration is no longer requested.
733  */
734 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
735 {
736         static int requests[2];
737         int r = 0;
738         unsigned long flags;
739         u32 val;
740         u32 bits;
741         u32 mask;
742         u32 div_mask;
743
744         BUG_ON(clkout > 1);
745         BUG_ON(div > 63);
746         BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
747
748         if (!div && !requests[clkout])
749                 return -EINVAL;
750
751         switch (clkout) {
752         case 0:
753                 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
754                 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
755                 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
756                         (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
757                 break;
758         case 1:
759                 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
760                 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
761                         PRCM_CLKOCR_CLK1TYPE);
762                 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
763                         (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
764                 break;
765         }
766         bits &= mask;
767
768         spin_lock_irqsave(&clkout_lock, flags);
769
770         val = readl(PRCM_CLKOCR);
771         if (val & div_mask) {
772                 if (div) {
773                         if ((val & mask) != bits) {
774                                 r = -EBUSY;
775                                 goto unlock_and_return;
776                         }
777                 } else {
778                         if ((val & mask & ~div_mask) != bits) {
779                                 r = -EINVAL;
780                                 goto unlock_and_return;
781                         }
782                 }
783         }
784         writel((bits | (val & ~mask)), PRCM_CLKOCR);
785         requests[clkout] += (div ? 1 : -1);
786
787 unlock_and_return:
788         spin_unlock_irqrestore(&clkout_lock, flags);
789
790         return r;
791 }
792
793 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
794 {
795         unsigned long flags;
796
797         BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
798
799         spin_lock_irqsave(&mb0_transfer.lock, flags);
800
801         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
802                 cpu_relax();
803
804         writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
805         writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
806         writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
807         writeb((keep_ulp_clk ? 1 : 0),
808                 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
809         writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
810         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
811
812         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
813
814         return 0;
815 }
816
817 u8 db8500_prcmu_get_power_state_result(void)
818 {
819         return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
820 }
821
822 /* This function should only be called while mb0_transfer.lock is held. */
823 static void config_wakeups(void)
824 {
825         const u8 header[2] = {
826                 MB0H_CONFIG_WAKEUPS_EXE,
827                 MB0H_CONFIG_WAKEUPS_SLEEP
828         };
829         static u32 last_dbb_events;
830         static u32 last_abb_events;
831         u32 dbb_events;
832         u32 abb_events;
833         unsigned int i;
834
835         dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
836         dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
837
838         abb_events = mb0_transfer.req.abb_events;
839
840         if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
841                 return;
842
843         for (i = 0; i < 2; i++) {
844                 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
845                         cpu_relax();
846                 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
847                 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
848                 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
849                 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
850         }
851         last_dbb_events = dbb_events;
852         last_abb_events = abb_events;
853 }
854
855 void db8500_prcmu_enable_wakeups(u32 wakeups)
856 {
857         unsigned long flags;
858         u32 bits;
859         int i;
860
861         BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
862
863         for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
864                 if (wakeups & BIT(i))
865                         bits |= prcmu_wakeup_bit[i];
866         }
867
868         spin_lock_irqsave(&mb0_transfer.lock, flags);
869
870         mb0_transfer.req.dbb_wakeups = bits;
871         config_wakeups();
872
873         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
874 }
875
876 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
877 {
878         unsigned long flags;
879
880         spin_lock_irqsave(&mb0_transfer.lock, flags);
881
882         mb0_transfer.req.abb_events = abb_events;
883         config_wakeups();
884
885         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
886 }
887
888 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
889 {
890         if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
891                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
892         else
893                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
894 }
895
896 /**
897  * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
898  * @opp: The new ARM operating point to which transition is to be made
899  * Returns: 0 on success, non-zero on failure
900  *
901  * This function sets the the operating point of the ARM.
902  */
903 int db8500_prcmu_set_arm_opp(u8 opp)
904 {
905         int r;
906
907         if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
908                 return -EINVAL;
909
910         r = 0;
911
912         mutex_lock(&mb1_transfer.lock);
913
914         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
915                 cpu_relax();
916
917         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
918         writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
919         writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
920
921         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
922         wait_for_completion(&mb1_transfer.work);
923
924         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
925                 (mb1_transfer.ack.arm_opp != opp))
926                 r = -EIO;
927
928         mutex_unlock(&mb1_transfer.lock);
929
930         return r;
931 }
932
933 /**
934  * db8500_prcmu_get_arm_opp - get the current ARM OPP
935  *
936  * Returns: the current ARM OPP
937  */
938 int db8500_prcmu_get_arm_opp(void)
939 {
940         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
941 }
942
943 /**
944  * db8500_prcmu_get_ddr_opp - get the current DDR OPP
945  *
946  * Returns: the current DDR OPP
947  */
948 int db8500_prcmu_get_ddr_opp(void)
949 {
950         return readb(PRCM_DDR_SUBSYS_APE_MINBW);
951 }
952
953 /**
954  * db8500_set_ddr_opp - set the appropriate DDR OPP
955  * @opp: The new DDR operating point to which transition is to be made
956  * Returns: 0 on success, non-zero on failure
957  *
958  * This function sets the operating point of the DDR.
959  */
960 static bool enable_set_ddr_opp;
961 int db8500_prcmu_set_ddr_opp(u8 opp)
962 {
963         if (opp < DDR_100_OPP || opp > DDR_25_OPP)
964                 return -EINVAL;
965         /* Changing the DDR OPP can hang the hardware pre-v21 */
966         if (enable_set_ddr_opp)
967                 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
968
969         return 0;
970 }
971
972 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
973 static void request_even_slower_clocks(bool enable)
974 {
975         u32 clock_reg[] = {
976                 PRCM_ACLK_MGT,
977                 PRCM_DMACLK_MGT
978         };
979         unsigned long flags;
980         unsigned int i;
981
982         spin_lock_irqsave(&clk_mgt_lock, flags);
983
984         /* Grab the HW semaphore. */
985         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
986                 cpu_relax();
987
988         for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
989                 u32 val;
990                 u32 div;
991
992                 val = readl(prcmu_base + clock_reg[i]);
993                 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
994                 if (enable) {
995                         if ((div <= 1) || (div > 15)) {
996                                 pr_err("prcmu: Bad clock divider %d in %s\n",
997                                         div, __func__);
998                                 goto unlock_and_return;
999                         }
1000                         div <<= 1;
1001                 } else {
1002                         if (div <= 2)
1003                                 goto unlock_and_return;
1004                         div >>= 1;
1005                 }
1006                 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1007                         (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1008                 writel(val, prcmu_base + clock_reg[i]);
1009         }
1010
1011 unlock_and_return:
1012         /* Release the HW semaphore. */
1013         writel(0, PRCM_SEM);
1014
1015         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1016 }
1017
1018 /**
1019  * db8500_set_ape_opp - set the appropriate APE OPP
1020  * @opp: The new APE operating point to which transition is to be made
1021  * Returns: 0 on success, non-zero on failure
1022  *
1023  * This function sets the operating point of the APE.
1024  */
1025 int db8500_prcmu_set_ape_opp(u8 opp)
1026 {
1027         int r = 0;
1028
1029         if (opp == mb1_transfer.ape_opp)
1030                 return 0;
1031
1032         mutex_lock(&mb1_transfer.lock);
1033
1034         if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1035                 request_even_slower_clocks(false);
1036
1037         if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1038                 goto skip_message;
1039
1040         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1041                 cpu_relax();
1042
1043         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1044         writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1045         writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1046                 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1047
1048         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1049         wait_for_completion(&mb1_transfer.work);
1050
1051         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1052                 (mb1_transfer.ack.ape_opp != opp))
1053                 r = -EIO;
1054
1055 skip_message:
1056         if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1057                 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1058                 request_even_slower_clocks(true);
1059         if (!r)
1060                 mb1_transfer.ape_opp = opp;
1061
1062         mutex_unlock(&mb1_transfer.lock);
1063
1064         return r;
1065 }
1066
1067 /**
1068  * db8500_prcmu_get_ape_opp - get the current APE OPP
1069  *
1070  * Returns: the current APE OPP
1071  */
1072 int db8500_prcmu_get_ape_opp(void)
1073 {
1074         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1075 }
1076
1077 /**
1078  * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1079  * @enable: true to request the higher voltage, false to drop a request.
1080  *
1081  * Calls to this function to enable and disable requests must be balanced.
1082  */
1083 int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1084 {
1085         int r = 0;
1086         u8 header;
1087         static unsigned int requests;
1088
1089         mutex_lock(&mb1_transfer.lock);
1090
1091         if (enable) {
1092                 if (0 != requests++)
1093                         goto unlock_and_return;
1094                 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1095         } else {
1096                 if (requests == 0) {
1097                         r = -EIO;
1098                         goto unlock_and_return;
1099                 } else if (1 != requests--) {
1100                         goto unlock_and_return;
1101                 }
1102                 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1103         }
1104
1105         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1106                 cpu_relax();
1107
1108         writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1109
1110         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1111         wait_for_completion(&mb1_transfer.work);
1112
1113         if ((mb1_transfer.ack.header != header) ||
1114                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1115                 r = -EIO;
1116
1117 unlock_and_return:
1118         mutex_unlock(&mb1_transfer.lock);
1119
1120         return r;
1121 }
1122
1123 /**
1124  * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1125  *
1126  * This function releases the power state requirements of a USB wakeup.
1127  */
1128 int prcmu_release_usb_wakeup_state(void)
1129 {
1130         int r = 0;
1131
1132         mutex_lock(&mb1_transfer.lock);
1133
1134         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1135                 cpu_relax();
1136
1137         writeb(MB1H_RELEASE_USB_WAKEUP,
1138                 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1139
1140         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1141         wait_for_completion(&mb1_transfer.work);
1142
1143         if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1144                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1145                 r = -EIO;
1146
1147         mutex_unlock(&mb1_transfer.lock);
1148
1149         return r;
1150 }
1151
1152 static int request_pll(u8 clock, bool enable)
1153 {
1154         int r = 0;
1155
1156         if (clock == PRCMU_PLLSOC0)
1157                 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1158         else if (clock == PRCMU_PLLSOC1)
1159                 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1160         else
1161                 return -EINVAL;
1162
1163         mutex_lock(&mb1_transfer.lock);
1164
1165         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1166                 cpu_relax();
1167
1168         writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1169         writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1170
1171         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1172         wait_for_completion(&mb1_transfer.work);
1173
1174         if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1175                 r = -EIO;
1176
1177         mutex_unlock(&mb1_transfer.lock);
1178
1179         return r;
1180 }
1181
1182 /**
1183  * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1184  * @epod_id: The EPOD to set
1185  * @epod_state: The new EPOD state
1186  *
1187  * This function sets the state of a EPOD (power domain). It may not be called
1188  * from interrupt context.
1189  */
1190 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1191 {
1192         int r = 0;
1193         bool ram_retention = false;
1194         int i;
1195
1196         /* check argument */
1197         BUG_ON(epod_id >= NUM_EPOD_ID);
1198
1199         /* set flag if retention is possible */
1200         switch (epod_id) {
1201         case EPOD_ID_SVAMMDSP:
1202         case EPOD_ID_SIAMMDSP:
1203         case EPOD_ID_ESRAM12:
1204         case EPOD_ID_ESRAM34:
1205                 ram_retention = true;
1206                 break;
1207         }
1208
1209         /* check argument */
1210         BUG_ON(epod_state > EPOD_STATE_ON);
1211         BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1212
1213         /* get lock */
1214         mutex_lock(&mb2_transfer.lock);
1215
1216         /* wait for mailbox */
1217         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1218                 cpu_relax();
1219
1220         /* fill in mailbox */
1221         for (i = 0; i < NUM_EPOD_ID; i++)
1222                 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1223         writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1224
1225         writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1226
1227         writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1228
1229         /*
1230          * The current firmware version does not handle errors correctly,
1231          * and we cannot recover if there is an error.
1232          * This is expected to change when the firmware is updated.
1233          */
1234         if (!wait_for_completion_timeout(&mb2_transfer.work,
1235                         msecs_to_jiffies(20000))) {
1236                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1237                         __func__);
1238                 r = -EIO;
1239                 goto unlock_and_return;
1240         }
1241
1242         if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1243                 r = -EIO;
1244
1245 unlock_and_return:
1246         mutex_unlock(&mb2_transfer.lock);
1247         return r;
1248 }
1249
1250 /**
1251  * prcmu_configure_auto_pm - Configure autonomous power management.
1252  * @sleep: Configuration for ApSleep.
1253  * @idle:  Configuration for ApIdle.
1254  */
1255 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1256         struct prcmu_auto_pm_config *idle)
1257 {
1258         u32 sleep_cfg;
1259         u32 idle_cfg;
1260         unsigned long flags;
1261
1262         BUG_ON((sleep == NULL) || (idle == NULL));
1263
1264         sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1265         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1266         sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1267         sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1268         sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1269         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1270
1271         idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1272         idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1273         idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1274         idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1275         idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1276         idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1277
1278         spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1279
1280         /*
1281          * The autonomous power management configuration is done through
1282          * fields in mailbox 2, but these fields are only used as shared
1283          * variables - i.e. there is no need to send a message.
1284          */
1285         writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1286         writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1287
1288         mb2_transfer.auto_pm_enabled =
1289                 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1290                  (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1291                  (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1292                  (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1293
1294         spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1295 }
1296 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1297
1298 bool prcmu_is_auto_pm_enabled(void)
1299 {
1300         return mb2_transfer.auto_pm_enabled;
1301 }
1302
1303 static int request_sysclk(bool enable)
1304 {
1305         int r;
1306         unsigned long flags;
1307
1308         r = 0;
1309
1310         mutex_lock(&mb3_transfer.sysclk_lock);
1311
1312         spin_lock_irqsave(&mb3_transfer.lock, flags);
1313
1314         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1315                 cpu_relax();
1316
1317         writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1318
1319         writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1320         writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1321
1322         spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1323
1324         /*
1325          * The firmware only sends an ACK if we want to enable the
1326          * SysClk, and it succeeds.
1327          */
1328         if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1329                         msecs_to_jiffies(20000))) {
1330                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1331                         __func__);
1332                 r = -EIO;
1333         }
1334
1335         mutex_unlock(&mb3_transfer.sysclk_lock);
1336
1337         return r;
1338 }
1339
1340 static int request_timclk(bool enable)
1341 {
1342         u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1343
1344         if (!enable)
1345                 val |= PRCM_TCR_STOP_TIMERS;
1346         writel(val, PRCM_TCR);
1347
1348         return 0;
1349 }
1350
1351 static int request_clock(u8 clock, bool enable)
1352 {
1353         u32 val;
1354         unsigned long flags;
1355
1356         spin_lock_irqsave(&clk_mgt_lock, flags);
1357
1358         /* Grab the HW semaphore. */
1359         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1360                 cpu_relax();
1361
1362         val = readl(prcmu_base + clk_mgt[clock].offset);
1363         if (enable) {
1364                 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1365         } else {
1366                 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1367                 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1368         }
1369         writel(val, prcmu_base + clk_mgt[clock].offset);
1370
1371         /* Release the HW semaphore. */
1372         writel(0, PRCM_SEM);
1373
1374         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1375
1376         return 0;
1377 }
1378
1379 static int request_sga_clock(u8 clock, bool enable)
1380 {
1381         u32 val;
1382         int ret;
1383
1384         if (enable) {
1385                 val = readl(PRCM_CGATING_BYPASS);
1386                 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1387         }
1388
1389         ret = request_clock(clock, enable);
1390
1391         if (!ret && !enable) {
1392                 val = readl(PRCM_CGATING_BYPASS);
1393                 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1394         }
1395
1396         return ret;
1397 }
1398
1399 static inline bool plldsi_locked(void)
1400 {
1401         return (readl(PRCM_PLLDSI_LOCKP) &
1402                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1403                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1404                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1405                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1406 }
1407
1408 static int request_plldsi(bool enable)
1409 {
1410         int r = 0;
1411         u32 val;
1412
1413         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1414                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1415                 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1416
1417         val = readl(PRCM_PLLDSI_ENABLE);
1418         if (enable)
1419                 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1420         else
1421                 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1422         writel(val, PRCM_PLLDSI_ENABLE);
1423
1424         if (enable) {
1425                 unsigned int i;
1426                 bool locked = plldsi_locked();
1427
1428                 for (i = 10; !locked && (i > 0); --i) {
1429                         udelay(100);
1430                         locked = plldsi_locked();
1431                 }
1432                 if (locked) {
1433                         writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1434                                 PRCM_APE_RESETN_SET);
1435                 } else {
1436                         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1437                                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1438                                 PRCM_MMIP_LS_CLAMP_SET);
1439                         val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1440                         writel(val, PRCM_PLLDSI_ENABLE);
1441                         r = -EAGAIN;
1442                 }
1443         } else {
1444                 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1445         }
1446         return r;
1447 }
1448
1449 static int request_dsiclk(u8 n, bool enable)
1450 {
1451         u32 val;
1452
1453         val = readl(PRCM_DSI_PLLOUT_SEL);
1454         val &= ~dsiclk[n].divsel_mask;
1455         val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1456                 dsiclk[n].divsel_shift);
1457         writel(val, PRCM_DSI_PLLOUT_SEL);
1458         return 0;
1459 }
1460
1461 static int request_dsiescclk(u8 n, bool enable)
1462 {
1463         u32 val;
1464
1465         val = readl(PRCM_DSITVCLK_DIV);
1466         enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1467         writel(val, PRCM_DSITVCLK_DIV);
1468         return 0;
1469 }
1470
1471 /**
1472  * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1473  * @clock:      The clock for which the request is made.
1474  * @enable:     Whether the clock should be enabled (true) or disabled (false).
1475  *
1476  * This function should only be used by the clock implementation.
1477  * Do not use it from any other place!
1478  */
1479 int db8500_prcmu_request_clock(u8 clock, bool enable)
1480 {
1481         if (clock == PRCMU_SGACLK)
1482                 return request_sga_clock(clock, enable);
1483         else if (clock < PRCMU_NUM_REG_CLOCKS)
1484                 return request_clock(clock, enable);
1485         else if (clock == PRCMU_TIMCLK)
1486                 return request_timclk(enable);
1487         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1488                 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1489         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1490                 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1491         else if (clock == PRCMU_PLLDSI)
1492                 return request_plldsi(enable);
1493         else if (clock == PRCMU_SYSCLK)
1494                 return request_sysclk(enable);
1495         else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1496                 return request_pll(clock, enable);
1497         else
1498                 return -EINVAL;
1499 }
1500
1501 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1502         int branch)
1503 {
1504         u64 rate;
1505         u32 val;
1506         u32 d;
1507         u32 div = 1;
1508
1509         val = readl(reg);
1510
1511         rate = src_rate;
1512         rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1513
1514         d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1515         if (d > 1)
1516                 div *= d;
1517
1518         d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1519         if (d > 1)
1520                 div *= d;
1521
1522         if (val & PRCM_PLL_FREQ_SELDIV2)
1523                 div *= 2;
1524
1525         if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1526                 (val & PRCM_PLL_FREQ_DIV2EN) &&
1527                 ((reg == PRCM_PLLSOC0_FREQ) ||
1528                  (reg == PRCM_PLLARM_FREQ) ||
1529                  (reg == PRCM_PLLDDR_FREQ))))
1530                 div *= 2;
1531
1532         (void)do_div(rate, div);
1533
1534         return (unsigned long)rate;
1535 }
1536
1537 #define ROOT_CLOCK_RATE 38400000
1538
1539 static unsigned long clock_rate(u8 clock)
1540 {
1541         u32 val;
1542         u32 pllsw;
1543         unsigned long rate = ROOT_CLOCK_RATE;
1544
1545         val = readl(prcmu_base + clk_mgt[clock].offset);
1546
1547         if (val & PRCM_CLK_MGT_CLK38) {
1548                 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1549                         rate /= 2;
1550                 return rate;
1551         }
1552
1553         val |= clk_mgt[clock].pllsw;
1554         pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1555
1556         if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1557                 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1558         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1559                 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1560         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1561                 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1562         else
1563                 return 0;
1564
1565         if ((clock == PRCMU_SGACLK) &&
1566                 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1567                 u64 r = (rate * 10);
1568
1569                 (void)do_div(r, 25);
1570                 return (unsigned long)r;
1571         }
1572         val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1573         if (val)
1574                 return rate / val;
1575         else
1576                 return 0;
1577 }
1578
1579 static unsigned long armss_rate(void)
1580 {
1581         u32 r;
1582         unsigned long rate;
1583
1584         r = readl(PRCM_ARM_CHGCLKREQ);
1585
1586         if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1587                 /* External ARMCLKFIX clock */
1588
1589                 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1590
1591                 /* Check PRCM_ARM_CHGCLKREQ divider */
1592                 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1593                         rate /= 2;
1594
1595                 /* Check PRCM_ARMCLKFIX_MGT divider */
1596                 r = readl(PRCM_ARMCLKFIX_MGT);
1597                 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1598                 rate /= r;
1599
1600         } else {/* ARM PLL */
1601                 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1602         }
1603
1604         return rate;
1605 }
1606
1607 static unsigned long dsiclk_rate(u8 n)
1608 {
1609         u32 divsel;
1610         u32 div = 1;
1611
1612         divsel = readl(PRCM_DSI_PLLOUT_SEL);
1613         divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1614
1615         if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1616                 divsel = dsiclk[n].divsel;
1617         else
1618                 dsiclk[n].divsel = divsel;
1619
1620         switch (divsel) {
1621         case PRCM_DSI_PLLOUT_SEL_PHI_4:
1622                 div *= 2;
1623         case PRCM_DSI_PLLOUT_SEL_PHI_2:
1624                 div *= 2;
1625         case PRCM_DSI_PLLOUT_SEL_PHI:
1626                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1627                         PLL_RAW) / div;
1628         default:
1629                 return 0;
1630         }
1631 }
1632
1633 static unsigned long dsiescclk_rate(u8 n)
1634 {
1635         u32 div;
1636
1637         div = readl(PRCM_DSITVCLK_DIV);
1638         div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1639         return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1640 }
1641
1642 unsigned long prcmu_clock_rate(u8 clock)
1643 {
1644         if (clock < PRCMU_NUM_REG_CLOCKS)
1645                 return clock_rate(clock);
1646         else if (clock == PRCMU_TIMCLK)
1647                 return ROOT_CLOCK_RATE / 16;
1648         else if (clock == PRCMU_SYSCLK)
1649                 return ROOT_CLOCK_RATE;
1650         else if (clock == PRCMU_PLLSOC0)
1651                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1652         else if (clock == PRCMU_PLLSOC1)
1653                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1654         else if (clock == PRCMU_ARMSS)
1655                 return armss_rate();
1656         else if (clock == PRCMU_PLLDDR)
1657                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1658         else if (clock == PRCMU_PLLDSI)
1659                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1660                         PLL_RAW);
1661         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1662                 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1663         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1664                 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1665         else
1666                 return 0;
1667 }
1668
1669 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1670 {
1671         if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1672                 return ROOT_CLOCK_RATE;
1673         clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1674         if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1675                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1676         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1677                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1678         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1679                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1680         else
1681                 return 0;
1682 }
1683
1684 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1685 {
1686         u32 div;
1687
1688         div = (src_rate / rate);
1689         if (div == 0)
1690                 return 1;
1691         if (rate < (src_rate / div))
1692                 div++;
1693         return div;
1694 }
1695
1696 static long round_clock_rate(u8 clock, unsigned long rate)
1697 {
1698         u32 val;
1699         u32 div;
1700         unsigned long src_rate;
1701         long rounded_rate;
1702
1703         val = readl(prcmu_base + clk_mgt[clock].offset);
1704         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1705                 clk_mgt[clock].branch);
1706         div = clock_divider(src_rate, rate);
1707         if (val & PRCM_CLK_MGT_CLK38) {
1708                 if (clk_mgt[clock].clk38div) {
1709                         if (div > 2)
1710                                 div = 2;
1711                 } else {
1712                         div = 1;
1713                 }
1714         } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1715                 u64 r = (src_rate * 10);
1716
1717                 (void)do_div(r, 25);
1718                 if (r <= rate)
1719                         return (unsigned long)r;
1720         }
1721         rounded_rate = (src_rate / min(div, (u32)31));
1722
1723         return rounded_rate;
1724 }
1725
1726 /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */
1727 static struct cpufreq_frequency_table db8500_cpufreq_table[] = {
1728         { .frequency = 200000, .driver_data = ARM_EXTCLK,},
1729         { .frequency = 400000, .driver_data = ARM_50_OPP,},
1730         { .frequency = 800000, .driver_data = ARM_100_OPP,},
1731         { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */
1732         { .frequency = CPUFREQ_TABLE_END,},
1733 };
1734
1735 static long round_armss_rate(unsigned long rate)
1736 {
1737         struct cpufreq_frequency_table *pos;
1738         long freq = 0;
1739
1740         /* cpufreq table frequencies is in KHz. */
1741         rate = rate / 1000;
1742
1743         /* Find the corresponding arm opp from the cpufreq table. */
1744         cpufreq_for_each_entry(pos, db8500_cpufreq_table) {
1745                 freq = pos->frequency;
1746                 if (freq == rate)
1747                         break;
1748         }
1749
1750         /* Return the last valid value, even if a match was not found. */
1751         return freq * 1000;
1752 }
1753
1754 #define MIN_PLL_VCO_RATE 600000000ULL
1755 #define MAX_PLL_VCO_RATE 1680640000ULL
1756
1757 static long round_plldsi_rate(unsigned long rate)
1758 {
1759         long rounded_rate = 0;
1760         unsigned long src_rate;
1761         unsigned long rem;
1762         u32 r;
1763
1764         src_rate = clock_rate(PRCMU_HDMICLK);
1765         rem = rate;
1766
1767         for (r = 7; (rem > 0) && (r > 0); r--) {
1768                 u64 d;
1769
1770                 d = (r * rate);
1771                 (void)do_div(d, src_rate);
1772                 if (d < 6)
1773                         d = 6;
1774                 else if (d > 255)
1775                         d = 255;
1776                 d *= src_rate;
1777                 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1778                         ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1779                         continue;
1780                 (void)do_div(d, r);
1781                 if (rate < d) {
1782                         if (rounded_rate == 0)
1783                                 rounded_rate = (long)d;
1784                         break;
1785                 }
1786                 if ((rate - d) < rem) {
1787                         rem = (rate - d);
1788                         rounded_rate = (long)d;
1789                 }
1790         }
1791         return rounded_rate;
1792 }
1793
1794 static long round_dsiclk_rate(unsigned long rate)
1795 {
1796         u32 div;
1797         unsigned long src_rate;
1798         long rounded_rate;
1799
1800         src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1801                 PLL_RAW);
1802         div = clock_divider(src_rate, rate);
1803         rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1804
1805         return rounded_rate;
1806 }
1807
1808 static long round_dsiescclk_rate(unsigned long rate)
1809 {
1810         u32 div;
1811         unsigned long src_rate;
1812         long rounded_rate;
1813
1814         src_rate = clock_rate(PRCMU_TVCLK);
1815         div = clock_divider(src_rate, rate);
1816         rounded_rate = (src_rate / min(div, (u32)255));
1817
1818         return rounded_rate;
1819 }
1820
1821 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1822 {
1823         if (clock < PRCMU_NUM_REG_CLOCKS)
1824                 return round_clock_rate(clock, rate);
1825         else if (clock == PRCMU_ARMSS)
1826                 return round_armss_rate(rate);
1827         else if (clock == PRCMU_PLLDSI)
1828                 return round_plldsi_rate(rate);
1829         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1830                 return round_dsiclk_rate(rate);
1831         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1832                 return round_dsiescclk_rate(rate);
1833         else
1834                 return (long)prcmu_clock_rate(clock);
1835 }
1836
1837 static void set_clock_rate(u8 clock, unsigned long rate)
1838 {
1839         u32 val;
1840         u32 div;
1841         unsigned long src_rate;
1842         unsigned long flags;
1843
1844         spin_lock_irqsave(&clk_mgt_lock, flags);
1845
1846         /* Grab the HW semaphore. */
1847         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1848                 cpu_relax();
1849
1850         val = readl(prcmu_base + clk_mgt[clock].offset);
1851         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1852                 clk_mgt[clock].branch);
1853         div = clock_divider(src_rate, rate);
1854         if (val & PRCM_CLK_MGT_CLK38) {
1855                 if (clk_mgt[clock].clk38div) {
1856                         if (div > 1)
1857                                 val |= PRCM_CLK_MGT_CLK38DIV;
1858                         else
1859                                 val &= ~PRCM_CLK_MGT_CLK38DIV;
1860                 }
1861         } else if (clock == PRCMU_SGACLK) {
1862                 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1863                         PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1864                 if (div == 3) {
1865                         u64 r = (src_rate * 10);
1866
1867                         (void)do_div(r, 25);
1868                         if (r <= rate) {
1869                                 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1870                                 div = 0;
1871                         }
1872                 }
1873                 val |= min(div, (u32)31);
1874         } else {
1875                 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1876                 val |= min(div, (u32)31);
1877         }
1878         writel(val, prcmu_base + clk_mgt[clock].offset);
1879
1880         /* Release the HW semaphore. */
1881         writel(0, PRCM_SEM);
1882
1883         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1884 }
1885
1886 static int set_armss_rate(unsigned long rate)
1887 {
1888         struct cpufreq_frequency_table *pos;
1889
1890         /* cpufreq table frequencies is in KHz. */
1891         rate = rate / 1000;
1892
1893         /* Find the corresponding arm opp from the cpufreq table. */
1894         cpufreq_for_each_entry(pos, db8500_cpufreq_table)
1895                 if (pos->frequency == rate)
1896                         break;
1897
1898         if (pos->frequency != rate)
1899                 return -EINVAL;
1900
1901         /* Set the new arm opp. */
1902         return db8500_prcmu_set_arm_opp(pos->driver_data);
1903 }
1904
1905 static int set_plldsi_rate(unsigned long rate)
1906 {
1907         unsigned long src_rate;
1908         unsigned long rem;
1909         u32 pll_freq = 0;
1910         u32 r;
1911
1912         src_rate = clock_rate(PRCMU_HDMICLK);
1913         rem = rate;
1914
1915         for (r = 7; (rem > 0) && (r > 0); r--) {
1916                 u64 d;
1917                 u64 hwrate;
1918
1919                 d = (r * rate);
1920                 (void)do_div(d, src_rate);
1921                 if (d < 6)
1922                         d = 6;
1923                 else if (d > 255)
1924                         d = 255;
1925                 hwrate = (d * src_rate);
1926                 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1927                         ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1928                         continue;
1929                 (void)do_div(hwrate, r);
1930                 if (rate < hwrate) {
1931                         if (pll_freq == 0)
1932                                 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1933                                         (r << PRCM_PLL_FREQ_R_SHIFT));
1934                         break;
1935                 }
1936                 if ((rate - hwrate) < rem) {
1937                         rem = (rate - hwrate);
1938                         pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1939                                 (r << PRCM_PLL_FREQ_R_SHIFT));
1940                 }
1941         }
1942         if (pll_freq == 0)
1943                 return -EINVAL;
1944
1945         pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1946         writel(pll_freq, PRCM_PLLDSI_FREQ);
1947
1948         return 0;
1949 }
1950
1951 static void set_dsiclk_rate(u8 n, unsigned long rate)
1952 {
1953         u32 val;
1954         u32 div;
1955
1956         div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1957                         clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1958
1959         dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1960                            (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1961                            /* else */   PRCM_DSI_PLLOUT_SEL_PHI_4;
1962
1963         val = readl(PRCM_DSI_PLLOUT_SEL);
1964         val &= ~dsiclk[n].divsel_mask;
1965         val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1966         writel(val, PRCM_DSI_PLLOUT_SEL);
1967 }
1968
1969 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1970 {
1971         u32 val;
1972         u32 div;
1973
1974         div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1975         val = readl(PRCM_DSITVCLK_DIV);
1976         val &= ~dsiescclk[n].div_mask;
1977         val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1978         writel(val, PRCM_DSITVCLK_DIV);
1979 }
1980
1981 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1982 {
1983         if (clock < PRCMU_NUM_REG_CLOCKS)
1984                 set_clock_rate(clock, rate);
1985         else if (clock == PRCMU_ARMSS)
1986                 return set_armss_rate(rate);
1987         else if (clock == PRCMU_PLLDSI)
1988                 return set_plldsi_rate(rate);
1989         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1990                 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1991         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1992                 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1993         return 0;
1994 }
1995
1996 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1997 {
1998         if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1999             (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2000                 return -EINVAL;
2001
2002         mutex_lock(&mb4_transfer.lock);
2003
2004         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2005                 cpu_relax();
2006
2007         writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2008         writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2009                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2010         writeb(DDR_PWR_STATE_ON,
2011                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2012         writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2013
2014         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2015         wait_for_completion(&mb4_transfer.work);
2016
2017         mutex_unlock(&mb4_transfer.lock);
2018
2019         return 0;
2020 }
2021
2022 int db8500_prcmu_config_hotdog(u8 threshold)
2023 {
2024         mutex_lock(&mb4_transfer.lock);
2025
2026         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2027                 cpu_relax();
2028
2029         writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2030         writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2031
2032         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2033         wait_for_completion(&mb4_transfer.work);
2034
2035         mutex_unlock(&mb4_transfer.lock);
2036
2037         return 0;
2038 }
2039
2040 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2041 {
2042         mutex_lock(&mb4_transfer.lock);
2043
2044         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2045                 cpu_relax();
2046
2047         writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2048         writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2049         writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2050                 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2051         writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2052
2053         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2054         wait_for_completion(&mb4_transfer.work);
2055
2056         mutex_unlock(&mb4_transfer.lock);
2057
2058         return 0;
2059 }
2060
2061 static int config_hot_period(u16 val)
2062 {
2063         mutex_lock(&mb4_transfer.lock);
2064
2065         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2066                 cpu_relax();
2067
2068         writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2069         writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2070
2071         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2072         wait_for_completion(&mb4_transfer.work);
2073
2074         mutex_unlock(&mb4_transfer.lock);
2075
2076         return 0;
2077 }
2078
2079 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2080 {
2081         if (cycles32k == 0xFFFF)
2082                 return -EINVAL;
2083
2084         return config_hot_period(cycles32k);
2085 }
2086
2087 int db8500_prcmu_stop_temp_sense(void)
2088 {
2089         return config_hot_period(0xFFFF);
2090 }
2091
2092 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2093 {
2094
2095         mutex_lock(&mb4_transfer.lock);
2096
2097         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2098                 cpu_relax();
2099
2100         writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2101         writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2102         writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2103         writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2104
2105         writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2106
2107         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2108         wait_for_completion(&mb4_transfer.work);
2109
2110         mutex_unlock(&mb4_transfer.lock);
2111
2112         return 0;
2113
2114 }
2115
2116 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2117 {
2118         BUG_ON(num == 0 || num > 0xf);
2119         return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2120                             sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2121                             A9WDOG_AUTO_OFF_DIS);
2122 }
2123 EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
2124
2125 int db8500_prcmu_enable_a9wdog(u8 id)
2126 {
2127         return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2128 }
2129 EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
2130
2131 int db8500_prcmu_disable_a9wdog(u8 id)
2132 {
2133         return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2134 }
2135 EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
2136
2137 int db8500_prcmu_kick_a9wdog(u8 id)
2138 {
2139         return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2140 }
2141 EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
2142
2143 /*
2144  * timeout is 28 bit, in ms.
2145  */
2146 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2147 {
2148         return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2149                             (id & A9WDOG_ID_MASK) |
2150                             /*
2151                              * Put the lowest 28 bits of timeout at
2152                              * offset 4. Four first bits are used for id.
2153                              */
2154                             (u8)((timeout << 4) & 0xf0),
2155                             (u8)((timeout >> 4) & 0xff),
2156                             (u8)((timeout >> 12) & 0xff),
2157                             (u8)((timeout >> 20) & 0xff));
2158 }
2159 EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
2160
2161 /**
2162  * prcmu_abb_read() - Read register value(s) from the ABB.
2163  * @slave:      The I2C slave address.
2164  * @reg:        The (start) register address.
2165  * @value:      The read out value(s).
2166  * @size:       The number of registers to read.
2167  *
2168  * Reads register value(s) from the ABB.
2169  * @size has to be 1 for the current firmware version.
2170  */
2171 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2172 {
2173         int r;
2174
2175         if (size != 1)
2176                 return -EINVAL;
2177
2178         mutex_lock(&mb5_transfer.lock);
2179
2180         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2181                 cpu_relax();
2182
2183         writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2184         writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2185         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2186         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2187         writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2188
2189         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2190
2191         if (!wait_for_completion_timeout(&mb5_transfer.work,
2192                                 msecs_to_jiffies(20000))) {
2193                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2194                         __func__);
2195                 r = -EIO;
2196         } else {
2197                 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2198         }
2199
2200         if (!r)
2201                 *value = mb5_transfer.ack.value;
2202
2203         mutex_unlock(&mb5_transfer.lock);
2204
2205         return r;
2206 }
2207
2208 /**
2209  * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2210  * @slave:      The I2C slave address.
2211  * @reg:        The (start) register address.
2212  * @value:      The value(s) to write.
2213  * @mask:       The mask(s) to use.
2214  * @size:       The number of registers to write.
2215  *
2216  * Writes masked register value(s) to the ABB.
2217  * For each @value, only the bits set to 1 in the corresponding @mask
2218  * will be written. The other bits are not changed.
2219  * @size has to be 1 for the current firmware version.
2220  */
2221 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2222 {
2223         int r;
2224
2225         if (size != 1)
2226                 return -EINVAL;
2227
2228         mutex_lock(&mb5_transfer.lock);
2229
2230         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2231                 cpu_relax();
2232
2233         writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2234         writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2235         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2236         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2237         writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2238
2239         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2240
2241         if (!wait_for_completion_timeout(&mb5_transfer.work,
2242                                 msecs_to_jiffies(20000))) {
2243                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2244                         __func__);
2245                 r = -EIO;
2246         } else {
2247                 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2248         }
2249
2250         mutex_unlock(&mb5_transfer.lock);
2251
2252         return r;
2253 }
2254
2255 /**
2256  * prcmu_abb_write() - Write register value(s) to the ABB.
2257  * @slave:      The I2C slave address.
2258  * @reg:        The (start) register address.
2259  * @value:      The value(s) to write.
2260  * @size:       The number of registers to write.
2261  *
2262  * Writes register value(s) to the ABB.
2263  * @size has to be 1 for the current firmware version.
2264  */
2265 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2266 {
2267         u8 mask = ~0;
2268
2269         return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2270 }
2271
2272 /**
2273  * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2274  */
2275 int prcmu_ac_wake_req(void)
2276 {
2277         u32 val;
2278         int ret = 0;
2279
2280         mutex_lock(&mb0_transfer.ac_wake_lock);
2281
2282         val = readl(PRCM_HOSTACCESS_REQ);
2283         if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2284                 goto unlock_and_return;
2285
2286         atomic_set(&ac_wake_req_state, 1);
2287
2288         /*
2289          * Force Modem Wake-up before hostaccess_req ping-pong.
2290          * It prevents Modem to enter in Sleep while acking the hostaccess
2291          * request. The 31us delay has been calculated by HWI.
2292          */
2293         val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2294         writel(val, PRCM_HOSTACCESS_REQ);
2295
2296         udelay(31);
2297
2298         val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2299         writel(val, PRCM_HOSTACCESS_REQ);
2300
2301         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2302                         msecs_to_jiffies(5000))) {
2303                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2304                         __func__);
2305                 ret = -EFAULT;
2306         }
2307
2308 unlock_and_return:
2309         mutex_unlock(&mb0_transfer.ac_wake_lock);
2310         return ret;
2311 }
2312
2313 /**
2314  * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2315  */
2316 void prcmu_ac_sleep_req(void)
2317 {
2318         u32 val;
2319
2320         mutex_lock(&mb0_transfer.ac_wake_lock);
2321
2322         val = readl(PRCM_HOSTACCESS_REQ);
2323         if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2324                 goto unlock_and_return;
2325
2326         writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2327                 PRCM_HOSTACCESS_REQ);
2328
2329         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2330                         msecs_to_jiffies(5000))) {
2331                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2332                         __func__);
2333         }
2334
2335         atomic_set(&ac_wake_req_state, 0);
2336
2337 unlock_and_return:
2338         mutex_unlock(&mb0_transfer.ac_wake_lock);
2339 }
2340
2341 bool db8500_prcmu_is_ac_wake_requested(void)
2342 {
2343         return (atomic_read(&ac_wake_req_state) != 0);
2344 }
2345
2346 /**
2347  * db8500_prcmu_system_reset - System reset
2348  *
2349  * Saves the reset reason code and then sets the APE_SOFTRST register which
2350  * fires interrupt to fw
2351  */
2352 void db8500_prcmu_system_reset(u16 reset_code)
2353 {
2354         writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2355         writel(1, PRCM_APE_SOFTRST);
2356 }
2357
2358 /**
2359  * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2360  *
2361  * Retrieves the reset reason code stored by prcmu_system_reset() before
2362  * last restart.
2363  */
2364 u16 db8500_prcmu_get_reset_code(void)
2365 {
2366         return readw(tcdm_base + PRCM_SW_RST_REASON);
2367 }
2368
2369 /**
2370  * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2371  */
2372 void db8500_prcmu_modem_reset(void)
2373 {
2374         mutex_lock(&mb1_transfer.lock);
2375
2376         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2377                 cpu_relax();
2378
2379         writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2380         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2381         wait_for_completion(&mb1_transfer.work);
2382
2383         /*
2384          * No need to check return from PRCMU as modem should go in reset state
2385          * This state is already managed by upper layer
2386          */
2387
2388         mutex_unlock(&mb1_transfer.lock);
2389 }
2390
2391 static void ack_dbb_wakeup(void)
2392 {
2393         unsigned long flags;
2394
2395         spin_lock_irqsave(&mb0_transfer.lock, flags);
2396
2397         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2398                 cpu_relax();
2399
2400         writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2401         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2402
2403         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2404 }
2405
2406 static inline void print_unknown_header_warning(u8 n, u8 header)
2407 {
2408         pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2409                 header, n);
2410 }
2411
2412 static bool read_mailbox_0(void)
2413 {
2414         bool r;
2415         u32 ev;
2416         unsigned int n;
2417         u8 header;
2418
2419         header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2420         switch (header) {
2421         case MB0H_WAKEUP_EXE:
2422         case MB0H_WAKEUP_SLEEP:
2423                 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2424                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2425                 else
2426                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2427
2428                 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2429                         complete(&mb0_transfer.ac_wake_work);
2430                 if (ev & WAKEUP_BIT_SYSCLK_OK)
2431                         complete(&mb3_transfer.sysclk_work);
2432
2433                 ev &= mb0_transfer.req.dbb_irqs;
2434
2435                 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2436                         if (ev & prcmu_irq_bit[n])
2437                                 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2438                 }
2439                 r = true;
2440                 break;
2441         default:
2442                 print_unknown_header_warning(0, header);
2443                 r = false;
2444                 break;
2445         }
2446         writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2447         return r;
2448 }
2449
2450 static bool read_mailbox_1(void)
2451 {
2452         mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2453         mb1_transfer.ack.arm_opp = readb(tcdm_base +
2454                 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2455         mb1_transfer.ack.ape_opp = readb(tcdm_base +
2456                 PRCM_ACK_MB1_CURRENT_APE_OPP);
2457         mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2458                 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2459         writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2460         complete(&mb1_transfer.work);
2461         return false;
2462 }
2463
2464 static bool read_mailbox_2(void)
2465 {
2466         mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2467         writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2468         complete(&mb2_transfer.work);
2469         return false;
2470 }
2471
2472 static bool read_mailbox_3(void)
2473 {
2474         writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2475         return false;
2476 }
2477
2478 static bool read_mailbox_4(void)
2479 {
2480         u8 header;
2481         bool do_complete = true;
2482
2483         header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2484         switch (header) {
2485         case MB4H_MEM_ST:
2486         case MB4H_HOTDOG:
2487         case MB4H_HOTMON:
2488         case MB4H_HOT_PERIOD:
2489         case MB4H_A9WDOG_CONF:
2490         case MB4H_A9WDOG_EN:
2491         case MB4H_A9WDOG_DIS:
2492         case MB4H_A9WDOG_LOAD:
2493         case MB4H_A9WDOG_KICK:
2494                 break;
2495         default:
2496                 print_unknown_header_warning(4, header);
2497                 do_complete = false;
2498                 break;
2499         }
2500
2501         writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2502
2503         if (do_complete)
2504                 complete(&mb4_transfer.work);
2505
2506         return false;
2507 }
2508
2509 static bool read_mailbox_5(void)
2510 {
2511         mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2512         mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2513         writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2514         complete(&mb5_transfer.work);
2515         return false;
2516 }
2517
2518 static bool read_mailbox_6(void)
2519 {
2520         writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2521         return false;
2522 }
2523
2524 static bool read_mailbox_7(void)
2525 {
2526         writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2527         return false;
2528 }
2529
2530 static bool (* const read_mailbox[NUM_MB])(void) = {
2531         read_mailbox_0,
2532         read_mailbox_1,
2533         read_mailbox_2,
2534         read_mailbox_3,
2535         read_mailbox_4,
2536         read_mailbox_5,
2537         read_mailbox_6,
2538         read_mailbox_7
2539 };
2540
2541 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2542 {
2543         u32 bits;
2544         u8 n;
2545         irqreturn_t r;
2546
2547         bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2548         if (unlikely(!bits))
2549                 return IRQ_NONE;
2550
2551         r = IRQ_HANDLED;
2552         for (n = 0; bits; n++) {
2553                 if (bits & MBOX_BIT(n)) {
2554                         bits -= MBOX_BIT(n);
2555                         if (read_mailbox[n]())
2556                                 r = IRQ_WAKE_THREAD;
2557                 }
2558         }
2559         return r;
2560 }
2561
2562 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2563 {
2564         ack_dbb_wakeup();
2565         return IRQ_HANDLED;
2566 }
2567
2568 static void prcmu_mask_work(struct work_struct *work)
2569 {
2570         unsigned long flags;
2571
2572         spin_lock_irqsave(&mb0_transfer.lock, flags);
2573
2574         config_wakeups();
2575
2576         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2577 }
2578
2579 static void prcmu_irq_mask(struct irq_data *d)
2580 {
2581         unsigned long flags;
2582
2583         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2584
2585         mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2586
2587         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2588
2589         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2590                 schedule_work(&mb0_transfer.mask_work);
2591 }
2592
2593 static void prcmu_irq_unmask(struct irq_data *d)
2594 {
2595         unsigned long flags;
2596
2597         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2598
2599         mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2600
2601         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2602
2603         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2604                 schedule_work(&mb0_transfer.mask_work);
2605 }
2606
2607 static void noop(struct irq_data *d)
2608 {
2609 }
2610
2611 static struct irq_chip prcmu_irq_chip = {
2612         .name           = "prcmu",
2613         .irq_disable    = prcmu_irq_mask,
2614         .irq_ack        = noop,
2615         .irq_mask       = prcmu_irq_mask,
2616         .irq_unmask     = prcmu_irq_unmask,
2617 };
2618
2619 static __init char *fw_project_name(u32 project)
2620 {
2621         switch (project) {
2622         case PRCMU_FW_PROJECT_U8500:
2623                 return "U8500";
2624         case PRCMU_FW_PROJECT_U8400:
2625                 return "U8400";
2626         case PRCMU_FW_PROJECT_U9500:
2627                 return "U9500";
2628         case PRCMU_FW_PROJECT_U8500_MBB:
2629                 return "U8500 MBB";
2630         case PRCMU_FW_PROJECT_U8500_C1:
2631                 return "U8500 C1";
2632         case PRCMU_FW_PROJECT_U8500_C2:
2633                 return "U8500 C2";
2634         case PRCMU_FW_PROJECT_U8500_C3:
2635                 return "U8500 C3";
2636         case PRCMU_FW_PROJECT_U8500_C4:
2637                 return "U8500 C4";
2638         case PRCMU_FW_PROJECT_U9500_MBL:
2639                 return "U9500 MBL";
2640         case PRCMU_FW_PROJECT_U8500_MBL:
2641                 return "U8500 MBL";
2642         case PRCMU_FW_PROJECT_U8500_MBL2:
2643                 return "U8500 MBL2";
2644         case PRCMU_FW_PROJECT_U8520:
2645                 return "U8520 MBL";
2646         case PRCMU_FW_PROJECT_U8420:
2647                 return "U8420";
2648         case PRCMU_FW_PROJECT_U9540:
2649                 return "U9540";
2650         case PRCMU_FW_PROJECT_A9420:
2651                 return "A9420";
2652         case PRCMU_FW_PROJECT_L8540:
2653                 return "L8540";
2654         case PRCMU_FW_PROJECT_L8580:
2655                 return "L8580";
2656         default:
2657                 return "Unknown";
2658         }
2659 }
2660
2661 static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2662                                 irq_hw_number_t hwirq)
2663 {
2664         irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2665                                 handle_simple_irq);
2666         set_irq_flags(virq, IRQF_VALID);
2667
2668         return 0;
2669 }
2670
2671 static struct irq_domain_ops db8500_irq_ops = {
2672         .map    = db8500_irq_map,
2673         .xlate  = irq_domain_xlate_twocell,
2674 };
2675
2676 static int db8500_irq_init(struct device_node *np)
2677 {
2678         int i;
2679
2680         db8500_irq_domain = irq_domain_add_simple(
2681                 np, NUM_PRCMU_WAKEUPS, 0,
2682                 &db8500_irq_ops, NULL);
2683
2684         if (!db8500_irq_domain) {
2685                 pr_err("Failed to create irqdomain\n");
2686                 return -ENOSYS;
2687         }
2688
2689         /* All wakeups will be used, so create mappings for all */
2690         for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2691                 irq_create_mapping(db8500_irq_domain, i);
2692
2693         return 0;
2694 }
2695
2696 static void dbx500_fw_version_init(struct platform_device *pdev,
2697                             u32 version_offset)
2698 {
2699         struct resource *res;
2700         void __iomem *tcpm_base;
2701         u32 version;
2702
2703         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2704                                            "prcmu-tcpm");
2705         if (!res) {
2706                 dev_err(&pdev->dev,
2707                         "Error: no prcmu tcpm memory region provided\n");
2708                 return;
2709         }
2710         tcpm_base = ioremap(res->start, resource_size(res));
2711         if (!tcpm_base) {
2712                 dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n");
2713                 return;
2714         }
2715
2716         version = readl(tcpm_base + version_offset);
2717         fw_info.version.project = (version & 0xFF);
2718         fw_info.version.api_version = (version >> 8) & 0xFF;
2719         fw_info.version.func_version = (version >> 16) & 0xFF;
2720         fw_info.version.errata = (version >> 24) & 0xFF;
2721         strncpy(fw_info.version.project_name,
2722                 fw_project_name(fw_info.version.project),
2723                 PRCMU_FW_PROJECT_NAME_LEN);
2724         fw_info.valid = true;
2725         pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2726                 fw_info.version.project_name,
2727                 fw_info.version.project,
2728                 fw_info.version.api_version,
2729                 fw_info.version.func_version,
2730                 fw_info.version.errata);
2731         iounmap(tcpm_base);
2732 }
2733
2734 void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
2735 {
2736         /*
2737          * This is a temporary remap to bring up the clocks. It is
2738          * subsequently replaces with a real remap. After the merge of
2739          * the mailbox subsystem all of this early code goes away, and the
2740          * clock driver can probe independently. An early initcall will
2741          * still be needed, but it can be diverted into drivers/clk/ux500.
2742          */
2743         prcmu_base = ioremap(phy_base, size);
2744         if (!prcmu_base)
2745                 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2746
2747         spin_lock_init(&mb0_transfer.lock);
2748         spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2749         mutex_init(&mb0_transfer.ac_wake_lock);
2750         init_completion(&mb0_transfer.ac_wake_work);
2751         mutex_init(&mb1_transfer.lock);
2752         init_completion(&mb1_transfer.work);
2753         mb1_transfer.ape_opp = APE_NO_CHANGE;
2754         mutex_init(&mb2_transfer.lock);
2755         init_completion(&mb2_transfer.work);
2756         spin_lock_init(&mb2_transfer.auto_pm_lock);
2757         spin_lock_init(&mb3_transfer.lock);
2758         mutex_init(&mb3_transfer.sysclk_lock);
2759         init_completion(&mb3_transfer.sysclk_work);
2760         mutex_init(&mb4_transfer.lock);
2761         init_completion(&mb4_transfer.work);
2762         mutex_init(&mb5_transfer.lock);
2763         init_completion(&mb5_transfer.work);
2764
2765         INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2766 }
2767
2768 static void __init init_prcm_registers(void)
2769 {
2770         u32 val;
2771
2772         val = readl(PRCM_A9PL_FORCE_CLKEN);
2773         val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2774                 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2775         writel(val, (PRCM_A9PL_FORCE_CLKEN));
2776 }
2777
2778 /*
2779  * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2780  */
2781 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2782         REGULATOR_SUPPLY("v-ape", NULL),
2783         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2784         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2785         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2786         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2787         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2788         /* "v-mmc" changed to "vcore" in the mainline kernel */
2789         REGULATOR_SUPPLY("vcore", "sdi0"),
2790         REGULATOR_SUPPLY("vcore", "sdi1"),
2791         REGULATOR_SUPPLY("vcore", "sdi2"),
2792         REGULATOR_SUPPLY("vcore", "sdi3"),
2793         REGULATOR_SUPPLY("vcore", "sdi4"),
2794         REGULATOR_SUPPLY("v-dma", "dma40.0"),
2795         REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2796         /* "v-uart" changed to "vcore" in the mainline kernel */
2797         REGULATOR_SUPPLY("vcore", "uart0"),
2798         REGULATOR_SUPPLY("vcore", "uart1"),
2799         REGULATOR_SUPPLY("vcore", "uart2"),
2800         REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2801         REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2802         REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2803 };
2804
2805 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2806         REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2807         /* AV8100 regulator */
2808         REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2809 };
2810
2811 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2812         REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2813         REGULATOR_SUPPLY("vsupply", "mcde"),
2814 };
2815
2816 /* SVA MMDSP regulator switch */
2817 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2818         REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2819 };
2820
2821 /* SVA pipe regulator switch */
2822 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2823         REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2824 };
2825
2826 /* SIA MMDSP regulator switch */
2827 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2828         REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2829 };
2830
2831 /* SIA pipe regulator switch */
2832 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2833         REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2834 };
2835
2836 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2837         REGULATOR_SUPPLY("v-mali", NULL),
2838 };
2839
2840 /* ESRAM1 and 2 regulator switch */
2841 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2842         REGULATOR_SUPPLY("esram12", "cm_control"),
2843 };
2844
2845 /* ESRAM3 and 4 regulator switch */
2846 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2847         REGULATOR_SUPPLY("v-esram34", "mcde"),
2848         REGULATOR_SUPPLY("esram34", "cm_control"),
2849         REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2850 };
2851
2852 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2853         [DB8500_REGULATOR_VAPE] = {
2854                 .constraints = {
2855                         .name = "db8500-vape",
2856                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2857                         .always_on = true,
2858                 },
2859                 .consumer_supplies = db8500_vape_consumers,
2860                 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2861         },
2862         [DB8500_REGULATOR_VARM] = {
2863                 .constraints = {
2864                         .name = "db8500-varm",
2865                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2866                 },
2867         },
2868         [DB8500_REGULATOR_VMODEM] = {
2869                 .constraints = {
2870                         .name = "db8500-vmodem",
2871                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2872                 },
2873         },
2874         [DB8500_REGULATOR_VPLL] = {
2875                 .constraints = {
2876                         .name = "db8500-vpll",
2877                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2878                 },
2879         },
2880         [DB8500_REGULATOR_VSMPS1] = {
2881                 .constraints = {
2882                         .name = "db8500-vsmps1",
2883                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2884                 },
2885         },
2886         [DB8500_REGULATOR_VSMPS2] = {
2887                 .constraints = {
2888                         .name = "db8500-vsmps2",
2889                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2890                 },
2891                 .consumer_supplies = db8500_vsmps2_consumers,
2892                 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2893         },
2894         [DB8500_REGULATOR_VSMPS3] = {
2895                 .constraints = {
2896                         .name = "db8500-vsmps3",
2897                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2898                 },
2899         },
2900         [DB8500_REGULATOR_VRF1] = {
2901                 .constraints = {
2902                         .name = "db8500-vrf1",
2903                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2904                 },
2905         },
2906         [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2907                 /* dependency to u8500-vape is handled outside regulator framework */
2908                 .constraints = {
2909                         .name = "db8500-sva-mmdsp",
2910                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2911                 },
2912                 .consumer_supplies = db8500_svammdsp_consumers,
2913                 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2914         },
2915         [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2916                 .constraints = {
2917                         /* "ret" means "retention" */
2918                         .name = "db8500-sva-mmdsp-ret",
2919                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2920                 },
2921         },
2922         [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2923                 /* dependency to u8500-vape is handled outside regulator framework */
2924                 .constraints = {
2925                         .name = "db8500-sva-pipe",
2926                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2927                 },
2928                 .consumer_supplies = db8500_svapipe_consumers,
2929                 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2930         },
2931         [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2932                 /* dependency to u8500-vape is handled outside regulator framework */
2933                 .constraints = {
2934                         .name = "db8500-sia-mmdsp",
2935                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2936                 },
2937                 .consumer_supplies = db8500_siammdsp_consumers,
2938                 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2939         },
2940         [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2941                 .constraints = {
2942                         .name = "db8500-sia-mmdsp-ret",
2943                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2944                 },
2945         },
2946         [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2947                 /* dependency to u8500-vape is handled outside regulator framework */
2948                 .constraints = {
2949                         .name = "db8500-sia-pipe",
2950                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2951                 },
2952                 .consumer_supplies = db8500_siapipe_consumers,
2953                 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2954         },
2955         [DB8500_REGULATOR_SWITCH_SGA] = {
2956                 .supply_regulator = "db8500-vape",
2957                 .constraints = {
2958                         .name = "db8500-sga",
2959                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2960                 },
2961                 .consumer_supplies = db8500_sga_consumers,
2962                 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2963
2964         },
2965         [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2966                 .supply_regulator = "db8500-vape",
2967                 .constraints = {
2968                         .name = "db8500-b2r2-mcde",
2969                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2970                 },
2971                 .consumer_supplies = db8500_b2r2_mcde_consumers,
2972                 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2973         },
2974         [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2975                 /*
2976                  * esram12 is set in retention and supplied by Vsafe when Vape is off,
2977                  * no need to hold Vape
2978                  */
2979                 .constraints = {
2980                         .name = "db8500-esram12",
2981                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2982                 },
2983                 .consumer_supplies = db8500_esram12_consumers,
2984                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2985         },
2986         [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2987                 .constraints = {
2988                         .name = "db8500-esram12-ret",
2989                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2990                 },
2991         },
2992         [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2993                 /*
2994                  * esram34 is set in retention and supplied by Vsafe when Vape is off,
2995                  * no need to hold Vape
2996                  */
2997                 .constraints = {
2998                         .name = "db8500-esram34",
2999                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3000                 },
3001                 .consumer_supplies = db8500_esram34_consumers,
3002                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
3003         },
3004         [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3005                 .constraints = {
3006                         .name = "db8500-esram34-ret",
3007                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3008                 },
3009         },
3010 };
3011
3012 static struct ux500_wdt_data db8500_wdt_pdata = {
3013         .timeout = 600, /* 10 minutes */
3014         .has_28_bits_resolution = true,
3015 };
3016 /*
3017  * Thermal Sensor
3018  */
3019
3020 static struct resource db8500_thsens_resources[] = {
3021         {
3022                 .name = "IRQ_HOTMON_LOW",
3023                 .start  = IRQ_PRCMU_HOTMON_LOW,
3024                 .end    = IRQ_PRCMU_HOTMON_LOW,
3025                 .flags  = IORESOURCE_IRQ,
3026         },
3027         {
3028                 .name = "IRQ_HOTMON_HIGH",
3029                 .start  = IRQ_PRCMU_HOTMON_HIGH,
3030                 .end    = IRQ_PRCMU_HOTMON_HIGH,
3031                 .flags  = IORESOURCE_IRQ,
3032         },
3033 };
3034
3035 static struct db8500_thsens_platform_data db8500_thsens_data = {
3036         .trip_points[0] = {
3037                 .temp = 70000,
3038                 .type = THERMAL_TRIP_ACTIVE,
3039                 .cdev_name = {
3040                         [0] = "thermal-cpufreq-0",
3041                 },
3042         },
3043         .trip_points[1] = {
3044                 .temp = 75000,
3045                 .type = THERMAL_TRIP_ACTIVE,
3046                 .cdev_name = {
3047                         [0] = "thermal-cpufreq-0",
3048                 },
3049         },
3050         .trip_points[2] = {
3051                 .temp = 80000,
3052                 .type = THERMAL_TRIP_ACTIVE,
3053                 .cdev_name = {
3054                         [0] = "thermal-cpufreq-0",
3055                 },
3056         },
3057         .trip_points[3] = {
3058                 .temp = 85000,
3059                 .type = THERMAL_TRIP_CRITICAL,
3060         },
3061         .num_trips = 4,
3062 };
3063
3064 static const struct mfd_cell common_prcmu_devs[] = {
3065         {
3066                 .name = "ux500_wdt",
3067                 .platform_data = &db8500_wdt_pdata,
3068                 .pdata_size = sizeof(db8500_wdt_pdata),
3069                 .id = -1,
3070         },
3071 };
3072
3073 static const struct mfd_cell db8500_prcmu_devs[] = {
3074         {
3075                 .name = "db8500-prcmu-regulators",
3076                 .of_compatible = "stericsson,db8500-prcmu-regulator",
3077                 .platform_data = &db8500_regulators,
3078                 .pdata_size = sizeof(db8500_regulators),
3079         },
3080         {
3081                 .name = "cpufreq-ux500",
3082                 .of_compatible = "stericsson,cpufreq-ux500",
3083                 .platform_data = &db8500_cpufreq_table,
3084                 .pdata_size = sizeof(db8500_cpufreq_table),
3085         },
3086         {
3087                 .name = "cpuidle-dbx500",
3088                 .of_compatible = "stericsson,cpuidle-dbx500",
3089         },
3090         {
3091                 .name = "db8500-thermal",
3092                 .num_resources = ARRAY_SIZE(db8500_thsens_resources),
3093                 .resources = db8500_thsens_resources,
3094                 .platform_data = &db8500_thsens_data,
3095                 .pdata_size = sizeof(db8500_thsens_data),
3096         },
3097 };
3098
3099 static void db8500_prcmu_update_cpufreq(void)
3100 {
3101         if (prcmu_has_arm_maxopp()) {
3102                 db8500_cpufreq_table[3].frequency = 1000000;
3103                 db8500_cpufreq_table[3].driver_data = ARM_MAX_OPP;
3104         }
3105 }
3106
3107 static int db8500_prcmu_register_ab8500(struct device *parent,
3108                                         struct ab8500_platform_data *pdata)
3109 {
3110         struct device_node *np;
3111         struct resource ab8500_resource;
3112         const struct mfd_cell ab8500_cell = {
3113                 .name = "ab8500-core",
3114                 .of_compatible = "stericsson,ab8500",
3115                 .id = AB8500_VERSION_AB8500,
3116                 .platform_data = pdata,
3117                 .pdata_size = sizeof(struct ab8500_platform_data),
3118                 .resources = &ab8500_resource,
3119                 .num_resources = 1,
3120         };
3121
3122         if (!parent->of_node)
3123                 return -ENODEV;
3124
3125         /* Look up the device node, sneak the IRQ out of it */
3126         for_each_child_of_node(parent->of_node, np) {
3127                 if (of_device_is_compatible(np, ab8500_cell.of_compatible))
3128                         break;
3129         }
3130         if (!np) {
3131                 dev_info(parent, "could not find AB8500 node in the device tree\n");
3132                 return -ENODEV;
3133         }
3134         of_irq_to_resource_table(np, &ab8500_resource, 1);
3135
3136         return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
3137 }
3138
3139 /**
3140  * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3141  *
3142  */
3143 static int db8500_prcmu_probe(struct platform_device *pdev)
3144 {
3145         struct device_node *np = pdev->dev.of_node;
3146         struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev);
3147         int irq = 0, err = 0;
3148         struct resource *res;
3149
3150         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3151         if (!res) {
3152                 dev_err(&pdev->dev, "no prcmu memory region provided\n");
3153                 return -EINVAL;
3154         }
3155         prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3156         if (!prcmu_base) {
3157                 dev_err(&pdev->dev,
3158                         "failed to ioremap prcmu register memory\n");
3159                 return -ENOMEM;
3160         }
3161         init_prcm_registers();
3162         dbx500_fw_version_init(pdev, pdata->version_offset);
3163         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3164         if (!res) {
3165                 dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3166                 return -EINVAL;
3167         }
3168         tcdm_base = devm_ioremap(&pdev->dev, res->start,
3169                         resource_size(res));
3170         if (!tcdm_base) {
3171                 dev_err(&pdev->dev,
3172                         "failed to ioremap prcmu-tcdm register memory\n");
3173                 return -ENOMEM;
3174         }
3175
3176         /* Clean up the mailbox interrupts after pre-kernel code. */
3177         writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3178
3179         irq = platform_get_irq(pdev, 0);
3180         if (irq <= 0) {
3181                 dev_err(&pdev->dev, "no prcmu irq provided\n");
3182                 return irq;
3183         }
3184
3185         err = request_threaded_irq(irq, prcmu_irq_handler,
3186                 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3187         if (err < 0) {
3188                 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3189                 return err;
3190         }
3191
3192         db8500_irq_init(np);
3193
3194         prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3195
3196         db8500_prcmu_update_cpufreq();
3197
3198         err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3199                               ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
3200         if (err) {
3201                 pr_err("prcmu: Failed to add subdevices\n");
3202                 return err;
3203         }
3204
3205         /* TODO: Remove restriction when clk definitions are available. */
3206         if (!of_machine_is_compatible("st-ericsson,u8540")) {
3207                 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3208                                       ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3209                                       db8500_irq_domain);
3210                 if (err) {
3211                         mfd_remove_devices(&pdev->dev);
3212                         pr_err("prcmu: Failed to add subdevices\n");
3213                         return err;
3214                 }
3215         }
3216
3217         err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata);
3218         if (err) {
3219                 mfd_remove_devices(&pdev->dev);
3220                 pr_err("prcmu: Failed to add ab8500 subdevice\n");
3221                 return err;
3222         }
3223
3224         pr_info("DB8500 PRCMU initialized\n");
3225         return err;
3226 }
3227 static const struct of_device_id db8500_prcmu_match[] = {
3228         { .compatible = "stericsson,db8500-prcmu"},
3229         { },
3230 };
3231
3232 static struct platform_driver db8500_prcmu_driver = {
3233         .driver = {
3234                 .name = "db8500-prcmu",
3235                 .of_match_table = db8500_prcmu_match,
3236         },
3237         .probe = db8500_prcmu_probe,
3238 };
3239
3240 static int __init db8500_prcmu_init(void)
3241 {
3242         return platform_driver_register(&db8500_prcmu_driver);
3243 }
3244
3245 core_initcall(db8500_prcmu_init);
3246
3247 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3248 MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3249 MODULE_LICENSE("GPL v2");