2 * intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC
4 * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * Author: Yang, Bin <bin.yang@intel.com>
16 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
19 #include <linux/mfd/core.h>
20 #include <linux/interrupt.h>
21 #include <linux/regmap.h>
22 #include <linux/mfd/intel_soc_pmic.h>
23 #include "intel_soc_pmic_core.h"
25 #define CRYSTAL_COVE_MAX_REGISTER 0xC6
27 #define CRYSTAL_COVE_REG_IRQLVL1 0x02
28 #define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
30 #define CRYSTAL_COVE_IRQ_PWRSRC 0
31 #define CRYSTAL_COVE_IRQ_THRM 1
32 #define CRYSTAL_COVE_IRQ_BCU 2
33 #define CRYSTAL_COVE_IRQ_ADC 3
34 #define CRYSTAL_COVE_IRQ_CHGR 4
35 #define CRYSTAL_COVE_IRQ_GPIO 5
36 #define CRYSTAL_COVE_IRQ_VHDMIOCP 6
38 static struct resource gpio_resources[] = {
41 .start = CRYSTAL_COVE_IRQ_GPIO,
42 .end = CRYSTAL_COVE_IRQ_GPIO,
43 .flags = IORESOURCE_IRQ,
47 static struct resource pwrsrc_resources[] = {
50 .start = CRYSTAL_COVE_IRQ_PWRSRC,
51 .end = CRYSTAL_COVE_IRQ_PWRSRC,
52 .flags = IORESOURCE_IRQ,
56 static struct resource adc_resources[] = {
59 .start = CRYSTAL_COVE_IRQ_ADC,
60 .end = CRYSTAL_COVE_IRQ_ADC,
61 .flags = IORESOURCE_IRQ,
65 static struct resource thermal_resources[] = {
68 .start = CRYSTAL_COVE_IRQ_THRM,
69 .end = CRYSTAL_COVE_IRQ_THRM,
70 .flags = IORESOURCE_IRQ,
74 static struct resource bcu_resources[] = {
77 .start = CRYSTAL_COVE_IRQ_BCU,
78 .end = CRYSTAL_COVE_IRQ_BCU,
79 .flags = IORESOURCE_IRQ,
83 static struct mfd_cell crystal_cove_dev[] = {
85 .name = "crystal_cove_pwrsrc",
86 .num_resources = ARRAY_SIZE(pwrsrc_resources),
87 .resources = pwrsrc_resources,
90 .name = "crystal_cove_adc",
91 .num_resources = ARRAY_SIZE(adc_resources),
92 .resources = adc_resources,
95 .name = "crystal_cove_thermal",
96 .num_resources = ARRAY_SIZE(thermal_resources),
97 .resources = thermal_resources,
100 .name = "crystal_cove_bcu",
101 .num_resources = ARRAY_SIZE(bcu_resources),
102 .resources = bcu_resources,
105 .name = "crystal_cove_gpio",
106 .num_resources = ARRAY_SIZE(gpio_resources),
107 .resources = gpio_resources,
111 static struct regmap_config crystal_cove_regmap_config = {
115 .max_register = CRYSTAL_COVE_MAX_REGISTER,
116 .cache_type = REGCACHE_NONE,
119 static const struct regmap_irq crystal_cove_irqs[] = {
120 [CRYSTAL_COVE_IRQ_PWRSRC] = {
121 .mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC),
123 [CRYSTAL_COVE_IRQ_THRM] = {
124 .mask = BIT(CRYSTAL_COVE_IRQ_THRM),
126 [CRYSTAL_COVE_IRQ_BCU] = {
127 .mask = BIT(CRYSTAL_COVE_IRQ_BCU),
129 [CRYSTAL_COVE_IRQ_ADC] = {
130 .mask = BIT(CRYSTAL_COVE_IRQ_ADC),
132 [CRYSTAL_COVE_IRQ_CHGR] = {
133 .mask = BIT(CRYSTAL_COVE_IRQ_CHGR),
135 [CRYSTAL_COVE_IRQ_GPIO] = {
136 .mask = BIT(CRYSTAL_COVE_IRQ_GPIO),
138 [CRYSTAL_COVE_IRQ_VHDMIOCP] = {
139 .mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP),
143 static struct regmap_irq_chip crystal_cove_irq_chip = {
144 .name = "Crystal Cove",
145 .irqs = crystal_cove_irqs,
146 .num_irqs = ARRAY_SIZE(crystal_cove_irqs),
148 .status_base = CRYSTAL_COVE_REG_IRQLVL1,
149 .mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
152 struct intel_soc_pmic_config intel_soc_pmic_config_crc = {
153 .irq_flags = IRQF_TRIGGER_RISING,
154 .cell_dev = crystal_cove_dev,
155 .n_cell_devs = ARRAY_SIZE(crystal_cove_dev),
156 .regmap_config = &crystal_cove_regmap_config,
157 .irq_chip = &crystal_cove_irq_chip,