2 * Maxim MAX77620 MFD Driver
4 * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
7 * Laxman Dewangan <ldewangan@nvidia.com>
8 * Chaitanya Bandi <bandik@nvidia.com>
9 * Mallikarjun Kasoju <mkasoju@nvidia.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 /****************** Teminology used in driver ********************
17 * Here are some terminology used from datasheet for quick reference:
18 * Flexible Power Sequence (FPS):
19 * The Flexible Power Sequencer (FPS) allows each regulator to power up under
20 * hardware or software control. Additionally, each regulator can power on
21 * independently or among a group of other regulators with an adjustable
22 * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can
23 * be programmed to be part of a sequence allowing external regulators to be
24 * sequenced along with internal regulators. 32KHz clock can be programmed to
25 * be part of a sequence.
26 * There is 3 FPS confguration registers and all resources are configured to
27 * any of these FPS or no FPS.
30 #include <linux/i2c.h>
31 #include <linux/interrupt.h>
32 #include <linux/mfd/core.h>
33 #include <linux/mfd/max77620.h>
34 #include <linux/module.h>
36 #include <linux/of_device.h>
37 #include <linux/regmap.h>
38 #include <linux/slab.h>
40 static struct resource gpio_resources[] = {
41 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),
44 static struct resource power_resources[] = {
45 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),
48 static struct resource rtc_resources[] = {
49 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),
52 static struct resource thermal_resources[] = {
53 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),
54 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),
57 static const struct regmap_irq max77620_top_irqs[] = {
58 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),
59 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),
60 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),
61 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),
62 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),
63 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),
64 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),
65 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),
66 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),
67 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),
70 static const struct mfd_cell max77620_children[] = {
71 { .name = "max77620-pinctrl", },
72 { .name = "max77620-clock", },
73 { .name = "max77620-pmic", },
74 { .name = "max77620-watchdog", },
76 .name = "max77620-gpio",
77 .resources = gpio_resources,
78 .num_resources = ARRAY_SIZE(gpio_resources),
80 .name = "max77620-rtc",
81 .resources = rtc_resources,
82 .num_resources = ARRAY_SIZE(rtc_resources),
84 .name = "max77620-power",
85 .resources = power_resources,
86 .num_resources = ARRAY_SIZE(power_resources),
88 .name = "max77620-thermal",
89 .resources = thermal_resources,
90 .num_resources = ARRAY_SIZE(thermal_resources),
94 static const struct mfd_cell max20024_children[] = {
95 { .name = "max20024-pinctrl", },
96 { .name = "max77620-clock", },
97 { .name = "max20024-pmic", },
98 { .name = "max77620-watchdog", },
100 .name = "max77620-gpio",
101 .resources = gpio_resources,
102 .num_resources = ARRAY_SIZE(gpio_resources),
104 .name = "max77620-rtc",
105 .resources = rtc_resources,
106 .num_resources = ARRAY_SIZE(rtc_resources),
108 .name = "max20024-power",
109 .resources = power_resources,
110 .num_resources = ARRAY_SIZE(power_resources),
114 static struct regmap_irq_chip max77620_top_irq_chip = {
115 .name = "max77620-top",
116 .irqs = max77620_top_irqs,
117 .num_irqs = ARRAY_SIZE(max77620_top_irqs),
119 .status_base = MAX77620_REG_IRQTOP,
120 .mask_base = MAX77620_REG_IRQTOPM,
123 static const struct regmap_range max77620_readable_ranges[] = {
124 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
127 static const struct regmap_access_table max77620_readable_table = {
128 .yes_ranges = max77620_readable_ranges,
129 .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
132 static const struct regmap_range max20024_readable_ranges[] = {
133 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
134 regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
137 static const struct regmap_access_table max20024_readable_table = {
138 .yes_ranges = max20024_readable_ranges,
139 .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
142 static const struct regmap_range max77620_writable_ranges[] = {
143 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
146 static const struct regmap_access_table max77620_writable_table = {
147 .yes_ranges = max77620_writable_ranges,
148 .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
151 static const struct regmap_range max77620_cacheable_ranges[] = {
152 regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
153 regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
156 static const struct regmap_access_table max77620_volatile_table = {
157 .no_ranges = max77620_cacheable_ranges,
158 .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
161 static const struct regmap_config max77620_regmap_config = {
162 .name = "power-slave",
165 .max_register = MAX77620_REG_DVSSD4 + 1,
166 .cache_type = REGCACHE_RBTREE,
167 .rd_table = &max77620_readable_table,
168 .wr_table = &max77620_writable_table,
169 .volatile_table = &max77620_volatile_table,
172 static const struct regmap_config max20024_regmap_config = {
173 .name = "power-slave",
176 .max_register = MAX20024_REG_MAX_ADD + 1,
177 .cache_type = REGCACHE_RBTREE,
178 .rd_table = &max20024_readable_table,
179 .wr_table = &max77620_writable_table,
180 .volatile_table = &max77620_volatile_table,
183 /* max77620_get_fps_period_reg_value: Get FPS bit field value from
185 * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560
186 * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,
187 * 160, 320, 540, 1280 and 2560 microseconds.
188 * The FPS register has 3 bits field to set the FPS period as
189 * bits max77620 max20024
194 static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
200 switch (chip->chip_id) {
202 fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
205 fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
210 for (i = 0; i < 7; i++) {
211 if (fps_min_period >= tperiod)
219 /* max77620_config_fps: Configure FPS configuration registers
220 * based on platform specific information.
222 static int max77620_config_fps(struct max77620_chip *chip,
223 struct device_node *fps_np)
225 struct device *dev = chip->dev;
226 unsigned int mask = 0, config = 0;
233 switch (chip->chip_id) {
235 fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
238 fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
243 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
244 sprintf(fps_name, "fps%d", fps_id);
245 if (!strcmp(fps_np->name, fps_name))
249 if (fps_id == MAX77620_FPS_COUNT) {
250 dev_err(dev, "FPS node name %s is not valid\n", fps_np->name);
254 ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",
257 mask |= MAX77620_FPS_TIME_PERIOD_MASK;
258 chip->shutdown_fps_period[fps_id] = min(param_val,
260 tperiod = max77620_get_fps_period_reg_value(chip,
261 chip->shutdown_fps_period[fps_id]);
262 config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
265 ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",
268 chip->suspend_fps_period[fps_id] = min(param_val,
271 ret = of_property_read_u32(fps_np, "maxim,fps-event-source",
275 dev_err(dev, "FPS%d event-source invalid\n", fps_id);
278 mask |= MAX77620_FPS_EN_SRC_MASK;
279 config |= param_val << MAX77620_FPS_EN_SRC_SHIFT;
280 if (param_val == 2) {
281 mask |= MAX77620_FPS_ENFPS_SW_MASK;
282 config |= MAX77620_FPS_ENFPS_SW;
286 if (!chip->sleep_enable && !chip->enable_global_lpm) {
287 ret = of_property_read_u32(fps_np,
288 "maxim,device-state-on-disabled-event",
292 chip->sleep_enable = true;
293 else if (param_val == 1)
294 chip->enable_global_lpm = true;
298 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
301 dev_err(dev, "Failed to update FPS CFG: %d\n", ret);
308 static int max77620_initialise_fps(struct max77620_chip *chip)
310 struct device *dev = chip->dev;
311 struct device_node *fps_np, *fps_child;
316 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
317 chip->shutdown_fps_period[fps_id] = -1;
318 chip->suspend_fps_period[fps_id] = -1;
321 fps_np = of_get_child_by_name(dev->of_node, "fps");
325 for_each_child_of_node(fps_np, fps_child) {
326 ret = max77620_config_fps(chip, fps_child);
331 config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
332 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
333 MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
335 dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);
340 /* Enable wake on EN0 pin */
341 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
342 MAX77620_ONOFFCNFG2_WK_EN0,
343 MAX77620_ONOFFCNFG2_WK_EN0);
345 dev_err(dev, "Failed to update WK_EN0: %d\n", ret);
349 /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
350 if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
351 config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
352 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
355 dev_err(dev, "Failed to update SLPEN: %d\n", ret);
363 static int max77620_read_es_version(struct max77620_chip *chip)
370 for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {
371 ret = regmap_read(chip->rmap, i, &val);
373 dev_err(chip->dev, "Failed to read CID: %d\n", ret);
376 dev_dbg(chip->dev, "CID%d: 0x%02x\n",
377 i - MAX77620_REG_CID0, val);
378 cid_val[i - MAX77620_REG_CID0] = val;
381 /* CID4 is OTP Version and CID5 is ES version */
382 dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
383 cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
388 static int max77620_probe(struct i2c_client *client,
389 const struct i2c_device_id *id)
391 const struct regmap_config *rmap_config;
392 struct max77620_chip *chip;
393 const struct mfd_cell *mfd_cells;
397 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
401 i2c_set_clientdata(client, chip);
402 chip->dev = &client->dev;
404 chip->chip_irq = client->irq;
405 chip->chip_id = (enum max77620_chip_id)id->driver_data;
407 switch (chip->chip_id) {
409 mfd_cells = max77620_children;
410 n_mfd_cells = ARRAY_SIZE(max77620_children);
411 rmap_config = &max77620_regmap_config;
414 mfd_cells = max20024_children;
415 n_mfd_cells = ARRAY_SIZE(max20024_children);
416 rmap_config = &max20024_regmap_config;
419 dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
423 chip->rmap = devm_regmap_init_i2c(client, rmap_config);
424 if (IS_ERR(chip->rmap)) {
425 ret = PTR_ERR(chip->rmap);
426 dev_err(chip->dev, "Failed to intialise regmap: %d\n", ret);
430 ret = max77620_read_es_version(chip);
434 ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
435 IRQF_ONESHOT | IRQF_SHARED,
436 chip->irq_base, &max77620_top_irq_chip,
437 &chip->top_irq_data);
439 dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
443 ret = max77620_initialise_fps(chip);
447 ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
448 mfd_cells, n_mfd_cells, NULL, 0,
449 regmap_irq_get_domain(chip->top_irq_data));
451 dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
458 #ifdef CONFIG_PM_SLEEP
459 static int max77620_set_fps_period(struct max77620_chip *chip,
460 int fps_id, int time_period)
462 int period = max77620_get_fps_period_reg_value(chip, time_period);
465 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
466 MAX77620_FPS_TIME_PERIOD_MASK,
467 period << MAX77620_FPS_TIME_PERIOD_SHIFT);
469 dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
476 static int max77620_i2c_suspend(struct device *dev)
478 struct max77620_chip *chip = dev_get_drvdata(dev);
479 struct i2c_client *client = to_i2c_client(dev);
484 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
485 if (chip->suspend_fps_period[fps] < 0)
488 ret = max77620_set_fps_period(chip, fps,
489 chip->suspend_fps_period[fps]);
495 * For MAX20024: No need to configure SLPEN on suspend as
496 * it will be configured on Init.
498 if (chip->chip_id == MAX20024)
501 config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
502 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
503 MAX77620_ONOFFCNFG1_SLPEN,
506 dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);
511 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
512 MAX77620_ONOFFCNFG2_WK_EN0, 0);
514 dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);
519 disable_irq(client->irq);
524 static int max77620_i2c_resume(struct device *dev)
526 struct max77620_chip *chip = dev_get_drvdata(dev);
527 struct i2c_client *client = to_i2c_client(dev);
531 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
532 if (chip->shutdown_fps_period[fps] < 0)
535 ret = max77620_set_fps_period(chip, fps,
536 chip->shutdown_fps_period[fps]);
542 * For MAX20024: No need to configure WKEN0 on resume as
543 * it is configured on Init.
545 if (chip->chip_id == MAX20024)
549 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
550 MAX77620_ONOFFCNFG2_WK_EN0,
551 MAX77620_ONOFFCNFG2_WK_EN0);
553 dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);
558 enable_irq(client->irq);
564 static const struct i2c_device_id max77620_id[] = {
565 {"max77620", MAX77620},
566 {"max20024", MAX20024},
569 MODULE_DEVICE_TABLE(i2c, max77620_id);
571 static const struct dev_pm_ops max77620_pm_ops = {
572 SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
575 static struct i2c_driver max77620_driver = {
578 .pm = &max77620_pm_ops,
580 .probe = max77620_probe,
581 .id_table = max77620_id,
584 module_i2c_driver(max77620_driver);
586 MODULE_DESCRIPTION("MAX77620/MAX20024 Multi Function Device Core Driver");
587 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
588 MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
589 MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>");
590 MODULE_LICENSE("GPL v2");