drivers/mfd/mxc-hdmi-core.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  *
  18  */
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/clk.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/irq.h>
  29 #include <linux/interrupt.h>
  30
  31 #include <linux/platform_device.h>
  32 #include <linux/regulator/machine.h>
  33 #include <asm/mach-types.h>
  34
  35 #include <video/mxc_hdmi.h>
  36 #include <linux/ipu-v3.h>
  37 #include <video/mxc_edid.h>
  38 #include "../mxc/ipu3/ipu_prv.h"
  39 #include <linux/mfd/mxc-hdmi-core.h>
  40 #include <linux/of_device.h>
  41 #include <linux/mod_devicetable.h>
  42 #include <linux/mfd/mxc-hdmi-core.h>
  43
  44 struct mxc_hdmi_data {
  45         struct platform_device *pdev;
  46         unsigned long __iomem *reg_base;
  47         unsigned long reg_phys_base;
  48         struct device *dev;
  49 };
  50
  51 static void __iomem *hdmi_base;
  52 static struct clk *isfr_clk;
  53 static struct clk *iahb_clk;
  54 static spinlock_t irq_spinlock;
  55 static spinlock_t edid_spinlock;
  56 static unsigned int sample_rate;
  57 static unsigned long pixel_clk_rate;
  58 static struct clk *pixel_clk;
  59 static int hdmi_ratio;
  60 int mxc_hdmi_ipu_id;
  61 int mxc_hdmi_disp_id;
  62 static struct mxc_edid_cfg hdmi_core_edid_cfg;
  63 static int hdmi_core_init;
  64 static unsigned int hdmi_dma_running;
  65 static struct snd_pcm_substream *hdmi_audio_stream_playback;
  66 static unsigned int hdmi_cable_state;
  67 static unsigned int hdmi_blank_state;
  68 static spinlock_t hdmi_audio_lock, hdmi_blank_state_lock, hdmi_cable_state_lock;
  69
  70 unsigned int hdmi_set_cable_state(unsigned int state)
  71 {
  72         unsigned long flags;
  73         struct snd_pcm_substream *substream = hdmi_audio_stream_playback;
  74
  75         spin_lock_irqsave(&hdmi_cable_state_lock, flags);
  76         hdmi_cable_state = state;
  77         spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
  78
  79         if (check_hdmi_state() && substream)
  80                 substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_START);
  81         return 0;
  82 }
  83 EXPORT_SYMBOL(hdmi_set_cable_state);
  84
  85 unsigned int hdmi_set_blank_state(unsigned int state)
  86 {
  87         unsigned long flags;
  88         struct snd_pcm_substream *substream = hdmi_audio_stream_playback;
  89
  90         spin_lock_irqsave(&hdmi_blank_state_lock, flags);
  91         hdmi_blank_state = state;
  92         spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
  93
  94         if (check_hdmi_state() && substream)
  95                 substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_START);
  96
  97         return 0;
  98 }
  99 EXPORT_SYMBOL(hdmi_set_blank_state);
 100
 101 static void hdmi_audio_abort_stream(struct snd_pcm_substream *substream)
 102 {
 103         unsigned long flags;
 104
 105         snd_pcm_stream_lock_irqsave(substream, flags);
 106
 107         if (snd_pcm_running(substream))
 108                 substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_STOP);
 109
 110         snd_pcm_stream_unlock_irqrestore(substream, flags);
 111 }
 112
 113 int mxc_hdmi_abort_stream(void)
 114 {
 115         unsigned long flags;
 116         spin_lock_irqsave(&hdmi_audio_lock, flags);
 117         if (hdmi_audio_stream_playback)
 118                 hdmi_audio_abort_stream(hdmi_audio_stream_playback);
 119         spin_unlock_irqrestore(&hdmi_audio_lock, flags);
 120
 121         return 0;
 122 }
 123 EXPORT_SYMBOL(mxc_hdmi_abort_stream);
 124
 125 int check_hdmi_state(void)
 126 {
 127         unsigned long flags1, flags2;
 128         unsigned int ret;
 129
 130         spin_lock_irqsave(&hdmi_cable_state_lock, flags1);
 131         spin_lock_irqsave(&hdmi_blank_state_lock, flags2);
 132
 133         ret = hdmi_cable_state && hdmi_blank_state;
 134
 135         spin_unlock_irqrestore(&hdmi_blank_state_lock, flags2);
 136         spin_unlock_irqrestore(&hdmi_cable_state_lock, flags1);
 137
 138         return ret;
 139 }
 140 EXPORT_SYMBOL(check_hdmi_state);
 141
 142 int mxc_hdmi_register_audio(struct snd_pcm_substream *substream)
 143 {
 144         unsigned long flags, flags1;
 145         int ret = 0;
 146
 147         snd_pcm_stream_lock_irqsave(substream, flags);
 148
 149         if (substream && check_hdmi_state()) {
 150                 spin_lock_irqsave(&hdmi_audio_lock, flags1);
 151                 if (hdmi_audio_stream_playback) {
 152                         pr_err("%s unconsist hdmi auido stream!\n", __func__);
 153                         ret = -EINVAL;
 154                 }
 155                 hdmi_audio_stream_playback = substream;
 156                 spin_unlock_irqrestore(&hdmi_audio_lock, flags1);
 157         } else
 158                 ret = -EINVAL;
 159
 160         snd_pcm_stream_unlock_irqrestore(substream, flags);
 161
 162         return ret;
 163 }
 164 EXPORT_SYMBOL(mxc_hdmi_register_audio);
 165
 166 void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream)
 167 {
 168         unsigned long flags;
 169
 170         spin_lock_irqsave(&hdmi_audio_lock, flags);
 171         hdmi_audio_stream_playback = NULL;
 172         spin_unlock_irqrestore(&hdmi_audio_lock, flags);
 173 }
 174 EXPORT_SYMBOL(mxc_hdmi_unregister_audio);
 175
 176 u8 hdmi_readb(unsigned int reg)
 177 {
 178         u8 value;
 179
 180         value = __raw_readb(hdmi_base + reg);
 181
 182         return value;
 183 }
 184 EXPORT_SYMBOL(hdmi_readb);
 185
 186 #ifdef DEBUG
 187 static bool overflow_lo;
 188 static bool overflow_hi;
 189
 190 bool hdmi_check_overflow(void)
 191 {
 192         u8 val, lo, hi;
 193
 194         val = hdmi_readb(HDMI_IH_FC_STAT2);
 195         lo = (val & HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW) != 0;
 196         hi = (val & HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW) != 0;
 197
 198         if ((lo != overflow_lo) || (hi != overflow_hi)) {
 199                 pr_debug("%s LowPriority=%d HighPriority=%d  <=======================\n",
 200                         __func__, lo, hi);
 201                 overflow_lo = lo;
 202                 overflow_hi = hi;
 203                 return true;
 204         }
 205         return false;
 206 }
 207 #else
 208 bool hdmi_check_overflow(void)
 209 {
 210         return false;
 211 }
 212 #endif
 213 EXPORT_SYMBOL(hdmi_check_overflow);
 214
 215 void hdmi_writeb(u8 value, unsigned int reg)
 216 {
 217         hdmi_check_overflow();
 218         __raw_writeb(value, hdmi_base + reg);
 219         hdmi_check_overflow();
 220 }
 221 EXPORT_SYMBOL(hdmi_writeb);
 222
 223 void hdmi_mask_writeb(u8 data, unsigned int reg, u8 shift, u8 mask)
 224 {
 225         u8 value = hdmi_readb(reg) & ~mask;
 226         value |= (data << shift) & mask;
 227         hdmi_writeb(value, reg);
 228 }
 229 EXPORT_SYMBOL(hdmi_mask_writeb);
 230
 231 unsigned int hdmi_read4(unsigned int reg)
 232 {
 233         /* read a four byte address from registers */
 234         return (hdmi_readb(reg + 3) << 24) |
 235                 (hdmi_readb(reg + 2) << 16) |
 236                 (hdmi_readb(reg + 1) << 8) |
 237                 hdmi_readb(reg);
 238 }
 239 EXPORT_SYMBOL(hdmi_read4);
 240
 241 void hdmi_write4(unsigned int value, unsigned int reg)
 242 {
 243         /* write a four byte address to hdmi regs */
 244         hdmi_writeb(value & 0xff, reg);
 245         hdmi_writeb((value >> 8) & 0xff, reg + 1);
 246         hdmi_writeb((value >> 16) & 0xff, reg + 2);
 247         hdmi_writeb((value >> 24) & 0xff, reg + 3);
 248 }
 249 EXPORT_SYMBOL(hdmi_write4);
 250
 251 static void initialize_hdmi_ih_mutes(void)
 252 {
 253         u8 ih_mute;
 254
 255         /*
 256          * Boot up defaults are:
 257          * HDMI_IH_MUTE   = 0x03 (disabled)
 258          * HDMI_IH_MUTE_* = 0x00 (enabled)
 259          */
 260
 261         /* Disable top level interrupt bits in HDMI block */
 262         ih_mute = hdmi_readb(HDMI_IH_MUTE) |
 263                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
 264                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
 265
 266         hdmi_writeb(ih_mute, HDMI_IH_MUTE);
 267
 268         /* by default mask all interrupts */
 269         hdmi_writeb(0xff, HDMI_VP_MASK);
 270         hdmi_writeb(0xff, HDMI_FC_MASK0);
 271         hdmi_writeb(0xff, HDMI_FC_MASK1);
 272         hdmi_writeb(0xff, HDMI_FC_MASK2);
 273         hdmi_writeb(0xff, HDMI_PHY_MASK0);
 274         hdmi_writeb(0xff, HDMI_PHY_I2CM_INT_ADDR);
 275         hdmi_writeb(0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
 276         hdmi_writeb(0xff, HDMI_AUD_INT);
 277         hdmi_writeb(0xff, HDMI_AUD_SPDIFINT);
 278         hdmi_writeb(0xff, HDMI_AUD_HBR_MASK);
 279         hdmi_writeb(0xff, HDMI_GP_MASK);
 280         hdmi_writeb(0xff, HDMI_A_APIINTMSK);
 281         hdmi_writeb(0xff, HDMI_CEC_MASK);
 282         hdmi_writeb(0xff, HDMI_I2CM_INT);
 283         hdmi_writeb(0xff, HDMI_I2CM_CTLINT);
 284
 285         /* Disable interrupts in the IH_MUTE_* registers */
 286         hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT0);
 287         hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT1);
 288         hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT2);
 289         hdmi_writeb(0xff, HDMI_IH_MUTE_AS_STAT0);
 290         hdmi_writeb(0xff, HDMI_IH_MUTE_PHY_STAT0);
 291         hdmi_writeb(0xff, HDMI_IH_MUTE_I2CM_STAT0);
 292         hdmi_writeb(0xff, HDMI_IH_MUTE_CEC_STAT0);
 293         hdmi_writeb(0xff, HDMI_IH_MUTE_VP_STAT0);
 294         hdmi_writeb(0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
 295         hdmi_writeb(0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
 296
 297         /* Enable top level interrupt bits in HDMI block */
 298         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
 299                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
 300         hdmi_writeb(ih_mute, HDMI_IH_MUTE);
 301 }
 302
 303 static void hdmi_set_clock_regenerator_n(unsigned int value)
 304 {
 305         u8 val;
 306
 307         if (!hdmi_dma_running) {
 308                 hdmi_writeb(value & 0xff, HDMI_AUD_N1);
 309                 hdmi_writeb(0, HDMI_AUD_N2);
 310                 hdmi_writeb(0, HDMI_AUD_N3);
 311         }
 312
 313         hdmi_writeb(value & 0xff, HDMI_AUD_N1);
 314         hdmi_writeb((value >> 8) & 0xff, HDMI_AUD_N2);
 315         hdmi_writeb((value >> 16) & 0x0f, HDMI_AUD_N3);
 316
 317         /* nshift factor = 0 */
 318         val = hdmi_readb(HDMI_AUD_CTS3);
 319         val &= ~HDMI_AUD_CTS3_N_SHIFT_MASK;
 320         hdmi_writeb(val, HDMI_AUD_CTS3);
 321 }
 322
 323 static void hdmi_set_clock_regenerator_cts(unsigned int cts)
 324 {
 325         u8 val;
 326
 327         if (!hdmi_dma_running) {
 328                 hdmi_writeb(cts & 0xff, HDMI_AUD_CTS1);
 329                 hdmi_writeb(0, HDMI_AUD_CTS2);
 330                 hdmi_writeb(0, HDMI_AUD_CTS3);
 331         }
 332
 333         /* Must be set/cleared first */
 334         val = hdmi_readb(HDMI_AUD_CTS3);
 335         val &= ~HDMI_AUD_CTS3_CTS_MANUAL;
 336         hdmi_writeb(val, HDMI_AUD_CTS3);
 337
 338         hdmi_writeb(cts & 0xff, HDMI_AUD_CTS1);
 339         hdmi_writeb((cts >> 8) & 0xff, HDMI_AUD_CTS2);
 340         hdmi_writeb(((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 341                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 342 }
 343
 344 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
 345                                    unsigned int ratio)
 346 {
 347         unsigned int n = (128 * freq) / 1000;
 348
 349         switch (freq) {
 350         case 32000:
 351                 if (pixel_clk == 25174000)
 352                         n = (ratio == 150) ? 9152 : 4576;
 353                 else if (pixel_clk == 27020000)
 354                         n = (ratio == 150) ? 8192 : 4096;
 355                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
 356                         n = 11648;
 357                 else if (pixel_clk == 297000000)
 358                         n = (ratio == 150) ? 6144 : 3072;
 359                 else
 360                         n = 4096;
 361                 break;
 362
 363         case 44100:
 364                 if (pixel_clk == 25174000)
 365                         n = 7007;
 366                 else if (pixel_clk == 74170000)
 367                         n = 17836;
 368                 else if (pixel_clk == 148350000)
 369                         n = (ratio == 150) ? 17836 : 8918;
 370                 else if (pixel_clk == 297000000)
 371                         n = (ratio == 150) ? 9408 : 4704;
 372                 else
 373                         n = 6272;
 374                 break;
 375
 376         case 48000:
 377                 if (pixel_clk == 25174000)
 378                         n = (ratio == 150) ? 9152 : 6864;
 379                 else if (pixel_clk == 27020000)
 380                         n = (ratio == 150) ? 8192 : 6144;
 381                 else if (pixel_clk == 74170000)
 382                         n = 11648;
 383                 else if (pixel_clk == 148350000)
 384                         n = (ratio == 150) ? 11648 : 5824;
 385                 else if (pixel_clk == 297000000)
 386                         n = (ratio == 150) ? 10240 : 5120;
 387                 else
 388                         n = 6144;
 389                 break;
 390
 391         case 88200:
 392                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
 393                 break;
 394
 395         case 96000:
 396                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
 397                 break;
 398
 399         case 176400:
 400                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
 401                 break;
 402
 403         case 192000:
 404                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
 405                 break;
 406
 407         default:
 408                 break;
 409         }
 410
 411         return n;
 412 }
 413
 414 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
 415                                      unsigned int ratio)
 416 {
 417         unsigned int cts = 0;
 418         switch (freq) {
 419         case 32000:
 420                 if (pixel_clk == 297000000) {
 421                         cts = 222750;
 422                         break;
 423                 } else if (pixel_clk == 25174000) {
 424                         cts = 28125;
 425                         break;
 426                 }
 427         case 48000:
 428         case 96000:
 429         case 192000:
 430                 switch (pixel_clk) {
 431                 case 25200000:
 432                 case 27000000:
 433                 case 54000000:
 434                 case 74250000:
 435                 case 148500000:
 436                         cts = pixel_clk / 1000;
 437                         break;
 438                 case 297000000:
 439                         cts = 247500;
 440                         break;
 441                 case 25174000:
 442                         cts = 28125l;
 443                         break;
 444                 /*
 445                  * All other TMDS clocks are not supported by
 446                  * DWC_hdmi_tx. The TMDS clocks divided or
 447                  * multiplied by 1,001 coefficients are not
 448                  * supported.
 449                  */
 450                 default:
 451                         break;
 452                 }
 453                 break;
 454         case 44100:
 455         case 88200:
 456         case 176400:
 457                 switch (pixel_clk) {
 458                 case 25200000:
 459                         cts = 28000;
 460                         break;
 461                 case 25174000:
 462                         cts = 31250;
 463                         break;
 464                 case 27000000:
 465                         cts = 30000;
 466                         break;
 467                 case 54000000:
 468                         cts = 60000;
 469                         break;
 470                 case 74250000:
 471                         cts = 82500;
 472                         break;
 473                 case 148500000:
 474                         cts = 165000;
 475                         break;
 476                 case 297000000:
 477                         cts = 247500;
 478                         break;
 479                 default:
 480                         break;
 481                 }
 482                 break;
 483         default:
 484                 break;
 485         }
 486         if (ratio == 100)
 487                 return cts;
 488         else
 489                 return (cts * ratio) / 100;
 490 }
 491
 492 static void hdmi_set_clk_regenerator(void)
 493 {
 494         unsigned int clk_n, clk_cts;
 495
 496         clk_n = hdmi_compute_n(sample_rate, pixel_clk_rate, hdmi_ratio);
 497         clk_cts = hdmi_compute_cts(sample_rate, pixel_clk_rate, hdmi_ratio);
 498
 499         if (clk_cts == 0) {
 500                 pr_debug("%s: pixel clock not supported: %d\n",
 501                         __func__, (int)pixel_clk_rate);
 502                 return;
 503         }
 504
 505         pr_debug("%s: samplerate=%d  ratio=%d  pixelclk=%d  N=%d  cts=%d\n",
 506                 __func__, sample_rate, hdmi_ratio, (int)pixel_clk_rate,
 507                 clk_n, clk_cts);
 508
 509         hdmi_set_clock_regenerator_cts(clk_cts);
 510         hdmi_set_clock_regenerator_n(clk_n);
 511 }
 512
 513 static int hdmi_core_get_of_property(struct platform_device *pdev)
 514 {
 515         struct device_node *np = pdev->dev.of_node;
 516         int err;
 517         int ipu_id, disp_id;
 518
 519         err = of_property_read_u32(np, "ipu_id", &ipu_id);
 520         if (err) {
 521                 dev_dbg(&pdev->dev, "get of property ipu_id fail\n");
 522                 return err;
 523         }
 524         err = of_property_read_u32(np, "disp_id", &disp_id);
 525         if (err) {
 526                 dev_dbg(&pdev->dev, "get of property disp_id fail\n");
 527                 return err;
 528         }
 529
 530         mxc_hdmi_ipu_id = ipu_id;
 531         mxc_hdmi_disp_id = disp_id;
 532
 533         return err;
 534 }
 535
 536 /* Need to run this before phy is enabled the first time to prevent
 537  * overflow condition in HDMI_IH_FC_STAT2 */
 538 void hdmi_init_clk_regenerator(void)
 539 {
 540         if (pixel_clk_rate == 0) {
 541                 pixel_clk_rate = 74250000;
 542                 hdmi_set_clk_regenerator();
 543         }
 544 }
 545 EXPORT_SYMBOL(hdmi_init_clk_regenerator);
 546
 547 void hdmi_clk_regenerator_update_pixel_clock(u32 pixclock)
 548 {
 549
 550         /* Translate pixel clock in ps (pico seconds) to Hz  */
 551         pixel_clk_rate = PICOS2KHZ(pixclock) * 1000UL;
 552         hdmi_set_clk_regenerator();
 553 }
 554 EXPORT_SYMBOL(hdmi_clk_regenerator_update_pixel_clock);
 555
 556 void hdmi_set_dma_mode(unsigned int dma_running)
 557 {
 558         hdmi_dma_running = dma_running;
 559         hdmi_set_clk_regenerator();
 560 }
 561 EXPORT_SYMBOL(hdmi_set_dma_mode);
 562
 563 void hdmi_set_sample_rate(unsigned int rate)
 564 {
 565         sample_rate = rate;
 566 }
 567 EXPORT_SYMBOL(hdmi_set_sample_rate);
 568
 569 void hdmi_set_edid_cfg(struct mxc_edid_cfg *cfg)
 570 {
 571         unsigned long flags;
 572
 573         spin_lock_irqsave(&edid_spinlock, flags);
 574         memcpy(&hdmi_core_edid_cfg, cfg, sizeof(struct mxc_edid_cfg));
 575         spin_unlock_irqrestore(&edid_spinlock, flags);
 576 }
 577 EXPORT_SYMBOL(hdmi_set_edid_cfg);
 578
 579 void hdmi_get_edid_cfg(struct mxc_edid_cfg *cfg)
 580 {
 581         unsigned long flags;
 582
 583         spin_lock_irqsave(&edid_spinlock, flags);
 584         memcpy(cfg, &hdmi_core_edid_cfg, sizeof(struct mxc_edid_cfg));
 585         spin_unlock_irqrestore(&edid_spinlock, flags);
 586 }
 587 EXPORT_SYMBOL(hdmi_get_edid_cfg);
 588
 589 void hdmi_set_registered(int registered)
 590 {
 591         hdmi_core_init = registered;
 592 }
 593 EXPORT_SYMBOL(hdmi_set_registered);
 594
 595 int hdmi_get_registered(void)
 596 {
 597         return hdmi_core_init;
 598 }
 599 EXPORT_SYMBOL(hdmi_get_registered);
 600
 601 static int mxc_hdmi_core_probe(struct platform_device *pdev)
 602 {
 603         struct mxc_hdmi_data *hdmi_data;
 604         struct resource *res;
 605         unsigned long flags;
 606         int ret = 0;
 607
 608 #ifdef DEBUG
 609         overflow_lo = false;
 610         overflow_hi = false;
 611 #endif
 612
 613         hdmi_core_init = 0;
 614         hdmi_dma_running = 0;
 615
 616         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 617         if (!res)
 618                 return -ENOENT;
 619
 620         ret = hdmi_core_get_of_property(pdev);
 621         if (ret < 0) {
 622                 dev_err(&pdev->dev, "get hdmi of property fail\n");
 623                 return -ENOENT;
 624         }
 625
 626         hdmi_data = devm_kzalloc(&pdev->dev, sizeof(struct mxc_hdmi_data), GFP_KERNEL);
 627         if (!hdmi_data) {
 628                 dev_err(&pdev->dev, "Couldn't allocate mxc hdmi mfd device\n");
 629                 return -ENOMEM;
 630         }
 631         hdmi_data->pdev = pdev;
 632
 633         pixel_clk = NULL;
 634         sample_rate = 48000;
 635         pixel_clk_rate = 0;
 636         hdmi_ratio = 100;
 637
 638         spin_lock_init(&irq_spinlock);
 639         spin_lock_init(&edid_spinlock);
 640
 641
 642         spin_lock_init(&hdmi_cable_state_lock);
 643         spin_lock_init(&hdmi_blank_state_lock);
 644         spin_lock_init(&hdmi_audio_lock);
 645
 646         spin_lock_irqsave(&hdmi_cable_state_lock, flags);
 647         hdmi_cable_state = 0;
 648         spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
 649
 650         spin_lock_irqsave(&hdmi_blank_state_lock, flags);
 651         hdmi_blank_state = 0;
 652         spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
 653
 654         spin_lock_irqsave(&hdmi_audio_lock, flags);
 655         hdmi_audio_stream_playback = NULL;
 656         spin_unlock_irqrestore(&hdmi_audio_lock, flags);
 657
 658         isfr_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_isfr");
 659         if (IS_ERR(isfr_clk)) {
 660                 ret = PTR_ERR(isfr_clk);
 661                 dev_err(&hdmi_data->pdev->dev,
 662                         "Unable to get HDMI isfr clk: %d\n", ret);
 663                 goto eclkg;
 664         }
 665
 666         ret = clk_prepare_enable(isfr_clk);
 667         if (ret < 0) {
 668                 dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
 669                 goto eclke;
 670         }
 671
 672         pr_debug("%s isfr_clk:%d\n", __func__,
 673                 (int)clk_get_rate(isfr_clk));
 674
 675         iahb_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_iahb");
 676         if (IS_ERR(iahb_clk)) {
 677                 ret = PTR_ERR(iahb_clk);
 678                 dev_err(&hdmi_data->pdev->dev,
 679                         "Unable to get HDMI iahb clk: %d\n", ret);
 680                 goto eclkg2;
 681         }
 682
 683         ret = clk_prepare_enable(iahb_clk);
 684         if (ret < 0) {
 685                 dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
 686                 goto eclke2;
 687         }
 688
 689         hdmi_data->reg_phys_base = res->start;
 690         if (!request_mem_region(res->start, resource_size(res),
 691                                 dev_name(&pdev->dev))) {
 692                 dev_err(&pdev->dev, "request_mem_region failed\n");
 693                 ret = -EBUSY;
 694                 goto emem;
 695         }
 696
 697         hdmi_data->reg_base = ioremap(res->start, resource_size(res));
 698         if (!hdmi_data->reg_base) {
 699                 dev_err(&pdev->dev, "ioremap failed\n");
 700                 ret = -ENOMEM;
 701                 goto eirq;
 702         }
 703         hdmi_base = hdmi_data->reg_base;
 704
 705         pr_debug("\n%s hdmi hw base = 0x%08x\n\n", __func__, (int)res->start);
 706
 707         initialize_hdmi_ih_mutes();
 708
 709         /* Disable HDMI clocks until video/audio sub-drivers are initialized */
 710         clk_disable_unprepare(isfr_clk);
 711         clk_disable_unprepare(iahb_clk);
 712
 713         /* Replace platform data coming in with a local struct */
 714         platform_set_drvdata(pdev, hdmi_data);
 715
 716         return ret;
 717
 718 eirq:
 719         release_mem_region(res->start, resource_size(res));
 720 emem:
 721         clk_disable_unprepare(iahb_clk);
 722 eclke2:
 723         clk_put(iahb_clk);
 724 eclkg2:
 725         clk_disable_unprepare(isfr_clk);
 726 eclke:
 727         clk_put(isfr_clk);
 728 eclkg:
 729         return ret;
 730 }
 731
 732
 733 static int __exit mxc_hdmi_core_remove(struct platform_device *pdev)
 734 {
 735         struct mxc_hdmi_data *hdmi_data = platform_get_drvdata(pdev);
 736         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 737
 738         iounmap(hdmi_data->reg_base);
 739         release_mem_region(res->start, resource_size(res));
 740
 741         return 0;
 742 }
 743
 744 static const struct of_device_id imx_hdmi_dt_ids[] = {
 745         { .compatible = "fsl,imx6q-hdmi-core", },
 746         { .compatible = "fsl,imx6dl-hdmi-core", },
 747         { /* sentinel */ }
 748 };
 749
 750 static struct platform_driver mxc_hdmi_core_driver = {
 751         .driver = {
 752                 .name = "mxc_hdmi_core",
 753                 .of_match_table = imx_hdmi_dt_ids,
 754                 .owner = THIS_MODULE,
 755         },
 756         .remove = __exit_p(mxc_hdmi_core_remove),
 757 };
 758
 759 static int __init mxc_hdmi_core_init(void)
 760 {
 761         return platform_driver_probe(&mxc_hdmi_core_driver,
 762                                      mxc_hdmi_core_probe);
 763 }
 764
 765 static void __exit mxc_hdmi_core_exit(void)
 766 {
 767         platform_driver_unregister(&mxc_hdmi_core_driver);
 768 }
 769
 770 subsys_initcall(mxc_hdmi_core_init);
 771 module_exit(mxc_hdmi_core_exit);
 772
 773 MODULE_DESCRIPTION("Core driver for Freescale i.Mx on-chip HDMI");
 774 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 775 MODULE_LICENSE("GPL");