drivers/mfd/rtsx_pcr.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/module.h>
  25 #include <linux/slab.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/highmem.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/delay.h>
  30 #include <linux/idr.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/mfd/core.h>
  33 #include <linux/mfd/rtsx_pci.h>
  34 #include <asm/unaligned.h>
  35
  36 #include "rtsx_pcr.h"
  37
  38 static bool msi_en = true;
  39 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
  40 MODULE_PARM_DESC(msi_en, "Enable MSI");
  41
  42 static DEFINE_IDR(rtsx_pci_idr);
  43 static DEFINE_SPINLOCK(rtsx_pci_lock);
  44
  45 static struct mfd_cell rtsx_pcr_cells[] = {
  46         [RTSX_SD_CARD] = {
  47                 .name = DRV_NAME_RTSX_PCI_SDMMC,
  48         },
  49         [RTSX_MS_CARD] = {
  50                 .name = DRV_NAME_RTSX_PCI_MS,
  51         },
  52 };
  53
  54 static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
  55         { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  56         { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  57         { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  58         { 0, }
  59 };
  60
  61 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
  62
  63 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
  64 {
  65         /* If pci device removed, don't queue idle work any more */
  66         if (pcr->remove_pci)
  67                 return;
  68
  69         if (pcr->state != PDEV_STAT_RUN) {
  70                 pcr->state = PDEV_STAT_RUN;
  71                 if (pcr->ops->enable_auto_blink)
  72                         pcr->ops->enable_auto_blink(pcr);
  73         }
  74
  75         mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
  76 }
  77 EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
  78
  79 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
  80 {
  81         int i;
  82         u32 val = HAIMR_WRITE_START;
  83
  84         val |= (u32)(addr & 0x3FFF) << 16;
  85         val |= (u32)mask << 8;
  86         val |= (u32)data;
  87
  88         rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  89
  90         for (i = 0; i < MAX_RW_REG_CNT; i++) {
  91                 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  92                 if ((val & HAIMR_TRANS_END) == 0) {
  93                         if (data != (u8)val)
  94                                 return -EIO;
  95                         return 0;
  96                 }
  97         }
  98
  99         return -ETIMEDOUT;
 100 }
 101 EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
 102
 103 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
 104 {
 105         u32 val = HAIMR_READ_START;
 106         int i;
 107
 108         val |= (u32)(addr & 0x3FFF) << 16;
 109         rtsx_pci_writel(pcr, RTSX_HAIMR, val);
 110
 111         for (i = 0; i < MAX_RW_REG_CNT; i++) {
 112                 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
 113                 if ((val & HAIMR_TRANS_END) == 0)
 114                         break;
 115         }
 116
 117         if (i >= MAX_RW_REG_CNT)
 118                 return -ETIMEDOUT;
 119
 120         if (data)
 121                 *data = (u8)(val & 0xFF);
 122
 123         return 0;
 124 }
 125 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
 126
 127 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 128 {
 129         int err, i, finished = 0;
 130         u8 tmp;
 131
 132         rtsx_pci_init_cmd(pcr);
 133
 134         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
 135         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
 136         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 137         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
 138
 139         err = rtsx_pci_send_cmd(pcr, 100);
 140         if (err < 0)
 141                 return err;
 142
 143         for (i = 0; i < 100000; i++) {
 144                 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 145                 if (err < 0)
 146                         return err;
 147
 148                 if (!(tmp & 0x80)) {
 149                         finished = 1;
 150                         break;
 151                 }
 152         }
 153
 154         if (!finished)
 155                 return -ETIMEDOUT;
 156
 157         return 0;
 158 }
 159 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
 160
 161 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 162 {
 163         int err, i, finished = 0;
 164         u16 data;
 165         u8 *ptr, tmp;
 166
 167         rtsx_pci_init_cmd(pcr);
 168
 169         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 170         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
 171
 172         err = rtsx_pci_send_cmd(pcr, 100);
 173         if (err < 0)
 174                 return err;
 175
 176         for (i = 0; i < 100000; i++) {
 177                 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 178                 if (err < 0)
 179                         return err;
 180
 181                 if (!(tmp & 0x80)) {
 182                         finished = 1;
 183                         break;
 184                 }
 185         }
 186
 187         if (!finished)
 188                 return -ETIMEDOUT;
 189
 190         rtsx_pci_init_cmd(pcr);
 191
 192         rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
 193         rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
 194
 195         err = rtsx_pci_send_cmd(pcr, 100);
 196         if (err < 0)
 197                 return err;
 198
 199         ptr = rtsx_pci_get_cmd_data(pcr);
 200         data = ((u16)ptr[1] << 8) | ptr[0];
 201
 202         if (val)
 203                 *val = data;
 204
 205         return 0;
 206 }
 207 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
 208
 209 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
 210 {
 211         rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
 212         rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
 213
 214         rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
 215         rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
 216 }
 217 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
 218
 219 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
 220                 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
 221 {
 222         unsigned long flags;
 223         u32 val = 0;
 224         u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
 225
 226         val |= (u32)(cmd_type & 0x03) << 30;
 227         val |= (u32)(reg_addr & 0x3FFF) << 16;
 228         val |= (u32)mask << 8;
 229         val |= (u32)data;
 230
 231         spin_lock_irqsave(&pcr->lock, flags);
 232         ptr += pcr->ci;
 233         if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
 234                 put_unaligned_le32(val, ptr);
 235                 ptr++;
 236                 pcr->ci++;
 237         }
 238         spin_unlock_irqrestore(&pcr->lock, flags);
 239 }
 240 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
 241
 242 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
 243 {
 244         u32 val = 1 << 31;
 245
 246         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 247
 248         val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 249         /* Hardware Auto Response */
 250         val |= 0x40000000;
 251         rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 252 }
 253 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
 254
 255 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
 256 {
 257         struct completion trans_done;
 258         u32 val = 1 << 31;
 259         long timeleft;
 260         unsigned long flags;
 261         int err = 0;
 262
 263         spin_lock_irqsave(&pcr->lock, flags);
 264
 265         /* set up data structures for the wakeup system */
 266         pcr->done = &trans_done;
 267         pcr->trans_result = TRANS_NOT_READY;
 268         init_completion(&trans_done);
 269
 270         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 271
 272         val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 273         /* Hardware Auto Response */
 274         val |= 0x40000000;
 275         rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 276
 277         spin_unlock_irqrestore(&pcr->lock, flags);
 278
 279         /* Wait for TRANS_OK_INT */
 280         timeleft = wait_for_completion_interruptible_timeout(
 281                         &trans_done, msecs_to_jiffies(timeout));
 282         if (timeleft <= 0) {
 283                 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 284                                 __func__, __LINE__);
 285                 err = -ETIMEDOUT;
 286                 goto finish_send_cmd;
 287         }
 288
 289         spin_lock_irqsave(&pcr->lock, flags);
 290         if (pcr->trans_result == TRANS_RESULT_FAIL)
 291                 err = -EINVAL;
 292         else if (pcr->trans_result == TRANS_RESULT_OK)
 293                 err = 0;
 294         else if (pcr->trans_result == TRANS_NO_DEVICE)
 295                 err = -ENODEV;
 296         spin_unlock_irqrestore(&pcr->lock, flags);
 297
 298 finish_send_cmd:
 299         spin_lock_irqsave(&pcr->lock, flags);
 300         pcr->done = NULL;
 301         spin_unlock_irqrestore(&pcr->lock, flags);
 302
 303         if ((err < 0) && (err != -ENODEV))
 304                 rtsx_pci_stop_cmd(pcr);
 305
 306         if (pcr->finish_me)
 307                 complete(pcr->finish_me);
 308
 309         return err;
 310 }
 311 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
 312
 313 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
 314                 dma_addr_t addr, unsigned int len, int end)
 315 {
 316         u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
 317         u64 val;
 318         u8 option = SG_VALID | SG_TRANS_DATA;
 319
 320         dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
 321                         (unsigned int)addr, len);
 322
 323         if (end)
 324                 option |= SG_END;
 325         val = ((u64)addr << 32) | ((u64)len << 12) | option;
 326
 327         put_unaligned_le64(val, ptr);
 328         pcr->sgi++;
 329 }
 330
 331 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 332                 int num_sg, bool read, int timeout)
 333 {
 334         struct completion trans_done;
 335         u8 dir;
 336         int err = 0, i, count;
 337         long timeleft;
 338         unsigned long flags;
 339         struct scatterlist *sg;
 340         enum dma_data_direction dma_dir;
 341         u32 val;
 342         dma_addr_t addr;
 343         unsigned int len;
 344
 345         dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
 346
 347         /* don't transfer data during abort processing */
 348         if (pcr->remove_pci)
 349                 return -EINVAL;
 350
 351         if ((sglist == NULL) || (num_sg <= 0))
 352                 return -EINVAL;
 353
 354         if (read) {
 355                 dir = DEVICE_TO_HOST;
 356                 dma_dir = DMA_FROM_DEVICE;
 357         } else {
 358                 dir = HOST_TO_DEVICE;
 359                 dma_dir = DMA_TO_DEVICE;
 360         }
 361
 362         count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
 363         if (count < 1) {
 364                 dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
 365                 return -EINVAL;
 366         }
 367         dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
 368
 369         val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
 370         pcr->sgi = 0;
 371         for_each_sg(sglist, sg, count, i) {
 372                 addr = sg_dma_address(sg);
 373                 len = sg_dma_len(sg);
 374                 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
 375         }
 376
 377         spin_lock_irqsave(&pcr->lock, flags);
 378
 379         pcr->done = &trans_done;
 380         pcr->trans_result = TRANS_NOT_READY;
 381         init_completion(&trans_done);
 382         rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
 383         rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
 384
 385         spin_unlock_irqrestore(&pcr->lock, flags);
 386
 387         timeleft = wait_for_completion_interruptible_timeout(
 388                         &trans_done, msecs_to_jiffies(timeout));
 389         if (timeleft <= 0) {
 390                 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 391                                 __func__, __LINE__);
 392                 err = -ETIMEDOUT;
 393                 goto out;
 394         }
 395
 396         spin_lock_irqsave(&pcr->lock, flags);
 397
 398         if (pcr->trans_result == TRANS_RESULT_FAIL)
 399                 err = -EINVAL;
 400         else if (pcr->trans_result == TRANS_NO_DEVICE)
 401                 err = -ENODEV;
 402
 403         spin_unlock_irqrestore(&pcr->lock, flags);
 404
 405 out:
 406         spin_lock_irqsave(&pcr->lock, flags);
 407         pcr->done = NULL;
 408         spin_unlock_irqrestore(&pcr->lock, flags);
 409
 410         dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
 411
 412         if ((err < 0) && (err != -ENODEV))
 413                 rtsx_pci_stop_cmd(pcr);
 414
 415         if (pcr->finish_me)
 416                 complete(pcr->finish_me);
 417
 418         return err;
 419 }
 420 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
 421
 422 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 423 {
 424         int err;
 425         int i, j;
 426         u16 reg;
 427         u8 *ptr;
 428
 429         if (buf_len > 512)
 430                 buf_len = 512;
 431
 432         ptr = buf;
 433         reg = PPBUF_BASE2;
 434         for (i = 0; i < buf_len / 256; i++) {
 435                 rtsx_pci_init_cmd(pcr);
 436
 437                 for (j = 0; j < 256; j++)
 438                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 439
 440                 err = rtsx_pci_send_cmd(pcr, 250);
 441                 if (err < 0)
 442                         return err;
 443
 444                 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
 445                 ptr += 256;
 446         }
 447
 448         if (buf_len % 256) {
 449                 rtsx_pci_init_cmd(pcr);
 450
 451                 for (j = 0; j < buf_len % 256; j++)
 452                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 453
 454                 err = rtsx_pci_send_cmd(pcr, 250);
 455                 if (err < 0)
 456                         return err;
 457         }
 458
 459         memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
 460
 461         return 0;
 462 }
 463 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
 464
 465 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 466 {
 467         int err;
 468         int i, j;
 469         u16 reg;
 470         u8 *ptr;
 471
 472         if (buf_len > 512)
 473                 buf_len = 512;
 474
 475         ptr = buf;
 476         reg = PPBUF_BASE2;
 477         for (i = 0; i < buf_len / 256; i++) {
 478                 rtsx_pci_init_cmd(pcr);
 479
 480                 for (j = 0; j < 256; j++) {
 481                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 482                                         reg++, 0xFF, *ptr);
 483                         ptr++;
 484                 }
 485
 486                 err = rtsx_pci_send_cmd(pcr, 250);
 487                 if (err < 0)
 488                         return err;
 489         }
 490
 491         if (buf_len % 256) {
 492                 rtsx_pci_init_cmd(pcr);
 493
 494                 for (j = 0; j < buf_len % 256; j++) {
 495                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 496                                         reg++, 0xFF, *ptr);
 497                         ptr++;
 498                 }
 499
 500                 err = rtsx_pci_send_cmd(pcr, 250);
 501                 if (err < 0)
 502                         return err;
 503         }
 504
 505         return 0;
 506 }
 507 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
 508
 509 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
 510 {
 511         int err;
 512
 513         rtsx_pci_init_cmd(pcr);
 514
 515         while (*tbl & 0xFFFF0000) {
 516                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 517                                 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
 518                 tbl++;
 519         }
 520
 521         err = rtsx_pci_send_cmd(pcr, 100);
 522         if (err < 0)
 523                 return err;
 524
 525         return 0;
 526 }
 527
 528 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
 529 {
 530         const u32 *tbl;
 531
 532         if (card == RTSX_SD_CARD)
 533                 tbl = pcr->sd_pull_ctl_enable_tbl;
 534         else if (card == RTSX_MS_CARD)
 535                 tbl = pcr->ms_pull_ctl_enable_tbl;
 536         else
 537                 return -EINVAL;
 538
 539         return rtsx_pci_set_pull_ctl(pcr, tbl);
 540 }
 541 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
 542
 543 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
 544 {
 545         const u32 *tbl;
 546
 547         if (card == RTSX_SD_CARD)
 548                 tbl = pcr->sd_pull_ctl_disable_tbl;
 549         else if (card == RTSX_MS_CARD)
 550                 tbl = pcr->ms_pull_ctl_disable_tbl;
 551         else
 552                 return -EINVAL;
 553
 554
 555         return rtsx_pci_set_pull_ctl(pcr, tbl);
 556 }
 557 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
 558
 559 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
 560 {
 561         pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
 562
 563         if (pcr->num_slots > 1)
 564                 pcr->bier |= MS_INT_EN;
 565
 566         /* Enable Bus Interrupt */
 567         rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
 568
 569         dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
 570 }
 571
 572 static inline u8 double_ssc_depth(u8 depth)
 573 {
 574         return ((depth > 1) ? (depth - 1) : depth);
 575 }
 576
 577 static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
 578 {
 579         if (div > CLK_DIV_1) {
 580                 if (ssc_depth > (div - 1))
 581                         ssc_depth -= (div - 1);
 582                 else
 583                         ssc_depth = SSC_DEPTH_4M;
 584         }
 585
 586         return ssc_depth;
 587 }
 588
 589 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 590                 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
 591 {
 592         int err, clk;
 593         u8 N, min_N, max_N, clk_divider;
 594         u8 mcu_cnt, div, max_div;
 595         u8 depth[] = {
 596                 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
 597                 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
 598                 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
 599                 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
 600                 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
 601         };
 602
 603         if (initial_mode) {
 604                 /* We use 250k(around) here, in initial stage */
 605                 clk_divider = SD_CLK_DIVIDE_128;
 606                 card_clock = 30000000;
 607         } else {
 608                 clk_divider = SD_CLK_DIVIDE_0;
 609         }
 610         err = rtsx_pci_write_register(pcr, SD_CFG1,
 611                         SD_CLK_DIVIDE_MASK, clk_divider);
 612         if (err < 0)
 613                 return err;
 614
 615         card_clock /= 1000000;
 616         dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
 617
 618         min_N = 80;
 619         max_N = 208;
 620         max_div = CLK_DIV_8;
 621
 622         clk = card_clock;
 623         if (!initial_mode && double_clk)
 624                 clk = card_clock * 2;
 625         dev_dbg(&(pcr->pci->dev),
 626                         "Internal SSC clock: %dMHz (cur_clock = %d)\n",
 627                         clk, pcr->cur_clock);
 628
 629         if (clk == pcr->cur_clock)
 630                 return 0;
 631
 632         if (pcr->ops->conv_clk_and_div_n)
 633                 N = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
 634         else
 635                 N = (u8)(clk - 2);
 636         if ((clk <= 2) || (N > max_N))
 637                 return -EINVAL;
 638
 639         mcu_cnt = (u8)(125/clk + 3);
 640         if (mcu_cnt > 15)
 641                 mcu_cnt = 15;
 642
 643         /* Make sure that the SSC clock div_n is equal or greater than min_N */
 644         div = CLK_DIV_1;
 645         while ((N < min_N) && (div < max_div)) {
 646                 if (pcr->ops->conv_clk_and_div_n) {
 647                         int dbl_clk = pcr->ops->conv_clk_and_div_n(N,
 648                                         DIV_N_TO_CLK) * 2;
 649                         N = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
 650                                         CLK_TO_DIV_N);
 651                 } else {
 652                         N = (N + 2) * 2 - 2;
 653                 }
 654                 div++;
 655         }
 656         dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", N, div);
 657
 658         ssc_depth = depth[ssc_depth];
 659         if (double_clk)
 660                 ssc_depth = double_ssc_depth(ssc_depth);
 661
 662         ssc_depth = revise_ssc_depth(ssc_depth, div);
 663         dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
 664
 665         rtsx_pci_init_cmd(pcr);
 666         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 667                         CLK_LOW_FREQ, CLK_LOW_FREQ);
 668         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
 669                         0xFF, (div << 4) | mcu_cnt);
 670         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
 671         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
 672                         SSC_DEPTH_MASK, ssc_depth);
 673         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
 674         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 675         if (vpclk) {
 676                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 677                                 PHASE_NOT_RESET, 0);
 678                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 679                                 PHASE_NOT_RESET, PHASE_NOT_RESET);
 680         }
 681
 682         err = rtsx_pci_send_cmd(pcr, 2000);
 683         if (err < 0)
 684                 return err;
 685
 686         /* Wait SSC clock stable */
 687         udelay(10);
 688         err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 689         if (err < 0)
 690                 return err;
 691
 692         pcr->cur_clock = clk;
 693         return 0;
 694 }
 695 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
 696
 697 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
 698 {
 699         if (pcr->ops->card_power_on)
 700                 return pcr->ops->card_power_on(pcr, card);
 701
 702         return 0;
 703 }
 704 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
 705
 706 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
 707 {
 708         if (pcr->ops->card_power_off)
 709                 return pcr->ops->card_power_off(pcr, card);
 710
 711         return 0;
 712 }
 713 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
 714
 715 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 716 {
 717         if (pcr->ops->switch_output_voltage)
 718                 return pcr->ops->switch_output_voltage(pcr, voltage);
 719
 720         return 0;
 721 }
 722 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
 723
 724 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
 725 {
 726         unsigned int val;
 727
 728         val = rtsx_pci_readl(pcr, RTSX_BIPR);
 729         if (pcr->ops->cd_deglitch)
 730                 val = pcr->ops->cd_deglitch(pcr);
 731
 732         return val;
 733 }
 734 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
 735
 736 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
 737 {
 738         struct completion finish;
 739
 740         pcr->finish_me = &finish;
 741         init_completion(&finish);
 742
 743         if (pcr->done)
 744                 complete(pcr->done);
 745
 746         if (!pcr->remove_pci)
 747                 rtsx_pci_stop_cmd(pcr);
 748
 749         wait_for_completion_interruptible_timeout(&finish,
 750                         msecs_to_jiffies(2));
 751         pcr->finish_me = NULL;
 752 }
 753 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
 754
 755 static void rtsx_pci_card_detect(struct work_struct *work)
 756 {
 757         struct delayed_work *dwork;
 758         struct rtsx_pcr *pcr;
 759         unsigned long flags;
 760         unsigned int card_detect = 0;
 761         u32 irq_status;
 762
 763         dwork = to_delayed_work(work);
 764         pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
 765
 766         dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 767
 768         spin_lock_irqsave(&pcr->lock, flags);
 769
 770         irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
 771         dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
 772
 773         if (pcr->card_inserted || pcr->card_removed) {
 774                 dev_dbg(&(pcr->pci->dev),
 775                                 "card_inserted: 0x%x, card_removed: 0x%x\n",
 776                                 pcr->card_inserted, pcr->card_removed);
 777
 778                 if (pcr->ops->cd_deglitch)
 779                         pcr->card_inserted = pcr->ops->cd_deglitch(pcr);
 780
 781                 card_detect = pcr->card_inserted | pcr->card_removed;
 782                 pcr->card_inserted = 0;
 783                 pcr->card_removed = 0;
 784         }
 785
 786         spin_unlock_irqrestore(&pcr->lock, flags);
 787
 788         if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
 789                 pcr->slots[RTSX_SD_CARD].card_event(
 790                                 pcr->slots[RTSX_SD_CARD].p_dev);
 791         if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
 792                 pcr->slots[RTSX_MS_CARD].card_event(
 793                                 pcr->slots[RTSX_MS_CARD].p_dev);
 794 }
 795
 796 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
 797 {
 798         struct rtsx_pcr *pcr = dev_id;
 799         u32 int_reg;
 800
 801         if (!pcr)
 802                 return IRQ_NONE;
 803
 804         spin_lock(&pcr->lock);
 805
 806         int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
 807         /* Clear interrupt flag */
 808         rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
 809         if ((int_reg & pcr->bier) == 0) {
 810                 spin_unlock(&pcr->lock);
 811                 return IRQ_NONE;
 812         }
 813         if (int_reg == 0xFFFFFFFF) {
 814                 spin_unlock(&pcr->lock);
 815                 return IRQ_HANDLED;
 816         }
 817
 818         int_reg &= (pcr->bier | 0x7FFFFF);
 819
 820         if (int_reg & SD_INT) {
 821                 if (int_reg & SD_EXIST) {
 822                         pcr->card_inserted |= SD_EXIST;
 823                 } else {
 824                         pcr->card_removed |= SD_EXIST;
 825                         pcr->card_inserted &= ~SD_EXIST;
 826                 }
 827         }
 828
 829         if (int_reg & MS_INT) {
 830                 if (int_reg & MS_EXIST) {
 831                         pcr->card_inserted |= MS_EXIST;
 832                 } else {
 833                         pcr->card_removed |= MS_EXIST;
 834                         pcr->card_inserted &= ~MS_EXIST;
 835                 }
 836         }
 837
 838         if (pcr->card_inserted || pcr->card_removed)
 839                 schedule_delayed_work(&pcr->carddet_work,
 840                                 msecs_to_jiffies(200));
 841
 842         if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
 843                 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
 844                         pcr->trans_result = TRANS_RESULT_FAIL;
 845                         if (pcr->done)
 846                                 complete(pcr->done);
 847                 } else if (int_reg & TRANS_OK_INT) {
 848                         pcr->trans_result = TRANS_RESULT_OK;
 849                         if (pcr->done)
 850                                 complete(pcr->done);
 851                 }
 852         }
 853
 854         spin_unlock(&pcr->lock);
 855         return IRQ_HANDLED;
 856 }
 857
 858 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
 859 {
 860         dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
 861                         __func__, pcr->msi_en, pcr->pci->irq);
 862
 863         if (request_irq(pcr->pci->irq, rtsx_pci_isr,
 864                         pcr->msi_en ? 0 : IRQF_SHARED,
 865                         DRV_NAME_RTSX_PCI, pcr)) {
 866                 dev_err(&(pcr->pci->dev),
 867                         "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
 868                         pcr->pci->irq);
 869                 return -1;
 870         }
 871
 872         pcr->irq = pcr->pci->irq;
 873         pci_intx(pcr->pci, !pcr->msi_en);
 874
 875         return 0;
 876 }
 877
 878 static void rtsx_pci_idle_work(struct work_struct *work)
 879 {
 880         struct delayed_work *dwork = to_delayed_work(work);
 881         struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
 882
 883         dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 884
 885         mutex_lock(&pcr->pcr_mutex);
 886
 887         pcr->state = PDEV_STAT_IDLE;
 888
 889         if (pcr->ops->disable_auto_blink)
 890                 pcr->ops->disable_auto_blink(pcr);
 891         if (pcr->ops->turn_off_led)
 892                 pcr->ops->turn_off_led(pcr);
 893
 894         mutex_unlock(&pcr->pcr_mutex);
 895 }
 896
 897 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
 898 {
 899         int err;
 900
 901         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 902
 903         rtsx_pci_enable_bus_int(pcr);
 904
 905         /* Power on SSC */
 906         err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
 907         if (err < 0)
 908                 return err;
 909
 910         /* Wait SSC power stable */
 911         udelay(200);
 912
 913         if (pcr->ops->optimize_phy) {
 914                 err = pcr->ops->optimize_phy(pcr);
 915                 if (err < 0)
 916                         return err;
 917         }
 918
 919         rtsx_pci_init_cmd(pcr);
 920
 921         /* Set mcu_cnt to 7 to ensure data can be sampled properly */
 922         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
 923
 924         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
 925         /* Disable card clock */
 926         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
 927         /* Reset ASPM state to default value */
 928         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 929         /* Reset delink mode */
 930         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
 931         /* Card driving select */
 932         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
 933                         0x07, DRIVER_TYPE_D);
 934         /* Enable SSC Clock */
 935         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
 936                         0xFF, SSC_8X_EN | SSC_SEL_4M);
 937         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
 938         /* Disable cd_pwr_save */
 939         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
 940         /* Clear Link Ready Interrupt */
 941         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 942                         LINK_RDY_INT, LINK_RDY_INT);
 943         /* Enlarge the estimation window of PERST# glitch
 944          * to reduce the chance of invalid card interrupt
 945          */
 946         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 947         /* Update RC oscillator to 400k
 948          * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
 949          *                1: 2M  0: 400k
 950          */
 951         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
 952         /* Set interrupt write clear
 953          * bit 1: U_elbi_if_rd_clr_en
 954          *      1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
 955          *      0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
 956          */
 957         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
 958         /* Force CLKREQ# PIN to drive 0 to request clock */
 959         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
 960
 961         err = rtsx_pci_send_cmd(pcr, 100);
 962         if (err < 0)
 963                 return err;
 964
 965         /* Enable clk_request_n to enable clock power management */
 966         rtsx_pci_write_config_byte(pcr, 0x81, 1);
 967         /* Enter L1 when host tx idle */
 968         rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
 969
 970         if (pcr->ops->extra_init_hw) {
 971                 err = pcr->ops->extra_init_hw(pcr);
 972                 if (err < 0)
 973                         return err;
 974         }
 975
 976         return 0;
 977 }
 978
 979 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
 980 {
 981         int err;
 982
 983         spin_lock_init(&pcr->lock);
 984         mutex_init(&pcr->pcr_mutex);
 985
 986         switch (PCI_PID(pcr)) {
 987         default:
 988         case 0x5209:
 989                 rts5209_init_params(pcr);
 990                 break;
 991
 992         case 0x5229:
 993                 rts5229_init_params(pcr);
 994                 break;
 995
 996         case 0x5289:
 997                 rtl8411_init_params(pcr);
 998                 break;
 999         }
1000
1001         dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1002                         PCI_PID(pcr), pcr->ic_version);
1003
1004         pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1005                         GFP_KERNEL);
1006         if (!pcr->slots)
1007                 return -ENOMEM;
1008
1009         pcr->state = PDEV_STAT_IDLE;
1010         err = rtsx_pci_init_hw(pcr);
1011         if (err < 0) {
1012                 kfree(pcr->slots);
1013                 return err;
1014         }
1015
1016         return 0;
1017 }
1018
1019 static int rtsx_pci_probe(struct pci_dev *pcidev,
1020                           const struct pci_device_id *id)
1021 {
1022         struct rtsx_pcr *pcr;
1023         struct pcr_handle *handle;
1024         u32 base, len;
1025         int ret, i;
1026
1027         dev_dbg(&(pcidev->dev),
1028                 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1029                 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1030                 (int)pcidev->revision);
1031
1032         ret = pci_enable_device(pcidev);
1033         if (ret)
1034                 return ret;
1035
1036         ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1037         if (ret)
1038                 goto disable;
1039
1040         pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1041         if (!pcr) {
1042                 ret = -ENOMEM;
1043                 goto release_pci;
1044         }
1045
1046         handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1047         if (!handle) {
1048                 ret = -ENOMEM;
1049                 goto free_pcr;
1050         }
1051         handle->pcr = pcr;
1052
1053         if (!idr_pre_get(&rtsx_pci_idr, GFP_KERNEL)) {
1054                 ret = -ENOMEM;
1055                 goto free_handle;
1056         }
1057
1058         spin_lock(&rtsx_pci_lock);
1059         ret = idr_get_new(&rtsx_pci_idr, pcr, &pcr->id);
1060         spin_unlock(&rtsx_pci_lock);
1061         if (ret)
1062                 goto free_handle;
1063
1064         pcr->pci = pcidev;
1065         dev_set_drvdata(&pcidev->dev, handle);
1066
1067         len = pci_resource_len(pcidev, 0);
1068         base = pci_resource_start(pcidev, 0);
1069         pcr->remap_addr = ioremap_nocache(base, len);
1070         if (!pcr->remap_addr) {
1071                 ret = -ENOMEM;
1072                 goto free_host;
1073         }
1074
1075         pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1076                         RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1077                         GFP_KERNEL);
1078         if (pcr->rtsx_resv_buf == NULL) {
1079                 ret = -ENXIO;
1080                 goto unmap;
1081         }
1082         pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1083         pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1084         pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1085         pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1086
1087         pcr->card_inserted = 0;
1088         pcr->card_removed = 0;
1089         INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1090         INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1091
1092         pcr->msi_en = msi_en;
1093         if (pcr->msi_en) {
1094                 ret = pci_enable_msi(pcidev);
1095                 if (ret < 0)
1096                         pcr->msi_en = false;
1097         }
1098
1099         ret = rtsx_pci_acquire_irq(pcr);
1100         if (ret < 0)
1101                 goto free_dma;
1102
1103         pci_set_master(pcidev);
1104         synchronize_irq(pcr->irq);
1105
1106         ret = rtsx_pci_init_chip(pcr);
1107         if (ret < 0)
1108                 goto disable_irq;
1109
1110         for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1111                 rtsx_pcr_cells[i].platform_data = handle;
1112                 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1113         }
1114         ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1115                         ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1116         if (ret < 0)
1117                 goto disable_irq;
1118
1119         schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1120
1121         return 0;
1122
1123 disable_irq:
1124         free_irq(pcr->irq, (void *)pcr);
1125 free_dma:
1126         dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1127                         pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1128 unmap:
1129         iounmap(pcr->remap_addr);
1130 free_host:
1131         dev_set_drvdata(&pcidev->dev, NULL);
1132 free_handle:
1133         kfree(handle);
1134 free_pcr:
1135         kfree(pcr);
1136 release_pci:
1137         pci_release_regions(pcidev);
1138 disable:
1139         pci_disable_device(pcidev);
1140
1141         return ret;
1142 }
1143
1144 static void rtsx_pci_remove(struct pci_dev *pcidev)
1145 {
1146         struct pcr_handle *handle = pci_get_drvdata(pcidev);
1147         struct rtsx_pcr *pcr = handle->pcr;
1148
1149         pcr->remove_pci = true;
1150
1151         cancel_delayed_work(&pcr->carddet_work);
1152         cancel_delayed_work(&pcr->idle_work);
1153
1154         mfd_remove_devices(&pcidev->dev);
1155
1156         dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1157                         pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1158         free_irq(pcr->irq, (void *)pcr);
1159         if (pcr->msi_en)
1160                 pci_disable_msi(pcr->pci);
1161         iounmap(pcr->remap_addr);
1162
1163         dev_set_drvdata(&pcidev->dev, NULL);
1164         pci_release_regions(pcidev);
1165         pci_disable_device(pcidev);
1166
1167         spin_lock(&rtsx_pci_lock);
1168         idr_remove(&rtsx_pci_idr, pcr->id);
1169         spin_unlock(&rtsx_pci_lock);
1170
1171         kfree(pcr->slots);
1172         kfree(pcr);
1173         kfree(handle);
1174
1175         dev_dbg(&(pcidev->dev),
1176                 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1177                 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1178 }
1179
1180 #ifdef CONFIG_PM
1181
1182 static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1183 {
1184         struct pcr_handle *handle;
1185         struct rtsx_pcr *pcr;
1186         int ret = 0;
1187
1188         dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1189
1190         handle = pci_get_drvdata(pcidev);
1191         pcr = handle->pcr;
1192
1193         cancel_delayed_work(&pcr->carddet_work);
1194         cancel_delayed_work(&pcr->idle_work);
1195
1196         mutex_lock(&pcr->pcr_mutex);
1197
1198         if (pcr->ops->turn_off_led)
1199                 pcr->ops->turn_off_led(pcr);
1200
1201         rtsx_pci_writel(pcr, RTSX_BIER, 0);
1202         pcr->bier = 0;
1203
1204         rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1205         rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02);
1206
1207         pci_save_state(pcidev);
1208         pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1209         pci_disable_device(pcidev);
1210         pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1211
1212         mutex_unlock(&pcr->pcr_mutex);
1213         return ret;
1214 }
1215
1216 static int rtsx_pci_resume(struct pci_dev *pcidev)
1217 {
1218         struct pcr_handle *handle;
1219         struct rtsx_pcr *pcr;
1220         int ret = 0;
1221
1222         dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1223
1224         handle = pci_get_drvdata(pcidev);
1225         pcr = handle->pcr;
1226
1227         mutex_lock(&pcr->pcr_mutex);
1228
1229         pci_set_power_state(pcidev, PCI_D0);
1230         pci_restore_state(pcidev);
1231         ret = pci_enable_device(pcidev);
1232         if (ret)
1233                 goto out;
1234         pci_set_master(pcidev);
1235
1236         ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1237         if (ret)
1238                 goto out;
1239
1240         ret = rtsx_pci_init_hw(pcr);
1241         if (ret)
1242                 goto out;
1243
1244         schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1245
1246 out:
1247         mutex_unlock(&pcr->pcr_mutex);
1248         return ret;
1249 }
1250
1251 #else /* CONFIG_PM */
1252
1253 #define rtsx_pci_suspend NULL
1254 #define rtsx_pci_resume NULL
1255
1256 #endif /* CONFIG_PM */
1257
1258 static struct pci_driver rtsx_pci_driver = {
1259         .name = DRV_NAME_RTSX_PCI,
1260         .id_table = rtsx_pci_ids,
1261         .probe = rtsx_pci_probe,
1262         .remove = rtsx_pci_remove,
1263         .suspend = rtsx_pci_suspend,
1264         .resume = rtsx_pci_resume,
1265 };
1266 module_pci_driver(rtsx_pci_driver);
1267
1268 MODULE_LICENSE("GPL");
1269 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1270 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");