1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23 #include <linux/pci.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/highmem.h>
28 #include <linux/interrupt.h>
29 #include <linux/delay.h>
30 #include <linux/idr.h>
31 #include <linux/platform_device.h>
32 #include <linux/mfd/core.h>
33 #include <linux/mfd/rtsx_pci.h>
34 #include <asm/unaligned.h>
38 static bool msi_en = true;
39 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
40 MODULE_PARM_DESC(msi_en, "Enable MSI");
42 static DEFINE_IDR(rtsx_pci_idr);
43 static DEFINE_SPINLOCK(rtsx_pci_lock);
45 static struct mfd_cell rtsx_pcr_cells[] = {
47 .name = DRV_NAME_RTSX_PCI_SDMMC,
50 .name = DRV_NAME_RTSX_PCI_MS,
54 static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
55 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
58 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
59 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
60 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
64 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
66 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
68 /* If pci device removed, don't queue idle work any more */
72 if (pcr->state != PDEV_STAT_RUN) {
73 pcr->state = PDEV_STAT_RUN;
74 if (pcr->ops->enable_auto_blink)
75 pcr->ops->enable_auto_blink(pcr);
78 rtsx_pci_write_config_byte(pcr, LCTLR, 0);
81 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
83 EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
85 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
88 u32 val = HAIMR_WRITE_START;
90 val |= (u32)(addr & 0x3FFF) << 16;
91 val |= (u32)mask << 8;
94 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
96 for (i = 0; i < MAX_RW_REG_CNT; i++) {
97 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
98 if ((val & HAIMR_TRANS_END) == 0) {
107 EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
109 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
111 u32 val = HAIMR_READ_START;
114 val |= (u32)(addr & 0x3FFF) << 16;
115 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
117 for (i = 0; i < MAX_RW_REG_CNT; i++) {
118 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
119 if ((val & HAIMR_TRANS_END) == 0)
123 if (i >= MAX_RW_REG_CNT)
127 *data = (u8)(val & 0xFF);
131 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
133 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
135 int err, i, finished = 0;
138 rtsx_pci_init_cmd(pcr);
140 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
141 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
142 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
143 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
145 err = rtsx_pci_send_cmd(pcr, 100);
149 for (i = 0; i < 100000; i++) {
150 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
165 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
167 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
169 int err, i, finished = 0;
173 rtsx_pci_init_cmd(pcr);
175 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
176 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
178 err = rtsx_pci_send_cmd(pcr, 100);
182 for (i = 0; i < 100000; i++) {
183 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
196 rtsx_pci_init_cmd(pcr);
198 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
199 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
201 err = rtsx_pci_send_cmd(pcr, 100);
205 ptr = rtsx_pci_get_cmd_data(pcr);
206 data = ((u16)ptr[1] << 8) | ptr[0];
213 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
215 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
217 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
218 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
220 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
221 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
223 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
225 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
226 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
230 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
232 val |= (u32)(cmd_type & 0x03) << 30;
233 val |= (u32)(reg_addr & 0x3FFF) << 16;
234 val |= (u32)mask << 8;
237 spin_lock_irqsave(&pcr->lock, flags);
239 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
240 put_unaligned_le32(val, ptr);
244 spin_unlock_irqrestore(&pcr->lock, flags);
246 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
248 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
252 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
254 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
255 /* Hardware Auto Response */
257 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
259 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
261 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
263 struct completion trans_done;
269 spin_lock_irqsave(&pcr->lock, flags);
271 /* set up data structures for the wakeup system */
272 pcr->done = &trans_done;
273 pcr->trans_result = TRANS_NOT_READY;
274 init_completion(&trans_done);
276 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
278 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
279 /* Hardware Auto Response */
281 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
283 spin_unlock_irqrestore(&pcr->lock, flags);
285 /* Wait for TRANS_OK_INT */
286 timeleft = wait_for_completion_interruptible_timeout(
287 &trans_done, msecs_to_jiffies(timeout));
289 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
292 goto finish_send_cmd;
295 spin_lock_irqsave(&pcr->lock, flags);
296 if (pcr->trans_result == TRANS_RESULT_FAIL)
298 else if (pcr->trans_result == TRANS_RESULT_OK)
300 else if (pcr->trans_result == TRANS_NO_DEVICE)
302 spin_unlock_irqrestore(&pcr->lock, flags);
305 spin_lock_irqsave(&pcr->lock, flags);
307 spin_unlock_irqrestore(&pcr->lock, flags);
309 if ((err < 0) && (err != -ENODEV))
310 rtsx_pci_stop_cmd(pcr);
313 complete(pcr->finish_me);
317 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
319 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
320 dma_addr_t addr, unsigned int len, int end)
322 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
324 u8 option = SG_VALID | SG_TRANS_DATA;
326 dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
327 (unsigned int)addr, len);
331 val = ((u64)addr << 32) | ((u64)len << 12) | option;
333 put_unaligned_le64(val, ptr);
337 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
338 int num_sg, bool read, int timeout)
340 struct completion trans_done;
342 int err = 0, i, count;
345 struct scatterlist *sg;
346 enum dma_data_direction dma_dir;
351 dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
353 /* don't transfer data during abort processing */
357 if ((sglist == NULL) || (num_sg <= 0))
361 dir = DEVICE_TO_HOST;
362 dma_dir = DMA_FROM_DEVICE;
364 dir = HOST_TO_DEVICE;
365 dma_dir = DMA_TO_DEVICE;
368 count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
370 dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
373 dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
375 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
377 for_each_sg(sglist, sg, count, i) {
378 addr = sg_dma_address(sg);
379 len = sg_dma_len(sg);
380 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
383 spin_lock_irqsave(&pcr->lock, flags);
385 pcr->done = &trans_done;
386 pcr->trans_result = TRANS_NOT_READY;
387 init_completion(&trans_done);
388 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
389 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
391 spin_unlock_irqrestore(&pcr->lock, flags);
393 timeleft = wait_for_completion_interruptible_timeout(
394 &trans_done, msecs_to_jiffies(timeout));
396 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
402 spin_lock_irqsave(&pcr->lock, flags);
404 if (pcr->trans_result == TRANS_RESULT_FAIL)
406 else if (pcr->trans_result == TRANS_NO_DEVICE)
409 spin_unlock_irqrestore(&pcr->lock, flags);
412 spin_lock_irqsave(&pcr->lock, flags);
414 spin_unlock_irqrestore(&pcr->lock, flags);
416 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
418 if ((err < 0) && (err != -ENODEV))
419 rtsx_pci_stop_cmd(pcr);
422 complete(pcr->finish_me);
426 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
428 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
440 for (i = 0; i < buf_len / 256; i++) {
441 rtsx_pci_init_cmd(pcr);
443 for (j = 0; j < 256; j++)
444 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
446 err = rtsx_pci_send_cmd(pcr, 250);
450 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
455 rtsx_pci_init_cmd(pcr);
457 for (j = 0; j < buf_len % 256; j++)
458 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
460 err = rtsx_pci_send_cmd(pcr, 250);
465 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
469 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
471 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
483 for (i = 0; i < buf_len / 256; i++) {
484 rtsx_pci_init_cmd(pcr);
486 for (j = 0; j < 256; j++) {
487 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
492 err = rtsx_pci_send_cmd(pcr, 250);
498 rtsx_pci_init_cmd(pcr);
500 for (j = 0; j < buf_len % 256; j++) {
501 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
506 err = rtsx_pci_send_cmd(pcr, 250);
513 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
515 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
519 rtsx_pci_init_cmd(pcr);
521 while (*tbl & 0xFFFF0000) {
522 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
523 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
527 err = rtsx_pci_send_cmd(pcr, 100);
534 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
538 if (card == RTSX_SD_CARD)
539 tbl = pcr->sd_pull_ctl_enable_tbl;
540 else if (card == RTSX_MS_CARD)
541 tbl = pcr->ms_pull_ctl_enable_tbl;
545 return rtsx_pci_set_pull_ctl(pcr, tbl);
547 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
549 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
553 if (card == RTSX_SD_CARD)
554 tbl = pcr->sd_pull_ctl_disable_tbl;
555 else if (card == RTSX_MS_CARD)
556 tbl = pcr->ms_pull_ctl_disable_tbl;
561 return rtsx_pci_set_pull_ctl(pcr, tbl);
563 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
565 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
567 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
569 if (pcr->num_slots > 1)
570 pcr->bier |= MS_INT_EN;
572 /* Enable Bus Interrupt */
573 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
575 dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
578 static inline u8 double_ssc_depth(u8 depth)
580 return ((depth > 1) ? (depth - 1) : depth);
583 static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
585 if (div > CLK_DIV_1) {
586 if (ssc_depth > (div - 1))
587 ssc_depth -= (div - 1);
589 ssc_depth = SSC_DEPTH_4M;
595 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
596 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
599 u8 n, clk_divider, mcu_cnt, div;
601 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
602 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
603 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
604 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
605 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
609 /* We use 250k(around) here, in initial stage */
610 clk_divider = SD_CLK_DIVIDE_128;
611 card_clock = 30000000;
613 clk_divider = SD_CLK_DIVIDE_0;
615 err = rtsx_pci_write_register(pcr, SD_CFG1,
616 SD_CLK_DIVIDE_MASK, clk_divider);
620 card_clock /= 1000000;
621 dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
624 if (!initial_mode && double_clk)
625 clk = card_clock * 2;
626 dev_dbg(&(pcr->pci->dev),
627 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
628 clk, pcr->cur_clock);
630 if (clk == pcr->cur_clock)
633 if (pcr->ops->conv_clk_and_div_n)
634 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
637 if ((clk <= 2) || (n > MAX_DIV_N_PCR))
640 mcu_cnt = (u8)(125/clk + 3);
644 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
646 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
647 if (pcr->ops->conv_clk_and_div_n) {
648 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
650 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
657 dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
659 ssc_depth = depth[ssc_depth];
661 ssc_depth = double_ssc_depth(ssc_depth);
663 ssc_depth = revise_ssc_depth(ssc_depth, div);
664 dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
666 rtsx_pci_init_cmd(pcr);
667 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
668 CLK_LOW_FREQ, CLK_LOW_FREQ);
669 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
670 0xFF, (div << 4) | mcu_cnt);
671 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
672 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
673 SSC_DEPTH_MASK, ssc_depth);
674 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
675 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
677 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
679 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
680 PHASE_NOT_RESET, PHASE_NOT_RESET);
683 err = rtsx_pci_send_cmd(pcr, 2000);
687 /* Wait SSC clock stable */
689 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
693 pcr->cur_clock = clk;
696 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
698 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
700 if (pcr->ops->card_power_on)
701 return pcr->ops->card_power_on(pcr, card);
705 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
707 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
709 if (pcr->ops->card_power_off)
710 return pcr->ops->card_power_off(pcr, card);
714 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
716 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
718 unsigned int cd_mask[] = {
719 [RTSX_SD_CARD] = SD_EXIST,
720 [RTSX_MS_CARD] = MS_EXIST
723 if (!(pcr->flags & PCR_MS_PMOS)) {
724 /* When using single PMOS, accessing card is not permitted
725 * if the existing card is not the designated one.
727 if (pcr->card_exist & (~cd_mask[card]))
733 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
735 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
737 if (pcr->ops->switch_output_voltage)
738 return pcr->ops->switch_output_voltage(pcr, voltage);
742 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
744 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
748 val = rtsx_pci_readl(pcr, RTSX_BIPR);
749 if (pcr->ops->cd_deglitch)
750 val = pcr->ops->cd_deglitch(pcr);
754 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
756 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
758 struct completion finish;
760 pcr->finish_me = &finish;
761 init_completion(&finish);
766 if (!pcr->remove_pci)
767 rtsx_pci_stop_cmd(pcr);
769 wait_for_completion_interruptible_timeout(&finish,
770 msecs_to_jiffies(2));
771 pcr->finish_me = NULL;
773 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
775 static void rtsx_pci_card_detect(struct work_struct *work)
777 struct delayed_work *dwork;
778 struct rtsx_pcr *pcr;
780 unsigned int card_detect = 0, card_inserted, card_removed;
783 dwork = to_delayed_work(work);
784 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
786 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
788 mutex_lock(&pcr->pcr_mutex);
789 spin_lock_irqsave(&pcr->lock, flags);
791 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
792 dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
794 irq_status &= CARD_EXIST;
795 card_inserted = pcr->card_inserted & irq_status;
796 card_removed = pcr->card_removed;
797 pcr->card_inserted = 0;
798 pcr->card_removed = 0;
800 spin_unlock_irqrestore(&pcr->lock, flags);
802 if (card_inserted || card_removed) {
803 dev_dbg(&(pcr->pci->dev),
804 "card_inserted: 0x%x, card_removed: 0x%x\n",
805 card_inserted, card_removed);
807 if (pcr->ops->cd_deglitch)
808 card_inserted = pcr->ops->cd_deglitch(pcr);
810 card_detect = card_inserted | card_removed;
812 pcr->card_exist |= card_inserted;
813 pcr->card_exist &= ~card_removed;
816 mutex_unlock(&pcr->pcr_mutex);
818 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
819 pcr->slots[RTSX_SD_CARD].card_event(
820 pcr->slots[RTSX_SD_CARD].p_dev);
821 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
822 pcr->slots[RTSX_MS_CARD].card_event(
823 pcr->slots[RTSX_MS_CARD].p_dev);
826 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
828 struct rtsx_pcr *pcr = dev_id;
834 spin_lock(&pcr->lock);
836 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
837 /* Clear interrupt flag */
838 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
839 if ((int_reg & pcr->bier) == 0) {
840 spin_unlock(&pcr->lock);
843 if (int_reg == 0xFFFFFFFF) {
844 spin_unlock(&pcr->lock);
848 int_reg &= (pcr->bier | 0x7FFFFF);
850 if (int_reg & SD_INT) {
851 if (int_reg & SD_EXIST) {
852 pcr->card_inserted |= SD_EXIST;
854 pcr->card_removed |= SD_EXIST;
855 pcr->card_inserted &= ~SD_EXIST;
859 if (int_reg & MS_INT) {
860 if (int_reg & MS_EXIST) {
861 pcr->card_inserted |= MS_EXIST;
863 pcr->card_removed |= MS_EXIST;
864 pcr->card_inserted &= ~MS_EXIST;
868 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
869 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
870 pcr->trans_result = TRANS_RESULT_FAIL;
873 } else if (int_reg & TRANS_OK_INT) {
874 pcr->trans_result = TRANS_RESULT_OK;
880 if (pcr->card_inserted || pcr->card_removed)
881 schedule_delayed_work(&pcr->carddet_work,
882 msecs_to_jiffies(200));
884 spin_unlock(&pcr->lock);
888 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
890 dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
891 __func__, pcr->msi_en, pcr->pci->irq);
893 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
894 pcr->msi_en ? 0 : IRQF_SHARED,
895 DRV_NAME_RTSX_PCI, pcr)) {
896 dev_err(&(pcr->pci->dev),
897 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
902 pcr->irq = pcr->pci->irq;
903 pci_intx(pcr->pci, !pcr->msi_en);
908 static void rtsx_pci_idle_work(struct work_struct *work)
910 struct delayed_work *dwork = to_delayed_work(work);
911 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
913 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
915 mutex_lock(&pcr->pcr_mutex);
917 pcr->state = PDEV_STAT_IDLE;
919 if (pcr->ops->disable_auto_blink)
920 pcr->ops->disable_auto_blink(pcr);
921 if (pcr->ops->turn_off_led)
922 pcr->ops->turn_off_led(pcr);
925 rtsx_pci_write_config_byte(pcr, LCTLR, pcr->aspm_en);
927 mutex_unlock(&pcr->pcr_mutex);
930 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
934 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
936 rtsx_pci_enable_bus_int(pcr);
939 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
943 /* Wait SSC power stable */
946 if (pcr->ops->optimize_phy) {
947 err = pcr->ops->optimize_phy(pcr);
952 rtsx_pci_init_cmd(pcr);
954 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
955 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
957 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
958 /* Disable card clock */
959 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
960 /* Reset ASPM state to default value */
961 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
962 /* Reset delink mode */
963 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
964 /* Card driving select */
965 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
966 0xFF, pcr->card_drive_sel);
967 /* Enable SSC Clock */
968 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
969 0xFF, SSC_8X_EN | SSC_SEL_4M);
970 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
971 /* Disable cd_pwr_save */
972 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
973 /* Clear Link Ready Interrupt */
974 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
975 LINK_RDY_INT, LINK_RDY_INT);
976 /* Enlarge the estimation window of PERST# glitch
977 * to reduce the chance of invalid card interrupt
979 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
980 /* Update RC oscillator to 400k
981 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
984 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
985 /* Set interrupt write clear
986 * bit 1: U_elbi_if_rd_clr_en
987 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
988 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
990 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
991 /* Force CLKREQ# PIN to drive 0 to request clock */
992 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
994 err = rtsx_pci_send_cmd(pcr, 100);
998 rtsx_pci_write_config_byte(pcr, LCTLR, 0);
1000 /* Enable clk_request_n to enable clock power management */
1001 rtsx_pci_write_config_byte(pcr, 0x81, 1);
1002 /* Enter L1 when host tx idle */
1003 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1005 if (pcr->ops->extra_init_hw) {
1006 err = pcr->ops->extra_init_hw(pcr);
1011 /* No CD interrupt if probing driver with card inserted.
1012 * So we need to initialize pcr->card_exist here.
1014 if (pcr->ops->cd_deglitch)
1015 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1017 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1022 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1026 spin_lock_init(&pcr->lock);
1027 mutex_init(&pcr->pcr_mutex);
1029 switch (PCI_PID(pcr)) {
1032 rts5209_init_params(pcr);
1036 rts5229_init_params(pcr);
1040 rtl8411_init_params(pcr);
1044 rts5227_init_params(pcr);
1048 rts5249_init_params(pcr);
1052 rtl8411b_init_params(pcr);
1056 dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1057 PCI_PID(pcr), pcr->ic_version);
1059 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1064 if (pcr->ops->fetch_vendor_settings)
1065 pcr->ops->fetch_vendor_settings(pcr);
1067 dev_dbg(&(pcr->pci->dev), "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1068 dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1069 pcr->sd30_drive_sel_1v8);
1070 dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1071 pcr->sd30_drive_sel_3v3);
1072 dev_dbg(&(pcr->pci->dev), "pcr->card_drive_sel = 0x%x\n",
1073 pcr->card_drive_sel);
1074 dev_dbg(&(pcr->pci->dev), "pcr->flags = 0x%x\n", pcr->flags);
1076 pcr->state = PDEV_STAT_IDLE;
1077 err = rtsx_pci_init_hw(pcr);
1086 static int rtsx_pci_probe(struct pci_dev *pcidev,
1087 const struct pci_device_id *id)
1089 struct rtsx_pcr *pcr;
1090 struct pcr_handle *handle;
1094 dev_dbg(&(pcidev->dev),
1095 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1096 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1097 (int)pcidev->revision);
1099 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1103 ret = pci_enable_device(pcidev);
1107 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1111 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1117 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1124 idr_preload(GFP_KERNEL);
1125 spin_lock(&rtsx_pci_lock);
1126 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1129 spin_unlock(&rtsx_pci_lock);
1135 dev_set_drvdata(&pcidev->dev, handle);
1137 len = pci_resource_len(pcidev, 0);
1138 base = pci_resource_start(pcidev, 0);
1139 pcr->remap_addr = ioremap_nocache(base, len);
1140 if (!pcr->remap_addr) {
1145 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1146 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1148 if (pcr->rtsx_resv_buf == NULL) {
1152 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1153 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1154 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1155 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1157 pcr->card_inserted = 0;
1158 pcr->card_removed = 0;
1159 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1160 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1162 pcr->msi_en = msi_en;
1164 ret = pci_enable_msi(pcidev);
1166 pcr->msi_en = false;
1169 ret = rtsx_pci_acquire_irq(pcr);
1173 pci_set_master(pcidev);
1174 synchronize_irq(pcr->irq);
1176 ret = rtsx_pci_init_chip(pcr);
1180 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1181 rtsx_pcr_cells[i].platform_data = handle;
1182 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1184 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1185 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1189 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1194 free_irq(pcr->irq, (void *)pcr);
1197 pci_disable_msi(pcr->pci);
1198 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1199 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1201 iounmap(pcr->remap_addr);
1203 dev_set_drvdata(&pcidev->dev, NULL);
1209 pci_release_regions(pcidev);
1211 pci_disable_device(pcidev);
1216 static void rtsx_pci_remove(struct pci_dev *pcidev)
1218 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1219 struct rtsx_pcr *pcr = handle->pcr;
1221 pcr->remove_pci = true;
1223 cancel_delayed_work(&pcr->carddet_work);
1224 cancel_delayed_work(&pcr->idle_work);
1226 mfd_remove_devices(&pcidev->dev);
1228 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1229 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1230 free_irq(pcr->irq, (void *)pcr);
1232 pci_disable_msi(pcr->pci);
1233 iounmap(pcr->remap_addr);
1235 dev_set_drvdata(&pcidev->dev, NULL);
1236 pci_release_regions(pcidev);
1237 pci_disable_device(pcidev);
1239 spin_lock(&rtsx_pci_lock);
1240 idr_remove(&rtsx_pci_idr, pcr->id);
1241 spin_unlock(&rtsx_pci_lock);
1247 dev_dbg(&(pcidev->dev),
1248 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1249 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1254 static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1256 struct pcr_handle *handle;
1257 struct rtsx_pcr *pcr;
1260 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1262 handle = pci_get_drvdata(pcidev);
1265 cancel_delayed_work(&pcr->carddet_work);
1266 cancel_delayed_work(&pcr->idle_work);
1268 mutex_lock(&pcr->pcr_mutex);
1270 if (pcr->ops->turn_off_led)
1271 pcr->ops->turn_off_led(pcr);
1273 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1276 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1277 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02);
1279 pci_save_state(pcidev);
1280 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1281 pci_disable_device(pcidev);
1282 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1284 mutex_unlock(&pcr->pcr_mutex);
1288 static int rtsx_pci_resume(struct pci_dev *pcidev)
1290 struct pcr_handle *handle;
1291 struct rtsx_pcr *pcr;
1294 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1296 handle = pci_get_drvdata(pcidev);
1299 mutex_lock(&pcr->pcr_mutex);
1301 pci_set_power_state(pcidev, PCI_D0);
1302 pci_restore_state(pcidev);
1303 ret = pci_enable_device(pcidev);
1306 pci_set_master(pcidev);
1308 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1312 ret = rtsx_pci_init_hw(pcr);
1316 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1319 mutex_unlock(&pcr->pcr_mutex);
1323 #else /* CONFIG_PM */
1325 #define rtsx_pci_suspend NULL
1326 #define rtsx_pci_resume NULL
1328 #endif /* CONFIG_PM */
1330 static struct pci_driver rtsx_pci_driver = {
1331 .name = DRV_NAME_RTSX_PCI,
1332 .id_table = rtsx_pci_ids,
1333 .probe = rtsx_pci_probe,
1334 .remove = rtsx_pci_remove,
1335 .suspend = rtsx_pci_suspend,
1336 .resume = rtsx_pci_resume,
1338 module_pci_driver(rtsx_pci_driver);
1340 MODULE_LICENSE("GPL");
1341 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1342 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");