drivers/mfd/sm501.c

   1 /* linux/drivers/mfd/sm501.c
   2  *
   3  * Copyright (C) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *      Vincent Sanders <vince@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * SM501 MFD driver
  12 */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/list.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pci.h>
  22 #include <linux/gpio.h>
  23
  24 #include <linux/sm501.h>
  25 #include <linux/sm501-regs.h>
  26 #include <linux/serial_8250.h>
  27
  28 #include <asm/io.h>
  29
  30 struct sm501_device {
  31         struct list_head                list;
  32         struct platform_device          pdev;
  33 };
  34
  35 struct sm501_gpio;
  36
  37 struct sm501_gpio_chip {
  38         struct gpio_chip        gpio;
  39         struct sm501_gpio       *ourgpio;       /* to get back to parent. */
  40         void __iomem            *regbase;
  41 };
  42
  43 struct sm501_gpio {
  44         struct sm501_gpio_chip  low;
  45         struct sm501_gpio_chip  high;
  46         spinlock_t              lock;
  47
  48         unsigned int             registered : 1;
  49         void __iomem            *regs;
  50         struct resource         *regs_res;
  51 };
  52
  53 struct sm501_devdata {
  54         spinlock_t                       reg_lock;
  55         struct mutex                     clock_lock;
  56         struct list_head                 devices;
  57         struct sm501_gpio                gpio;
  58
  59         struct device                   *dev;
  60         struct resource                 *io_res;
  61         struct resource                 *mem_res;
  62         struct resource                 *regs_claim;
  63         struct sm501_platdata           *platdata;
  64
  65
  66         unsigned int                     in_suspend;
  67         unsigned long                    pm_misc;
  68
  69         int                              unit_power[20];
  70         unsigned int                     pdev_id;
  71         unsigned int                     irq;
  72         void __iomem                    *regs;
  73         unsigned int                     rev;
  74 };
  75
  76
  77 #define MHZ (1000 * 1000)
  78
  79 #ifdef DEBUG
  80 static const unsigned int div_tab[] = {
  81         [0]             = 1,
  82         [1]             = 2,
  83         [2]             = 4,
  84         [3]             = 8,
  85         [4]             = 16,
  86         [5]             = 32,
  87         [6]             = 64,
  88         [7]             = 128,
  89         [8]             = 3,
  90         [9]             = 6,
  91         [10]            = 12,
  92         [11]            = 24,
  93         [12]            = 48,
  94         [13]            = 96,
  95         [14]            = 192,
  96         [15]            = 384,
  97         [16]            = 5,
  98         [17]            = 10,
  99         [18]            = 20,
 100         [19]            = 40,
 101         [20]            = 80,
 102         [21]            = 160,
 103         [22]            = 320,
 104         [23]            = 604,
 105 };
 106
 107 static unsigned long decode_div(unsigned long pll2, unsigned long val,
 108                                 unsigned int lshft, unsigned int selbit,
 109                                 unsigned long mask)
 110 {
 111         if (val & selbit)
 112                 pll2 = 288 * MHZ;
 113
 114         return pll2 / div_tab[(val >> lshft) & mask];
 115 }
 116
 117 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
 118
 119 /* sm501_dump_clk
 120  *
 121  * Print out the current clock configuration for the device
 122 */
 123
 124 static void sm501_dump_clk(struct sm501_devdata *sm)
 125 {
 126         unsigned long misct = readl(sm->regs + SM501_MISC_TIMING);
 127         unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
 128         unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
 129         unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL);
 130         unsigned long sdclk0, sdclk1;
 131         unsigned long pll2 = 0;
 132
 133         switch (misct & 0x30) {
 134         case 0x00:
 135                 pll2 = 336 * MHZ;
 136                 break;
 137         case 0x10:
 138                 pll2 = 288 * MHZ;
 139                 break;
 140         case 0x20:
 141                 pll2 = 240 * MHZ;
 142                 break;
 143         case 0x30:
 144                 pll2 = 192 * MHZ;
 145                 break;
 146         }
 147
 148         sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
 149         sdclk0 /= div_tab[((misct >> 8) & 0xf)];
 150
 151         sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
 152         sdclk1 /= div_tab[((misct >> 16) & 0xf)];
 153
 154         dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
 155                 misct, pm0, pm1);
 156
 157         dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
 158                 fmt_freq(pll2), sdclk0, sdclk1);
 159
 160         dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
 161
 162         dev_dbg(sm->dev, "PM0[%c]: "
 163                  "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
 164                  "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
 165                  (pmc & 3 ) == 0 ? '*' : '-',
 166                  fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
 167                  fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
 168                  fmt_freq(decode_div(pll2, pm0, 8,  1<<12, 15)),
 169                  fmt_freq(decode_div(pll2, pm0, 0,  1<<4,  15)));
 170
 171         dev_dbg(sm->dev, "PM1[%c]: "
 172                 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
 173                 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
 174                 (pmc & 3 ) == 1 ? '*' : '-',
 175                 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
 176                 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
 177                 fmt_freq(decode_div(pll2, pm1, 8,  1<<12, 15)),
 178                 fmt_freq(decode_div(pll2, pm1, 0,  1<<4,  15)));
 179 }
 180
 181 static void sm501_dump_regs(struct sm501_devdata *sm)
 182 {
 183         void __iomem *regs = sm->regs;
 184
 185         dev_info(sm->dev, "System Control   %08x\n",
 186                         readl(regs + SM501_SYSTEM_CONTROL));
 187         dev_info(sm->dev, "Misc Control     %08x\n",
 188                         readl(regs + SM501_MISC_CONTROL));
 189         dev_info(sm->dev, "GPIO Control Low %08x\n",
 190                         readl(regs + SM501_GPIO31_0_CONTROL));
 191         dev_info(sm->dev, "GPIO Control Hi  %08x\n",
 192                         readl(regs + SM501_GPIO63_32_CONTROL));
 193         dev_info(sm->dev, "DRAM Control     %08x\n",
 194                         readl(regs + SM501_DRAM_CONTROL));
 195         dev_info(sm->dev, "Arbitration Ctrl %08x\n",
 196                         readl(regs + SM501_ARBTRTN_CONTROL));
 197         dev_info(sm->dev, "Misc Timing      %08x\n",
 198                         readl(regs + SM501_MISC_TIMING));
 199 }
 200
 201 static void sm501_dump_gate(struct sm501_devdata *sm)
 202 {
 203         dev_info(sm->dev, "CurrentGate      %08x\n",
 204                         readl(sm->regs + SM501_CURRENT_GATE));
 205         dev_info(sm->dev, "CurrentClock     %08x\n",
 206                         readl(sm->regs + SM501_CURRENT_CLOCK));
 207         dev_info(sm->dev, "PowerModeControl %08x\n",
 208                         readl(sm->regs + SM501_POWER_MODE_CONTROL));
 209 }
 210
 211 #else
 212 static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
 213 static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
 214 static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
 215 #endif
 216
 217 /* sm501_sync_regs
 218  *
 219  * ensure the
 220 */
 221
 222 static void sm501_sync_regs(struct sm501_devdata *sm)
 223 {
 224         readl(sm->regs);
 225 }
 226
 227 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
 228 {
 229         /* during suspend/resume, we are currently not allowed to sleep,
 230          * so change to using mdelay() instead of msleep() if we
 231          * are in one of these paths */
 232
 233         if (sm->in_suspend)
 234                 mdelay(delay);
 235         else
 236                 msleep(delay);
 237 }
 238
 239 /* sm501_misc_control
 240  *
 241  * alters the miscellaneous control parameters
 242 */
 243
 244 int sm501_misc_control(struct device *dev,
 245                        unsigned long set, unsigned long clear)
 246 {
 247         struct sm501_devdata *sm = dev_get_drvdata(dev);
 248         unsigned long misc;
 249         unsigned long save;
 250         unsigned long to;
 251
 252         spin_lock_irqsave(&sm->reg_lock, save);
 253
 254         misc = readl(sm->regs + SM501_MISC_CONTROL);
 255         to = (misc & ~clear) | set;
 256
 257         if (to != misc) {
 258                 writel(to, sm->regs + SM501_MISC_CONTROL);
 259                 sm501_sync_regs(sm);
 260
 261                 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
 262         }
 263
 264         spin_unlock_irqrestore(&sm->reg_lock, save);
 265         return to;
 266 }
 267
 268 EXPORT_SYMBOL_GPL(sm501_misc_control);
 269
 270 /* sm501_modify_reg
 271  *
 272  * Modify a register in the SM501 which may be shared with other
 273  * drivers.
 274 */
 275
 276 unsigned long sm501_modify_reg(struct device *dev,
 277                                unsigned long reg,
 278                                unsigned long set,
 279                                unsigned long clear)
 280 {
 281         struct sm501_devdata *sm = dev_get_drvdata(dev);
 282         unsigned long data;
 283         unsigned long save;
 284
 285         spin_lock_irqsave(&sm->reg_lock, save);
 286
 287         data = readl(sm->regs + reg);
 288         data |= set;
 289         data &= ~clear;
 290
 291         writel(data, sm->regs + reg);
 292         sm501_sync_regs(sm);
 293
 294         spin_unlock_irqrestore(&sm->reg_lock, save);
 295
 296         return data;
 297 }
 298
 299 EXPORT_SYMBOL_GPL(sm501_modify_reg);
 300
 301 /* sm501_unit_power
 302  *
 303  * alters the power active gate to set specific units on or off
 304  */
 305
 306 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
 307 {
 308         struct sm501_devdata *sm = dev_get_drvdata(dev);
 309         unsigned long mode;
 310         unsigned long gate;
 311         unsigned long clock;
 312
 313         mutex_lock(&sm->clock_lock);
 314
 315         mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
 316         gate = readl(sm->regs + SM501_CURRENT_GATE);
 317         clock = readl(sm->regs + SM501_CURRENT_CLOCK);
 318
 319         mode &= 3;              /* get current power mode */
 320
 321         if (unit >= ARRAY_SIZE(sm->unit_power)) {
 322                 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
 323                 goto already;
 324         }
 325
 326         dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
 327                 sm->unit_power[unit], to);
 328
 329         if (to == 0 && sm->unit_power[unit] == 0) {
 330                 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
 331                 goto already;
 332         }
 333
 334         sm->unit_power[unit] += to ? 1 : -1;
 335         to = sm->unit_power[unit] ? 1 : 0;
 336
 337         if (to) {
 338                 if (gate & (1 << unit))
 339                         goto already;
 340                 gate |= (1 << unit);
 341         } else {
 342                 if (!(gate & (1 << unit)))
 343                         goto already;
 344                 gate &= ~(1 << unit);
 345         }
 346
 347         switch (mode) {
 348         case 1:
 349                 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
 350                 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
 351                 mode = 0;
 352                 break;
 353         case 2:
 354         case 0:
 355                 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
 356                 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
 357                 mode = 1;
 358                 break;
 359
 360         default:
 361                 return -1;
 362         }
 363
 364         writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
 365         sm501_sync_regs(sm);
 366
 367         dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
 368                 gate, clock, mode);
 369
 370         sm501_mdelay(sm, 16);
 371
 372  already:
 373         mutex_unlock(&sm->clock_lock);
 374         return gate;
 375 }
 376
 377 EXPORT_SYMBOL_GPL(sm501_unit_power);
 378
 379
 380 /* Perform a rounded division. */
 381 static long sm501fb_round_div(long num, long denom)
 382 {
 383         /* n / d + 1 / 2 = (2n + d) / 2d */
 384         return (2 * num + denom) / (2 * denom);
 385 }
 386
 387 /* clock value structure. */
 388 struct sm501_clock {
 389         unsigned long mclk;
 390         int divider;
 391         int shift;
 392         unsigned int m, n, k;
 393 };
 394
 395 /* sm501_calc_clock
 396  *
 397  * Calculates the nearest discrete clock frequency that
 398  * can be achieved with the specified input clock.
 399  *   the maximum divisor is 3 or 5
 400  */
 401
 402 static int sm501_calc_clock(unsigned long freq,
 403                             struct sm501_clock *clock,
 404                             int max_div,
 405                             unsigned long mclk,
 406                             long *best_diff)
 407 {
 408         int ret = 0;
 409         int divider;
 410         int shift;
 411         long diff;
 412
 413         /* try dividers 1 and 3 for CRT and for panel,
 414            try divider 5 for panel only.*/
 415
 416         for (divider = 1; divider <= max_div; divider += 2) {
 417                 /* try all 8 shift values.*/
 418                 for (shift = 0; shift < 8; shift++) {
 419                         /* Calculate difference to requested clock */
 420                         diff = sm501fb_round_div(mclk, divider << shift) - freq;
 421                         if (diff < 0)
 422                                 diff = -diff;
 423
 424                         /* If it is less than the current, use it */
 425                         if (diff < *best_diff) {
 426                                 *best_diff = diff;
 427
 428                                 clock->mclk = mclk;
 429                                 clock->divider = divider;
 430                                 clock->shift = shift;
 431                                 ret = 1;
 432                         }
 433                 }
 434         }
 435
 436         return ret;
 437 }
 438
 439 /* sm501_calc_pll
 440  *
 441  * Calculates the nearest discrete clock frequency that can be
 442  * achieved using the programmable PLL.
 443  *   the maximum divisor is 3 or 5
 444  */
 445
 446 static unsigned long sm501_calc_pll(unsigned long freq,
 447                                         struct sm501_clock *clock,
 448                                         int max_div)
 449 {
 450         unsigned long mclk;
 451         unsigned int m, n, k;
 452         long best_diff = 999999999;
 453
 454         /*
 455          * The SM502 datasheet doesn't specify the min/max values for M and N.
 456          * N = 1 at least doesn't work in practice.
 457          */
 458         for (m = 2; m <= 255; m++) {
 459                 for (n = 2; n <= 127; n++) {
 460                         for (k = 0; k <= 1; k++) {
 461                                 mclk = (24000000UL * m / n) >> k;
 462
 463                                 if (sm501_calc_clock(freq, clock, max_div,
 464                                                      mclk, &best_diff)) {
 465                                         clock->m = m;
 466                                         clock->n = n;
 467                                         clock->k = k;
 468                                 }
 469                         }
 470                 }
 471         }
 472
 473         /* Return best clock. */
 474         return clock->mclk / (clock->divider << clock->shift);
 475 }
 476
 477 /* sm501_select_clock
 478  *
 479  * Calculates the nearest discrete clock frequency that can be
 480  * achieved using the 288MHz and 336MHz PLLs.
 481  *   the maximum divisor is 3 or 5
 482  */
 483
 484 static unsigned long sm501_select_clock(unsigned long freq,
 485                                         struct sm501_clock *clock,
 486                                         int max_div)
 487 {
 488         unsigned long mclk;
 489         long best_diff = 999999999;
 490
 491         /* Try 288MHz and 336MHz clocks. */
 492         for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
 493                 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
 494         }
 495
 496         /* Return best clock. */
 497         return clock->mclk / (clock->divider << clock->shift);
 498 }
 499
 500 /* sm501_set_clock
 501  *
 502  * set one of the four clock sources to the closest available frequency to
 503  *  the one specified
 504 */
 505
 506 unsigned long sm501_set_clock(struct device *dev,
 507                               int clksrc,
 508                               unsigned long req_freq)
 509 {
 510         struct sm501_devdata *sm = dev_get_drvdata(dev);
 511         unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
 512         unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
 513         unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
 514         unsigned char reg;
 515         unsigned int pll_reg = 0;
 516         unsigned long sm501_freq; /* the actual frequency acheived */
 517
 518         struct sm501_clock to;
 519
 520         /* find achivable discrete frequency and setup register value
 521          * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
 522          * has an extra bit for the divider */
 523
 524         switch (clksrc) {
 525         case SM501_CLOCK_P2XCLK:
 526                 /* This clock is divided in half so to achive the
 527                  * requested frequency the value must be multiplied by
 528                  * 2. This clock also has an additional pre divisor */
 529
 530                 if (sm->rev >= 0xC0) {
 531                         /* SM502 -> use the programmable PLL */
 532                         sm501_freq = (sm501_calc_pll(2 * req_freq,
 533                                                      &to, 5) / 2);
 534                         reg = to.shift & 0x07;/* bottom 3 bits are shift */
 535                         if (to.divider == 3)
 536                                 reg |= 0x08; /* /3 divider required */
 537                         else if (to.divider == 5)
 538                                 reg |= 0x10; /* /5 divider required */
 539                         reg |= 0x40; /* select the programmable PLL */
 540                         pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
 541                 } else {
 542                         sm501_freq = (sm501_select_clock(2 * req_freq,
 543                                                          &to, 5) / 2);
 544                         reg = to.shift & 0x07;/* bottom 3 bits are shift */
 545                         if (to.divider == 3)
 546                                 reg |= 0x08; /* /3 divider required */
 547                         else if (to.divider == 5)
 548                                 reg |= 0x10; /* /5 divider required */
 549                         if (to.mclk != 288000000)
 550                                 reg |= 0x20; /* which mclk pll is source */
 551                 }
 552                 break;
 553
 554         case SM501_CLOCK_V2XCLK:
 555                 /* This clock is divided in half so to achive the
 556                  * requested frequency the value must be multiplied by 2. */
 557
 558                 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
 559                 reg=to.shift & 0x07;    /* bottom 3 bits are shift */
 560                 if (to.divider == 3)
 561                         reg |= 0x08;    /* /3 divider required */
 562                 if (to.mclk != 288000000)
 563                         reg |= 0x10;    /* which mclk pll is source */
 564                 break;
 565
 566         case SM501_CLOCK_MCLK:
 567         case SM501_CLOCK_M1XCLK:
 568                 /* These clocks are the same and not further divided */
 569
 570                 sm501_freq = sm501_select_clock( req_freq, &to, 3);
 571                 reg=to.shift & 0x07;    /* bottom 3 bits are shift */
 572                 if (to.divider == 3)
 573                         reg |= 0x08;    /* /3 divider required */
 574                 if (to.mclk != 288000000)
 575                         reg |= 0x10;    /* which mclk pll is source */
 576                 break;
 577
 578         default:
 579                 return 0; /* this is bad */
 580         }
 581
 582         mutex_lock(&sm->clock_lock);
 583
 584         mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
 585         gate = readl(sm->regs + SM501_CURRENT_GATE);
 586         clock = readl(sm->regs + SM501_CURRENT_CLOCK);
 587
 588         clock = clock & ~(0xFF << clksrc);
 589         clock |= reg<<clksrc;
 590
 591         mode &= 3;      /* find current mode */
 592
 593         switch (mode) {
 594         case 1:
 595                 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
 596                 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
 597                 mode = 0;
 598                 break;
 599         case 2:
 600         case 0:
 601                 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
 602                 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
 603                 mode = 1;
 604                 break;
 605
 606         default:
 607                 mutex_unlock(&sm->clock_lock);
 608                 return -1;
 609         }
 610
 611         writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
 612
 613         if (pll_reg)
 614                 writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
 615
 616         sm501_sync_regs(sm);
 617
 618         dev_info(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
 619                  gate, clock, mode);
 620
 621         sm501_mdelay(sm, 16);
 622         mutex_unlock(&sm->clock_lock);
 623
 624         sm501_dump_clk(sm);
 625
 626         return sm501_freq;
 627 }
 628
 629 EXPORT_SYMBOL_GPL(sm501_set_clock);
 630
 631 /* sm501_find_clock
 632  *
 633  * finds the closest available frequency for a given clock
 634 */
 635
 636 unsigned long sm501_find_clock(struct device *dev,
 637                                int clksrc,
 638                                unsigned long req_freq)
 639 {
 640         struct sm501_devdata *sm = dev_get_drvdata(dev);
 641         unsigned long sm501_freq; /* the frequency achiveable by the 501 */
 642         struct sm501_clock to;
 643
 644         switch (clksrc) {
 645         case SM501_CLOCK_P2XCLK:
 646                 if (sm->rev >= 0xC0) {
 647                         /* SM502 -> use the programmable PLL */
 648                         sm501_freq = (sm501_calc_pll(2 * req_freq,
 649                                                      &to, 5) / 2);
 650                 } else {
 651                         sm501_freq = (sm501_select_clock(2 * req_freq,
 652                                                          &to, 5) / 2);
 653                 }
 654                 break;
 655
 656         case SM501_CLOCK_V2XCLK:
 657                 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
 658                 break;
 659
 660         case SM501_CLOCK_MCLK:
 661         case SM501_CLOCK_M1XCLK:
 662                 sm501_freq = sm501_select_clock(req_freq, &to, 3);
 663                 break;
 664
 665         default:
 666                 sm501_freq = 0;         /* error */
 667         }
 668
 669         return sm501_freq;
 670 }
 671
 672 EXPORT_SYMBOL_GPL(sm501_find_clock);
 673
 674 static struct sm501_device *to_sm_device(struct platform_device *pdev)
 675 {
 676         return container_of(pdev, struct sm501_device, pdev);
 677 }
 678
 679 /* sm501_device_release
 680  *
 681  * A release function for the platform devices we create to allow us to
 682  * free any items we allocated
 683 */
 684
 685 static void sm501_device_release(struct device *dev)
 686 {
 687         kfree(to_sm_device(to_platform_device(dev)));
 688 }
 689
 690 /* sm501_create_subdev
 691  *
 692  * Create a skeleton platform device with resources for passing to a
 693  * sub-driver
 694 */
 695
 696 static struct platform_device *
 697 sm501_create_subdev(struct sm501_devdata *sm, char *name,
 698                     unsigned int res_count, unsigned int platform_data_size)
 699 {
 700         struct sm501_device *smdev;
 701
 702         smdev = kzalloc(sizeof(struct sm501_device) +
 703                         (sizeof(struct resource) * res_count) +
 704                         platform_data_size, GFP_KERNEL);
 705         if (!smdev)
 706                 return NULL;
 707
 708         smdev->pdev.dev.release = sm501_device_release;
 709
 710         smdev->pdev.name = name;
 711         smdev->pdev.id = sm->pdev_id;
 712         smdev->pdev.dev.parent = sm->dev;
 713
 714         if (res_count) {
 715                 smdev->pdev.resource = (struct resource *)(smdev+1);
 716                 smdev->pdev.num_resources = res_count;
 717         }
 718         if (platform_data_size)
 719                 smdev->pdev.dev.platform_data = (void *)(smdev+1);
 720
 721         return &smdev->pdev;
 722 }
 723
 724 /* sm501_register_device
 725  *
 726  * Register a platform device created with sm501_create_subdev()
 727 */
 728
 729 static int sm501_register_device(struct sm501_devdata *sm,
 730                                  struct platform_device *pdev)
 731 {
 732         struct sm501_device *smdev = to_sm_device(pdev);
 733         int ptr;
 734         int ret;
 735
 736         for (ptr = 0; ptr < pdev->num_resources; ptr++) {
 737                 printk("%s[%d] flags %08lx: %08llx..%08llx\n",
 738                        pdev->name, ptr,
 739                        pdev->resource[ptr].flags,
 740                        (unsigned long long)pdev->resource[ptr].start,
 741                        (unsigned long long)pdev->resource[ptr].end);
 742         }
 743
 744         ret = platform_device_register(pdev);
 745
 746         if (ret >= 0) {
 747                 dev_dbg(sm->dev, "registered %s\n", pdev->name);
 748                 list_add_tail(&smdev->list, &sm->devices);
 749         } else
 750                 dev_err(sm->dev, "error registering %s (%d)\n",
 751                         pdev->name, ret);
 752
 753         return ret;
 754 }
 755
 756 /* sm501_create_subio
 757  *
 758  * Fill in an IO resource for a sub device
 759 */
 760
 761 static void sm501_create_subio(struct sm501_devdata *sm,
 762                                struct resource *res,
 763                                resource_size_t offs,
 764                                resource_size_t size)
 765 {
 766         res->flags = IORESOURCE_MEM;
 767         res->parent = sm->io_res;
 768         res->start = sm->io_res->start + offs;
 769         res->end = res->start + size - 1;
 770 }
 771
 772 /* sm501_create_mem
 773  *
 774  * Fill in an MEM resource for a sub device
 775 */
 776
 777 static void sm501_create_mem(struct sm501_devdata *sm,
 778                              struct resource *res,
 779                              resource_size_t *offs,
 780                              resource_size_t size)
 781 {
 782         *offs -= size;          /* adjust memory size */
 783
 784         res->flags = IORESOURCE_MEM;
 785         res->parent = sm->mem_res;
 786         res->start = sm->mem_res->start + *offs;
 787         res->end = res->start + size - 1;
 788 }
 789
 790 /* sm501_create_irq
 791  *
 792  * Fill in an IRQ resource for a sub device
 793 */
 794
 795 static void sm501_create_irq(struct sm501_devdata *sm,
 796                              struct resource *res)
 797 {
 798         res->flags = IORESOURCE_IRQ;
 799         res->parent = NULL;
 800         res->start = res->end = sm->irq;
 801 }
 802
 803 static int sm501_register_usbhost(struct sm501_devdata *sm,
 804                                   resource_size_t *mem_avail)
 805 {
 806         struct platform_device *pdev;
 807
 808         pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
 809         if (!pdev)
 810                 return -ENOMEM;
 811
 812         sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
 813         sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
 814         sm501_create_irq(sm, &pdev->resource[2]);
 815
 816         return sm501_register_device(sm, pdev);
 817 }
 818
 819 static void sm501_setup_uart_data(struct sm501_devdata *sm,
 820                                   struct plat_serial8250_port *uart_data,
 821                                   unsigned int offset)
 822 {
 823         uart_data->membase = sm->regs + offset;
 824         uart_data->mapbase = sm->io_res->start + offset;
 825         uart_data->iotype = UPIO_MEM;
 826         uart_data->irq = sm->irq;
 827         uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
 828         uart_data->regshift = 2;
 829         uart_data->uartclk = (9600 * 16);
 830 }
 831
 832 static int sm501_register_uart(struct sm501_devdata *sm, int devices)
 833 {
 834         struct platform_device *pdev;
 835         struct plat_serial8250_port *uart_data;
 836
 837         pdev = sm501_create_subdev(sm, "serial8250", 0,
 838                                    sizeof(struct plat_serial8250_port) * 3);
 839         if (!pdev)
 840                 return -ENOMEM;
 841
 842         uart_data = pdev->dev.platform_data;
 843
 844         if (devices & SM501_USE_UART0) {
 845                 sm501_setup_uart_data(sm, uart_data++, 0x30000);
 846                 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
 847                 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
 848                 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
 849         }
 850         if (devices & SM501_USE_UART1) {
 851                 sm501_setup_uart_data(sm, uart_data++, 0x30020);
 852                 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
 853                 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
 854                 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
 855         }
 856
 857         pdev->id = PLAT8250_DEV_SM501;
 858
 859         return sm501_register_device(sm, pdev);
 860 }
 861
 862 static int sm501_register_display(struct sm501_devdata *sm,
 863                                   resource_size_t *mem_avail)
 864 {
 865         struct platform_device *pdev;
 866
 867         pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
 868         if (!pdev)
 869                 return -ENOMEM;
 870
 871         sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
 872         sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
 873         sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
 874         sm501_create_irq(sm, &pdev->resource[3]);
 875
 876         return sm501_register_device(sm, pdev);
 877 }
 878
 879 #ifdef CONFIG_MFD_SM501_GPIO
 880
 881 static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc)
 882 {
 883         return container_of(gc, struct sm501_gpio_chip, gpio);
 884 }
 885
 886 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
 887 {
 888         return container_of(gpio, struct sm501_devdata, gpio);
 889 }
 890
 891 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
 892
 893 {
 894         struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip);
 895         unsigned long result;
 896
 897         result = readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
 898         result >>= offset;
 899
 900         return result & 1UL;
 901 }
 902
 903 static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 904
 905 {
 906         struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
 907         struct sm501_gpio *smgpio = smchip->ourgpio;
 908         unsigned long bit = 1 << offset;
 909         void __iomem *regs = smchip->regbase;
 910         unsigned long save;
 911         unsigned long val;
 912
 913         dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
 914                 __func__, chip, offset);
 915
 916         spin_lock_irqsave(&smgpio->lock, save);
 917
 918         val = readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
 919         if (value)
 920                 val |= bit;
 921         writel(val, regs);
 922
 923         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 924         spin_unlock_irqrestore(&smgpio->lock, save);
 925 }
 926
 927 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
 928 {
 929         struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
 930         struct sm501_gpio *smgpio = smchip->ourgpio;
 931         void __iomem *regs = smchip->regbase;
 932         unsigned long bit = 1 << offset;
 933         unsigned long save;
 934         unsigned long ddr;
 935
 936         dev_info(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
 937                  __func__, chip, offset);
 938
 939         spin_lock_irqsave(&smgpio->lock, save);
 940
 941         ddr = readl(regs + SM501_GPIO_DDR_LOW);
 942         writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
 943
 944         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 945         spin_unlock_irqrestore(&smgpio->lock, save);
 946
 947         return 0;
 948 }
 949
 950 static int sm501_gpio_output(struct gpio_chip *chip,
 951                              unsigned offset, int value)
 952 {
 953         struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
 954         struct sm501_gpio *smgpio = smchip->ourgpio;
 955         unsigned long bit = 1 << offset;
 956         void __iomem *regs = smchip->regbase;
 957         unsigned long save;
 958         unsigned long val;
 959         unsigned long ddr;
 960
 961         dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
 962                 __func__, chip, offset, value);
 963
 964         spin_lock_irqsave(&smgpio->lock, save);
 965
 966         val = readl(regs + SM501_GPIO_DATA_LOW);
 967         if (value)
 968                 val |= bit;
 969         else
 970                 val &= ~bit;
 971         writel(val, regs);
 972
 973         ddr = readl(regs + SM501_GPIO_DDR_LOW);
 974         writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
 975
 976         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 977         writel(val, regs + SM501_GPIO_DATA_LOW);
 978
 979         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 980         spin_unlock_irqrestore(&smgpio->lock, save);
 981
 982         return 0;
 983 }
 984
 985 static struct gpio_chip gpio_chip_template = {
 986         .ngpio                  = 32,
 987         .direction_input        = sm501_gpio_input,
 988         .direction_output       = sm501_gpio_output,
 989         .set                    = sm501_gpio_set,
 990         .get                    = sm501_gpio_get,
 991 };
 992
 993 static int __devinit sm501_gpio_register_chip(struct sm501_devdata *sm,
 994                                               struct sm501_gpio *gpio,
 995                                               struct sm501_gpio_chip *chip)
 996 {
 997         struct sm501_platdata *pdata = sm->platdata;
 998         struct gpio_chip *gchip = &chip->gpio;
 999         int base = pdata->gpio_base;
1000
1001         memcpy(chip, &gpio_chip_template, sizeof(struct gpio_chip));
1002
1003         if (chip == &gpio->high) {
1004                 if (base > 0)
1005                         base += 32;
1006                 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1007                 gchip->label  = "SM501-HIGH";
1008         } else {
1009                 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1010                 gchip->label  = "SM501-LOW";
1011         }
1012
1013         gchip->base   = base;
1014         chip->ourgpio = gpio;
1015
1016         return gpiochip_add(gchip);
1017 }
1018
1019 static int sm501_register_gpio(struct sm501_devdata *sm)
1020 {
1021         struct sm501_gpio *gpio = &sm->gpio;
1022         resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1023         int ret;
1024         int tmp;
1025
1026         dev_dbg(sm->dev, "registering gpio block %08llx\n",
1027                 (unsigned long long)iobase);
1028
1029         spin_lock_init(&gpio->lock);
1030
1031         gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1032         if (gpio->regs_res == NULL) {
1033                 dev_err(sm->dev, "gpio: failed to request region\n");
1034                 return -ENXIO;
1035         }
1036
1037         gpio->regs = ioremap(iobase, 0x20);
1038         if (gpio->regs == NULL) {
1039                 dev_err(sm->dev, "gpio: failed to remap registers\n");
1040                 ret = -ENXIO;
1041                 goto err_mapped;
1042         }
1043
1044         /* Register both our chips. */
1045
1046         ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1047         if (ret) {
1048                 dev_err(sm->dev, "failed to add low chip\n");
1049                 goto err_mapped;
1050         }
1051
1052         ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1053         if (ret) {
1054                 dev_err(sm->dev, "failed to add high chip\n");
1055                 goto err_low_chip;
1056         }
1057
1058         gpio->registered = 1;
1059
1060         return 0;
1061
1062  err_low_chip:
1063         tmp = gpiochip_remove(&gpio->low.gpio);
1064         if (tmp) {
1065                 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1066                 return ret;
1067         }
1068
1069  err_mapped:
1070         release_resource(gpio->regs_res);
1071         kfree(gpio->regs_res);
1072
1073         return ret;
1074 }
1075
1076 static void sm501_gpio_remove(struct sm501_devdata *sm)
1077 {
1078         int ret;
1079
1080         ret = gpiochip_remove(&sm->gpio.low.gpio);
1081         if (ret)
1082                 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1083
1084         ret = gpiochip_remove(&sm->gpio.high.gpio);
1085         if (ret)
1086                 dev_err(sm->dev, "cannot remove high chip, cannot tidy up\n");
1087 }
1088
1089 #else
1090 static int sm501_register_gpio(struct sm501_devdata *sm)
1091 {
1092         return 0;
1093 }
1094
1095 static void sm501_gpio_remove(struct sm501_devdata *sm)
1096 {
1097 }
1098 #endif
1099
1100 /* sm501_dbg_regs
1101  *
1102  * Debug attribute to attach to parent device to show core registers
1103 */
1104
1105 static ssize_t sm501_dbg_regs(struct device *dev,
1106                               struct device_attribute *attr, char *buff)
1107 {
1108         struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1109         unsigned int reg;
1110         char *ptr = buff;
1111         int ret;
1112
1113         for (reg = 0x00; reg < 0x70; reg += 4) {
1114                 ret = sprintf(ptr, "%08x = %08x\n",
1115                               reg, readl(sm->regs + reg));
1116                 ptr += ret;
1117         }
1118
1119         return ptr - buff;
1120 }
1121
1122
1123 static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
1124
1125 /* sm501_init_reg
1126  *
1127  * Helper function for the init code to setup a register
1128  *
1129  * clear the bits which are set in r->mask, and then set
1130  * the bits set in r->set.
1131 */
1132
1133 static inline void sm501_init_reg(struct sm501_devdata *sm,
1134                                   unsigned long reg,
1135                                   struct sm501_reg_init *r)
1136 {
1137         unsigned long tmp;
1138
1139         tmp = readl(sm->regs + reg);
1140         tmp &= ~r->mask;
1141         tmp |= r->set;
1142         writel(tmp, sm->regs + reg);
1143 }
1144
1145 /* sm501_init_regs
1146  *
1147  * Setup core register values
1148 */
1149
1150 static void sm501_init_regs(struct sm501_devdata *sm,
1151                             struct sm501_initdata *init)
1152 {
1153         sm501_misc_control(sm->dev,
1154                            init->misc_control.set,
1155                            init->misc_control.mask);
1156
1157         sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1158         sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1159         sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1160
1161         if (init->m1xclk) {
1162                 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1163                 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1164         }
1165
1166         if (init->mclk) {
1167                 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1168                 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1169         }
1170
1171 }
1172
1173 /* Check the PLL sources for the M1CLK and M1XCLK
1174  *
1175  * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1176  * there is a risk (see errata AB-5) that the SM501 will cease proper
1177  * function. If this happens, then it is likely the SM501 will
1178  * hang the system.
1179 */
1180
1181 static int sm501_check_clocks(struct sm501_devdata *sm)
1182 {
1183         unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK);
1184         unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1185         unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1186
1187         return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1188 }
1189
1190 static unsigned int sm501_mem_local[] = {
1191         [0]     = 4*1024*1024,
1192         [1]     = 8*1024*1024,
1193         [2]     = 16*1024*1024,
1194         [3]     = 32*1024*1024,
1195         [4]     = 64*1024*1024,
1196         [5]     = 2*1024*1024,
1197 };
1198
1199 /* sm501_init_dev
1200  *
1201  * Common init code for an SM501
1202 */
1203
1204 static int sm501_init_dev(struct sm501_devdata *sm)
1205 {
1206         struct sm501_initdata *idata;
1207         resource_size_t mem_avail;
1208         unsigned long dramctrl;
1209         unsigned long devid;
1210         int ret;
1211
1212         mutex_init(&sm->clock_lock);
1213         spin_lock_init(&sm->reg_lock);
1214
1215         INIT_LIST_HEAD(&sm->devices);
1216
1217         devid = readl(sm->regs + SM501_DEVICEID);
1218
1219         if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1220                 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1221                 return -EINVAL;
1222         }
1223
1224         /* disable irqs */
1225         writel(0, sm->regs + SM501_IRQ_MASK);
1226
1227         dramctrl = readl(sm->regs + SM501_DRAM_CONTROL);
1228         mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1229
1230         dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1231                  sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1232
1233         sm->rev = devid & SM501_DEVICEID_REVMASK;
1234
1235         sm501_dump_gate(sm);
1236
1237         ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1238         if (ret)
1239                 dev_err(sm->dev, "failed to create debug regs file\n");
1240
1241         sm501_dump_clk(sm);
1242
1243         /* check to see if we have some device initialisation */
1244
1245         idata = sm->platdata ? sm->platdata->init : NULL;
1246         if (idata) {
1247                 sm501_init_regs(sm, idata);
1248
1249                 if (idata->devices & SM501_USE_USB_HOST)
1250                         sm501_register_usbhost(sm, &mem_avail);
1251                 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1252                         sm501_register_uart(sm, idata->devices);
1253                 if (idata->devices & SM501_USE_GPIO)
1254                         sm501_register_gpio(sm);
1255         }
1256
1257         ret = sm501_check_clocks(sm);
1258         if (ret) {
1259                 dev_err(sm->dev, "M1X and M clocks sourced from different "
1260                                         "PLLs\n");
1261                 return -EINVAL;
1262         }
1263
1264         /* always create a framebuffer */
1265         sm501_register_display(sm, &mem_avail);
1266
1267         return 0;
1268 }
1269
1270 static int sm501_plat_probe(struct platform_device *dev)
1271 {
1272         struct sm501_devdata *sm;
1273         int err;
1274
1275         sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1276         if (sm == NULL) {
1277                 dev_err(&dev->dev, "no memory for device data\n");
1278                 err = -ENOMEM;
1279                 goto err1;
1280         }
1281
1282         sm->dev = &dev->dev;
1283         sm->pdev_id = dev->id;
1284         sm->irq = platform_get_irq(dev, 0);
1285         sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1286         sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1287         sm->platdata = dev->dev.platform_data;
1288
1289         if (sm->irq < 0) {
1290                 dev_err(&dev->dev, "failed to get irq resource\n");
1291                 err = sm->irq;
1292                 goto err_res;
1293         }
1294
1295         if (sm->io_res == NULL || sm->mem_res == NULL) {
1296                 dev_err(&dev->dev, "failed to get IO resource\n");
1297                 err = -ENOENT;
1298                 goto err_res;
1299         }
1300
1301         sm->regs_claim = request_mem_region(sm->io_res->start,
1302                                             0x100, "sm501");
1303
1304         if (sm->regs_claim == NULL) {
1305                 dev_err(&dev->dev, "cannot claim registers\n");
1306                 err= -EBUSY;
1307                 goto err_res;
1308         }
1309
1310         platform_set_drvdata(dev, sm);
1311
1312         sm->regs = ioremap(sm->io_res->start,
1313                            (sm->io_res->end - sm->io_res->start) - 1);
1314
1315         if (sm->regs == NULL) {
1316                 dev_err(&dev->dev, "cannot remap registers\n");
1317                 err = -EIO;
1318                 goto err_claim;
1319         }
1320
1321         return sm501_init_dev(sm);
1322
1323  err_claim:
1324         release_resource(sm->regs_claim);
1325         kfree(sm->regs_claim);
1326  err_res:
1327         kfree(sm);
1328  err1:
1329         return err;
1330
1331 }
1332
1333 #ifdef CONFIG_PM
1334
1335 /* power management support */
1336
1337 static void sm501_set_power(struct sm501_devdata *sm, int on)
1338 {
1339         struct sm501_platdata *pd = sm->platdata;
1340
1341         if (pd == NULL)
1342                 return;
1343
1344         if (pd->get_power) {
1345                 if (pd->get_power(sm->dev) == on) {
1346                         dev_dbg(sm->dev, "is already %d\n", on);
1347                         return;
1348                 }
1349         }
1350
1351         if (pd->set_power) {
1352                 dev_dbg(sm->dev, "setting power to %d\n", on);
1353
1354                 pd->set_power(sm->dev, on);
1355                 sm501_mdelay(sm, 10);
1356         }
1357 }
1358
1359 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1360 {
1361         struct sm501_devdata *sm = platform_get_drvdata(pdev);
1362
1363         sm->in_suspend = 1;
1364         sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL);
1365
1366         sm501_dump_regs(sm);
1367
1368         if (sm->platdata) {
1369                 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1370                         sm501_set_power(sm, 0);
1371         }
1372
1373         return 0;
1374 }
1375
1376 static int sm501_plat_resume(struct platform_device *pdev)
1377 {
1378         struct sm501_devdata *sm = platform_get_drvdata(pdev);
1379
1380         sm501_set_power(sm, 1);
1381
1382         sm501_dump_regs(sm);
1383         sm501_dump_gate(sm);
1384         sm501_dump_clk(sm);
1385
1386         /* check to see if we are in the same state as when suspended */
1387
1388         if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1389                 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1390                 writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1391
1392                 /* our suspend causes the controller state to change,
1393                  * either by something attempting setup, power loss,
1394                  * or an external reset event on power change */
1395
1396                 if (sm->platdata && sm->platdata->init) {
1397                         sm501_init_regs(sm, sm->platdata->init);
1398                 }
1399         }
1400
1401         /* dump our state from resume */
1402
1403         sm501_dump_regs(sm);
1404         sm501_dump_clk(sm);
1405
1406         sm->in_suspend = 0;
1407
1408         return 0;
1409 }
1410 #else
1411 #define sm501_plat_suspend NULL
1412 #define sm501_plat_resume NULL
1413 #endif
1414
1415 /* Initialisation data for PCI devices */
1416
1417 static struct sm501_initdata sm501_pci_initdata = {
1418         .gpio_high      = {
1419                 .set    = 0x3F000000,           /* 24bit panel */
1420                 .mask   = 0x0,
1421         },
1422         .misc_timing    = {
1423                 .set    = 0x010100,             /* SDRAM timing */
1424                 .mask   = 0x1F1F00,
1425         },
1426         .misc_control   = {
1427                 .set    = SM501_MISC_PNL_24BIT,
1428                 .mask   = 0,
1429         },
1430
1431         .devices        = SM501_USE_ALL,
1432
1433         /* Errata AB-3 says that 72MHz is the fastest available
1434          * for 33MHZ PCI with proper bus-mastering operation */
1435
1436         .mclk           = 72 * MHZ,
1437         .m1xclk         = 144 * MHZ,
1438 };
1439
1440 static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1441         .flags          = (SM501FB_FLAG_USE_INIT_MODE |
1442                            SM501FB_FLAG_USE_HWCURSOR |
1443                            SM501FB_FLAG_USE_HWACCEL |
1444                            SM501FB_FLAG_DISABLE_AT_EXIT),
1445 };
1446
1447 static struct sm501_platdata_fb sm501_fb_pdata = {
1448         .fb_route       = SM501_FB_OWN,
1449         .fb_crt         = &sm501_pdata_fbsub,
1450         .fb_pnl         = &sm501_pdata_fbsub,
1451 };
1452
1453 static struct sm501_platdata sm501_pci_platdata = {
1454         .init           = &sm501_pci_initdata,
1455         .fb             = &sm501_fb_pdata,
1456         .gpio_base      = -1,
1457 };
1458
1459 static int sm501_pci_probe(struct pci_dev *dev,
1460                            const struct pci_device_id *id)
1461 {
1462         struct sm501_devdata *sm;
1463         int err;
1464
1465         sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1466         if (sm == NULL) {
1467                 dev_err(&dev->dev, "no memory for device data\n");
1468                 err = -ENOMEM;
1469                 goto err1;
1470         }
1471
1472         /* set a default set of platform data */
1473         dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1474
1475         /* set a hopefully unique id for our child platform devices */
1476         sm->pdev_id = 32 + dev->devfn;
1477
1478         pci_set_drvdata(dev, sm);
1479
1480         err = pci_enable_device(dev);
1481         if (err) {
1482                 dev_err(&dev->dev, "cannot enable device\n");
1483                 goto err2;
1484         }
1485
1486         sm->dev = &dev->dev;
1487         sm->irq = dev->irq;
1488
1489 #ifdef __BIG_ENDIAN
1490         /* if the system is big-endian, we most probably have a
1491          * translation in the IO layer making the PCI bus little endian
1492          * so make the framebuffer swapped pixels */
1493
1494         sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1495 #endif
1496
1497         /* check our resources */
1498
1499         if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1500                 dev_err(&dev->dev, "region #0 is not memory?\n");
1501                 err = -EINVAL;
1502                 goto err3;
1503         }
1504
1505         if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1506                 dev_err(&dev->dev, "region #1 is not memory?\n");
1507                 err = -EINVAL;
1508                 goto err3;
1509         }
1510
1511         /* make our resources ready for sharing */
1512
1513         sm->io_res = &dev->resource[1];
1514         sm->mem_res = &dev->resource[0];
1515
1516         sm->regs_claim = request_mem_region(sm->io_res->start,
1517                                             0x100, "sm501");
1518         if (sm->regs_claim == NULL) {
1519                 dev_err(&dev->dev, "cannot claim registers\n");
1520                 err= -EBUSY;
1521                 goto err3;
1522         }
1523
1524         sm->regs = ioremap(pci_resource_start(dev, 1),
1525                            pci_resource_len(dev, 1));
1526
1527         if (sm->regs == NULL) {
1528                 dev_err(&dev->dev, "cannot remap registers\n");
1529                 err = -EIO;
1530                 goto err4;
1531         }
1532
1533         sm501_init_dev(sm);
1534         return 0;
1535
1536  err4:
1537         release_resource(sm->regs_claim);
1538         kfree(sm->regs_claim);
1539  err3:
1540         pci_disable_device(dev);
1541  err2:
1542         pci_set_drvdata(dev, NULL);
1543         kfree(sm);
1544  err1:
1545         return err;
1546 }
1547
1548 static void sm501_remove_sub(struct sm501_devdata *sm,
1549                              struct sm501_device *smdev)
1550 {
1551         list_del(&smdev->list);
1552         platform_device_unregister(&smdev->pdev);
1553 }
1554
1555 static void sm501_dev_remove(struct sm501_devdata *sm)
1556 {
1557         struct sm501_device *smdev, *tmp;
1558
1559         list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1560                 sm501_remove_sub(sm, smdev);
1561
1562         device_remove_file(sm->dev, &dev_attr_dbg_regs);
1563
1564         if (sm->gpio.registered)
1565                 sm501_gpio_remove(sm);
1566 }
1567
1568 static void sm501_pci_remove(struct pci_dev *dev)
1569 {
1570         struct sm501_devdata *sm = pci_get_drvdata(dev);
1571
1572         sm501_dev_remove(sm);
1573         iounmap(sm->regs);
1574
1575         release_resource(sm->regs_claim);
1576         kfree(sm->regs_claim);
1577
1578         pci_set_drvdata(dev, NULL);
1579         pci_disable_device(dev);
1580 }
1581
1582 static int sm501_plat_remove(struct platform_device *dev)
1583 {
1584         struct sm501_devdata *sm = platform_get_drvdata(dev);
1585
1586         sm501_dev_remove(sm);
1587         iounmap(sm->regs);
1588
1589         release_resource(sm->regs_claim);
1590         kfree(sm->regs_claim);
1591
1592         return 0;
1593 }
1594
1595 static struct pci_device_id sm501_pci_tbl[] = {
1596         { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1597         { 0, },
1598 };
1599
1600 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1601
1602 static struct pci_driver sm501_pci_drv = {
1603         .name           = "sm501",
1604         .id_table       = sm501_pci_tbl,
1605         .probe          = sm501_pci_probe,
1606         .remove         = sm501_pci_remove,
1607 };
1608
1609 MODULE_ALIAS("platform:sm501");
1610
1611 static struct platform_driver sm501_plat_drv = {
1612         .driver         = {
1613                 .name   = "sm501",
1614                 .owner  = THIS_MODULE,
1615         },
1616         .probe          = sm501_plat_probe,
1617         .remove         = sm501_plat_remove,
1618         .suspend        = sm501_plat_suspend,
1619         .resume         = sm501_plat_resume,
1620 };
1621
1622 static int __init sm501_base_init(void)
1623 {
1624         platform_driver_register(&sm501_plat_drv);
1625         return pci_register_driver(&sm501_pci_drv);
1626 }
1627
1628 static void __exit sm501_base_exit(void)
1629 {
1630         platform_driver_unregister(&sm501_plat_drv);
1631         pci_unregister_driver(&sm501_pci_drv);
1632 }
1633
1634 module_init(sm501_base_init);
1635 module_exit(sm501_base_exit);
1636
1637 MODULE_DESCRIPTION("SM501 Core Driver");
1638 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1639 MODULE_LICENSE("GPL v2");